System memory management methods, circuits and electronic devices

Abstract

This application provides a system memory management method, circuit, and electronic device. The method includes: during the initialization phase, storing a first number of consecutive conversion relationships extracted from a memory module into a cache module, wherein the conversion relationship refers to the relationship between the virtual address and the physical address of video data; when a second number of preceding conversion relationships among the first number of consecutive conversion relationships stored in the cache module are used up, extracting a second number of consecutive conversion relationships from the memory module; wherein the extracted second number of consecutive conversion relationships have a linear temporal progression relationship with the conversion relationships currently stored in the cache module; and using a cross-replacement strategy, replacing the used second number of preceding conversion relationships in the cache module with the second number of consecutive conversion relationships extracted from the memory module.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more specifically, to a system memory management method, circuit, and electronic device. Background Technology

[0002] The system memory management unit uses the mapping from virtual addresses to physical addresses, such as... Figure 1 As shown, to achieve functions such as scene virtualization and hardware-level security isolation, it has become a key technology component of current cloud servers, multi-core processors and edge computing devices, playing an important role in supporting memory resource virtualization, enhancing system security and improving I / O device performance.

[0003] Traditional system memory management primarily uses a lookup table to translate virtual addresses to physical addresses, with the translation table stored in memory. To reduce address translation latency, a cache is typically introduced to store frequently used translation relationships. The replacement strategy is mainly based on the time the translation occurred (replacing the longest existing one) or the number of times it occurred (replacing the least used one). By prioritizing the retention of high-frequency, recently used translation relationships, the address translation efficiency for regular data transmission is improved.

[0004] However, this traditional cache replacement method has significant drawbacks when processing video data transmission within the chip. Because video data exhibits characteristics such as linear distribution of virtual addresses within a frame and cyclic reuse across multiple frames, the traditional replacement strategy is incompatible with these characteristics, resulting in extremely low address translation efficiency. To ensure low latency requirements for video data transmission, existing technologies require large-capacity caches to store sufficient translation relationships. Especially with the continuous increase in video resolution and transmission bandwidth, the demand for cache capacity is constantly increasing, directly leading to increased chip area overhead and higher hardware costs. If the cache depth is insufficient to store enough translation relationships, the traditional cache replacement method will experience cache misses due to address boundaries. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a system memory management method, circuit and electronic device that solves the problem that the address translation of video data in traditional memory management requires a large cache capacity and is prone to cache misses leading to high latency.

[0006] In a first aspect, embodiments of this application provide a system memory management method, applied to a system memory management circuit, comprising:

[0007] During the initialization phase, a first number of consecutive conversion relationships extracted from the memory module are stored in the cache module, wherein the conversion relationship refers to the relationship between the virtual address and the physical address of the video data;

[0008] When the second number of preceding transformation relationships in the first number of consecutive transformation relationships stored in the cache module are used up, the second number of consecutive transformation relationships are extracted from the memory module; wherein, the extracted second number of consecutive transformation relationships have a linear temporal progressive relationship with the transformation relationships currently stored in the cache module;

[0009] Using a cross-replacement strategy, a second number of consecutive transformation relationships extracted from the memory module are used to replace a second number of pre-sequence transformation relationships that have been exhausted in the cache module.

[0010] In one optional embodiment, the step of filling the cache module with a first number of consecutive transformation relationships extracted from the memory module during the initialization phase includes:

[0011] Based on the pre-configured cache depth threshold of the cache module, a first number of consecutive transformation relationships of video data are read and stored in the cache module during the first memory access; wherein, the first number is the same as the cache depth threshold.

[0012] In one optional embodiment, the cache depth threshold of the cache module is obtained by processing the acquired configuration input parameters according to a preset algorithm. The configuration input parameters include device configuration information, the average time of virtual address translation commands, and the time to find and read the translation relationship from the memory module.

[0013] In one optional embodiment, the cache depth threshold of the cache module is directly proportional to a specified time ratio, which refers to the ratio between the address sending time and the time to read a conversion relationship from the memory module. The address sending time refers to the sum of the transmission time of a virtual address to the system memory management circuit, the hit time of the virtual address in the cache module of the system memory management circuit, and the time to convert the virtual address into a physical address.

[0014] In one optional embodiment, the step of using a cross-replacement strategy to replace the second number of used preceding transformation relationships in the cache module with the second number of consecutive transformation relationships extracted from the memory module includes:

[0015] When the second number of preceding transformation relationships stored in the cache module are used up, the next set of the second number of consecutive transformation relationships extracted from the memory module will replace the second number of preceding transformation relationships that have been used up in the cache module.

[0016] The process is repeated in sequence. For each set of a second number of consecutive transformation relationships, the second number of pre-sequence transformation relationships that have been used up in the cache module are cross-replaced until all transformation relationships in the video data are stored in the cache module.

[0017] In one alternative embodiment, the first quantity is twice the second quantity.

[0018] Secondly, embodiments of this application provide a system memory management circuit, including: a conversion decision module and a cache module;

[0019] The cache module is used to store a first number of consecutive transformation relationships;

[0020] The conversion decision module is used to execute the system memory management method described above.

[0021] In an optional embodiment, it further includes: a register, which is used to perform calculations on the written configuration input parameters using a preset algorithm and output the cache depth threshold of the cache module; wherein the configuration input parameters include device configuration information, the average time of virtual address translation commands, and the time to find and read the translation relationship from the memory module.

[0022] In an optional embodiment, it further includes: a configuration path, the configuration path being used to collect configuration input parameters and write the collected configuration input parameters into a register.

[0023] Thirdly, embodiments of this application also provide an electronic device, including: the above-described system memory management circuit, memory, and bus, wherein the system memory management circuit and the memory communicate via the bus.

[0024] The system memory management method, circuit, and electronic device provided in this application, by storing a first number of consecutive conversion relationships in the cache module during the initialization phase, provides a basis for subsequent address translation and avoids the delay caused by frequent reading of conversion relationships from the memory module in the initial phase; when the second number of preceding conversion relationships in the cache module are used up, a second number of conversion relationships that are linearly sequential with the current cache conversion relationship are extracted to ensure that the conversion relationship matches the linear address requirements of the video data; and then the used preceding conversion relationships are replaced by a cross-replacement strategy. This technical means of combining multiple conversion relationship prefetching and cross-replacement effectively reduces the initialization time, greatly improves the cache hit rate of address translation, and ultimately achieves the effect of completing video data address translation with a very small cache capacity and a very low conversion latency. It solves the problem that video data address translation requires a large cache capacity and is prone to cache misses leading to high latency in traditional memory management, and reduces chip area overhead.

[0025] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram illustrating the storage conversion relationship of a cache module provided by existing technology;

[0028] Figure 2 A schematic diagram of a video address translation relationship provided by existing technology;

[0029] Figure 3 A flowchart illustrating a system memory management method provided in an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of the structure of a system memory management circuit provided in an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of a video address translation relationship provided in an embodiment of this application;

[0032] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0034] First, the applicable application scenarios of this application will be introduced. This application can be applied to the chip industry.

[0035] Research has shown that traditional system memory management primarily uses a lookup table to translate virtual addresses to physical addresses, with the translation table stored in memory. To reduce address translation latency, a cache is typically introduced to store frequently used translation relationships. The replacement strategy is mainly based on the time the translation occurred (replacing the longest existing one) or the number of times it occurred (replacing the least used one). By prioritizing the retention of high-frequency, recently used translation relationships, the address translation efficiency for regular data transmission is improved.

[0036] However, this traditional cache replacement method has significant drawbacks when processing video data transmission within the chip. Because video data exhibits characteristics such as linear distribution of virtual addresses within a frame and cyclic reuse across multiple frames, the traditional replacement strategy is incompatible with these characteristics, resulting in extremely low address translation efficiency. To ensure low latency requirements for video data transmission, existing technologies require large-capacity caches to store sufficient translation relationships. Especially with the continuous increase in video resolution and transmission bandwidth, the demand for cache capacity is constantly increasing, directly leading to increased chip area overhead and higher hardware costs. If the cache depth is insufficient to store enough translation relationships, the traditional cache replacement method will experience cache misses due to address boundaries.

[0037] Assuming the physical address of a video frame is AN, and the translation relationship between physical and virtual addresses is ATN, taking a 1MB video frame as an example, 256 4K address translations are required. Figure 1 As shown, if the depth of the cache module is greater than or equal to 256, then after initialization, all translation relationships are stored in the cache module to ensure that all subsequent virtual addresses can be hit in the cache module. Figure 2 As shown, if the cache module depth is reduced to 200, it can only store 200 conversion relationships (e.g., AT0-AT199). However, video addresses are linearly continuous within a frame, sequentially crossing each 4K block boundary (from block 1 to block 256). When the video address accesses block 201 and beyond (corresponding to AT200-AT255), these conversion relationships are not stored in the 200-deep cache module. Furthermore, traditional cache replacement methods (based on time / usage count) do not prioritize retaining the continuous conversion relationships needed for subsequent video frames. This results in the cache module failing to find the corresponding conversion relationship when the address crosses a 4K boundary. Figure 2 The question marks in sections A0 to A255 indicate that the match was not found.

[0038] Based on this, the present application provides a system memory management method applied to a system memory management circuit, which solves the problems of high latency caused by large cache capacity for video data address translation and easy cache misses in traditional memory management.

[0039] Please see Figure 3 , Figure 3This is a flowchart illustrating a system memory management method provided in an embodiment of this application. Figure 3 As shown in the embodiments of this application, the method includes:

[0040] Step S101: During the initialization phase, the first number of consecutive conversion relationships extracted from the memory module are stored in the cache module. Here, the conversion relationship refers to the relationship between the virtual address and the physical address of the video data.

[0041] Step S102: When the second number of preceding transformation relationships in the first number of consecutive transformation relationships stored in the cache module are used up, the second number of consecutive transformation relationships are extracted from the memory module; wherein, the extracted second number of consecutive transformation relationships have a linear temporal progressive relationship with the transformation relationships currently stored in the cache module;

[0042] Step S103: Using a cross-replacement strategy, the second number of consecutive transformation relationships extracted from the memory module are used to replace the second number of pre-transformation relationships that have been exhausted in the cache module.

[0043] The method provided in this application stores a first number of consecutive conversion relationships in the cache module during the initialization phase, providing a basis for subsequent address translation and avoiding the delay caused by frequent reading of conversion relationships from the memory module during the initial phase. When the second number of preceding conversion relationships in the cache module are used up, a second number of conversion relationships that are linearly sequential with the current cached conversion relationship are extracted to ensure that the conversion relationship matches the linear address requirements of the video data. Then, the used preceding conversion relationships are replaced by a cross-replacement strategy. This technical means of combining multiple conversion relationship prefetching and cross-replacement effectively reduces the initialization time, greatly improves the cache hit rate of address translation, and ultimately achieves the effect of completing video data address translation with a very small cache capacity and very low translation latency. This solves the problem that video data address translation in traditional memory management requires a large cache capacity and is prone to cache misses leading to high latency, and reduces chip area overhead.

[0044] The following is a detailed explanation of steps S101 to S103 above:

[0045] In step S101, during the initialization phase, a first number of consecutive conversion relationships extracted from the memory module are stored in the cache module. Here, the conversion relationship refers to the relationship between the virtual address and the physical address of the video data.

[0046] Here, the initialization phase refers to the initial operation phase that prepares for subsequent video data address conversion when the system memory management method starts to execute. Its function is to store a certain number of conversion relationships in the cache module in advance to avoid frequently reading conversion relationships from the memory module during subsequent address conversion, thereby reducing the initial conversion delay.

[0047] Specifically, the initialization phase is a crucial preparatory stage after system startup and before formally processing video data address translation requests. This phase completes the initial data loading of the cache module. For example, when the chip begins processing the address translation task of a certain video stream, it first enters the initialization phase. At this time, the system will first read the required translation relationship from the memory module and store it in the cache module, laying the foundation for subsequently receiving the virtual address of video data and quickly completing the translation.

[0048] The memory module stores the translation relationship between the virtual address and physical address of video data. For example, the memory module can be a storage device such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR), which has a large storage capacity and can store the translation relationships corresponding to a large number of video frames. For instance, for video data with high resolution and a large number of frames, all its corresponding translation relationships are stored in the memory module, and when the cache module needs to replenish the translation relationships, it reads them from the memory module.

[0049] The cache module is a high-speed storage unit used to temporarily store translation relationships. It can shorten the time to obtain translation relationships during address translation. When address translation is required, the translation relationship is first searched in the cache module. If a match is found, it is used directly, avoiding the time-consuming problem of accessing the memory module.

[0050] Specifically, the cache module has a much higher read and write speed than the memory module. For example, when a translation relationship is found in the cache module, the address translation time T1 is only a few nanoseconds, while the time T2 to read the translation relationship from the memory module and complete the translation takes tens to hundreds of nanoseconds. The existence of the cache module significantly reduces address translation latency. For example, when processing virtual address translation requests for video data, the cache module is first checked to see if a corresponding translation relationship exists. If it does, the virtual address to physical address translation is completed directly using that relationship, without needing to access the memory module.

[0051] Optionally, the conversion relationship refers to the relationship between the virtual address and physical address of video data, that is, the mapping rule used to determine the physical address corresponding to a certain virtual address of video data, which can achieve accurate conversion from virtual address to physical address of video data. For example, the conversion relationship usually exists in the form of a data table, and each conversion relationship contains a virtual address segment and the corresponding physical address segment information.

[0052] Furthermore, the continuous conversion relationship refers to the correspondence between adjacent virtual addresses and physical addresses arranged sequentially in terms of timing or address order. This is used to match the linear distribution of virtual addresses within a frame of video data, ensuring that the required conversion relationships can be quickly obtained sequentially during address conversion. Here, the continuous conversion relationship corresponds to the conversion requirements of consecutive virtual address segments in a video frame. For example, a 1MB video frame might have its virtual address divided into 256 consecutive address segments per 4K page, corresponding to 256 conversion relationships AT0~AT0. 255 This is a continuous translation relationship, with each translation relationship corresponding to the translation of a 4K page's virtual address to its physical address, arranged sequentially according to the address segment order.

[0053] In one optional embodiment, step S101 specifically includes: reading a first number of consecutive transformation relationships of video data in the first memory access and storing them in the cache module according to a pre-configured cache depth threshold; wherein the first number is the same as the cache depth threshold.

[0054] In the above steps, the cache depth threshold of the cache module is first determined. This cache depth threshold is a parameter that is pre-configured according to system requirements and hardware characteristics to limit the maximum number of transformation relationships that the cache module can store, so as to clarify the upper limit of the storage capacity of the cache module and then determine the number of transformation relationships to be extracted in the initialization phase (i.e., the first number).

[0055] The first quantity is the number of consecutive transformation relationships extracted from the memory module and stored in the cache module during the initialization phase. It is used to determine the total number of transformation relationships loaded by the cache module during the initialization phase and directly affects the initial hit effect of the cache module after initialization. This first quantity needs to be set in conjunction with the cache depth threshold of the cache module.

[0056] Optionally, the first quantity is the same as the cache depth threshold. During the initial memory access, the system reads a number of consecutive video data conversion relationships from the memory module, matching the cache depth threshold, and fills the cache module with these relationships. This ensures the cache module is fully utilized during initialization, storing the maximum number of initial conversion relationships and providing more sufficient cached data support for subsequent address translations. For example, if the cache depth threshold of the cache module is 20, the first quantity can be set to 20. This means that during initialization, 20 consecutive conversion relationships are extracted from the memory module and stored in the cache module. In this case, the cache module's storage space is fully utilized, allowing the system to directly retrieve conversion relationships from the cache module for the first 20 address translation requests during initialization. This further reduces the probability of cache misses during the initial address translations after initialization and improves address translation efficiency.

[0057] In one optional embodiment, the cache depth threshold of the cache module is obtained by processing the acquired configuration input parameters according to a preset algorithm. The configuration input parameters include device configuration information, the average time of virtual address translation commands, and the time to search for and read the translation relationship from the memory module.

[0058] Here, the cache depth threshold of the cache module is not a fixed value, but a dynamic value obtained by calculating the collected configuration input parameters through a preset algorithm. This allows the cache depth threshold to adapt to different system operating environments and hardware conditions, ensuring that the storage capacity of the cache module matches the actual address translation requirements, and avoiding excessively large cache capacity leading to wasted chip area or excessively small capacity leading to increased cache miss probability.

[0059] For example, the preset algorithm can be a mathematical operation rule or logical processing flow used to calculate the cache depth threshold. This preset algorithm can transform multiple different types of configuration input parameters into specific cache depth threshold values. It can comprehensively consider the impact of each parameter on address translation efficiency, ensuring the reasonableness of the calculation result. For instance, the preset algorithm can be a weighted summation algorithm based on each configuration input parameter. For example, the weight of device configuration information can be set to 0.3, the weight of the average time of virtual address translation commands to 0.4, and the weight of the time to find and read the translation relationship from the memory module to 0.3. After standardizing each parameter, multiplying it by its corresponding weight, and then summing the results, the integer part of the sum is the cache depth threshold. Alternatively, it can be calculated based on the proportional relationship between parameters. For example, the cache depth threshold can be calculated by combining the ratio of the average time of virtual address translation commands to the time to read the translation relationship from the memory module with the maximum number of concurrent translation requests in the device configuration information.

[0060] The configuration input parameters include device configuration information, the average time of virtual address translation commands, and the time to find and read translation relationships from memory modules. These parameters reflect the system hardware characteristics and operating status, and can provide a calculation basis for the preset algorithm, ensuring that the calculation of the cache depth threshold can fit the actual system situation.

[0061] Specifically, device configuration information refers to hardware parameters related to system memory management. These may include the maximum supported video data bandwidth, maximum concurrent address translation requests, and memory module read / write speeds, reflecting the upper limit of the device's hardware capabilities and ensuring that the cache depth threshold does not exceed the device's hardware capacity. The average time for virtual address translation commands is the average time elapsed from when the system sends a virtual address translation command until the translation is completed. This reflects the processing efficiency of the address translation command itself. A longer time means more time a single translation consumes system resources; therefore, the cache depth threshold can be appropriately increased to reduce the frequent triggering of translation commands. The time to look up and read the translation relationship from the memory module is the average time elapsed from when the system initiates a read request to when it obtains the translation relationship from the memory module. This reflects the latency of memory access. A longer time means a greater impact of memory access on translation latency; therefore, the cache depth threshold needs to be increased to reduce the number of accesses to the memory module. The time to look up and read the translation relationship from the memory module may include memory address addressing time, data reading time, and data transfer time to the cache module.

[0062] In one optional embodiment, the cache depth threshold of the cache module is directly proportional to a specified time ratio, which refers to the ratio between the address sending time and the time to read a translation relationship from the memory module. The address sending time refers to the sum of the transmission time of a virtual address to the system memory management circuit, the hit time of the virtual address in the cache module of the system memory management circuit, and the time to convert the virtual address into a physical address.

[0063] Here, the specified time ratio is used to measure the relative relationship between address sending efficiency and memory read latency. The address sending time is the total time required to complete one virtual address to physical address translation (with the translation relationship being hit in the cache module), including the time for the virtual address to be transmitted to the system memory management circuit (i.e., address transmission time), the time for the virtual address to be hit in the cache module (i.e., cache lookup time), and the time for the virtual address to be converted into a physical address (i.e., address translation processing time). This time directly reflects the address translation efficiency when the cache module hits. The time to read a translation relationship from the memory module reflects the time spent obtaining the translation relationship when the cache module misses.

[0064] Specifically, the specified time ratio is calculated as: address sending time / time to read a translation relationship from the memory module. A larger specified time ratio indicates a longer address sending time relative to memory reading time. In this case, if a cache miss occurs, the additional memory reading time has a relatively small impact on the total translation latency. However, to avoid the accumulation of total latency due to the inherently long address sending time, the cache depth threshold still needs to be appropriately increased to reduce the number of cache misses. Conversely, a smaller specified time ratio indicates a longer memory reading time relative to address sending time. The additional latency when a cache miss occurs is more significant, thus requiring a larger cache depth threshold to improve the cache hit rate and reduce memory accesses. Since the cache depth threshold can be adjusted according to changes in the specified time ratio to adapt to different latency impacts, the cache depth threshold of the cache module is directly proportional to the specified time ratio, further optimizing address translation efficiency.

[0065] In step S102, when the second number of preceding transformation relationships among the first number of consecutive transformation relationships stored in the cache module are used up, the second number of consecutive transformation relationships are extracted from the memory module; wherein, the extracted second number of consecutive transformation relationships have a linear temporal progression relationship with the transformation relationships currently stored in the cache module.

[0066] In this step, the second number of preceding conversion relationships are the second number of conversion relationships that are ranked first in the order of use among the first number of consecutive conversion relationships stored in the cache module. When this part of the conversion relationships is used up, it indicates that some of the conversion relationships in the cache module no longer have a need for further use, and new conversion relationships need to be added.

[0067] Specifically, the second number of preceding transformation relations are the first-used parts of the first number of transformation relations. For example, when the first number is 20 and the second number is 10, the cache module initially stores 20 transformation relations AT0~AT0. 19 In the first 10 conversion relationships AT0 to AT9, there are two preceding conversion relationships. When the system processes an address translation request, it uses AT0 to AT9 in sequence. When AT9 is used up, it triggers the extraction of a new conversion relationship from the memory module.

[0068] Here, "used translation relationships" refers to translation relationships in the cache module that have been used to complete the corresponding virtual address to physical address translation, and there will be no further virtual address translation needs for a period of time. For example, if the system processes 10 virtual address translation requests consecutively, and uses the 10 translation relationships AT0 to AT9 in the cache module respectively, all subsequent virtual addresses to be processed will correspond to AT0. 10And the subsequent conversion relationships, at this point it can be determined that AT0 to AT9 have been used up, and there is no need to use these 10 conversion relationships to process the address conversion request of the current video frame.

[0069] Among them, the extracted second number of continuous conversion relationships have a linear temporal progressive relationship with the conversion relationships currently stored in the cache module. In other words, the newly extracted second number of continuous conversion relationships have a continuous and progressive temporal or address order relationship with the remaining conversion relationships in the cache module. Its function is to ensure that the newly added conversion relationships can be seamlessly connected with the remaining conversion relationships in the current cache, so as to meet the requirements of linear address conversion of video data.

[0070] For example, a linear temporal progression relationship can be represented as the sequential number of a newly extracted transformation relationship, which continuously increases with the maximum sequential number of the transformation relationship currently stored in the cache module. For instance, the transformation relationship currently stored in the cache module is AT. 10 ~AT 19 (That is, of the first 20 conversion relationships, the first 10 AT0~AT9 have been used up), then the second number (10) consecutive conversion relationships extracted from the memory module are AT 20 ~AT 29 AT 20 The sequential numbering follows AT 19 , forming AT 10 ~AT 19 ~AT 20 ~AT 29 The linear time progression relationship ensures that subsequent AT processing... 20 When making subsequent virtual address translation requests, the corresponding translation relationship can be retrieved from the cache.

[0071] In step S103, a cross-substitution strategy is used to replace the second number of consecutive transformation relationships extracted from the memory module with the second number of pre-transformation relationships that have been used up in the cache module.

[0072] In this step, the cross-replacement strategy refers to replacing the replacement rules of the second number of preceding transformation relationships that have been used up in the cache module with the newly extracted second number of consecutive transformation relationships. This ensures that the cache module always stores the latest required transformation relationships while maximizing the use of cache capacity, avoiding cache space waste, and ensuring a high hit rate for subsequent address translations.

[0073] Specifically, in the cross-replacement strategy, newly extracted transformation relationships are used to fill the space occupied by transformation relationships that have been used up and are no longer needed in the cache module. Both the number of replacements and the number of newly extracted relationships are the second number, achieving cyclical utilization of cache space. For example, the cache module may have AT0~AT9 (a total of 10, i.e., the second number is 10) preorder transformation relationships that have been used up, and the newly extracted transformation relationships from the memory module are AT... 20 ~AT 29 (Total 10), at this point, using a cross-replacement strategy, the storage locations occupied by AT0~AT9 in the cache module are replaced with AT. 20 ~AT 29 This makes the conversion relationship stored in the replaced cache module AT. 10 ~AT 19 (Original remaining portion) and AT 20 ~AT 29 (New replacement section) Ensures subsequent AT processing 10 ~AT 29 When a virtual address translation request is made, it can be hit in the cache module.

[0074] In one optional embodiment, step S103 specifically includes: after the second number of preceding conversion relationships stored in the cache module are used up, the next set of the second number of consecutive conversion relationships extracted from the memory module is used to replace the second number of preceding conversion relationships already used in the cache module; this process is repeated, with each set of the second number of consecutive conversion relationships extracted replacing the second number of preceding conversion relationships already used in the cache module, until all conversion relationships in the video data are stored in the cache module.

[0075] Here, the specific execution process of the cross-replacement strategy is a phased, cyclical replacement. First, the usage status of the second number of preceding translation relationships in the cache module needs to be monitored in real time. When the second number of preceding translation relationships is detected to be used up, the operation of extracting the next set of the second number of consecutive translation relationships from the memory module is immediately triggered. The newly extracted translation relationships must maintain a linear temporal progression relationship with the currently remaining translation relationships in the cache module to ensure the continuity of address translation. After extraction, the newly extracted translation relationships directly replace the used preceding translation relationships in the cache module, completing one replacement operation.

[0076] Afterward, the system continues to process address translation requests. When the latest second-order conversion relationships in the cache module (i.e., the second-order conversion relationships in the cache module after the last replacement) are used up, the above extraction and replacement process is triggered again. This process is repeated in a loop until all conversion relationships corresponding to the video data are stored and used in the cache module, that is, all virtual addresses of the video data are converted to physical addresses.

[0077] The first number is twice the second number. Setting the first number to twice the second number is an optimization design based on cache space utilization efficiency and address translation continuity. This ensures that there are always conversion relationships between the used part and the part to be used in the cache module. When the used part (i.e., the second number of preceding conversion relationships) is used up, the part to be used (also the second number of conversion relationships) can be put into use immediately. At the same time, there is sufficient time to extract new second number of conversion relationships from the memory module to replace them, avoiding address translation wait caused by missing conversion relationships in the cache module.

[0078] For example, if the second quantity is set to 8, then the first quantity is set to 16. During the initialization phase, the cache module stores 16 consecutive conversion relationships AT0~AT0. 15 The first 8 AT0~AT7 are the preorder conversion relationships to be used, and the last 8 AT8~AT7 are the preorder conversion relationships to be used. 15 These are the conversion relationships to be used later. When the system has used up AT0~AT7 (the second number of preceding conversion relationships), AT8~AT7 will still be in the cache. 15 This can be used to process the next 8 address translation requests. During the processing of these 8 requests, the system has ample time to retrieve the next set of 8 translation relationships (such as AT) from the memory module. 16 ~AT 23 ), and in AT8~AT 15 Replace AT0~AT7 before use to ensure that there are always enough translation relationships available in the cache module, achieve seamless address translation, further reduce translation latency, and make the cache space allocation more balanced, avoiding cache space waste or insufficiency.

[0079] For example, processing 50 transformation relationships AT0~AT 49 The video data is set to a first quantity of 16 (cache depth threshold of 16) and a second quantity of 8. During the initialization phase, the cache module stores AT0~AT0. 15 (16); After AT0~AT7 (8 preorder conversion relationships) are used up, retrieve AT from the memory module. 16 ~AT 23 (Next group of 8), replace AT0~AT7 in the cache module. At this time, the cache module stores AT8~AT7. 15 and AT 16 ~AT 23 Next, when AT8~AT 15 After use, extract AT. 24 ~AT 31 Replace AT8~AT 15 The cache module stores AT16 ~AT 23 and AT 24 ~AT 31 Continue the loop until AT 16 ~AT 23 After use, extract AT. 32 ~AT 39 Replace; AT 24 ~AT 31 After use, extract AT. 40 ~AT 47 Replace; AT 32 ~AT 39 After use, extract AT. 48 ~AT 49 (Although there are fewer than 8, this represents all remaining transformation relationships) Replace the preorder transformation relationships that have been used up, up to AT0~AT 49 All conversion relationships are stored and used in the cache module to complete the address conversion of the video data. The entire process is carried out through cyclical cross-replacement, which ensures the stability of the cache hit rate and avoids misses.

[0080] Secondly, embodiments of this application provide a system memory management circuit, including: a conversion decision module and a cache module; the cache module is used to store a first number of consecutive conversion relationships; the conversion decision module is used to execute, for example... Figure 3 The system memory management method described above.

[0081] The system memory management circuit provided in this application embodiment achieves efficient management of video data address translation through the collaborative work of the conversion decision module and the cache module.

[0082] Here, the main function of the caching module is to store a first number of consecutive conversion relationships. It can respond to conversion relationship lookup requests from the conversion decision module in a very short time. When the conversion decision module needs to perform address translation, it first retrieves the conversion relationship from the caching module. If a match is found, it is directly used for the translation, which can significantly shorten the translation time. Each conversion relationship occupies a fixed storage unit and is stored in a consecutive order for easy and fast lookup.

[0083] The conversion decision module is the control core of the system memory management circuit, and its function is to execute, for example, Figure 3The system memory management method specifically includes: during the initialization phase, controlling the extraction of a first number of consecutive conversion relationships from the memory module and sending them to the cache module for storage; real-time monitoring of the usage status of a second number of preceding conversion relationships in the cache module, and when it is detected that the conversion relationships have been used up, controlling the extraction of a new second number of consecutive conversion relationships from the memory module to ensure that the conversion relationships in the cache are linearly sequential; and controlling the execution of a cross-replacement strategy to replace the used preceding conversion relationships in the cache with the newly extracted conversion relationships.

[0084] In addition, if the calculation of the cache depth threshold is involved, the conversion decision module will also receive the cache depth threshold output by the register as the basis for determining the first quantity; if the first quantity is set to be twice the second quantity, the conversion decision module will set it according to the ratio and perform the extraction and replacement operations.

[0085] For example, when processing the address translation of certain video data, the translation decision module first receives the buffer depth threshold of 30 sent by the register (i.e., the first quantity is 30, and the second quantity is 15), and then controls the extraction of 30 consecutive translation relationships AT0~AT0 from the memory module during the first memory access. 29 The data is sent to the cache module for storage, completing the initialization; afterwards, the conversion decision module tracks AT0~AT0 in the cache module in real time. 14 The usage of (the second number of preorder transformation relations) when AT is detected 14 Once used, it is determined that the conversion relationship has been exhausted, and AT is immediately retrieved from the memory module. 30 ~AT 44 (Compared with AT in the current cache) 15 ~AT 29 (It proceeds in a linear time sequence), and controls the cache module to process AT0~AT 14 Replace with AT 30 ~AT 44 AT will continue to be monitored. 15 ~AT 29 The extraction and replacement operations are repeated as needed until all video data conversion relationships are processed. Throughout the process, the conversion decision module ensures that address conversion can be performed efficiently and with low latency through precise control of each step.

[0086] In one optional embodiment, the present application further includes: a register, which is used to perform calculations on the written configuration input parameters using a preset algorithm and output the cache depth threshold of the cache module; wherein, the configuration input parameters include device configuration information, the average time of virtual address translation commands, and the time to find and read the translation relationship from the memory module.

[0087] Specifically, the register is used to receive configuration input parameters written externally, process these parameters using a preset algorithm to obtain the cache depth threshold of the cache module, and output the threshold to the conversion decision module to provide a basis for the conversion decision module to determine the first quantity, ensuring that the first quantity matches the storage capacity of the cache module.

[0088] The register receives configuration input parameters including device configuration information, the average time of virtual address translation commands, and the time to find and read translation relationships from the memory module. The register must have the ability to temporarily store these parameters for processing. Specifically, the register integrates preset mathematical operation logic to standardize, weight, and perform proportional calculations on the received configuration input parameters, ultimately obtaining a specific cache depth threshold value. After the calculation, the register outputs the obtained cache depth threshold to the translation decision module. The translation decision module determines a first quantity based on this threshold and then performs subsequent translation relationship extraction and storage operations. Simultaneously, the register also has the ability to store the calculation results. If the configuration input parameters do not change during system operation, the register can continuously output the cache depth threshold without recalculation; if the parameters change, new parameters are rewritten, the register recalculates, and outputs a new cache depth threshold, ensuring that the cache depth threshold always adapts to the current system state.

[0089] Furthermore, embodiments of this application also include: a configuration path, which is used to collect configuration input parameters and write the collected configuration input parameters into a register.

[0090] Here, the configuration path can be a data acquisition and transmission channel, used to acquire configuration input parameters from inside or outside the system, such as device configuration information, the average time of virtual address translation commands, and the time to find and read the translation relationship from the memory module. The acquired parameters are then stably and accurately transmitted to the register, providing raw data support for the register operation cache depth threshold, thereby ensuring the accuracy of the cache depth threshold calculation.

[0091] For example, regarding device configuration information, the configuration path can connect to the system's hardware configuration register or device management module to directly read hardware parameters preset at the factory or dynamically updated during system operation, such as the maximum number of concurrent address translation requests supported by the device and the memory read / write rate configured by the memory controller. For the average time of virtual address translation commands, the configuration path can connect to the translation decision module or the system's performance monitoring module to collect the total time spent by the translation decision module processing virtual address translation commands over a period of time, divide it by the total number of translation commands, and obtain the average time. For the time to find and read translation relationships from the memory module, the configuration path can connect to the memory controller to collect the total time from the memory controller initiating a request to read the translation relationship to the data transmission to the cache module, and take the average of multiple collections as the final collection result.

[0092] After data acquisition, the configuration path can use the internal data transmission bus to write the three types of configuration input parameters into the designated storage unit of the register in a preset format, ensuring that the register can accurately receive and identify each parameter. If a configuration input parameter changes during system operation, the configuration path can monitor the change in real time, re-acquire the new parameter and write it into the register, triggering the register to recalculate the cache depth threshold, ensuring that the system always performs address translation management based on the latest parameters.

[0093] like Figure 4 and Figure 5 As shown, the conversion relationship AT0~AT0 is used to process 1MB video frames, corresponding to 256 4K pages. 255 Taking an example, the steps of the system memory management method in this application embodiment will be explained in conjunction with a specific scenario:

[0094] First, during the initialization phase, the system memory management circuit 400 collects configuration input parameters such as device configuration information, the average time of virtual address translation commands, and the time to find and read translation relationships from the memory module 500 through the configuration path 440. These parameters are written to register 430, which uses a preset algorithm to calculate the cache depth threshold of the cache module 420, which is 20 (i.e., the first quantity is 20). Subsequently, during the first memory access, the translation decision module 410 extracts 20 consecutive translation relationships AT0~AT0 from the memory module 500. 19 The data is then stored in the cache module 420 to complete the initialization process. At this point, the conversion relationships stored in the cache module 420 are AT0~AT0. 19 This prepares for subsequent address translation.

[0095] Next, the virtual address translation request for the 1M video frame is processed. The virtual addresses of the video frames are linearly distributed, so AT0~AT0 need to be used sequentially. 255The conversion relationship is determined. When address translation requests are processed continuously until the first 10 preceding conversion relationships AT0~AT9 out of the 20 conversion relationships stored in the cache module 420 are used up, it is determined that a new conversion relationship needs to be retrieved from the memory module 500. Since the virtual addresses of video data are linearly distributed, the newly retrieved conversion relationship needs to be compared with the remaining conversion relationships AT0~AT9 currently stored in the cache module 420. 10 ~AT 19 The transitions exhibit a linear, sequential relationship; therefore, the conversion decision module 410 extracts AT from the memory module 500. 20 ~AT 29 These 10 consecutive transformation relationships.

[0096] Finally, a cross-substitution operation is performed. Using the cross-substitution strategy, the transformation decision module 410 converts the 10 newly extracted transformation relationships AT... 20 ~AT 29 Replace the 10 used preceding transformation relationships AT0~AT9 in cache module 420. After the replacement, the transformation relationships stored in cache module 420 are AT 10 ~AT 19 and AT 20 ~AT 29 The system then continues to process address translation requests, when AT... 10 ~AT 19 When the AT is no longer needed, the conversion decision module 410 retrieves it from the memory module 500. 30 ~AT 39 Replace the used AT in cache module 420 10 ~AT 19 This process is repeated cyclically. Through this process, even if the cache depth of the cache module 420 is only 20 (far less than 256 total conversion relationships), it can ensure that all subsequent video virtual address conversion relationships can be hit in the cache module 420. This achieves address conversion with a very small cache capacity, and the conversion latency is only the time of a cache hit, which greatly reduces the conversion latency. At the same time, it avoids the cache miss problem caused by address crossing boundaries in the traditional cache replacement method, and reduces the cache area overhead of the chip.

[0097] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device 600 includes, as Figure 4 The system memory management circuit 400, memory 620, and bus 630 shown are connected. The system memory management circuit 400 communicates with the memory via the bus. The system memory management circuit 400 can perform actions such as... Figure 3The system memory management method shown can be found in the method implementation examples for details, which will not be repeated here.

[0098] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0100] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0102] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0103] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A system memory management method, applied to a system memory management circuit, characterized in that, include: Based on the pre-configured cache depth threshold of the cache module, a first number of consecutive conversion relationships of video data are read and stored in the cache module during the first memory access; wherein, the first number is the same as the cache depth threshold, and the conversion relationship refers to the relationship between the virtual address of the video data and the physical address; the cache depth threshold of the cache module is directly proportional to a specified time ratio, which is the ratio between the address sending time and the time to read a conversion relationship from the memory module, and the address sending time refers to the sum of the transmission time of a virtual address to the system memory management circuit, the hit time of the virtual address in the cache module of the system memory management circuit, and the time of conversion from virtual address to physical address; When the second number of preceding transformation relationships in the first number of consecutive transformation relationships stored in the cache module are used up, the second number of consecutive transformation relationships are extracted from the memory module; wherein, the extracted second number of consecutive transformation relationships have a linear temporal progressive relationship with the transformation relationships currently stored in the cache module; Using a cross-replacement strategy, a second number of consecutive transformation relationships extracted from the memory module are used to replace a second number of pre-sequence transformation relationships that have been exhausted in the cache module.

2. The method according to claim 1, characterized in that, The cache depth threshold of the cache module is obtained by processing the acquired configuration input parameters according to a preset algorithm. The configuration input parameters include device configuration information, the average time of virtual address translation commands, and the time to find and read the translation relationship from the memory module.

3. The method according to claim 1, characterized in that, The method of using a cross-replacement strategy to replace the second number of consecutive transformation relationships extracted from the memory module with the second number of pre-sequence transformation relationships that have been used up in the cache module includes: When the second number of preceding transformation relationships stored in the cache module are used up, the next set of the second number of consecutive transformation relationships extracted from the memory module will replace the second number of preceding transformation relationships that have been used up in the cache module. The process is repeated in sequence. For each set of a second number of consecutive transformation relationships, the second number of pre-sequence transformation relationships that have been used up in the cache module are cross-replaced until all transformation relationships in the video data are stored in the cache module.

4. The method according to claim 1, characterized in that, The first quantity is twice the second quantity.

5. A system memory management circuit, characterized in that, include: The conversion decision module and the caching module; The cache module is used to store a first number of consecutive transformation relationships; The conversion decision module is used to execute the system memory management method as described in any one of claims 1 to 4.

6. The circuit according to claim 5, characterized in that, Also includes: The register is used to process the written configuration input parameters using a preset algorithm and output the cache depth threshold of the cache module; wherein, the configuration input parameters include device configuration information, the average time of virtual address translation commands, and the time to find and read the translation relationship from the memory module.

7. The circuit according to claim 6, characterized in that, Also includes: A configuration path is configured to collect configuration input parameters and write the collected configuration input parameters into a register.

8. An electronic device, characterized in that, include: The system memory management circuit, memory, and bus as described in any one of claims 5 to 7, wherein the system memory management circuit communicates with the memory via a bus.

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