FPGA-based i3c master-slave device communication system

Abstract

The application provides an FPGA-based I3C master-slave device communication system, a user end of which comprises: a user end interface comprising an input data channel and an output data channel; a register module in communication connection with the user end interface, for writing input data into an internal register of the register module according to a data bit of the input data channel in response to an input command of the input data channel; for extracting output data from the internal register and transmitting the output data to the output data channel in response to an output command of the output data channel; and a state machine module comprising a plurality of state machines, for changing a current state of the state machines in response to a change in data in the register module, and for coordinating read and write operations of the internal register.The application realizes a complex I3C protocol through a simplified user end interface and a state machine and a register, optimizes the convenience of read and write operations of I3C master-slave devices, improves communication efficiency and quality, and improves user experience.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to an I3C master-slave device communication system based on FPGA. Background Technology

[0002] The I3C (Improved Inter-Integrated Circuit) protocol is a new sensor bus protocol designed to address the limitations of I2C and SPI protocols in terms of low power consumption, high performance, and high integration. While maintaining compatibility with I2C, I3C introduces many new features, such as Dynamic Address Allocation (DAA), High-Speed ​​Data Transfer (HDR), and advanced power management. I3C was initially designed to create a single interface for mobile devices capable of using multiple sensors. As modern mobile devices have increased the number of sensors and demanded higher performance, I2C and SPI have reached their limits. I3C was developed to solve this problem, allowing more sensor devices to be supported on a single mainline without adding extra logic signals to support interrupts or sleep modes. I3C can provide faster transmission rates with lower power consumption, a benefit not only to mobile devices but also to other embedded devices, such as wearable devices that require multiple sensors within limited physical space and lower power consumption. However, the current I3C internal protocol is complex regarding dynamic address allocation, interrupt arbitration, and CCC command protocol, requiring users to have specialized knowledge to use it. Even getting started with the basic I3C protocol is complicated. Summary of the Invention

[0003] This application discloses an FPGA-based I3C master-slave device communication system. It implements the complex I3C protocol through a simplified user interface, state machine, and registers, which improves the convenience of reading and writing operations of I3C master-slave devices, enhances communication efficiency and quality, and improves user experience.

[0004] Other objectives and advantages of this application can be further understood from the technical features disclosed herein.

[0005] To achieve one or more of the above objectives or other objectives, in a first aspect, this application provides an FPGA-based I3C master-slave device communication system, including a bus terminal and a user terminal, wherein the user terminal includes: a user terminal interface, including an input data channel and an output data channel;

[0006] The register module is communicatively connected to the user terminal interface. In response to the input command of the input data channel, it writes the input data into the internal register of the register module according to the data bits of the input data channel; in response to the output command of the output data channel, it extracts the output data from the internal register and transmits it to the output data channel.

[0007] The state machine module includes multiple state machines, which change the current state of the state machines in response to changes in the data in the register module, and coordinate the read and write operations of the internal registers.

[0008] As an optional embodiment, both the input data channel and the output data channel are 16-bit wide, the 16-bit width including read / write control bits, address bits and data bits, the read / write control bits being the most significant bit

[15] , the address bits being the middle bits [14:8], and the data bits being the least significant bits [7:0].

[0009] As an optional embodiment, the system includes an I3C host, which is used to determine the register address allocated to the internal register of the register module; when the read / write control bit is a write command, the I3C host writes the data of the data bit into the internal register corresponding to the register address.

[0010] As an optional embodiment, the I3C commands, addresses, and data in a row of the input data channel interact with each other: if a row of the input data channel contains only commands and data, a broadcast write is performed; if a row of the input data channel contains commands, addresses, and data, a direct write is performed; if a row of the input data channel contains only commands and addresses, a direct read is performed; if a row of the input data channel contains only addresses, data, and a special identifier, and

[15] is 0, a special write is performed; if a row of the input data channel contains only addresses and a special identifier, and

[15] is 1, a special read is performed; the I3C commands, addresses, and data in different rows of the input data channel are independent of each other.

[0011] As an optional embodiment, the internal registers include a data register for storing data, a flag register for recording the state of the state machine, and a setting register for initialization settings; the data register automatically identifies and classifies the data according to the current state of the state machine and stores the data in the corresponding registers.

[0012] As an optional embodiment, the state machine's state types include at least: start state, broadcast state, directed state, dedicated state, dynamically allocated state, interrupted state, and stopped state;

[0013] The start state includes idle state, start, and start delay;

[0014] The broadcast status includes broadcast address, broadcast address response, broadcast common command, broadcast restart, and broadcast data;

[0015] The directed status includes directed public command, directed first restart, I3C address, I3C address write response, I3C address read response, directed write data, directed read data, and directed restart;

[0016] The dedicated state includes I3C slave device address, I3C slave device write address response, I3C slave device read address response, dedicated message write data, dedicated message read data, and dedicated message restart;

[0017] The dynamic allocation status includes dynamic allocation of read data, dynamic allocation of write address, dynamic allocation of write address acknowledgment, dynamic allocation of restart, dynamic allocation of read address, and dynamic allocation of read address acknowledgment.

[0018] The interrupt status includes interrupt start, interrupt read address, interrupt acknowledge, and interrupt write data;

[0019] The stopped state includes being stopped.

[0020] As an optional embodiment, the state transition of the dedicated message restart includes: a transition from the slave device write address response, I3C slave device read address response, dedicated message write data, dedicated message read data, broadcast data, broadcast address response, broadcast common command to the dedicated message restart, and a transition from the dedicated message restart to the I3C slave device address.

[0021] As an optional embodiment, the broadcast address response, the directed public command, and the directed first restart have sequential state transition logic;

[0022] The state transition for the first targeted restart also includes a jump to the I3C address;

[0023] The state transitions of the I3C address include independent transitions to I3C address write acknowledgments and transitions to I3C address read acknowledgments.

[0024] As an optional embodiment, the interrupt response state transition includes: a transition from interrupt response to interrupt write data, a transition to stop, and a transition to idle state; the transition logic for interrupt write data is a transition to stop state.

[0025] As an optional embodiment, the bus terminal includes: a bus SDA control module, configured to receive SDA data from the bus, and upon receiving the SDA data, trigger a change in the state of the state machine and store the SDA data in the register module; when the state machine is in an output state, the bus SDA control module sends the SDA data from the register module to the bus terminal output port;

[0026] The bus SCL control module is used to control the SCL signal and synchronously control the transmission and recovery of the SDA data.

[0027] The aforementioned FPGA-based I3C master-slave device communication system has at least the following beneficial effects: 1) By implementing the I3C protocol through a simplified user interface, state machine, and registers, it optimizes the convenience of I3C master-slave device read / write operations, improves communication efficiency and quality, and enhances user experience; 2) By designing the data bit width and the meaning of different bits, it optimizes the efficiency and accuracy of data transmission, covering user needs and allowing input of corresponding instructions through table lookup, further improving the efficiency of writing / reading internal registers from a user interface; 3) Optimizing the state machine module and jump logic avoids infinite loop problems caused by bus instability or interference signals, improving communication efficiency and quality. To make the above and other objects, features, and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a block diagram of the host structure of the FPGA-based I3C master-slave device communication system of this application.

[0030] Figure 2 This is a block diagram of the slave device structure of the FPGA-based I3C master-slave device communication system of this application. Figure 3 This is a schematic diagram of the logical structure of state transitions in the state machine module of this application. Detailed Implementation

[0031] The foregoing and other technical contents, features, and effects of this application will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a method of distinguishing objects with the same attributes in the embodiments of this application.

[0032] refer to Figure 1 and Figure 2 This application provides an FPGA-based I3C master-slave device communication system, including a bus terminal and a user terminal. The user terminal includes a user terminal interface, a register module, and a state machine module. The bus terminal includes a bus SDA control module and a bus SCL control module. The communication system includes an I3C master device and an I3C slave device.

[0033] The user-end interface includes independent input and output data channels. Specifically, the user-end interface input consists of an enable signal and an input data channel, while the output consists of an enable signal, an output data channel, and an interrupt signal, facilitating easy connection to other devices or modules. The bus is designed according to the I3C protocol. The master device has a push-pull mode output SCL (Serial Clock) and a push-pull mode output / input SDA (Serial Data), while the slave device has an input SCL and an open-drain mode output / input SDA. For example, configuration commands can be input through the user-end interface to send or read CCC commands and data. The enable signal is low by default; a high enable signal indicates that the command input through the data channel is valid.

[0034] The register module is bidirectionally connected to the user interface. In response to input commands from the input data channel, it writes input data into the internal register of the register module according to the data bits of the input data channel. In response to output commands from the output data channel, it extracts output data from the internal register and transmits it to the output data channel. The host user can query the current status of each slave device through the registers (including but not limited to the slave device's PID, BCR, DCR, dynamic address, and received data) to monitor for errors on the bus in real time.

[0035] The state machine module includes multiple state machines, which change the current state of the state machine in response to changes in the data (i.e., register values) in the register module, and coordinate the read and write operations of the internal registers.

[0036] The FPGA-based I3C master-slave device communication system of this application design features an independent input and output data channel for the user-end interface. The register module directly connects to the user-end interface. Data input from the user-end is first stored in the register module, and data output from the user-end is also extracted from the register module before being transmitted to the user-end output interface. Furthermore, the state machine changes its current state based on changes in register values, coordinating the read and write operations of internal registers to achieve efficient and reliable data communication. This optimizes the convenience of I3C master-slave device read and write operations, improves communication efficiency and quality, and enhances the user experience.

[0037] Furthermore, both the input data channel and the output data channel are 16 bits wide. The 16-bit width includes read / write control bits, address bits, and data bits. The read / write control bits are the most significant bit

[15] , the address bits are the middle bits [14:8], and the data bits are the least significant bits [7:0]. When the most significant bit

[15] is 1, it indicates a read command; when the most significant bit

[15] is 0, it indicates a write command. The I3C host is used to determine the register address allocated to the internal register of the register module; when the read / write control bit is a write command, the I3C host writes the data of the data bits into the internal register corresponding to the register address. For example: input data channel in_data=16'b0_0001111_00010001 means writing data 8'b00010001 to address 7'b0001111; in_data=16'b1_0001111_00000000 means reading data to address 0x0001111. The data will be output through output data channel out_data, which is the data just written, 16'b1_0001111_00010001. When the enable signal out_data_rdy of the output data channel is a rising edge, it means that the data is valid.

[0038] In some embodiments, when the I3C host executes a command, the corresponding I3C command, address, and data are first written to the host and then the start flag signal is pulled high. If a special command is to be executed, the special flag signal is pulled high before the start flag signal is pulled high. The I3C command, address, and data in a row of the input data channel interact with each other: if a row of the input data channel contains only command and data, a broadcast write is performed; if a row of the input data channel contains command, address, and data, a direct write is performed; if a row of the input data channel contains only command and address, a direct read is performed; if a row of the input data channel contains only address, data, and special identifier, and

[15] is 0, a special write is performed; if a row of the input data channel contains only address and special identifier, and

[15] is 1, a special read is performed. The I3C command, address, and data in different rows of the input data channel are independent of each other. Only one row of I3C command, address, and data is sent in one process. If there is more content later, the next process will start after restarting; otherwise, it will stop.

[0039] In some embodiments, the register module includes a data register for storing data, a flag register for recording the state machine's state, and a setting register for initialization settings. The data register automatically identifies and classifies data according to the current state of the state machine, storing the data in the corresponding register. Specifically, the data register stores input / output data and stores it in different registers based on the current state of the state machine, automatically identifying continuous data as CCC command data, address data, host information data, slave information data, etc. Through automatic classification, users can easily retrieve the desired data directly through the user interface. The flag register records current system state information, such as error loggers, data reception success registers, data transmission completion registers, and interrupt request registers. Users can directly query the flag registers through the user interface to determine the current system state, facilitating subsequent operations. The setting register is used for system initialization settings, such as setting the clock frequency, preset dynamic address size, setting parity correction, and enabling interrupt response.

[0040] Furthermore, as the central hub of the entire system, the state machine module, in order to improve the stability, smoothness and efficiency of the system's operation according to the state machine process, includes at least the following state types: start state, broadcast state, directed state, dedicated state, dynamically allocated state, interrupted state, and stopped state.

[0041] Specifically, each state category has its own sub-states, totaling 33 states. The detailed state machine transitions are as follows: Figure 3As shown, the state machine for the start state includes: Idle state, Start, and Start delay, used for the initialization of the state machine. The state machine for the broadcast state includes: Broadcast address, Broadcast address acknowledgment, Broadcast common command, Broadcast restart, and Broadcast data, used by the master device to send general instructions to all slave devices. The state machine for the directed state includes: Directed common command, Directed first restart, I3C address, I3C address write acknowledgment, I3C address read acknowledgment, Directed write data, Directed read data, and Directed restart, used by the master device for one-to-one communication with a specific slave device to avoid bus conflicts, such as reading and writing data. The state machine for the dedicated state includes: I3C slave device address, I3C slave device write address acknowledgment, I3C slave device read address acknowledgment, Dedicated message write data, Dedicated message read data, and Dedicated message restart, used for dedicated states that only respond to specific commands or events, enhancing security. The state machine for dynamically allocated states includes: dynamically allocated read data, dynamically allocated write address, dynamically allocated write address acknowledgment, dynamically allocated restart, dynamically allocated read address, and dynamically allocated read address acknowledgment. This is used by the master device to assign a unique address to newly connected slave devices to support hot-swapping and flexible expansion. The state machine for interrupt states includes: interrupt initiation, interrupt read address, interrupt acknowledgment, and interrupt write data. This is used by slave devices to actively preempt the bus to trigger emergency events, achieving real-time response and replacing the performance bottleneck of polling mechanisms, avoiding problems such as low real-time performance, high resource consumption, and low efficiency. The state machine for stopped states includes: stop, used to terminate the state machine, indicating the end of the process or resource release, preventing invalid operations or continued execution. The interrupt states are used to detect status signals and, in response to abnormal status signals, control state transitions.

[0042] It should be noted that, Figure 3 The transition directions of the state machine shown are indicated by the arrows in the diagram, and will not be elaborated upon here. This application Figure 3The state machine shown differs from existing state machines in that: (1) it has an additional dedicated message restart state and corresponding state transitions. Specifically, the dedicated message restart state machine is used to monitor the transmission and execution status of signals such as I3C slave address write response, I3C slave address read response, dedicated message write data, dedicated message read data, broadcast data, broadcast address response, and broadcast common command. When erroneous data or state machine jamming is detected, it jumps to the dedicated message restart state to interrupt the infinite loop state and jumps to the state machine of the I3C slave address to re-execute the corresponding command. This design prevents the state machine from jamming when receiving erroneous data due to interference such as glitches on the bus, thus improving the clarity, smoothness, and completeness of the state machine control logic. (2) Unlike the existing state transition logic of directed public commands and subsequent states, specifically, after the directed public command state, it transitions to the directed first restart state. The state transition logic of the directed first restart includes a transition to the I3C address and a transition to the broadcast address response. Furthermore, the state transition logic of the I3C address includes independent transitions to the I3C address write response and to the I3C address read response. Thus, the directed write data and the directed read data are performed independently. This design avoids the problem of read and write operations being easily reversed or incorrect and unclear due to interference signals, further improving the accuracy of read and write operations. (3) The state transition logic of the directed write data and the directed read data includes: a transition to directed restart and a transition to stop. The transition logic of the directed restart is a transition to the broadcast address, thereby avoiding infinite loops and deadlocks in read and write operations. (4) The interrupt response state transition logic includes: transition to interrupt write data, transition to stop, and transition to idle state. The interrupt write data state transition logic is a transition to stop state, thereby avoiding the problem of high CPU usage and slow response speed caused by frequent loop operations, and avoiding message delay and dead loop problems, thus improving resource efficiency and real-time performance.

[0043] In some embodiments, the bus terminal includes a bus SDA control module and a bus SCL control module. The bus SDA control module receives SDA data from the bus and, upon receiving SDA data, triggers a state change in the state machine, storing the SDA data in the register module. When the state machine is in an output state, the bus SDA control module sends the SDA data from the register module to the bus terminal output port. The bus SCL control module controls the SCL signal, synchronously controlling the transmission and recovery of the SDA data.

[0044] The bus SCL control module includes a master bus SCL module and a slave bus SCL module. The master bus SCL module is used to send the bus terminal output SCL signal, and the slave bus SCL module is used to receive the bus terminal input SCL signal. The SCL signal is used to synchronously send and recover SDA data.

[0045] In some embodiments, the communication system operates on a 12.5MHz bus clock and a 50MHz system clock, performing system operations at 4x the clock speed. Upon receiving data, it can stably store the data within two clock cycles, and then respond and prepare for subsequent data transmission or retrieval within another two clock cycles. Simultaneously, the I3C master is also compatible with I2C mode and can communicate with I2C devices on the bus. The default I2C bus speed is 400K, which can be adjusted via configuration registers. Furthermore, the I3C slave is isolated; it will not respond upon receiving I2C information to avoid interfering with bus timing.

[0046] In summary, the FPGA-based I3C master-slave device communication system described in this application: 1) Implements the I3C protocol through a simplified user interface, state machine, and registers, optimizing the convenience of I3C master-slave device read / write operations, improving communication efficiency and quality, and enhancing user experience; 2) Optimizes data transmission efficiency and accuracy by designing data bit width and different bit meanings, covering user needs while allowing input of corresponding instructions via table lookup, further improving the efficiency of writing / reading internal registers from a single user interface, simplifying the management of multiple slave devices and reducing user learning difficulty, with high scalability to adapt to future development needs; 3) Optimizes the state machine module and jump logic to avoid dead loop problems caused by bus instability or interference signals, improving communication efficiency and quality. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims. It should be understood that certain features of this disclosure described in the context of individual embodiments for clarity may also be provided in combination in a single embodiment. Conversely, the various features of this disclosure described in the context of a single embodiment for clarity may also be provided individually or in any suitable combination or as part of any other described embodiment of this disclosure.

Claims

1. An FPGA-based I3C master-slave device communication system, comprising a bus end and a user end, characterized in that, The user terminal comprises a user terminal interface including an input data channel and an output data channel; a register module, in communication connection with the user terminal interface, for writing input data into an internal register of the register module according to data bits of the input data channel in response to an input command of the input data channel, and for extracting output data from the internal register and transmitting the output data to the output data channel in response to an output command of the output data channel; a state machine module including a plurality of state machines, for changing a current state of the state machines in response to a change in data in the register module, and for coordinating read and write operations of the internal register; the state of the state machines includes at least a broadcast state, a directional state, and a dedicated state; the broadcast state includes broadcast address response, broadcast public command, and broadcast data; the directional state includes directional first restart, I3C address, I3C address write response, and I3C address read response; and the dedicated state includes I3C slave address, I3C slave write address response, I3C slave read address response, dedicated message write data, dedicated message read data, and dedicated message restart; state jumps of the dedicated message restart include jumps from the I3C slave write address response, I3C slave read address response, dedicated message write data, dedicated message read data, broadcast data, broadcast address response, broadcast public command to the dedicated message restart, and a jump from the dedicated message restart to the I3C slave address; state jumps of the directional first restart include a jump to the I3C address; and state jumps of the I3C address include independent jumps to the I3C address write response and the I3C address read response.

2. The FPGA-based I3C master-slave communication system according to claim 1, wherein, The input data channel and the output data channel are both 16-bit wide, and the 16-bit wide includes read-write control bits, address bits, and data bits, the read-write control bits are the highest bit [15], the address bits are the middle bit [14:8], and the data bits are the low bit [7:0].

3. The FPGA-based I3C master-slave communication system of claim 2, wherein, The system includes an I3C host for determining a register address allocated to an internal register of the register module; and the I3C host writes data of the data bits into the internal register corresponding to the register address in response to the read-write control bits being a write command.

4. The FPGA-based I3C master-slave communication system of claim 2, wherein, I3C commands, addresses, and data in a row of the input data channel interact with each other: if only commands and data are present in a row of the input data channel, broadcast write is performed; if commands, addresses, and data are all present in a row of the input data channel, direct write is performed; if only commands and addresses are present in a row of the input data channel, direct read is performed; if only addresses, data, and a dedicated identifier are present in a row of the input data channel, and [15] is 0, dedicated write is performed; if only addresses and a dedicated identifier are present in a row of the input data channel, and [15] is 1, dedicated read is performed; and I3C commands and addresses, and data in different rows of the input data channel are irrelevant to each other.

5. The FPGA-based I3C master-slave communication system of claim 1, wherein, The internal register includes a data register for storing data, a flag register for recording the state of the state machine, and a setting register for initialization setting; the data register automatically identifies and classifies data according to the current state of the state machine, and stores the data into the corresponding register.

6. The FPGA-based I3C master-slave communication system of claim 1, wherein, The state of the state machine further includes a start state, a dynamic allocation state, an interruption state, and a stop state. The start state includes an idle state, a start, and a start delay. The broadcast state further includes a broadcast address and a broadcast restart. The directional state further includes a directional public command, directional write data, directional read data, and directional restart. The dynamic allocation state includes dynamic allocation read data, dynamic allocation write address, dynamic allocation write address response, dynamic allocation restart, dynamic allocation read address, and dynamic allocation read address response. The interruption state includes an interruption start, an interruption read address, an interruption response, and an interruption write data. The stop state includes a stop.

7. The FPGA-based I3C master-slave communication system of claim 6, wherein, The broadcast address response, the directional public command, and the directional first restart have sequential state jump logic.

8. The FPGA-based I3C master-slave communication system of claim 6, wherein, The state jump of the interruption response includes a jump from the interruption response to the interruption write data, a jump to the stop, and a jump to the idle state; the jump logic of the interruption write data is a jump to the stop state.

9. The FPGA-based I3C master-slave communication system of claim 1, wherein, The bus end includes a bus SDA control module for receiving SDA data of the bus, triggering a state change of the state machine when the SDA data is received, and storing the SDA data into the register module; when the state of the state machine is an output state, the bus SDA control module sends the SDA data of the register module to a bus end output port; and a bus SCL control module for controlling the SCL signal and synchronously controlling the sending and recovery of the SDA data.

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