A timing adjustment apparatus, method, high bandwidth memory and chip

Abstract

The application discloses a timing adjustment device, method, high-bandwidth memory and chip, the device comprises a delay determination circuit and a delay adjustment circuit; the delay determination circuit is used for outputting a preset delay value and receiving a phase feedback signal of DRAM; after determining a metastable signal from the phase feedback signal, a flip point is determined based on the metastable signal; the target delay value is determined and output according to the flip point; the delay adjustment circuit is used for adjusting the phase of the write data gate signal multiple times according to the received preset delay value, and sending the write data gate signal after each adjustment to the DRAM; after receiving the target delay value, the phase of the write data gate signal after the last adjustment is adjusted according to the target delay value, and the target write data gate signal is output. Therefore, the flip point is more accurately judged based on the delay determination circuit and the delay adjustment circuit, the misjudgment caused by jitter or glitch is avoided, and then the accurate writing of data of the DRAM based on the target write data gate signal is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chips, in particular to a timing adjustment device, method, high-bandwidth memory and chip. BACKGROUND

[0002] In the design of DRAM (Dynamic Random Access Memory), the timing of the CK clock signal and the WCK write data clock has a deviation, which may cause inaccurate data writing or reading, and further affect the stability of the system. Therefore, the phase of the WCK needs to be adjusted so that the rising edge of the WCK is aligned with the effective window of the CK, thereby ensuring the stable writing of data.

[0003] In actual application, the DRAM compares the edges of the CK and the WCK to obtain a comparison result, feeds back the comparison result to the controller, and the controller gradually adjusts the delay value of the WCK according to the feedback result until the turning point is found, so as to change the phase of the WCK based on the delay value corresponding to the turning point. However, this method has low accuracy in a high-noise scene, and is prone to misjudgment of the turning point due to jitter or glitches, thereby failing to ensure accurate data writing. SUMMARY

[0004] The present application provides a timing adjustment device, method, high-bandwidth memory and chip to solve the problem of low accuracy in a high-noise scene in the prior art, and the turning point is prone to misjudgment due to jitter or glitches, thereby failing to ensure accurate data writing.

[0005] In a first aspect, the present application provides a timing adjustment device, comprising a delay determination circuit and a delay adjustment circuit.

[0006] The delay determination circuit is configured to output a preset delay value, receive a phase feedback signal sent by a DRAM, determine a metastable state signal representing the existence of a level signal flip from the phase feedback signal, determine a turning point based on the metastable state signal, determine a target delay value according to the turning point, and output the target delay value.

[0007] The delay adjustment circuit is configured to adjust the phase of a write data gate signal multiple times according to the received preset delay value, send the write data gate signal after each adjustment to the DRAM, so that the DRAM outputs the phase feedback signal after receiving the adjusted write data gate signal, adjust the phase of the write data gate signal after the last adjustment according to the target delay value after receiving the target delay value, output a target write data gate signal, and send the target write data gate signal to the DRAM, so that the DRAM writes data based on the target write data gate signal.

[0008] In a possible implementation, the turning points include a first turning point and a second turning point.

[0009] The delay determination circuit is specifically configured to:

[0010] sample each received first phase feedback signal to obtain a first sampling signal corresponding to the first phase feedback signal after outputting a preset delay value for forward adjustment of a write data strobe signal, determine a first metastable state signal from a plurality of first sampling signals, determine the first turning point in the first metastable state signal, sample each received second phase feedback signal to obtain a second sampling signal corresponding to the second phase feedback signal after outputting a preset delay value for reverse adjustment of the write data strobe signal, determine a second metastable state signal from a plurality of second sampling signals, determine the second turning point in the second metastable state signal, and take an average of a first delay value corresponding to the first turning point and a second delay value corresponding to the second turning point as the target delay value.

[0011] In a possible implementation, the delay determination circuit includes a sampling register, a sampling decision circuit, and a result processing unit.

[0012] The sampling register is configured to perform a sampling operation on a received phase feedback signal and output a plurality of sampling signals to the sampling decision circuit.

[0013] The sampling decision circuit is configured to perform first logic processing on a received sampling signal, output a first decision signal for indicating whether the sampling signal is a stable state signal or a metastable state signal, and perform second logic processing on the sampling signal, output a second decision signal.

[0014] The result processing unit is configured to output the preset delay value, determine a turning point based on the second decision signal in a case where a first decision signal indicating that the sampling signal is a metastable state signal is received, determine a target delay value according to the turning point, and output the target delay value.

[0015] In a possible implementation, an input end of the sampling register is an input end of the delay determination circuit, and an output end of the sampling register is electrically connected to an input end of the sampling decision circuit.

[0016] A first output end of the sampling decision circuit and a second output end of the sampling decision circuit are electrically connected to the result processing unit.

[0017] An output end of the result processing unit is an output end of the delay determination circuit.

[0018] In a possible implementation, the delay determination circuit further includes a sampling width configuration unit.

[0019] The sampling width configuration unit is configured to configure the width of the sampling register.

[0020] In a possible implementation, the sampling decision circuit includes a first AND gate circuit, an OR gate circuit, and a second AND gate circuit.

[0021] The first AND gate circuit is configured to perform logical AND processing on the sampling signal to obtain a first processing signal; the OR gate circuit is configured to perform logical OR processing on the sampling signal to obtain a second processing signal; and the second AND gate circuit is configured to perform logical AND processing on the sampling signal except for the lowest bit to obtain the second decision signal.

[0022] The first processing signal and the second processing signal are spliced to obtain the first decision signal.

[0023] In a possible implementation, the input end of the sampling decision circuit is electrically connected to the input end of the first AND gate circuit, the input end of the OR gate circuit, and the input end of the second AND gate circuit respectively.

[0024] The output end of the first AND gate circuit and the output end of the OR gate circuit are electrically connected to the first output end of the sampling decision circuit.

[0025] The output end of the second AND gate circuit is electrically connected to the second output end of the sampling decision circuit.

[0026] In a second aspect, an embodiment of the present application provides a timing adjustment method, applied to the timing adjustment apparatus of any one of the first aspect, and the method includes the following steps.

[0027] The phase of the write data strobe signal is adjusted multiple times according to a preset delay value, the write data strobe signal after each adjustment is sent to a DRAM, and a phase feedback signal sent by the DRAM is received;

[0028] After a metastable state signal used to represent that there is a level signal flip is determined from the phase feedback signal, a flip point is determined based on the metastable state signal.

[0029] A target delay value is determined according to the flip point.

[0030] The phase of the write data strobe signal after the last adjustment is adjusted according to the target delay value, a target write data strobe signal is output, and the target write data strobe signal is sent to the DRAM, so that the DRAM performs data writing based on the target write data strobe signal.

[0031] In a possible implementation, the turning points include a first turning point and a second turning point.

[0032] The target delay value is determined according to the turning points, including:

[0033] The average of the first delay value corresponding to the first turning point and the second delay value corresponding to the second turning point is taken as the target delay value.

[0034] The first phase feedback signal is sampled to obtain a first sampling signal corresponding to the first phase feedback signal, and a first metastable signal is determined from a plurality of first sampling signals, and the first turning point is determined in the first metastable signal.

[0035] The second phase feedback signal is sampled to obtain a second sampling signal corresponding to the second phase feedback signal, and a second metastable signal is determined from a plurality of second sampling signals, and the second turning point is determined in the second metastable signal.

[0036] In a possible implementation, the first metastable signal is determined from the plurality of first sampling signals, including:

[0037] The first metastable signal is determined by performing logical AND and logical OR processing on each of the first sampling signals.

[0038] The second metastable signal is determined from the plurality of second sampling signals, including:

[0039] The second metastable signal is determined by performing logical AND and logical OR processing on each of the second sampling signals.

[0040] In a third aspect, an embodiment of the present application provides a high-bandwidth memory, including the timing adjustment device according to any one of the first aspect and a DRAM connected with the timing adjustment device.

[0041] In a fourth aspect, an embodiment of the present application provides a chip, including the high-bandwidth memory according to the third aspect.

[0042] The present application has the following advantages:

[0043] The embodiment of the application provides a timing adjustment device, method, high-bandwidth memory and chip, the timing adjustment device comprises a delay determination circuit and a delay adjustment circuit; the delay determination circuit is used for outputting a preset delay value, receiving a phase feedback signal sent by DRAM; after determining a metastable state signal for representing that a level signal flips from the phase feedback signal, determining a flip point based on the metastable state signal; determining a target delay value according to the flip point, and outputting the target delay value; the delay adjustment circuit is used for adjusting the phase of a write data gate signal multiple times according to the received preset delay value, and sending the write data gate signal after each adjustment to the DRAM, so that the DRAM outputs the phase feedback signal after receiving the adjusted write data gate signal; after receiving the target delay value, adjusting the phase of the write data gate signal after the last adjustment according to the target delay value, outputting the target write data gate signal, and sending the target write data gate signal to the DRAM, so that the DRAM writes data based on the target write data gate signal. Therefore, the flip point is more accurately judged based on the delay determination circuit and the delay adjustment circuit, the misjudgment of the flip point caused by jitter or glitch is avoided, and then the accurate writing of data by the DRAM based on the target write data gate signal is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0045] Fig. 1(a) is a flow diagram of a timing adjustment method in the related art provided by the application embodiment;

[0046] Fig. 1(b) is a flow diagram of another timing adjustment method in the related art provided by the application embodiment;

[0047] Figure 2 Fig. 1(b) is a flow diagram of another timing adjustment method in the related art provided by the application embodiment;

[0048] Figure 3 Fig. 1(b) is a flow diagram of another timing adjustment method in the related art provided by the application embodiment;

[0049] Figure 4 Fig. 1(b) is a flow diagram of another timing adjustment method in the related art provided by the application embodiment;

[0050] Figure 5 Fig. 1(b) is a flow diagram of another timing adjustment method in the related art provided by the application embodiment;

[0051] Figure 6Another structure schematic diagram of a timing adjustment device provided by an embodiment of the present application is shown in the figure.

[0052] Figure 7 A flowchart of a timing adjustment method provided by an embodiment of the present application is shown in the figure.

[0053] Figure 8 A complete flowchart of a timing adjustment method provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0055] Some technical terms related to the present application will be explained first.

[0056] 1) DRAM (Dynamic Random Access Memory): DRAM is one of the main memory types in modern computer systems, which provides temporary storage of programs and data.

[0057] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying sequence.

[0058] In the design of DRAM, the timing of the CK clock signal and the WCK write data clock has a deviation, which may cause inaccurate data writing or reading, and thus affect the stability of the system. Therefore, the delay of WCK needs to be adjusted so that the rising edge of WCK is aligned with the effective window of CK, thereby ensuring stable data writing.

[0059] The turning point is a critical point for representing that the timing of CK and WCK can accurately perform data writing. Therefore, in the related art, the first adjustment delay value of WCK is determined by determining the turning point, which mainly compares the edges of CK and WCK by DRAM, obtains a comparison result, feeds back the comparison result to a controller, and the controller gradually adjusts the delay value of WCK according to the feedback result until the turning point is found, so as to change the phase of WCK based on the first adjustment delay value corresponding to the turning point, so that data can be stably written.

[0060] For example, as shown in FIG. 1(a), a flowchart of a timing adjustment method in the related art provided by an embodiment of the present application is shown in the figure, and the specific steps are as follows:

[0061] S1011, acquire the phase feedback signal sent by the DRAM;

[0062] S1012, determine whether the phase feedback signal has a flip point, if yes, execute step S1013, otherwise, execute step S1014.

[0063] Specifically, the flip point can be a timing point at which the level signal is converted from a high level state to a low level state, or a timing point at which the level signal is converted from a low level state to a high level state.

[0064] S1013, determine a first adjustment delay value corresponding to the flip point, and adjust the phase of the WCK based on the first adjustment delay value;

[0065] S1014, adjust the phase of the WCK based on a preset delay value, output the adjusted WCK to the DRAM, and return to step S1011.

[0066] That is, the method gradually adjusts the phase of the WCK based on the preset delay value until the first adjustment delay value corresponding to the flip point is determined, and then adjusts the phase of the WCK based on the first adjustment delay value, so that the rising edge of the WCK is aligned with the valid window of the CK. However, the method has low accuracy in a high noise scenario, and is prone to misjudgment of the flip point due to jitter or glitches, thereby failing to ensure accurate data writing.

[0067] In related technologies, a second adjustment delay value of the WCK can also be determined by determining a window interval, where the window interval is a time interval for representing that the timing of the CK and the WCK can accurately perform data writing. The delay value of the WCK is gradually adjusted, the phase feedback signal sent by the DRAM after the WCK is adjusted is scanned until the maximum window interval is determined, and the middle value of the window interval is taken as the second delay adjustment value, so that the phase of the WCK is changed through the second delay adjustment value, and data can be stably written.

[0068] For example, as shown in FIG. 1(b), another related technology timing adjustment method flowchart provided by an embodiment of the application is shown, and the specific steps are as follows:

[0069] S1021, acquire the phase feedback signal sent by the DRAM;

[0070] S1022, determine whether the phase feedback signal is a high level and the delay value corresponding to the adjusted WCK is the maximum value, if yes, execute S1023, otherwise, execute S1024;

[0071] S1023. Scan the phase feedback signal to determine the maximum window interval, use the middle value of the window interval as the second delay adjustment value, and adjust the phase of WCK based on the second adjustment delay value;

[0072] S1024. Adjust the phase of WCK based on the preset delay value, output the adjusted WCK to DRAM, and return to step S1021.

[0073] In other words, this method gradually adjusts the phase of WCK based on a preset delay value until the maximum window interval is determined. The midpoint of this window interval is then used as the second delay adjustment value. The phase of WCK is adjusted using this second delay adjustment value, thereby aligning the rising edge of WCK with the effective window of CK. However, this method requires a full-range linear scan of the phase feedback signal, resulting in long processing time and low efficiency. Furthermore, during the linear scan at high speeds, power supply noise, channel crosstalk, and other factors may cause single-sample errors, making it impossible to find a stable window interval. This leads to misjudgment of the window interval and consequently, the inability to ensure accurate data writing.

[0074] To address the aforementioned issues, this application provides a timing adjustment device, method, high-bandwidth memory, and chip. The timing adjustment device includes a delay determination circuit and a delay adjustment circuit. The delay determination circuit determines the flip point by identifying a metastable signal that indicates a level signal flip, and then determines and outputs a target delay value based on the flip point. The delay adjustment circuit repeatedly adjusts the phase of the write data strobe signal until the target delay value is received. Then, based on the target delay value, the phase of the previously adjusted write data strobe signal is adjusted again, and a target write data strobe signal is output and sent to the DRAM, enabling the DRAM to write data based on the target write data strobe signal. This allows for more accurate determination of the flip point based on the delay determination circuit and the delay adjustment circuit, avoiding misjudgments caused by jitter or glitches, and ensuring accurate data writing by the DRAM based on the target write data strobe signal.

[0075] like Figure 2 The diagram shown is a schematic diagram of a timing adjustment device provided in an embodiment of this application, including a delay determination circuit 201 and a delay adjustment circuit 202;

[0076] The delay determination circuit 201 is used to output a preset delay value and receive a phase feedback signal sent by the DRAM; after determining the metastable signal that characterizes the existence of a level signal flip from the phase feedback signal, it determines the flip point based on the metastable signal; and determines the target delay value according to the flip point and outputs the target delay value.

[0077] The delay adjustment circuit 202 is configured to adjust the phase of the write data strobe signal multiple times according to a preset delay value, and send the write data strobe signal after each adjustment to the DRAM, so that the DRAM outputs a phase feedback signal after receiving the adjusted write data strobe signal; after receiving a target delay value, adjust the phase of the write data strobe signal after the last adjustment according to the target delay value, output a target write data strobe signal, and send the target write data strobe signal to the DRAM, so that the DRAM performs data writing based on the target write data strobe signal.

[0078] In the embodiment of the present application, the DRAM is configured to compare the clock edges of a write data strobe signal (WDQS) and a clock signal CK, and output a phase feedback signal representing an analysis conclusion, the phase feedback signal being a single-bit serial signal. The write data strobe signal WDQS works synchronously with the clock signal CK, so as to ensure that the timing of the data writing operation is accurate. If the phase relationship between the write data strobe signal WDQS and the clock signal CK is not aligned, the data writing may be erroneous or damaged.

[0079] Further, the phase feedback signal is a single-bit serial signal composed of 0 or 1, and the phase feedback signal is used to determine whether the data is sampled at the correct clock edge, thereby ensuring accurate data writing. For example, when the phase feedback signal is 0, it means that the synchronization between the data and the clock has an error, i.e., the phase alignment between the write data strobe signal WDQS and the clock edge has an error, which may cause data transmission error; when the phase feedback signal is 1, it means that the phase alignment between the write data strobe signal WDQS and the clock edge, and the data can be correctly written.

[0080] It should be noted that in some related technologies, the device for aligning the phase of the write data clock WCK and the clock signal CK for data writing is mainly applied to DDR (Double Data Rate) memory, while the timing adjustment device in the present application is applied to HBM (High-Bandwidth Memory), therefore, the present application can more accurately determine the flip point based on the delay determination circuit and the delay adjustment circuit, avoid misjudgment of the flip point caused by jitter or glitches, and thus ensure that the DRAM aligns the phase of the write data strobe signal WDQS and the clock signal CK, effectively improving the reliability and accuracy of data writing.

[0081] In addition, the preset delay value is preset, and after the phase of the write data strobe signal is adjusted according to the preset delay value each time, a delay value corresponding to the current write data strobe signal is recorded, and a phase feedback signal obtained based on the current write data strobe signal is determined, so as to establish a corresponding relationship between the delay value corresponding to the current write data strobe signal and the phase feedback signal. Since the flip point is a critical point for representing that data can be accurately written, after it is determined that the flip point exists, the delay value corresponding to the phase feedback signal with the flip point can be taken as the target delay value based on the corresponding relationship between the delay value and the phase feedback signal.

[0082] In specific embodiments, the delay determination circuit 201 outputs a preset delay value, the delay adjustment circuit 202 adjusts the phase of the write data strobe signal according to the received preset delay value, stores the delay value corresponding to the current write data strobe signal, and sends the write data strobe signal adjusted each time to the DRAM, and the delay determination circuit 201 receives the phase feedback signal sent by the DRAM.

[0083] In a possible implementation, the delay determination circuit 201 determines a metastable signal from the phase feedback signal, determines the flip point based on the metastable signal, determines the target delay value based on the corresponding relationship between the delay value and the phase feedback signal, outputs the target delay value, the delay adjustment circuit 202 adjusts the phase of the write data strobe signal according to the target delay value, outputs the target write data strobe signal, and sends the target write data strobe signal to the DRAM, so that the DRAM writes data based on the target write data strobe signal.

[0084] In another possible implementation, the delay determination circuit 201 does not determine a metastable signal from the phase feedback signal, i.e., all the phase feedback signal is a stable signal, and outputs a preset delay value. The delay adjustment circuit 202 adjusts the phase of the write data strobe signal according to the received preset delay value, stores the delay value corresponding to the current write data strobe signal, and sends the write data strobe signal adjusted each time to the DRAM, until the delay determination circuit 201 determines a metastable signal from the phase feedback signal.

[0085] It can be understood that the phase feedback signal includes a stable signal and a metastable signal, wherein the stable signal is used to represent that data can be correctly written, and the metastable signal is used to represent that there is a flip point, i.e., a critical point for accurately writing data. By determining the metastable signal and further determining the flip point in the metastable signal, the application realizes more accurate judgment of the flip point, avoids misjudgment of the flip point caused by jitter or glitches, and ensures accurate writing of data by the DRAM based on the target write data strobe signal.

[0086] In specific embodiments, the flip point includes a first flip point and a second flip point;

[0087] The delay determination circuit 201 is specifically configured to: output a preset delay value for forward adjustment of the write data strobe signal, sample each received first phase feedback signal to obtain a first sampling signal corresponding to the first phase feedback signal, and determine a first metastable state signal from a plurality of first sampling signals; and determine a first flip point in the first metastable state signal.

[0088] It can be understood that, based on the preset register width in the delay determination circuit 201, each received phase feedback signal is sampled to obtain a first sampling signal corresponding to the phase feedback signal. For example, with a sampling register length of 24 bits and an initial value of 000000000000000000000000, the phase feedback signal is transmitted from right to left to the sampling register bit by bit from the lowest bit. In the case of a register width of 4, the rightmost 4 bits are sampled to obtain a first sampling signal. In the case of a register width of 8, the rightmost 8 bits are sampled to obtain a first sampling signal.

[0089] For example, with a register width of 4 bits, in the case of a received first phase feedback signal of 0, the value of the sampling register is 000000000000000000000000, and the rightmost 4 bits are sampled to obtain a first sampling signal of 0000. In the case of a next received first phase feedback signal of 1, the value of the sampling register is 000000000000000000000001, and the rightmost 4 bits are sampled to obtain a first sampling signal of 0001. Thus, each received phase feedback signal is sampled to obtain a first sampling signal corresponding to the phase feedback signal.

[0090] In one possible implementation, after the delay determination circuit 201 outputs the preset delay value for forward adjustment of the write data strobe signal, the delay adjustment circuit 202 adjusts the phase of the write data strobe signal in the forward direction according to the received preset delay value, stores a first delay value corresponding to the current write data strobe signal, and sends each adjusted write data strobe signal to the DRAM, and then the delay determination circuit 201 receives the phase feedback signal sent by the DRAM.

[0091] The delay determination circuit 201 samples each received first phase feedback signal to obtain a first sampling signal corresponding to the first phase feedback signal. In the case that the delay determination circuit 201 determines that there is a first metastable state signal from a plurality of first sampling signals, a first flip point is determined based on the first metastable state signal, and a first delay value is determined based on the correspondence between the delay value and the phase feedback signal.

[0092] In another possible implementation, after the delay determination circuit 201 outputs the preset delay value for forward adjustment of the write data strobe signal, the delay adjustment circuit 202 adjusts the phase of the write data strobe signal according to the received preset delay value, stores the first delay value corresponding to the current write data strobe signal, and sends the write data strobe signal after each adjustment to the DRAM, and then the delay determination circuit 201 receives the phase feedback signal sent by the DRAM.

[0093] The delay determination circuit 201 samples each received first phase feedback signal to obtain a first sampling signal corresponding to the first phase feedback signal. In a case where the delay determination circuit 201 determines, from the obtained multiple first sampling signals, that there is no first metastable state signal, the delay determination circuit 201 outputs the preset delay value. The delay adjustment circuit 202 adjusts the phase of the write data strobe signal according to the received preset delay value until the delay determination circuit 201 determines, from sampling according to the received phase feedback signal, that there is a first metastable state signal.

[0094] After determining the first flip point, the delay determination circuit 201 is specifically configured to: after outputting the preset delay value for reverse adjustment of the write data strobe signal, sample each received second phase feedback signal to obtain a second sampling signal corresponding to the second phase feedback signal, determine a second metastable state signal from the multiple second sampling signals, and determine a second flip point in the second metastable state signal.

[0095] In another possible implementation, after the delay determination circuit 201 outputs the preset delay value for forward adjustment of the write data strobe signal, the delay adjustment circuit 202 adjusts the phase of the write data strobe signal according to the received preset delay value, stores the first delay value corresponding to the current write data strobe signal, and sends the write data strobe signal after each adjustment to the DRAM, and then the delay determination circuit 201 receives the phase feedback signal sent by the DRAM.

[0096] The delay determination circuit 201 samples each received second phase feedback signal to obtain a second sampling signal corresponding to the second phase feedback signal. In a case where the delay determination circuit 201 determines, from the obtained multiple second sampling signals, that there is a second metastable state signal, the delay determination circuit 201 determines a second flip point based on the second metastable state signal and determines a second delay value based on the correspondence between the delay value and the phase feedback signal.

[0097] In another possible implementation, after the delay determination circuit 201 outputs the preset delay value for reverse adjustment of the write data strobe signal, the delay adjustment circuit 202 adjusts the phase of the write data strobe signal based on the received preset delay value, stores the second delay value corresponding to the current write data strobe signal, and sends the write data strobe signal after each adjustment to the DRAM, and then the delay determination circuit 201 receives the phase feedback signal sent by the DRAM.

[0098] The delay determination circuit 201 samples each received second phase feedback signal to obtain a second sampling signal corresponding to the second phase feedback signal. In a case where the delay determination circuit 201 determines, from the obtained multiple second sampling signals, that there is no second metastable state signal, the preset delay value is output. The delay adjustment circuit 202 adjusts the phase of the write data strobe signal based on the received preset delay value until the delay determination circuit 201 determines, based on the sampling of the received phase feedback signal, that there is a second metastable state signal.

[0099] Thus, the delay determination circuit 201 takes the average of the first delay value corresponding to the first flip point and the second delay value corresponding to the second flip point as the target delay value. The delay adjustment circuit 202 adjusts the phase of the write data strobe signal after the last adjustment based on the target delay value, and outputs the target write data strobe signal, so that the DRAM performs data writing based on the target write data strobe signal.

[0100] It can be understood that, by the present application, the write data strobe signal is adjusted forward until the first flip point is determined, and then the write data strobe signal after the last adjustment is adjusted backward until the second flip point is determined, and the average of the first delay value corresponding to the first flip point and the second delay value corresponding to the second flip point is taken as the target delay value. Thus, the error is reduced, and the accuracy of the target delay value determination is improved.

[0101] The forward adjustment can be a successive increase of the phase of the write data strobe signal based on the preset delay value, and the backward adjustment can be a successive decrease of the phase of the write data strobe signal based on the preset delay value.

[0102] For example, as shown in FIG. 2, the delay determination circuit 201 receives the write data strobe signal from the delay adjustment circuit 202, and determines the first flip point in the write data strobe signal. Figure 3 As shown in FIG. 2, a timing diagram of target delay value determination provided by an embodiment of the present application is provided. In the process of forward adjustment of the write data strobe signal, the first flip point is determined, and then the first phase control signal ‘h2b0’ is determined. In the process of backward adjustment of the write data strobe signal, the second flip point is determined, and then the second phase control signal ‘h296’ is determined. The delay value corresponding to the average target control signal ‘h2a6’ of the first phase control signal ‘h2b0’ and the second phase control signal ‘h296’ is taken as the target delay value.

[0103] The phase control signal is used to represent a signal outputted by the delay determination circuit 201 to the delay adjustment circuit 202, which is used to forward adjust the write data strobe signal by a preset delay value, or a signal used to reverse adjust the write data strobe signal by a preset delay value.

[0104] The structure of the delay determination circuit in the embodiment of the present application is described in detail as follows. As shown in Figure 4 FIG. 2 is a structure diagram of another timing adjustment device provided by the embodiment of the present application. The delay determination circuit 201 comprises a sampling register 401, a sampling decision circuit 402 and a result processing unit 403.

[0105] The input end of the sampling register 401 is used as the input end of the delay determination circuit 201. The output end of the sampling register 401 is electrically connected with the input end of the sampling decision circuit 402. The first output end of the sampling decision circuit 402 and the second output end of the sampling decision circuit 402 are electrically connected with the result processing unit 403. The output end of the result processing unit 403 is used as the output end of the delay determination circuit 201.

[0106] In a specific embodiment, the sampling register 401 is used to perform sampling operation on the received phase feedback signal, and output a plurality of sampling signals to the sampling decision circuit 402.

[0107] In a possible implementation, as shown in Figure 5 FIG. 2 is a structure diagram of another timing adjustment device provided by the embodiment of the present application. The delay determination circuit 201 further comprises a sampling width configuration unit 501.

[0108] The sampling width configuration unit 501 is used to configure the width of the sampling register 401. For example, the width of the sampling register 401 can be configured as 4 bits, 8 bits, 16 bits and 24 bits. For example, taking the sampling register length as 24 bits and the initial value as 000000000000000000000000 as an example, if the received first phase feedback signal is 1, the value of the sampling register is 000000000000000000000001. In the case that the width of the sampling register is configured as 4 bits, the rightmost 4 bits are sampled to obtain a sampling signal, i.e. the sampling signal is 0001. In the case that the width of the sampling register is configured as 8 bits, the rightmost 8 bits are sampled to obtain a sampling signal, i.e. the sampling signal is 00000001. In actual application, logical operation is performed based on the sampling signal obtained by the sampling register.

[0109] Further, the width of the sampling register 401 can be configured according to the noise interference degree of the signal. In a low-noise environment, the width of the sampling register 401 can be set as a low sampling width, for example, the width of the sampling register 401 is set as 4 bits, so as to improve the processing efficiency of the sampling register; in a high-noise environment, the width of the sampling register 401 can be set as a high sampling width, for example, the width of the sampling register 401 is set as 16 bits, so as to enable the sampling register to filter the noise and improve the accuracy of the flip point judgment.

[0110] The sampling decision circuit 402 is configured to perform first logical processing on the received sampling signal, output a first decision signal for representing whether the sampling signal is a steady-state signal or a metastable-state signal, and perform second logical processing on the sampling signal, output a second decision signal.

[0111] In a possible implementation, the sampling signal includes a first sampling signal and a second sampling signal. In a case where the sampling decision circuit 402 receives the first sampling signal, the first sampling signal is subjected to the first logical processing, and it is determined whether the first sampling signal is a steady-state signal or a metastable-state signal, and the first sampling signal is subjected to the second logical processing, and a second decision signal corresponding to the first sampling signal is output.

[0112] In a case where the sampling decision circuit 402 receives the second sampling signal, the second sampling signal is subjected to the first logical processing, and it is determined whether the second sampling signal is a steady-state signal or a metastable-state signal, and the second sampling signal is subjected to the second logical processing, and a second decision signal corresponding to the second sampling signal is output.

[0113] In a specific implementation, the first logical processing includes logical AND processing and logical OR processing, and the second logical processing includes logical AND processing. Figure 6 As shown in FIG. 6, another structure of a timing adjustment device provided by an embodiment of the present application is shown, and the sampling decision circuit includes a first AND gate circuit A1, an OR gate circuit A2, and a second AND gate circuit A3; the input end of the sampling decision circuit 402 is electrically connected with the input end of the first AND gate circuit A1, the input end of the OR gate circuit A2, and the input end of the second AND gate circuit A3; the output end of the first AND gate circuit A1 and the output end of the OR gate circuit A2 are electrically connected with the first output end of the sampling decision circuit 402; and the output end of the second AND gate circuit A3 is electrically connected with the second output end of the sampling decision circuit.

[0114] In a possible implementation, the first AND gate circuit A1 is configured to perform logical AND processing on the sampling signal to obtain a first processing signal R1; the OR gate circuit A2 is configured to perform logical OR processing on the sampling signal to obtain a second processing signal R2; and the first processing signal R1 and the second processing signal R2 are spliced to obtain the first decision signal.

[0115] For example, when the obtained sampling signal is 0000, the first AND gate circuit A1 is used for performing logical AND processing on the sampling signal to obtain a first processing signal R1 as 0, or the OR gate circuit A2 is used for performing logical OR processing on the sampling signal to obtain a second processing signal R2 as 0, and the first processing signal R1 and the second processing signal R2 are spliced to obtain a first decision signal as 00.

[0116] For example, when the obtained sampling signal is 1111, the first AND gate circuit A1 is used for performing logical AND processing on the sampling signal to obtain a first processing signal R1 as 1, or the OR gate circuit A2 is used for performing logical OR processing on the sampling signal to obtain a second processing signal R2 as 1, and the first processing signal R1 and the second processing signal R2 are spliced to obtain a first decision signal as 11.

[0117] It can be understood that when the first decision signal is 00 or 11, it represents that the sampling signal is a stable signal, and in this state, the data can be correctly written.

[0118] For example, when the obtained sampling signal is 1110, the first AND gate circuit A1 is used for performing logical AND processing on the sampling signal to obtain a first processing signal R1 as 0, or the OR gate circuit A2 is used for performing logical OR processing on the sampling signal to obtain a second processing signal R2 as 1, and the first processing signal R1 and the second processing signal R2 are spliced to obtain a first decision signal as 01.

[0119] For example, when the obtained sampling signal is 0001, the first AND gate circuit A1 is used for performing logical AND processing on the sampling signal to obtain a first processing signal R1 as 0, or the OR gate circuit A2 is used for performing logical OR processing on the sampling signal to obtain a second processing signal R2 as 1, and the first processing signal R1 and the second processing signal R2 are spliced to obtain a first decision signal as 01.

[0120] It can be understood that when the first decision signal is 01, it represents that the sampling signal is a metastable signal, and in this state, there is a flip point for data, that is, there is a critical point for accurately writing data.

[0121] In a possible implementation, the second AND gate circuit A3 is used for performing logical AND processing on the sampling signal except the lowest bit to obtain a second decision signal.

[0122] For example, when the sampling register length is 24 bits, the sampling register width is set to 4 bits, and the initial value is 000000000000000000000000, the sampling register 401 is used for sampling the received phase feedback signal each time, and outputs a plurality of sampling signals to the sampling decision circuit 402.

[0123] The phase feedback signal is input into the sampling register 401 in the form of a single-bit signal. When the phase feedback signal is 0, the output sampling signal is 0000. When the next received first phase feedback signal is 1, the output sampling signal is 0001, and so on until the output sampling signal is 1111.

[0124] For the case where the sampling signal is 0000, the first decision signal obtained is 00. The second AND gate circuit A3 is used to perform logical AND processing on the signal of the sampling signal except the lowest bit to obtain the second decision signal, that is, the second AND gate circuit A3 is used to perform logical AND processing on the high three bits “000” to obtain the second decision signal, which is 0.

[0125] For the case where the sampling signal is 0001, the first decision signal obtained is 01. The second AND gate circuit A3 is used to perform logical AND processing on the signal of the sampling signal except the lowest bit to obtain the second decision signal, that is, the second AND gate circuit A3 is used to perform logical AND processing on the high three bits “000” to obtain the second decision signal, which is 0.

[0126] For the case where the sampling signal is 1111, the first decision signal obtained is 11. The second AND gate circuit A3 is used to perform logical AND processing on the signal of the sampling signal except the lowest bit to obtain the second decision signal, that is, the second AND gate circuit A3 is used to perform logical AND processing on “111” to obtain the second decision signal, which is 1.

[0127] The result processing unit 403 is configured to output a preset delay value, determine a flipping point based on the second decision signal when receiving a first decision signal representing that the sampling signal is a metastable signal, and determine a target delay value according to the flipping point and output the target delay value.

[0128] In specific embodiments, taking the above cases where the sampling signal is 0000, the sampling signal is 0001, and the sampling signal is 1111 as examples, when the sampling signal is 0000, the result processing unit 403 receives the first decision signal 00, and determines that the sampling signal is a stable signal in the case where the sampling signal is 0000. When the sampling signal is 1111, the result processing unit 403 receives the first decision signal 11, and determines that the sampling signal is a stable signal in the case where the sampling signal is 1111. When the sampling signal is 0001, the result processing unit 403 receives the first decision signal 01, and determines that the sampling signal is a metastable signal in the case where the sampling signal is 0001.

[0129] The result processing unit 403 judges the flip trend of the flip point accurately based on the second decision signal 0 corresponding to the sampling signal 0000, the second decision signal 0 corresponding to the sampling signal 0001, and the second decision signal 1 corresponding to the sampling signal 1111. For example, when the second decision signal changes from 0 to 1, it can be determined that the flip direction is from low level to high level; when the second decision signal changes from 1 to 0, it can be determined that the flip direction is from high level to low level. Thus, the delay value corresponding to the phase control signal for adjusting the write data strobe signal is taken as the delay value corresponding to the flip point.

[0130] For example, the delay value output by the result processing unit 403 includes a preset delay value and a target delay value. The result processing unit 403 outputs the preset delay value to make the delay adjustment circuit 202 adjust the phase of the write data strobe signal according to the received preset delay value; in the case where the result processing unit 403 receives the first decision signal for representing the sampling signal as a metastable signal and determines the flip point based on the second decision signal, the average of the first delay value corresponding to the first flip point and the second delay value corresponding to the second flip point is taken as the target delay value, and the target delay value is output to make the delay adjustment circuit 202 adjust the phase of the write data strobe signal according to the target delay value after the last adjustment, and output the target write data strobe signal to make the DRAM write data based on the target write data strobe signal.

[0131] The embodiment of the present application provides a timing adjustment device, which comprises a delay determination circuit and a delay adjustment circuit; the delay determination circuit is used for outputting a preset delay value and receiving a phase feedback signal sent by a DRAM; after determining a metastable signal representing the existence of level signal flip from the phase feedback signal, the flip point is determined based on the metastable signal; the target delay value is determined according to the flip point, and the target delay value is output; the delay adjustment circuit is used for adjusting the phase of the write data strobe signal multiple times according to the received preset delay value, and sending the write data strobe signal after each adjustment to the DRAM, so that the DRAM outputs the phase feedback signal after receiving the adjusted write data strobe signal; after receiving the target delay value, the phase of the write data strobe signal after the last adjustment is adjusted according to the target delay value, the target write data strobe signal is output, and the target write data strobe signal is sent to the DRAM, so that the DRAM writes data based on the target write data strobe signal. Thus, the flip point is more accurately judged based on the delay determination circuit and the delay adjustment circuit, the misjudgment of the flip point caused by jitter or glitch is avoided, and then the accurate writing of data by the DRAM based on the target write data strobe signal is ensured.

[0132] Based on the same inventive concept, the embodiment of the present application further provides a timing adjustment method applied to any of the timing adjustment devices described above. The principle of solving the technical problem of the timing adjustment method is the same as that of the timing adjustment device of the present application. The implementation of the timing adjustment method can refer to the implementation of the timing adjustment device, and the repeated parts will not be described here.

[0133] As shown in FIG. 7, a flowchart of a timing adjustment method provided by the embodiment of the present application is shown, and the specific steps are as follows: Figure 7

[0134] S701, adjust the phase of the write data strobe signal multiple times according to the preset delay value, send the write data strobe signal after each adjustment to the DRAM, and receive the phase feedback signal sent by the DRAM;

[0135] S702, after determining the metastable state signal for representing the existence of level signal flip from the phase feedback signal, determine the flip point based on the metastable state signal;

[0136] S703, determine the target delay value according to the flip point;

[0137] S704, adjust the phase of the write data strobe signal after the last adjustment according to the target delay value, output the target write data strobe signal, and send the target write data strobe signal to the DRAM, so that the DRAM performs data writing based on the target write data strobe signal.

[0138] In the embodiment of the present application, the flip point includes a first flip point and a second flip point. Determining the target delay value according to the flip point includes: taking the average of the first delay value corresponding to the first flip point and the second delay value corresponding to the second flip point as the target delay value;

[0139] Wherein, after adjusting the write data strobe signal forward according to the preset delay value, sampling each received first phase feedback signal to obtain a first sampling signal corresponding to the first phase feedback signal, determining a first metastable state signal from a plurality of first sampling signals, and the first flip point is determined in the first metastable state signal;

[0140] After adjusting the write data strobe signal backward according to the preset delay value, sampling each received second phase feedback signal to obtain a second sampling signal corresponding to the second phase feedback signal, determining a second metastable state signal from a plurality of second sampling signals, and the second flip point is determined in the second metastable state signal.

[0141] ​In a possible implementation, determining the first metastable state signal from the plurality of first sampling signals comprises: determining the first metastable state signal by performing logical AND and logical OR processing on each first sampling signal; and determining the second metastable state signal from the plurality of second sampling signals comprises: determining the second metastable state signal by performing logical AND and logical OR processing on each second sampling signal.

[0142] The complete flowchart of the timing adjustment method provided in the embodiment of the application is described below.

[0143] As shown in the complete flowchart of the timing adjustment method provided in the embodiment of the application, the method comprises the following steps: Figure 8

[0144] S801, adjusting the phase of the write data gate signal in a forward direction according to a preset delay value, sending the write data gate signal adjusted in the forward direction to the DRAM, and receiving a phase feedback signal sent by the DRAM;

[0145] S802, sampling each received phase feedback signal to obtain a first sampling signal corresponding to a first phase feedback signal, determining whether there is a first metastable state signal from a plurality of first sampling signals, if yes, performing S803, otherwise, performing S801;

[0146] S803, determining a first flip point in the first metastable state signal;

[0147] S804, adjusting the phase of the write data gate signal in a reverse direction according to a preset delay value, sending the write data gate signal adjusted in the reverse direction to the DRAM, and receiving a phase feedback signal sent by the DRAM;

[0148] S805, sampling each received phase feedback signal to obtain a second sampling signal corresponding to a second phase feedback signal, determining whether there is a second metastable state signal from a plurality of second sampling signals, if yes, performing S806, otherwise, performing S804;

[0149] S806, determining a second flip point in the second metastable state signal;

[0150] S807, taking the average of the first delay value corresponding to the first flip point and the second delay value corresponding to the second flip point as a target delay value;

[0151] S808, adjusting the phase of the write data gate signal adjusted last time according to the target delay value, outputting a target write data gate signal, and sending the target write data gate signal to the DRAM, so that the DRAM performs data writing based on the target write data gate signal.

[0152] ​The embodiment of the present application provides a timing adjustment device and method, the phase of a write data gate signal is adjusted multiple times according to a preset delay value, the write data gate signal after each adjustment is sent to a DRAM, and a phase feedback signal sent by the DRAM is received; after determining a metastable state signal for representing that there is a level signal flip from the phase feedback signal, a flip point is determined based on the metastable state signal; a target delay value is determined according to the flip point; the phase of the write data gate signal after the last adjustment is adjusted according to the target delay value, a target write data gate signal is output, and the target write data gate signal is sent to the DRAM, so that the DRAM performs data writing based on the target write data gate signal. Therefore, the flip point is more accurately judged based on the delay determination circuit and the delay adjustment circuit, the misjudgment of the flip point caused by jitter or glitch is avoided, and then the accurate writing of data by the DRAM based on the target write data gate signal is ensured.

[0153] Based on the same inventive concept, the embodiment of the present application also provides a high-bandwidth memory applied to any one of the timing adjustment devices described above, the high-bandwidth memory comprising any one of the timing adjustment devices of the first aspect and a DRAM connected with the timing adjustment device, the principle of solving the technical problems of the high-bandwidth memory is the same as that of the timing adjustment device of the present application, and the implementation of the high-bandwidth memory can refer to the implementation of the timing adjustment device, and the repeated parts will not be described again.

[0154] Based on the same inventive concept, the embodiment of the present application also provides a chip comprising the high-bandwidth memory described above, the principle of solving the technical problems of the chip is the same as that of the timing adjustment device of the present application, and the implementation of the chip can refer to the implementation of the timing adjustment device, and the repeated parts will not be described again.

[0155] In specific embodiments, the chip can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose Graphics Processing Unit).

[0156] The embodiment of the present application provides a timing adjustment device, method, high bandwidth memory and chip, the timing adjustment device comprises a delay determination circuit and a delay adjustment circuit; the delay determination circuit is used for outputting a preset delay value, receiving a phase feedback signal sent by DRAM; after determining a metastable state signal for representing that there is a level signal flip from the phase feedback signal, determining a flip point based on the metastable state signal; determining a target delay value according to the flip point, and outputting the target delay value; the delay adjustment circuit is used for adjusting the phase of a write data gate signal multiple times according to the received preset delay value, and sending the write data gate signal after each adjustment to the DRAM, so that the DRAM outputs the phase feedback signal after receiving the adjusted write data gate signal; after receiving the target delay value, adjusting the phase of the write data gate signal after the last adjustment according to the target delay value, outputting the target write data gate signal, and sending the target write data gate signal to the DRAM, so that the DRAM performs data writing based on the target write data gate signal. Therefore, the delay determination circuit and the delay adjustment circuit are used to more accurately judge the flip point, avoid misjudgment of the flip point caused by jitter or glitches, and then ensure that the DRAM accurately writes data based on the target write data gate signal.

[0157] The application is described above with reference to block and / or flow diagrams illustrating the methodology, apparatus (system) and / or computer program products according to embodiments of the present application. It is understood that one of the blocks of the block and / or flow diagrams, as well as a combination of blocks of the block and / or flow diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, and / or other programmable data processing apparatus to produce a machine, so that the instructions executed by the computer processor and / or other programmable data processing apparatus create a method implemented for implementing the functions / acts specified in the block of the block and / or flow diagrams.

[0158] Accordingly, the present application can also be embodied in hardware and / or in software (including firmware, resident software, micro-code, etc.). Furthermore, the present application can take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the present context, a computer-usable or computer-readable medium can be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

[0159] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A timing adjustment device, characterized in that, Includes a delay determination circuit and a delay adjustment circuit; The delay determination circuit is used to output a preset delay value, receive a phase feedback signal sent by DRAM; determine a metastable signal from the phase feedback signal to characterize the existence of a level signal flip, determine the flip point based on the metastable signal; determine a target delay value according to the flip point, and output the target delay value. The delay adjustment circuit is used to adjust the phase of the write data strobe signal multiple times according to the received preset delay value, and send the adjusted write data strobe signal to the DRAM each time, so that the DRAM outputs the phase feedback signal after receiving the adjusted write data strobe signal; after receiving the target delay value, it adjusts the phase of the previously adjusted write data strobe signal according to the target delay value, outputs the target write data strobe signal, and sends the target write data strobe signal to the DRAM, so that the DRAM writes data based on the target write data strobe signal.

2. The apparatus as claimed in claim 1, characterized in that, The flip point includes a first flip point and a second flip point; The delay determination circuit is specifically used for: After outputting a preset delay value for positive adjustment of the write data strobe signal, the first phase feedback signal received each time is sampled to obtain a first sampled signal corresponding to the first phase feedback signal, and a first metastable signal is determined from multiple first sampled signals; the first flip point is determined from the first metastable signal. After outputting a preset delay value for reverse adjustment of the write data strobe signal, the second phase feedback signal received each time is sampled to obtain a second sampled signal corresponding to the second phase feedback signal. A second metastable signal is determined from multiple second sampled signals, and a second flip point is determined from the second metastable signal. The average value of the first delay value corresponding to the first flip point and the second delay value corresponding to the second flip point is taken as the target delay value.

3. The apparatus as described in claim 1, characterized in that, The delay determination circuit includes a sampling register, a sampling decision circuit, and a result processing unit; The sampling register is used to sample the received phase feedback signal and output multiple sampling signals to the sampling decision circuit. The sampling decision circuit is used to perform a first logic processing on the received sampling signal and output a first decision signal to characterize whether the sampling signal is a steady-state signal or a metastable signal, and to perform a second logic processing on the sampling signal and output a second decision signal. The result processing unit is used to output the preset delay value; Upon receiving a first decision signal characterizing the sampled signal as a metastable signal, a flip point is determined based on the second decision signal; a target delay value is determined based on the flip point, and the target delay value is output.

4. The apparatus as described in claim 3, characterized in that, The input terminal of the sampling register serves as the input terminal of the delay determination circuit, and the output terminal of the sampling register is electrically connected to the input terminal of the sampling decision circuit. The first output terminal and the second output terminal of the sampling decision circuit are electrically connected to the result processing unit; The output of the result processing unit serves as the output of the delay determination circuit.

5. The apparatus as described in claim 3, characterized in that, The delay determination circuit also includes a sampling width configuration unit; The sampling width configuration unit is used to configure the width of the sampling register.

6. The apparatus as claimed in claim 3, characterized in that, The sampling decision circuit includes a first AND gate, an OR gate, and a second AND gate; The first AND gate is used to perform a logical AND operation on the sampled signal to obtain a first processed signal; the OR gate is used to perform a logical OR operation on the sampled signal to obtain a second processed signal; the second AND gate is used to perform a logical AND operation on the sampled signal excluding the least significant bit to obtain a second decision signal; The first processing signal and the second processing signal are concatenated to obtain the first decision signal.

7. The apparatus as claimed in claim 6, characterized in that, The input terminal of the sampling decision circuit is electrically connected to the input terminal of the first AND gate circuit, the input terminal of the OR gate circuit, and the input terminal of the second AND gate circuit, respectively. The output terminal of the first AND gate circuit and the output terminal of the OR gate circuit are electrically connected to the first output terminal of the sampling decision circuit. The output terminal of the second AND gate circuit is electrically connected to the second output terminal of the sampling decision circuit.

8. A timing adjustment method, characterized in that, Applied to the timing adjustment apparatus as described in any one of claims 1 to 7, the method comprises: The phase of the write data strobe signal is adjusted multiple times according to a preset delay value, the adjusted write data strobe signal is sent to the DRAM after each adjustment, and the phase feedback signal sent by the DRAM is received. After determining the metastable signal from the phase feedback signal to characterize the existence of a level signal reversal, the reversal point is determined based on the metastable signal; The target delay value is determined based on the flip point; The phase of the previously adjusted write data strobe signal is adjusted according to the target delay value, a target write data strobe signal is output, and the target write data strobe signal is sent to the DRAM so that the DRAM can write data based on the target write data strobe signal.

9. The method as described in claim 8, characterized in that, The flip point includes a first flip point and a second flip point; Determining the target delay value based on the flip point includes: The average of the first delay value corresponding to the first flip point and the second delay value corresponding to the second flip point is taken as the target delay value; Specifically, after positively adjusting the write data strobe signal according to the preset delay value, the first phase feedback signal received each time is sampled to obtain the first sampled signal corresponding to the first phase feedback signal, and the first metastable signal is determined from multiple first sampled signals. The first flip point is determined from the first metastable signal. After the write data strobe signal is reversed according to the preset delay value, the second phase feedback signal received each time is sampled to obtain the second sampled signal corresponding to the second phase feedback signal. The second metastable signal is determined from multiple second sampled signals, and the second flip point is determined from the second metastable signal.

10. The method as described in claim 9, characterized in that, Determining the first metastable signal from the plurality of first sampled signals includes: The first metastable signal is determined by performing logical AND and logical OR operations on each of the first sampled signals; Determining the second metastable signal from the plurality of second sampled signals includes: The second metastable signal is determined by performing logical AND and logical OR operations on each of the second sampled signals.

11. A high-bandwidth memory, characterized in that, It includes the timing adjustment device as described in any one of claims 1 to 7 and the DRAM connected to the timing adjustment device.

12. A chip, characterized in that, Includes the high-bandwidth memory as described in claim 11.

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