Pressure sensor chip and method of manufacturing

Abstract

The application relates to the technical field of pressure sensors, in particular to a pressure sensor chip and a preparation method, which forms a metal electrode opening area, a p-type isolation channel and a bonding area by etching a p-type silicon carbide bonding layer of a silicon carbide epitaxial wafer; forms an n-type isolation channel, a resistance strip lead and an n-type silicon carbide pressure-sensitive resistor by etching an n-type silicon carbide device layer; sets a silicon dioxide layer on the sidewalls of the p-type isolation channel, the sidewalls of the n-type isolation channel and the passivation area of the wedge-shaped through hole which does not contact the p-type silicon carbide bonding layer; sets a metal electrode layer in the metal electrode opening area and in contact with the n-type silicon carbide device layer; etches the bottom of an n-type silicon carbide substrate to form a ring-shaped stepped pressure cavity, a blind groove and a wedge-shaped through hole are arranged in the center of a silicon carbide sealing cover plate, and the silicon carbide sealing cover plate is bonded to the top of the silicon carbide epitaxial wafer, so that the problem that a silicon carbide pressure sensor chip is difficult to meet the demand of high-precision pressure measurement is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of pressure sensor, in particular to a pressure sensor chip and a preparation method. BACKGROUND

[0002] In the field of high-temperature pressure testing, especially in harsh environments above 600℃, such as strong radiation, electromagnetic interference and strong corrosion conditions, the measurement accuracy and reliability of pressure sensors are required to be more stringent. Silicon carbide material has become an ideal choice for realizing high-temperature pressure sensing due to its excellent high-temperature stability, but it needs to overcome the challenges in processing and reliability to meet the actual application requirements.

[0003] Early pressure sensors mostly use silicon-based materials to realize pressure sensing through MEMS technology. Silicon-based sensors use PN junction characteristics for signal conversion, but the electrical properties of silicon material are limited in high-temperature environments, affecting stability. The sensor based on SOI technology uses an intermediate oxide layer isolation structure to improve the working temperature range, but due to the plastic deformation of silicon material itself at high temperature, its application temperature is difficult to break through 500℃ or above.

[0004] When silicon carbide pressure sensor chips are used in high-temperature applications, they still face problems such as difficulty in processing pressure cavities, poor pattern fidelity, and low front bonding strength, which leads to insufficient reliability and measurement accuracy of the sensor in harsh high-temperature environments, making it difficult to meet the demand for high-precision pressure measurement. SUMMARY

[0005] The present application provides a pressure sensor chip and a preparation method to solve the problem that silicon carbide pressure sensor chips are difficult to meet the demand for high-precision pressure measurement.

[0006] The first aspect of the present application provides a pressure sensor chip, comprising: a silicon carbide epitaxial wafer, a silicon dioxide layer, a metal electrode layer and a silicon carbide sealing cover plate;

[0007] The silicon carbide epitaxial wafer comprises a p-type silicon carbide bonding layer, an n-type silicon carbide device layer, a p-type silicon carbide isolation layer, an n-type silicon carbide buffer layer and an n-type silicon carbide substrate connected in order from top to bottom;

[0008] The p-type silicon carbide bonding layer is etched to form a metal electrode opening area, a p-type isolation channel and a bonding area;

[0009] The n-type silicon carbide device layer is etched to form an n-type isolation channel, a resistance strip lead and four n-type silicon carbide voltage-dependent resistors; the n-type isolation channel is arranged at the bottom of the p-type isolation channel, and the n-type silicon carbide voltage-dependent resistor is provided with a p-type silicon carbide bonding layer at the top;

[0010] The silicon dioxide layer is arranged on the sidewalls of the p-type isolation channel and the n-type isolation channel, and the passivation area of the wedge-shaped via hole not in contact with the p-type silicon carbide bonding layer;

[0011] The metal electrode layer is arranged in the metal electrode opening area and in contact with the n-type silicon carbide device layer;

[0012] The bottom of the n-type silicon carbide substrate is etched to form a ring-shaped stepped pressure cavity;

[0013] The silicon carbide sealing cover plate is centrally provided with a blind groove, and four wedge-shaped vias are arranged around the blind groove. The silicon carbide sealing cover plate is bonded to the top of the silicon carbide epitaxial wafer.

[0014] The pressure sensor chip of the present application improves the electrical insulation performance, reduces signal interference, and improves the accuracy of pressure measurement through the design of multi-layer silicon carbide structure and silicon dioxide. At the same time, the ring-shaped stepped pressure cavity and the silicon carbide sealing cover plate cooperate to help uniformly distribute pressure, optimize the response stability and sensitivity of the sensor, so as to solve the problem that the silicon carbide pressure sensor chip is difficult to meet the high-precision pressure measurement requirement.

[0015] Optionally, the n-type isolation channel and the p-type isolation channel have the same width; the four n-type silicon carbide pressure sensitive resistors have the same resistance and are distributed around the ring-shaped stepped pressure cavity; the n-type silicon carbide pressure sensitive resistor has a π-shaped structure for improving the pressure sensing capability and measurement accuracy.

[0016] By adopting the n-type and p-type isolation channels with the same width, the uniformity of electrical isolation is improved; the four pressure sensitive resistors with the same resistance and distributed around the cavity can reduce the influence of temperature change on the output and improve the measurement consistency; the π-shaped structure of the pressure sensitive resistor can enhance the strain sensing capability, thereby improving the sensitivity and accuracy of pressure measurement.

[0017] Optionally, the four n-type silicon carbide pressure sensitive resistors are connected in sequence through four resistance strip leads, and the patterns of the four resistance strip leads are completely the same and symmetrically distributed outside the stress area to form a Wheatstone bridge in a closed bridge form.

[0018] By connecting the four pressure sensitive resistors in sequence through the completely same resistance strip leads and symmetrically distributing them outside the stress area, the consistency of the lead patterns and the positional symmetry are achieved, thereby reducing the influence of process deviation and uneven stress distribution on the balance of the bridge; the Wheatstone bridge in a closed bridge form can improve the stability of the output signal, improve the common mode noise rejection capability, and further improve the accuracy and reliability of pressure measurement.

[0019] Optionally, the thickness of the silicon dioxide layer is 50-200 nm; the metal electrode layer comprises at least one metal selected from titanium, platinum, tungsten, titanium nitride and gold.

[0020] The thickness range of the silicon dioxide layer helps to reduce the stress of the dielectric layer while providing sufficient electrical insulation capability, thereby optimizing the reliability of long-term operation of the device; the material combination of the metal electrode layer can take into account good ohmic contact, adhesion and anti-electromigration performance, which helps to improve the stability of the electrode structure and the quality of signal transmission.

[0021] Optionally, the inner wall and / or the outer wall of the annular stepped pressure cavity are in an annular stepped structure; the annular stepped structure has one or more annular steps, and when there are multiple annular steps, the multiple annular steps are concentric annular steps.

[0022] The design of the annular stepped structure helps to disperse and buffer the stress concentration under pressure, reducing the risk of structural rupture; when there are multiple concentric annular steps, the uniformity of stress distribution can be further optimized, thereby improving the structural stability and measurement consistency of the pressure sensor under high pressure or cyclic load conditions.

[0023] Optionally, the wedge-shaped via is formed in the silicon carbide sealing cover plate near the metal electrode layer; the blind groove is formed in the silicon carbide sealing cover plate near the annular stepped pressure cavity; the silicon carbide sealing cover plate and the p-type silicon carbide bonding layer are homogeneously bonded by a surface activation bonding technology, and the bonding strength is greater than 32 MPa.

[0024] By arranging the wedge-shaped via near the metal electrode layer, the difficulty of electrode lead connection can be reduced and the parasitic effect of the signal transmission path can be reduced; the blind groove is located above the annular stepped pressure cavity, which can optimize the uniformity of pressure transmission and improve the consistency of sensor response; the surface activation bonding technology is used to realize the homogeneous bonding of the silicon carbide sealing cover plate and the bonding layer, and the bonding strength helps to improve the packaging airtightness and interface stability, thereby enhancing the long-term working reliability of the device in harsh environments.

[0025] The second aspect of the present application provides a pressure sensor chip preparation method for processing the pressure sensor chip of the first aspect, the method comprising:

[0026] A five-layer double-etched silicon carbide epitaxial wafer is selected as the processing substrate, and the silicon carbide epitaxial wafer comprises, from top to bottom, a p-type silicon carbide bonding layer, an n-type silicon carbide device layer, a p-type silicon carbide isolation layer, an n-type silicon carbide buffer layer and an n-type silicon carbide substrate;

[0027] The p-type silicon carbide bonding layer is etched by a dry etching process to form a metal electrode opening area, a p-type isolation channel and a bonding area.

[0028] The n-type silicon carbide device layer is etched by a dry etching process to form an n-type isolation channel, four resistance strip leads, and four n-type silicon carbide voltage-dependent resistors;

[0029] A silicon dioxide layer is grown on the upper surface of the silicon carbide epitaxial wafer by a thermal oxidation process;

[0030] The silicon dioxide layer is etched by a dry etching process to retain the sidewalls of the p-type isolation channel, the sidewalls of the n-type isolation channel, and the oxide layer of the passivation region;

[0031] A metal electrode layer is formed on the metal electrode opening area by a stripping process combined with an electron beam evaporation method, and annealing treatment is performed to form an ohmic contact;

[0032] The bottom of the n-type silicon carbide substrate is etched by a multiple laser processing process to form a ring-shaped stepped pressure cavity, and a deep dry etching technique is used to remove the laser damage layer;

[0033] A first etching process is used to etch the silicon carbide material to form a blind groove and a wedge-shaped via hole, and a silicon carbide sealing cover plate is obtained;

[0034] A surface activation bonding technique is used to homogeneously bond the silicon carbide sealing cover plate with the p-type silicon carbide bonding layer.

[0035] The above preparation method uses a five-layer structure silicon carbide epitaxial wafer as a substrate, which helps to ensure the consistency of the material and the process compatibility; a dry etching process is used to form an isolation channel and a resistance pattern, which can improve the etching precision and pattern uniformity, and reduce the size deviation; a thermal oxidation process is used to grow a silicon dioxide layer, which can optimize the coverage quality and passivation effect of the insulating layer; a stripping process and electron beam evaporation are used to prepare a metal electrode and perform annealing, which helps to form a stable ohmic contact and reduce the contact resistance; a multiple laser processing and deep dry etching are used to form a ring-shaped stepped pressure cavity and remove the damage layer, which can reduce the stress concentration introduced by processing and improve the integrity of the cavity structure; a surface activation bonding technique is used to achieve homogenous bonding, which helps to improve the bonding strength and air tightness of the packaging interface, thereby enhancing the overall reliability and measurement stability of the device.

[0036] Optionally, the first etching process uses one or more of a deep dry etching process, a laser processing process, and a mechanical grinding processing process; the dry etching process and the deep dry etching process both use an inductively coupled plasma etching process or a reactive ion etching process.

[0037] The combination of multiple processing techniques by the first etching process provides flexibility of process selection, which is helpful to adapt to the processing requirements of different structural features; the inductively coupled plasma etching or reactive ion etching is used in the dry etching process and the deep dry etching process, which can improve the precision and uniformity of the etched pattern, reduce the sidewall roughness and material damage in the etching process, and thus improve the integrity of the device structure and the stability of the electrical performance.

[0038] Optionally, the etching power of the deep dry etching process is 1000W to 1500W, the radio frequency bias is 100W to 300W, the working pressure is 0.34Pa to 1Pa, and the depth is 5μm to 10μm; the deep dry etching process uses a mixed gas of sulfur hexafluoride and oxygen or a mixed gas of carbon tetrafluoride and oxygen;

[0039] If the deep dry etching process uses a mixed gas of sulfur hexafluoride and oxygen, the flow rate of sulfur hexafluoride is 100sccm to 120sccm, and the flow rate of oxygen is 5sccm to 15sccm;

[0040] If the deep dry etching process uses a mixed gas of carbon tetrafluoride and oxygen, the flow rate of carbon tetrafluoride is 100sccm to 120sccm, and the flow rate of oxygen is 5sccm to 15sccm.

[0041] The deep dry etching process sets specific etching power, radio frequency bias, working pressure and depth range, and combines the mixed gas of sulfur hexafluoride and oxygen or carbon tetrafluoride and oxygen and its flow rate control, which is helpful to optimize the etching rate and directionality, reduce the sidewall roughness and lattice damage in the etching process, and thus improve the precision and structural integrity of the etched pattern and enhance the consistency and stability of the device performance.

[0042] Optionally, during the deep dry etching process, an oxidation layer is formed on the sidewall by controlling the gas composition and etching parameters to reduce lateral etching and improve the aspect ratio.

[0043] Forming an oxidation layer on the sidewall by controlling the gas composition and etching parameters is helpful to suppress lateral etching, improve the perpendicularity and aspect ratio of the etched structure, and thus improve the precision of pattern transfer and the consistency of structural size, and enhance the performance stability of the device at the microscale.

[0044] It can be known from the above technical solution that the application provides a pressure sensor chip and a preparation method, by selecting a five-layer structure double-etched silicon carbide wafer as a processing substrate, using a dry etching process to etch the p-type silicon carbide bonding layer to form a metal electrode opening area, a p-type isolation channel and a bonding area; using a dry etching process to etch the n-type silicon carbide device layer to form an n-type isolation channel, four resistance strip leads and four n-type silicon carbide pressure sensitive resistors; using a thermal oxidation process to grow a layer of silicon dioxide on the upper surface of the silicon carbide wafer; using a dry etching process to etch the silicon dioxide layer to retain the sidewalls of the p-type isolation channel, the sidewalls of the n-type isolation channel and the oxidation layer of the passivation area; using a stripping process combined with an electron beam evaporation method to form a metal electrode layer on the metal electrode opening area, and performing annealing treatment to form an ohmic contact; using a multiple laser processing process to etch the bottom of the n-type silicon carbide substrate to form a ring-shaped stepped pressure cavity, and removing the laser damage layer by deep dry etching technology; using a first etching process to etch the silicon carbide material to form a blind groove and a wedge-shaped via hole, and obtaining a silicon carbide sealing cover plate; using a surface activation bonding technology to homogeneously bond the silicon carbide sealing cover plate with the p-type silicon carbide bonding layer, so as to solve the problem that the silicon carbide pressure sensor chip is difficult to meet the high-precision pressure measurement requirement. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the application, the drawings required in the embodiments will be briefly introduced below. Obviously, other drawings can also be obtained by those skilled in the art without creative labor.

[0046] Figure 1 A planar structure schematic diagram of the pressure sensor chip provided by the embodiments of the application;

[0047] Figure 2 A processing flow schematic diagram of the pressure sensor chip preparation method provided by the embodiments of the application;

[0048] Figure 3 A photolithography mask layout for etching the p-type silicon carbide bonding layer in the pressure sensor chip preparation method provided by the embodiments of the application;

[0049] Figure 4 A photolithography mask layout for etching the n-type silicon carbide device layer in the pressure sensor chip preparation method provided by the embodiments of the application;

[0050] Figure 5 A photolithography mask layout for etching the silicon dioxide layer in the pressure sensor chip preparation method provided by the embodiments of the application;

[0051] Figure 6The photolithography mask pattern for preparing the metal electrode layer in the pressure sensor chip preparation method provided by the embodiments of the present application.

[0052] Illustration:

[0053] wherein 1 is an n-type silicon carbide substrate; 2 is an n-type silicon carbide buffer layer; 3 is a p-type silicon carbide isolation layer; 4 is an n-type silicon carbide device layer; 5 is a p-type silicon carbide bonding layer; 6 is a metal electrode opening area; 7 is a p-type isolation channel; 8 is a bonding area; 9 is an n-type isolation channel; 10 is an n-type silicon carbide pressure-sensitive resistor; 11 is a resistance strip lead; 12 is a silicon dioxide layer; 13 is a passivation area; 14 is a metal electrode layer; 15 is a ring-shaped stepped pressure cavity; 16 is a blind groove; and 17 is a wedge-shaped via hole. DETAILED DESCRIPTION

[0054] The embodiments will be described in detail below with reference to examples shown in the drawings. When the following description refers to the drawings, identical numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following examples do not represent all embodiments consistent with the present application. Rather, they are merely examples of systems and methods consistent with some aspects of the present application.

[0055] To solve the problem that the silicon carbide pressure sensor chip is difficult to meet the demand of high-precision pressure measurement, see Figures 1-6 The pressure sensor chip provided by some embodiments of the present application comprises a silicon carbide epitaxial wafer, a silicon dioxide layer 12, a metal electrode layer 14, and a silicon carbide sealing cover plate.

[0056] It should be understood that the silicon carbide epitaxial wafer and the silicon carbide sealing cover plate of the pressure sensor chip are both made of 4H-SiC material. 4H-SiC material refers to a silicon carbide polytype with a hexagonal crystal structure, where "4H" indicates that there are four double-layer periodic stacking units along the c-axis direction in its crystal structure. This material has excellent physical and chemical properties, such as high hardness, high thermal conductivity, high chemical stability, and good high-temperature stability, making it have a wide application prospect in extreme environments such as high pressure, high frequency, and high temperature. In particular, in the manufacture of pressure sensor chips, 4H-SiC material is favored for its outstanding performance.

[0057] The silicon carbide epitaxial wafer comprises a p-type silicon carbide bonding layer 5, an n-type silicon carbide device layer 4, a p-type silicon carbide isolation layer 3, an n-type silicon carbide buffer layer 2, and an n-type silicon carbide substrate 1; the p-type silicon carbide bonding layer 5, the n-type silicon carbide device layer 4, the p-type silicon carbide isolation layer 3, the n-type silicon carbide buffer layer 2, and the n-type silicon carbide substrate 1 are connected in order from top to bottom.

[0058] It should be understood that the n-type silicon carbide buffer layer 2 arranged above the n-type silicon carbide substrate 1 can greatly reduce the defects of the epitaxial layer and improve the quality of the epitaxial layer; the p-type silicon carbide isolation layer 3 arranged between the n-type silicon carbide buffer layer 2 and the n-type silicon carbide device layer 4 can realize electrical isolation between the n-type silicon carbide device layer 4 and the substrate, avoid device short circuit, and be applicable to high-temperature environment above 600℃; the p-type silicon carbide bonding layer 5 arranged above the n-type silicon carbide device layer 4 and homogeneously bonded with the silicon carbide sealing cover plate, the p-type silicon carbide bonding layer 5 and the silicon carbide sealing cover plate have the same thermal expansion coefficient, which can reduce the stress of the bonding interface; the n-type silicon carbide device layer 4 is not in direct contact with the silicon carbide sealing cover plate, which avoids the influence of the bonding interface on the electrical and mechanical properties of the device layer; the p-type silicon carbide bonding layer 5 can be used as a shielding layer to effectively protect the n-type silicon carbide device layer 4, reduce signal interference such as radiation and electromagnetic interference, and improve reliability.

[0059] The p-type silicon carbide bonding layer 5 is etched to form a metal electrode opening area 6, a p-type isolation channel 7 and a bonding area 8.

[0060] It should be understood that the metal electrode opening area 6 is used for the preparation of subsequent metal electrodes to realize the electrical connection between the device and the external circuit; the p-type isolation channel 7 can further enhance the electrical isolation effect between the device layer and the substrate and prevent the occurrence of electric leakage; and the bonding area 8 is a key area for homogenous bonding with the silicon carbide sealing cover plate, and the accurate control of the size and shape of the bonding area 8 is crucial to ensure the bonding quality. By reasonably designing the layout and parameters of these areas, the performance and reliability of the pressure sensor chip can be significantly improved.

[0061] The n-type silicon carbide device layer 4 is etched to form an n-type isolation channel 9, four resistance strip leads 11 and four n-type silicon carbide pressure sensitive resistors 10; the n-type isolation channel 9 is arranged at the bottom of the p-type isolation channel 7, and the n-type silicon carbide pressure sensitive resistor 10 has the p-type silicon carbide bonding layer 5 arranged at the top.

[0062] It should be understood that the four resistance bar leads 11 are completely the same in pattern and symmetrically distributed outside the stress area, sequentially connecting the four n-type silicon carbide varistors 10 (R1, R2, R3, R4) to form a Wheatstone bridge in the form of a closed bridge. The main role of the n-type isolation channel 9 is to further enhance the electrical isolation performance inside the device, ensuring that unnecessary electrical interference does not occur between the various functional areas. The four resistance bar leads 11 are respectively connected to the four n-type silicon carbide varistors 10, and these leads are responsible for transmitting the electrical signals generated by the varistors due to pressure changes, so that the subsequent circuit can process and analyze them. The four n-type silicon carbide varistors 10, as the core sensitive element of the pressure sensor, will have their resistance values change accordingly with the change in pressure. By detecting this change in resistance value, the magnitude of the pressure can be indirectly obtained. The p-type silicon carbide bonding layer 5 is arranged on the top of the n-type silicon carbide varistor 10. Not only can it protect the varistor to a certain extent, but it can also take advantage of the properties of p-type silicon carbide to further optimize the electrical performance and reliability of the sensor chip.

[0063] The silicon dioxide layer 12 is arranged on the sidewalls of the p-type isolation channel 7 and the n-type isolation channel 9, as well as the passivation area 13 of the wedge-shaped through hole 17 that does not contact the p-type silicon carbide bonding layer 5.

[0064] The metal electrode layer 14 is arranged in the metal electrode opening area 6 and contacts the n-type silicon carbide device layer 4, while achieving electrical insulation with the p-type silicon carbide bonding layer 5 through the silicon dioxide layer 12 on the sidewall.

[0065] The bottom of the n-type silicon carbide substrate 1 is etched to form a ring-shaped stepped pressure cavity 15.

[0066] The center of the silicon carbide sealing cover plate is provided with a blind groove 16, and four wedge-shaped through holes 17 are arranged around it. The silicon carbide sealing cover plate is bonded to the top of the silicon carbide epitaxial wafer.

[0067] It should be understood that the silicon carbide sealing cover plate can be front-bonded to the silicon carbide epitaxial wafer to form a front packaging structure, which can realize a leadless packaging structure of the sensor and improve the natural frequency of the sensor. The use of silicon carbide homogenous bonding, with the same thermal expansion coefficient, can reduce the stress at the bonding interface and increase the application temperature of the sensor to above 500°C.

[0068] The pressure sensor chip of the present application improves the electrical insulation performance and reduces signal interference through the design of multiple layers of silicon carbide structure and silicon dioxide layer 12, thereby improving the accuracy of pressure measurement. At the same time, the ring-shaped stepped pressure cavity 15 and the silicon carbide sealing cover plate cooperate to help distribute pressure uniformly, optimize the response stability and sensitivity of the sensor, and solve the problem that the silicon carbide pressure sensor chip is difficult to meet the high-precision pressure measurement requirement.

[0069] In some embodiments, the n-type isolation channel 9 and the p-type isolation channel 7 have the same width; the four n-type silicon carbide varistors 10 have the same resistance and are distributed along the periphery of the annular stepped pressure cavity 15; the n-type silicon carbide varistors 10 have a π-shaped structure to improve the pressure sensing capability and measurement accuracy.

[0070] It should be understood that the n-type silicon carbide varistors 10 having a π-shaped structure means that the cross section of the resistor is designed to be π-shaped, which can ensure that the four varistors have the same resistance, fully considers the lateral strain and longitudinal strain, and at the same time realizes that the resistance strip leads 11 have the same pattern and are symmetrically distributed outside the stress area, thereby reducing the measurement error caused by the asymmetric structure design and improving the measurement accuracy.

[0071] By using n-type and p-type isolation channels with the same width, the uniformity of electrical isolation can be improved; the four varistors with the same resistance and distributed along the periphery of the cavity can reduce the influence of temperature change on the output and improve the measurement consistency; the π-shaped varistors can enhance the strain sensing capability, thereby improving the sensitivity and accuracy of pressure measurement.

[0072] In some embodiments, the silicon carbide epitaxial wafer is a double-throw wafer, and the total thickness of the silicon carbide epitaxial wafer is 300-500 microns; the thickness of the p-type silicon carbide bonding layer 5 is 200 nanometers to 2 microns, and the corresponding doping concentration is 3×10 15 cm3 to 3×10 18 cm3; the thickness of the n-type silicon carbide device layer 4 is 200 nanometers to 2 microns, and the corresponding doping concentration is 1×10 19 cm3 to 3×10 20 cm3; the thickness of the p-type silicon carbide isolation layer 3 is 200 nanometers to 5 microns, and the corresponding doping concentration is 3×10 15 cm3 to 3×10 18 cm3; the thickness of the n-type silicon carbide buffer layer 2 is 200 nanometers to 2 microns, and the corresponding doping concentration is 3×10 15 cm3 to 3×10 18 cm3; the thickness of the n-type silicon carbide substrate 1 is 300-500 microns.

[0073] It should be understood that the thickness of 200 nanometers to 2 microns and the corresponding doping concentration of 3×10 15 cm3 to 3×10 18The n-type silicon carbide buffer layer 2 with a volume of 1 cubic centimeter can relieve stress and inhibit defect generation. Stress can be generated between the silicon carbide substrate and the epitaxial layer due to the difference in lattice constants (for example, lattice mismatch caused by the difference in concentration between the substrate and the epitaxial layer), and the buffer layer can release this stress through its own structure to prevent cracks, dislocations and other defects in the epitaxial layer due to stress concentration, thereby ensuring the structural integrity of the epitaxial layer. On the other hand, it can block the diffusion of defects and improve the purity of the epitaxial layer. Native defects such as dislocations and microtubules in the substrate can diffuse to the epitaxial layer, and the buffer layer can effectively block the transmission of these defects, reduce the defect density in the epitaxial layer, and improve the crystal quality of the epitaxial layer, thereby improving the yield of the device, such as reducing the leakage current and avoiding failure. The thickness is 200 nanometers to 5 microns, and the corresponding doping concentration is 3×10 15 1 cubic centimeter to 3×10 18 The p-type silicon carbide isolation layer 3 with a volume of 1 cubic centimeter has a thickness of 200 nanometers to 2 microns, and a corresponding doping concentration of 1×10 19 1 cubic centimeter to 3×10 20 The n-type silicon carbide device layer 4 with a volume of 1 cubic centimeter can ensure that the p-type silicon carbide isolation layer 3 and the n-type silicon carbide device layer 4 form a PN junction to achieve isolation between the n-type silicon carbide device layer 4 and the substrate; at the same time, the n-type silicon carbide voltage-dependent resistor 10 can have a high sensitivity output and a low temperature drift characteristic.

[0074] In some embodiments, the four n-type silicon carbide voltage-dependent resistors 10 are connected in sequence through four resistance strip leads 11, and the patterns of the four resistance strip leads 11 are completely the same and symmetrically distributed outside the stress area to form a closed bridge type Wheatstone bridge.

[0075] By connecting the four voltage-dependent resistors in sequence through the same resistance strip leads 11 and symmetrically distributing them outside the stress area, the consistency and positional symmetry of the lead patterns can be achieved, thereby reducing the influence of process deviation and uneven stress distribution on the balance of the bridge. The closed bridge type Wheatstone bridge can improve the stability of the output signal, improve the common mode noise rejection capability, and thus improve the accuracy and reliability of the pressure measurement.

[0076] In some embodiments, the thickness of the silicon dioxide layer 12 is 50 nanometers to 200 nanometers; and the metal electrode layer 14 includes at least one metal combination of titanium, platinum, tungsten, titanium nitride and gold.

[0077] It should be understood that the oxidation rate of the silicon carbide material is low, the dielectric constant is large, the thickness of the 50-200 nm silicon dioxide layer 12 can realize the electrical insulation of the metal electrode layer 14 and the p-type silicon carbide bonding layer 5, reduce the processing cost, and at the same time, can solidify the movable ions and interface defects of the silicon carbide and the silicon dioxide interface, resist micro-mechanical scratches and particle impacts, enhance the protection of the device layer, block the penetration of corrosive media such as water and chloride ions, enhance the insulation barrier, and reduce the leakage current.

[0078] The thickness range of the silicon dioxide layer 12 helps to reduce the stress of the dielectric layer while providing sufficient electrical insulation capability, thereby optimizing the reliability of the device during long-term operation; the selected material combination of the metal electrode layer 14 can take into account good ohmic contact, adhesion and anti-electromigration performance, which helps to improve the stability of the electrode structure and the quality of signal transmission.

[0079] In some embodiments, the inner wall and / or the outer wall of the annular stepped pressure cavity 15 are annular stepped structures; the annular stepped structure has one or more annular steps, and when there are multiple annular steps, the multiple annular steps are concentric annular steps.

[0080] It should be understood that due to the uneven distribution of energy within the laser spot, the energy is strong at the center and weak at the edge, and as the laser processing depth increases, the verticality of the side wall decreases, the pressure cavity pattern deforms, and then the stress distribution of the pressure sensitive diaphragm is uneven, which affects the measurement accuracy. The annular step is set to one or more, which avoids the problem of poor bottom corner verticality caused by excessive depth, helps to improve the verticality of the side wall of the pressure cavity, and ensures the pattern fidelity of the cavity; when there are multiple concentric annular steps, the uniformity of the stress distribution can be further optimized, thereby improving the structural stability and measurement consistency of the pressure sensor under high pressure or cyclic load conditions.

[0081] In some embodiments, the depth of the annular stepped pressure cavity 15 is 250-480 microns, the annular step can be set to multiple, and the height of each step can be 50-200 microns, and the depth of the dry etching is 5-10 microns.

[0082] It should be understood that the 250-480 micron processing depth can cover the low, medium and high range of the pressure sensor chip measurement range, meeting the measurement needs of different pressure environments. The multiple annular steps and the 50-200 micron step height can fully ensure the verticality of the side wall of the pressure cavity and the pattern fidelity of the cavity. The 5-10 micron dry etching depth can effectively remove the damage layer caused by laser processing, significantly improving the surface quality and mechanical strength of the pressure cavity.

[0083] In some embodiments, the wedge-shaped through hole 17 is formed near the metal electrode layer 14 of the silicon carbide sealing cover plate; the blind groove 16 is formed near the annular stepped pressure cavity 15 of the silicon carbide sealing cover plate; the silicon carbide sealing cover plate and the p-type silicon carbide bonding layer 5 are homogeneously bonded by surface activation bonding technology, and the bonding strength is greater than 32 MPa.

[0084] By placing the wedge-shaped through-hole 17 near the metal electrode layer 14, the difficulty of electrode lead connection is reduced and the parasitic effect of signal transmission path is reduced; the blind slot 16 is located above the annular stepped pressure cavity 15, which can optimize the uniformity of pressure transmission and improve the consistency of sensor response; the use of surface activation bonding technology to achieve homogeneous bonding between the silicon carbide sealing cover and the bonding layer, the bonding strength helps to improve the hermeticity of the package and the stability of the interface, thereby enhancing the long-term reliability of the device in harsh environments.

[0085] This application also provides a method for fabricating a pressure sensor chip, used to process the pressure sensor chip of the above embodiments, the method including:

[0086] S100: A five-layer double-polished silicon carbide epitaxial wafer is selected as the processing substrate. The silicon carbide epitaxial wafer includes, from top to bottom, a p-type silicon carbide bonding layer 5, an n-type silicon carbide device layer 4, a p-type silicon carbide isolation layer 3, an n-type silicon carbide buffer layer 2, and an n-type silicon carbide substrate 1.

[0087] S200: The p-type silicon carbide bonding layer 5 is etched using a dry etching process to form the metal electrode opening region 6, the p-type isolation channel 7, and the bonding region 8.

[0088] S300: The n-type silicon carbide device layer 4 is etched using a dry etching process to form an n-type isolation channel 9, four resistive leads 11, and four n-type silicon carbide varistors 10.

[0089] S400: A silicon dioxide layer 12 is grown on the surface of a silicon carbide epitaxial wafer using a thermal oxidation process.

[0090] S500: The silicon dioxide layer 12 is etched using a dry etching process to preserve the sidewalls of the p-type isolation channel 7, the sidewalls of the n-type isolation channel 9, and the oxide layer of the passivation region 13.

[0091] S600: A metal electrode layer 14 is formed on the metal electrode opening area 6 by using a stripping process combined with electron beam evaporation, and then annealing is performed to form an ohmic contact.

[0092] S700: The bottom of the n-type silicon carbide substrate 1 is etched using a multi-laser processing technique to form an annular stepped pressure cavity 15, and the laser-damaged layer is removed by a deep dry etching technique.

[0093] See Figure 2(a) Figure is a schematic diagram of step S100; (b) Figure is a schematic diagram of step S200; (c) Figure is a schematic diagram of step S300; (d) Figure is a schematic diagram of step S400; (e) Figure is a schematic diagram of step S500; (f) Figure is a schematic diagram of step S600; (g) Figure is a schematic diagram of step S700; (h) Figure is a schematic diagram of step S800; (i) Figure is a schematic diagram of step S900.

[0094] It should be understood that femtosecond lasers can be used in laser processing, with pulse widths controlled between 190 and 350 femtoseconds, effectively reducing the heat-affected zone and improving processing accuracy. Single-pulse energy ranges from 5 to 57 microjoules, avoiding edge chipping defects. Average power is set between 0.75 and 1.5 watts, scanning speed between 15 and 50 millimeters per second, spacing between adjacent processing lines is maintained at 20 to 50 micrometers, and spot diameter is between 1 and 20 micrometers. Deep dry etching technology uses inductively coupled plasma etching or reactive ion etching processes, with etching power selectable from 1000 to 1500 watts, RF bias voltage selectable from 100 to 300 watts, and operating pressure selectable from 0.34 to 1 Pa. The gas flow rates used are as follows: sulfur hexafluoride flow rate: 100 to 120 standard milliliters per minute; oxygen flow rate: 5 to 15 standard milliliters per minute (or 5% to 50% of the mixed gas volume fraction); if a combination of carbon tetrafluoride and oxygen is used, the carbon tetrafluoride flow rate is 100 to 120 standard milliliters per minute and the oxygen flow rate is 5 to 15 standard milliliters per minute. During the etching process, a sidewall protective layer is formed to reduce lateral etching, improve the aspect ratio, and the deep dry etching depth is 5 to 10 micrometers. This effectively removes the damage layer caused by laser processing and significantly improves the surface quality and mechanical strength of the pressure chamber.

[0095] S800: The silicon carbide material is etched using the first etching process to form blind trenches 16 and wedge-shaped through holes 17, and to obtain a silicon carbide sealing cover plate.

[0096] It should be understood that the primary etching gas in the deep silicon carbide etching process is sulfur hexafluoride (SF6). Fluorine radicals are generated through plasma decomposition, reacting with silicon carbide to form volatile silicon tetrafluoride (STF) and carbon (which requires removal by auxiliary gas). The etching rate is approximately 0.5 μm / min to 2 μm / min. The auxiliary gases are oxygen and argon. Oxygen is used to oxidize carbon impurities on the silicon carbide surface, increasing the etching rate; argon is used to dilute the plasma concentration, reducing excessive bombardment of the silicon carbide surface and preventing lattice damage. Simultaneously, argon ions can clean deposits (such as carbon particles) within the trenches, preventing blockage. The etching power is 1000 watts to 3000 watts, the bias power is 300 to 400 watts, the SF6 flow rate is 50 to 200 standard milliliters per minute, and the reaction chamber pressure is controlled at 5 mTorr to 20 mTorr. By precisely controlling these parameters, high-quality etching with an aspect ratio >20, sidewall perpendicularity <5°, and surface damage <10 nanometers can be achieved.

[0097] S900: The silicon carbide sealing cover plate and the p-type silicon carbide bonding layer 5 are homogeneously bonded using surface activation bonding technology.

[0098] It should be understood that surface activated bonding (SAB) is a key technology for achieving high-strength bonding of homogeneous silicon carbide materials at low / room temperature. Its core principle is to activate the silicon carbide surface, remove contaminants and oxide layers, and form strong covalent bonds under low-energy conditions. Surface activated bonding technology requires no chemical cleaning or annealing; by ion-activating the silicon carbide surface and annealing in the atmosphere, a bond can be achieved between the silicon carbide sealing cap and the p-type silicon carbide bonding layer, with a bonding strength >32 MPa, making it suitable for large-scale industrial production.

[0099] In some embodiments, argon ion / atomic beam bombardment is employed: at 10 -4 Up to 10 -7 In ultra-high vacuum, high-energy argon ions bombard the surface of silicon carbide. This process effectively removes the surface oxide layer and physically adsorbed organic / inorganic impurities, breaks silicon-carbon bonds to form dangling bonds, and significantly enhances surface reactivity. The ultra-high vacuum prevents oxygen and moisture in the air from re-contaminating the activated silicon carbide surface, ensuring bonding quality. The temperature is room temperature (25℃) or <200℃; room temperature bonding completely avoids thermal stress (the thermal expansion coefficient of silicon carbide is only 4.5 × 10⁻⁶). -6 / ℃), suitable for homogeneous bonding. Apply a vertical, uniform pressure of 4 MPa to 5 MPa, which must be uniformly transmitted through a custom-made graphite jig to avoid excessive local pressure that could cause wafer breakage. The bonding time is 300 seconds; too short a time will result in insufficient surface contact and low bonding strength; too long a time may introduce unnecessary heat accumulation.

[0100] The above-described preparation method, by selecting a five-layer silicon carbide epitaxial wafer as the substrate, helps to ensure material consistency and process compatibility; the dry etching process is used to form isolation channels and resistance patterns, which can improve etching accuracy and pattern uniformity, and reduce dimensional deviations; the thermal oxidation growth of silicon dioxide layer 12 combined with selective etching can optimize the insulation layer coverage quality and passivation effect; the metal electrode is prepared by lift-off process and electron beam evaporation and then annealed, which helps to form stable ohmic contacts and reduce contact resistance; the annular stepped pressure cavity 15 is formed by multiple laser processing and deep dry etching and the damaged layer is removed, which can reduce stress concentration introduced by processing and improve the integrity of the cavity structure; the use of surface activation bonding technology to achieve homogeneous bonding helps to improve the bonding strength and hermeticity of the packaging interface, thereby enhancing the overall reliability and measurement stability of the device.

[0101] In some embodiments, the first etching process employs one or more processes such as deep dry etching, laser processing, and mechanical polishing; both the dry etching process and the deep dry etching process employ inductively coupled plasma etching or reactive ion etching.

[0102] The first etching process employs a combination of various processing techniques, providing flexibility in process selection and helping to adapt to the processing requirements of different structural features. Both the dry etching process and the deep dry etching process use inductively coupled plasma etching or reactive ion etching, which can improve the accuracy and uniformity of the etched pattern, reduce sidewall roughness and material damage during the etching process, thereby improving the structural integrity and electrical performance stability of the device.

[0103] In some embodiments, the deep dry etching process has an etching power of 1000 W to 1500 W, an RF bias of 100 W to 300 W, an operating pressure of 0.34 Pa to 1 Pa, and a depth of 5 μm to 10 μm; the deep dry etching process uses a mixture of sulfur hexafluoride and oxygen or a mixture of carbon tetrafluoride and oxygen; if the deep dry etching process uses a mixture of sulfur hexafluoride and oxygen, the sulfur hexafluoride flow rate is 100 standard milliliters per minute to 120 standard milliliters per minute, and the oxygen flow rate is 5 standard milliliters per minute to 15 standard milliliters per minute; if the deep dry etching process uses a mixture of carbon tetrafluoride and oxygen, the carbon tetrafluoride flow rate is 100 standard milliliters per minute to 120 standard milliliters per minute, and the oxygen flow rate is 5 standard milliliters per minute to 15 standard milliliters per minute.

[0104] Deep dry etching process, by setting specific etching power, RF bias, working pressure and depth range, and combining sulfur hexafluoride and oxygen or carbon tetrafluoride and oxygen mixed gas and their flow control, helps to optimize etching rate and directionality, reduce sidewall roughness and lattice damage during etching, thereby improving the etching pattern accuracy and structural integrity, and enhancing device performance consistency and stability.

[0105] In some embodiments, during the deep dry etching process, an oxide layer is formed on the sidewall by controlling the gas composition and etching parameters to reduce lateral etching and improve the aspect ratio.

[0106] By controlling the gas composition and etching parameters to form an oxide layer on the sidewall, it is helpful to suppress lateral etching, improve the verticality and aspect ratio of the etched structure, thereby improving the pattern transfer accuracy and structural size consistency, and enhancing the performance stability of the device at the microscale.

[0107] As can be seen from the above technical solutions, the embodiments of this application provide a pressure sensor chip and its fabrication method. A five-layer double-polished silicon carbide epitaxial wafer is selected as the processing substrate. A dry etching process is used to etch the p-type silicon carbide bonding layer 5 to form the metal electrode opening region 6, the p-type isolation channel 7, and the bonding region 8. A dry etching process is used to etch the n-type silicon carbide device layer 4 to form the n-type isolation channel 9, four resistive leads 11, and four n-type silicon carbide varistors 10. A silicon dioxide layer 12 is grown on the surface of the silicon carbide epitaxial wafer using a thermal oxidation process. The silicon dioxide layer 12 is then etched using a dry etching process to retain the sidewalls of the p-type isolation channel 7 and the n-type isolation channel 9. The oxide layer in the wall and passivation region 13 is formed; a metal electrode layer 14 is formed on the metal electrode opening region 6 using a lift-off process combined with electron beam evaporation, and then annealed to form an ohmic contact; the bottom of the n-type silicon carbide substrate 1 is etched using a multi-laser processing process to form an annular stepped pressure cavity 15, and the laser damage layer is removed by a deep dry etching technique; the silicon carbide material is etched using a first etching process to form a blind trench 16 and a wedge-shaped through hole 17, and a silicon carbide sealing cover is obtained; the silicon carbide sealing cover is homogeneously bonded to the p-type silicon carbide bonding layer 5 using surface activation bonding technology to solve the problem that silicon carbide pressure sensor chips cannot meet the requirements of high-precision pressure measurement.

[0108] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.

Claims

1. A pressure sensor chip, characterized in that, include: Silicon carbide epitaxial wafer, silicon dioxide layer (12), metal electrode layer (14) and silicon carbide sealing cover plate; The silicon carbide epitaxial wafer includes, from top to bottom, a p-type silicon carbide bonding layer (5), an n-type silicon carbide device layer (4), a p-type silicon carbide isolation layer (3), an n-type silicon carbide buffer layer (2), and an n-type silicon carbide substrate (1). The p-type silicon carbide bonding layer (5) is etched to form a metal electrode opening area (6), a p-type isolation channel (7), and a bonding area (8); The n-type silicon carbide device layer (4) is etched to form an n-type isolation channel (9), a barrier lead (11), and four n-type silicon carbide varistors (10); the n-type isolation channel (9) is disposed at the bottom of the p-type isolation channel (7), and a p-type silicon carbide bonding layer (5) is disposed on the top of the n-type silicon carbide varistors (10). The silicon dioxide layer (12) is disposed on the sidewalls of the p-type isolation channel (7) and the n-type isolation channel (9), and in the passivation area (13) where the wedge-shaped through hole (17) does not contact the p-type silicon carbide bonding layer (5). The metal electrode layer (14) is disposed in the metal electrode opening area (6) and is in contact with the n-type silicon carbide device layer (4); The bottom of the n-type silicon carbide substrate (1) is etched to form an annular stepped pressure cavity (15). The silicon carbide sealing cover plate has a blind groove (16) in the center and four wedge-shaped through holes (17) around it. The silicon carbide sealing cover plate is bonded to the top of the silicon carbide epitaxial wafer.

2. The pressure sensor chip according to claim 1, characterized in that, The n-type isolation channel (9) and the p-type isolation channel (7) have the same width; the four n-type silicon carbide varistors (10) have the same resistance and are distributed around the annular stepped pressure cavity (15); the n-type silicon carbide varistors (10) have a π-shaped structure to improve pressure sensing capability and measurement accuracy.

3. The pressure sensor chip according to claim 2, characterized in that, The four n-type silicon carbide varistors (10) are connected in sequence by four resistance strip leads (11), and the four resistance strip leads (11) are identical in pattern and symmetrically distributed outside the stress zone to form a closed-bridge Wheatstone bridge.

4. The pressure sensor chip according to claim 1, characterized in that, The thickness of the silicon dioxide layer (12) is 50 nanometers to 200 nanometers; the metal electrode layer (14) comprises at least one metal combination selected from titanium, platinum, tungsten, titanium nitride and gold.

5. The pressure sensor chip according to claim 1, characterized in that, The inner and / or outer walls of the annular stepped pressure chamber (15) have an annular stepped structure. The annular stepped structure has one or more annular steps, and when there are multiple annular steps, the multiple annular steps are concentric annular steps.

6. The pressure sensor chip according to claim 1, characterized in that, The wedge-shaped through hole (17) is formed on the silicon carbide sealing cover plate near the metal electrode layer (14); the blind groove (16) is formed on the silicon carbide sealing cover plate near the annular stepped pressure cavity (15). The silicon carbide sealing cover and the p-type silicon carbide bonding layer (5) are homogeneously bonded by surface activated bonding (SAB) technology, with a bonding strength greater than 32 MPa.

7. A method for fabricating a pressure sensor chip, characterized in that, The method for processing the pressure sensor chip according to any one of claims 1-6 includes: A five-layer double-polished silicon carbide epitaxial wafer is selected as the processing substrate. The silicon carbide epitaxial wafer includes, from top to bottom, a p-type silicon carbide bonding layer (5), an n-type silicon carbide device layer (4), a p-type silicon carbide isolation layer (3), an n-type silicon carbide buffer layer (2), and an n-type silicon carbide substrate (1). The p-type silicon carbide bonding layer (5) is etched using a dry etching process to form a metal electrode opening region (6), a p-type isolation channel (7), and a bonding region (8). The n-type silicon carbide device layer (4) is etched using a dry etching process to form an n-type isolation channel (9), four barrier leads (11) and four n-type silicon carbide varistors (10). A silicon dioxide layer was grown on the surface of the silicon carbide epitaxial wafer using a thermal oxidation process (12). The silicon dioxide layer (12) is etched using a dry etching process to preserve the oxide layers of the p-type isolation channel (7), the n-type isolation channel (9), and the passivation region (13); A metal electrode layer (14) is formed on the metal electrode opening area (6) by a stripping process combined with electron beam evaporation, and then annealed to form an ohmic contact; The bottom of the n-type silicon carbide substrate (1) is etched by multiple laser processing techniques to form an annular stepped pressure cavity (15), and the laser-damaged layer is removed by deep dry etching technology. The silicon carbide material is etched using the first etching process to form blind trenches (16) and wedge-shaped through holes (17), and a silicon carbide sealing cover is obtained; The silicon carbide sealing cover plate and the p-type silicon carbide bonding layer (5) are homogeneously bonded using surface activation bonding technology.

8. The method for fabricating a pressure sensor chip according to claim 7, characterized in that, The first etching process employs one or more of the following processes: deep dry etching, laser processing, and mechanical polishing; both the dry etching process and the deep dry etching process employ inductively coupled plasma etching or reactive ion etching.

9. The method for fabricating a pressure sensor chip according to claim 8, characterized in that, The deep dry etching process has an etching power of 1000 watts to 1500 watts, an RF bias of 100 watts to 300 watts, an operating pressure of 0.34 Pa to 1 Pa, and a depth of 5 micrometers to 10 micrometers; the deep dry etching process uses a mixed gas of sulfur hexafluoride and oxygen or a mixed gas of carbon tetrafluoride and oxygen. If the deep dry etching process uses a mixture of sulfur hexafluoride and oxygen, the sulfur hexafluoride flow rate is 100 to 120 standard milliliters per minute and the oxygen flow rate is 5 to 15 standard milliliters per minute. If the deep dry etching process uses a mixture of carbon tetrafluoride and oxygen, the carbon tetrafluoride flow rate is 100 to 120 standard milliliters per minute and the oxygen flow rate is 5 to 15 standard milliliters per minute.

10. The method for fabricating a pressure sensor chip according to claim 9, characterized in that, In the deep dry etching process, an oxide layer is formed on the sidewall by controlling the gas composition and etching parameters to reduce lateral etching and improve the aspect ratio.

Images