A chip access verification method, device, medium and program product

Abstract

The application discloses a chip memory access verification method, device, medium and program product, and relates to the technical field of artificial intelligence, to solve the technical problem that the memory access verification of the memory access unit of a chip is insufficient in related technologies. The method issues unified memory access instructions to each target thread group currently to be run by the to-be-tested memory access unit, thereby realizing the uniformity of the number of memory access instructions issued by each target thread group and the content of the access instructions without affecting the memory access verification. The number of memory access instructions issued by each target thread group and the content of the access instructions can be used to detect whether each target thread group has executed the corresponding unified memory access instruction, so that the end time of the execution of the unified memory access instruction by each target thread group can be determined. Therefore, the memory access verification can be performed based on the to-be-tested memory data generated by each target thread group in a timely manner, and the memory access verification of the memory access unit can be fully performed, thereby ensuring the reliability of the memory access verification of the memory access unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence, and in particular to a chip memory access verification method, an electronic device, a computer readable storage medium and a computer program product. BACKGROUND

[0002] The parallel computing capability of a chip is embodied in the parallel execution of tasks by a large number of threads, wherein a plurality of TGs (Thread Groups) are dispatched to the same memory access unit for execution, and there can be a plurality of contexts executing on the same memory access unit at the same time. In order to ensure the parallel computing capability of the chip, the memory access unit of the chip needs to be fully verified.

[0003] In the related art, the memory access unit of the chip is verified by first configuring a single or multiple contexts and a plurality of TGs corresponding thereto, and then randomly selecting the configured contexts and TGs to issue memory access instructions according to a pre-configured total number of memory access instructions. However, this memory access verification method cannot control the number of memory access instructions issued for each TG, which results in the inability to check the intermediate memory data of each TG in a timely manner, thereby leading to insufficient memory access verification of the memory access unit of the chip. SUMMARY

[0004] The present application provides a chip memory access verification method, device, medium and program product to solve the technical problem of insufficient memory access verification of the memory access unit of the chip in the related art.

[0005] To solve the above technical problem, the first aspect of the present application provides a chip memory access verification method, comprising:

[0006] issuing a unified memory access instruction corresponding to each target thread group currently to be run to the to-be-tested memory access unit, to instruct the to-be-tested memory access unit to run the target thread group to execute the unified memory access instruction; wherein each target thread group corresponds to one or more context programs currently executed by the to-be-tested memory access unit;

[0007] obtaining to-be-tested memory data generated when the target thread group executes the unified memory access instruction;

[0008] verifying the to-be-tested memory access unit based on the to-be-tested memory data.

[0009] As a preferred solution, before the step of issuing a unified memory access instruction corresponding to each target thread group currently to be run to the to-be-tested memory access unit, the method further comprises:

[0010] issuing one or more context programs to the to-be-tested memory access unit;

[0011] According to a preset thread group issuing condition, at least one target thread group corresponding to at least one context program is issued to the to-be-tested memory unit.

[0012] As a preferred solution, the step of issuing one or more context programs to the to-be-tested memory unit specifically comprises:

[0013] Based on a pre-configured context program group, at least two context programs currently to be issued and an execution mode of each context program are determined;

[0014] When the execution mode is a serial execution mode and the to-be-tested memory unit is in an idle state, a target context program is determined from each context program currently to be issued and is issued to the to-be-tested memory unit; this step is repeated until each context program in the context program group is issued.

[0015] When the execution mode is a parallel execution mode and a current number of context programs executed by the to-be-tested memory unit is less than a preset parallel execution number threshold, at least one target context program having the same configuration parameters as a context program currently executed by the to-be-tested memory unit is determined from each context program currently to be issued and is issued to the to-be-tested memory unit; this step is repeated until each context program in the context program group is issued.

[0016] As a preferred solution, the thread group issuing condition specifically comprises that a current number of thread groups issued by the to-be-tested memory unit is less than a preset thread group issuing number threshold, and a thread group available memory address space of the to-be-tested memory unit is greater than or equal to a memory address space occupation amount of a target thread group currently to be issued.

[0017] As a preferred solution, the method further comprises:

[0018] When it is detected that the target thread group executes the uniform memory instruction, at least one target thread group corresponding to at least one context program currently executed by the to-be-tested memory unit is reissued to the to-be-tested memory unit until each target thread group corresponding to each context program currently executed by the to-be-tested memory unit executes the uniform memory instruction.

[0019] As a preferred solution, the method further comprises:

[0020] When the to-be-tested memory data is acquired, a memory address space of the to-be-tested memory unit currently occupied by the target thread group is recycled.

[0021] As a preferred solution, the method further comprises:

[0022] When it is detected that each of the target thread groups corresponding to any one of the context programs currently executed by the to-be-tested memory unit is executed to completion of the unified memory instruction, the resources occupied by the any one of the context programs are recycled.

[0023] As a preferred solution, the unified memory instruction comprises at least one of a read request instruction and a write request instruction.

[0024] The method specifically detects whether the target thread groups are executed to completion of the unified memory instruction by the following steps:

[0025] When the unified memory instruction is a read request instruction, and the memory read data corresponding to the read request instruction is received from the to-be-tested memory unit, it is determined that the target thread groups are executed to completion of the read request instruction.

[0026] When the unified memory instruction is a write request instruction, a synchronization instruction is issued to the to-be-tested memory unit; wherein the synchronization instruction is used to instruct the to-be-tested memory unit to feed back the synchronization response information corresponding to the synchronization instruction when the target thread groups are executed to completion of the write request instruction.

[0027] When the synchronization response information is received, it is determined that the target thread groups are executed to completion of the write request instruction.

[0028] As a preferred solution, the to-be-tested memory data generated when the target thread groups are executed to completion of the unified memory instruction specifically comprises:

[0029] A data read request is sent to the to-be-tested memory unit; wherein the data read request is used to instruct the to-be-tested memory unit to read the memory write data generated when the target thread groups are executed to completion of the write request instruction from the memory and return;

[0030] The memory write data returned by the to-be-tested memory unit in response to the data read request is acquired;

[0031] Or, the memory write data generated when the target thread groups are executed to completion of the write request instruction is directly acquired from the memory of the to-be-tested memory unit;

[0032] Based on the memory read data and the memory write data, the to-be-tested memory data is determined.

[0033] As a preferred solution, the to-be-tested memory unit is verified based on the to-be-tested memory data, specifically comprising:

[0034] The to-be-tested memory data is compared with reference memory data;

[0035] When the to-be-tested access data is inconsistent with the reference access data, it is determined that the access verification of the to-be-tested access unit fails.

[0036] The second aspect of the embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the chip access verification method of any one of the first aspect when executing the computer program.

[0037] The third aspect of the embodiment of the present application provides a computer readable storage medium comprising a stored computer program, wherein the computer readable storage medium controls the device where the computer readable storage medium is located to execute the chip access verification method of any one of the first aspect when the computer program is running.

[0038] The fourth aspect of the embodiment of the present application provides a computer program product comprising at least one of a computer program and computer instructions, and the at least one of the computer program and the computer instructions is executed by a processor to implement the steps of the chip access verification method of any one of the first aspect.

[0039] Compared with the prior art, the embodiment of the present application has the beneficial effect that by issuing unified access instructions to each target thread group currently to be run by the to-be-tested access unit, the number of access instructions issued to each target thread group and the access instruction content are unified without affecting the access verification, and each target thread group can be detected based on the number of access instructions issued by each target thread group and the access instruction content to determine whether each target thread group has executed the corresponding unified access instruction, so that the execution end time of each target thread group for the unified access instruction is determined, and therefore when the target thread group executes the unified access instruction, the access verification can be performed based on the to-be-tested access data generated by each target thread group in time, and the access unit can be fully verified, thereby ensuring the reliability of the access verification of the access unit. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a flowchart of the chip access verification method in the embodiment of the present application;

[0041] Figure 2 is a thread group number configuration diagram of the context program in the embodiment of the present application;

[0042] Figure 3 is a chip access verification flowchart in the embodiment of the present application;

[0043] Figure 4 is a structure diagram of the chip access verification device in the embodiment of the present application;

[0044] Figure 5 is a structural schematic diagram of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0046] Please refer to Figure 1 The first aspect of the embodiments of the present application provides a chip memory access verification method, comprising the following steps S1 to S3.

[0047] In step S1, a unified memory access instruction corresponding to each target thread group currently to be run is issued to a to-be-tested memory access unit, to instruct the to-be-tested memory access unit to run the target thread group to execute the unified memory access instruction; wherein each target thread group corresponds to one or more context programs currently executed by the to-be-tested memory access unit.

[0048] In step S2, to-be-tested memory access data generated when the target thread group executes the unified memory access instruction is obtained.

[0049] In step S3, memory access verification is performed on the to-be-tested memory access unit based on the to-be-tested memory access data.

[0050] It is worth noting that in the present embodiment, the chip containing the above-mentioned to-be-tested memory access unit can be a GPU (Graphic Processing Unit), a GPGPU (General Purpose GPU) or other parallel processors, which are not specifically limited in the present embodiment. When designing a chip, the instruction set architecture of the chip is usually defined according to the requirements of the target application, including supported instruction sets, register organization, memory mapping, etc. At the same time, the memory access logic of the chip is also implemented, including memory interface, data path, etc. The memory access verification in the present embodiment needs to verify whether the to-be-tested memory access unit in the to-be-tested chip can correctly implement memory access operations in the case of multi-task, multi-thread parallel access.

[0051] In actual use, although the instructions corresponding to each context program can be different, uniformizing the memory access instructions has little effect on the memory access verification result. Therefore, the embodiment further issues the uniform memory access instructions corresponding to the current target thread groups to be run to the to-be-tested memory unit after issuing the target thread groups to the to-be-tested memory unit. It should be noted that a thread group (TG) is composed of multiple warps, and a warp is a set of threads that share the same instruction stream during execution. These threads run the same instructions simultaneously in a single instruction multiple thread (SIMT) manner, but process different data. For example, in some artificial intelligence chips, a warp usually contains 32 threads. In addition, the multiple context programs configured in the embodiment can be configured in a serial execution mode or a parallel execution mode. Therefore, the target thread groups issued to the to-be-tested memory unit can correspond to the same context program, or two or more different context programs, which are not limited in the embodiment.

[0052] By issuing the uniform memory access instructions, the to-be-tested memory unit is instructed to run the target thread groups to execute the corresponding uniform memory access instructions, thereby generating the to-be-tested memory data corresponding to the memory operations. It can be understood that the uniform memory access instructions in the embodiment can be at least one of read request instructions, write request instructions, and other types of memory request instructions. When it is detected that the target thread groups have executed the uniform memory access instructions, the memory access verification needs to be performed based on the to-be-tested memory data generated thereby. It should be noted that the related art cannot determine when the target thread groups execute the corresponding memory access instructions because the number of memory access instructions issued to each thread group is uncontrollable. Therefore, the related art can only check uniformly at the end of the test case, thereby failing to check the intermediate memory data of the execution of each thread group in time, making it easy to cover up the problems and leading to insufficient memory access verification. The embodiment can verify the memory data according to the thread group granularity, thereby making the memory access verification of the to-be-tested memory unit more sufficient.

[0053] The chip access verification method provided by the embodiment of the present application can realize the uniformity of the number of access instructions and the content of access instructions issued to each target thread group without affecting the access verification, can detect whether each target thread group has executed the corresponding uniform access instruction based on the number of access instructions and the content of access instructions issued by each target thread group, can determine the execution end time of each target thread group for the uniform access instruction, and can perform access verification based on the to-be-tested access data generated by each target thread group when detecting that the target thread group has executed the uniform access instruction, thereby fully verifying the access unit and ensuring the reliability of the access verification of the access unit.

[0054] As a preferred solution, before the uniform access instruction corresponding to each target thread group currently to be executed is issued to the to-be-tested access unit, the method further comprises:

[0055] issuing one or more context programs to the to-be-tested access unit;

[0056] issuing at least one target thread group corresponding to at least one context program to the to-be-tested access unit according to a preset thread group issuing condition.

[0057] Specifically, one or more context programs are issued to the to-be-tested access unit according to the execution mode of each to-be-issued context program currently configured. Further, since the number of thread groups corresponding to each context program is different, as shown in Table 1, Figure 2 Figure 2 In Table 1, there are three contexts, namely context0, context1 and context2, wherein context0 corresponds to two TGs, namely TG0 and TG1; context1 corresponds to three TGs, namely TG2, TG3 and TG4; and context2 corresponds to four TGs, namely TG5, TG6, TG7 and TG8. The embodiment does not specifically limit the number of to-be-issued context programs and the number of thread groups corresponding to each context program.

[0058] ​Further, based on each context program issued to the to-be-tested memory unit, the embodiment needs to issue at least one target thread group corresponding to at least one context program to the to-be-tested memory unit according to the thread group. It can be understood that, in the case where the execution mode of the context program is a serial execution mode, the to-be-tested memory unit only executes one context program at the same time, and therefore the to-be-tested memory unit needs to be issued one or more target thread groups corresponding to the context program currently executed by the to-be-tested memory unit. In the case where the execution mode of the context program is a parallel execution mode, the to-be-tested memory unit can execute multiple context programs at the same time, for example, 2, 3, 4, 5, etc. context programs in parallel, which are not specifically limited in the embodiment, and therefore the to-be-tested memory unit needs to be issued target thread groups corresponding to one or more context programs currently executed by the to-be-tested memory unit.

[0059] As a preferred solution, the issuing of the one or more context programs to the to-be-tested memory unit specifically includes:

[0060] Based on the pre-configured context program group, at least two context programs to be currently issued and the execution mode of each context program are determined.

[0061] When the execution mode is a serial execution mode and the to-be-tested memory unit is in an idle state, a target context program is determined from each context program to be currently issued and is issued to the to-be-tested memory unit. This step is repeated until each context program in the context program group is issued.

[0062] When the execution mode is a parallel execution mode and the number of context programs currently executed by the to-be-tested memory unit is less than a preset parallel execution number threshold, at least one target context program with the same configuration parameters as the context program currently executed by the to-be-tested memory unit is determined from each context program to be currently issued and is issued to the to-be-tested memory unit. This step is repeated until each context program in the context program group is issued.

[0063] Specifically, the embodiment additionally defines a context program group containing multiple context programs to be issued, and configures the number of thread groups corresponding to each context program. The context programs in the context program group can all be configured in a serial execution mode or a parallel execution mode. For the multiple context programs configured in a parallel execution mode, the configuration parameters need to be consistent, including a memory size (a memory address space configuration parameter) and a tensor core enabling configuration parameter (a tensor calculation unit enabling configuration parameter).

[0064] When the context program needs to be issued, when the execution mode is the serial execution mode, and the to-be-tested memory unit is in an idle state, i.e., the current to-be-tested memory unit does not execute any context program, at this time, each context program currently to be issued can participate in the issuance arbitration to determine a target context program therefrom. In an optional embodiment, the System Verilog Semaphore mechanism is used to determine a target context program from each context program currently to be issued. Specifically, in the serial execution mode, the Semaphore is used to realize the resource competition control, and the number of available permissions is set to 1, so that each context program currently to be issued simultaneously calls the get function to compete for the only permission, and finally only one context program can acquire the permission, as the target context program currently issued to the to-be-tested memory unit, and the remaining context programs wait until the target context program ends the execution, calls the put function to return the permission, and then calls the get function to compete for the issuance. Repeat the context program issuance step in the serial execution mode until each context program in the context program group is issued.

[0065] When the execution mode is the parallel execution mode and the current number of context programs executed by the to-be-tested memory access unit is less than the preset parallel execution number threshold, it can be understood that the parallel execution number supported by the to-be-tested memory access unit is predetermined, for example, the parallel execution number is 2, 4, 8, etc., which is not limited in the embodiment. If the current number of context programs executed is less than the preset parallel execution number threshold, it indicates that the number of context programs currently executed by the to-be-tested memory access unit does not reach the upper limit of the parallel execution number of the context programs. At this time, in order to avoid resource conflicts and ensure that the parallel tasks can be executed cooperatively, the embodiment determines at least one target context program from the current to-be-issued context programs, which has the same configuration parameters as the context program currently executed by the to-be-tested memory access unit. It can be understood that the number of target context programs issued to the to-be-tested memory access unit depends on the difference between the current number of context programs executed and the parallel execution number threshold. In an optional embodiment, the System Verilog Semaphore mechanism is used to determine at least one target context program from the current to-be-issued context programs. Specifically, in the parallel execution mode, the number of available permissions can be set based on the difference between the current number of context programs executed and the parallel execution number threshold. For example, if the difference between the current number of context programs executed and the parallel execution number threshold is 2, it indicates that 2 target context programs can be issued and executed in parallel at the current time, and therefore the number of available permissions is set to 2, which will not be described in detail herein. By simultaneously calling the get function from the current to-be-issued context programs which have the same configuration parameters as the context program currently executed by the to-be-tested memory access unit, the number of context programs executed by the to-be-tested memory access unit can be ensured to be equal to the parallel execution number threshold after the target context program is issued. On the one hand, this can improve the memory access verification efficiency, and on the other hand, it can maximize the stress test of the to-be-tested memory access unit and ensure that the memory access verification of the to-be-tested memory access unit is more sufficient. When the current number of context programs executed by the to-be-tested memory access unit is equal to the preset parallel execution number threshold, the issuance of the context program to the to-be-tested memory access unit is stopped, and after the execution of any one of the issued context programs is completed, the context program issuance step in the parallel execution mode is continued until all the context programs in the context program group are issued.

[0066] As a preferred solution, the thread group issuance condition is specifically that the current number of thread groups issued by the to-be-tested memory access unit is less than the preset thread group issuance number threshold, and the available memory address space of the current thread group of the to-be-tested memory access unit is greater than or equal to the memory address space occupation amount of the target thread group to be issued at present.

[0067] Specifically, the to-be-tested memory access unit in the embodiment is pre-configured with a thread group issuing quantity threshold to limit the number of thread groups running in parallel in the to-be-tested memory access unit. When issuing a thread group to the to-be-tested memory access unit, it is required to ensure that the current thread group issuing quantity of the to-be-tested memory access unit is less than the preset thread group issuing quantity threshold, and the available memory address space of the current thread group of the to-be-tested memory access unit is greater than or equal to the memory address space occupation of the target thread group to be issued. It can be understood that if the available memory address space of the current thread group is less than the memory address space occupation of the target thread group to be issued, even if the current thread group issuing quantity of the to-be-tested memory access unit is less than the preset thread group issuing quantity threshold, the target thread group to be issued is issued to the to-be-tested memory access unit, but due to the insufficient available memory address space of the current thread group, the memory data generated by the execution of the uniform memory access instruction of the issued target thread group cannot be stored in the sufficient memory address space, thereby causing the obtained to-be-tested memory data to be incomplete, which is easy to misjudge that the to-be-tested memory access unit fails the memory access verification, resulting in inaccurate and unreliable memory access verification results.

[0068] As a preferred solution, the method further comprises:

[0069] When it is detected that the target thread group has completed the execution of the uniform memory access instruction, at least one target thread group corresponding to at least one context program currently executed by the to-be-tested memory access unit is reissued to the to-be-tested memory access unit until each target thread group corresponding to each context program currently executed by the to-be-tested memory access unit has completed the execution of the uniform memory access instruction.

[0070] Specifically, in the actual running situation of the to-be-tested memory access unit, the instructions of one thread group are executed and the subsequent thread group is issued to the to-be-tested memory access unit. However, in the related art, the number of memory access instructions issued to each thread group is uncontrollable, and it is impossible to determine when each thread group has completed the execution of the corresponding memory access instruction, so it is impossible to simulate the actual situation for memory access verification. In addition, the switching of the context program can only be performed after all thread groups corresponding to one context program have completed the execution of the corresponding instructions. However, in the related art, it is impossible to determine when each thread group has completed the execution of the corresponding memory access instruction, so it is also impossible to realize the timely switching of the context program. However, in the embodiment, the number and content of the memory access instructions corresponding to each target thread group are the same, so the embodiment can timely detect whether the uniform memory access instruction corresponding to the target thread group has been executed, and when it is detected that the target thread group has completed the execution of the uniform memory access instruction, at least one target thread group corresponding to at least one context program currently executed by the to-be-tested memory access unit is reissued to the to-be-tested memory access unit, so as to simulate the actual running situation of the to-be-tested memory access unit and ensure more sufficient memory access verification.

[0071] It can be understood that when the execution mode of each configured context program is a serial execution mode, and it is detected that the target thread group executes the unified memory access instruction, the target thread group corresponding to the current execution of one context program of the to-be-tested memory unit is re-issued, and the thread group issuing condition needs to be met when the target thread group is issued. In an optional embodiment, for each to-be-issued thread group corresponding to the context program, the issuing arbitration is performed through the SystemVerilog Semaphore mechanism, and the available number of permissions is determined based on the thread group issuing condition. For example, based on the thread group issuing condition, it is determined that 2 target thread groups are currently allowed to be issued, and the available number of permissions is set to 2. The get function is called by each to-be-issued thread group to compete for the current permission, so that the issuing arbitration of the thread group is realized under the condition that the thread group issuing condition is met, and the target thread group issued each time is determined. Until each target thread group corresponding to the current execution of the context program of the to-be-tested memory unit executes the unified memory access instruction, the context program switching is performed, and the actual running condition of the to-be-tested memory unit can be accurately simulated.

[0072] When the execution mode of each configured context program is a parallel execution mode, and it is detected that the target thread group executes the unified memory access instruction, the target thread group corresponding to the current execution of one or more context programs of the to-be-tested memory unit is re-issued. It can be understood that for all thread groups corresponding to each current execution context program, at least one target thread group needs to be determined from the thread group issuing condition. When the number of determined target thread groups is multiple, these target thread groups can correspond to the same current execution context program, or can correspond to different current execution context programs, which are not limited in the embodiment. Since in the parallel execution mode of the context program, the embodiment can continuously issue the target context program with the same configuration parameters to the to-be-tested memory unit when the number of current context programs of the to-be-tested memory unit is less than the preset parallel execution threshold, so as to realize the timely switching of the context program. Therefore, when each target thread group corresponding to each current execution context program of the to-be-tested memory unit executes the unified memory access instruction, it indicates that each context program in the context program group is issued, and the current execution context program in the to-be-tested memory unit is also executed, so that the thread group issuing process is stopped.

[0073] As a preferred solution, the method further comprises:

[0074] When the to-be-tested memory data is acquired, the memory address space of the to-be-tested memory unit currently occupied by the target thread group is recycled.

[0075] Specifically, when the target thread group corresponding to the to-be-tested memory data is acquired, it indicates that the target thread group has executed the corresponding unified memory instruction, and the subsequent thread group needs to be issued. In order to avoid the executed target thread group from continuing to occupy the memory address space and affecting the execution of the unified memory instruction of the subsequently issued target thread group, the embodiment needs to recycle the memory address space of the to-be-tested memory unit currently occupied by the executed target thread group, and update the thread group available memory address space of the to-be-tested memory unit, so as to ensure the smooth issuance of the subsequent thread group.

[0076] As a preferred solution, the method further comprises:

[0077] When it is detected that each target thread group corresponding to any one context program currently executed by the to-be-tested memory unit has executed the unified memory instruction, the resources occupied by the any one context program are recycled.

[0078] Specifically, when it is detected that each target thread group corresponding to any one context program currently executed by the to-be-tested memory unit has executed the corresponding unified memory instruction, it indicates that the context program has been executed. In order to avoid the issuance of the subsequent context program being affected, the embodiment recycles the resources occupied by the executed context program, so as to ensure the timely issuance of the subsequent context program, for example, recycling the memory address space occupied by the context program; if the System Verilog Semaphore mechanism is used for issuing and arbitrating the context programs, the permission obtained by the context program needs to be recycled, so that the remaining context programs to be issued can compete for the permission by calling the get function, so as to realize the competitive issuance of the context programs; the thread group corresponding to the context program occupies the resource quota, and the like, which will not be described in detail herein.

[0079] As a preferred solution, the unified memory instruction comprises at least one of a read request instruction and a write request instruction.

[0080] The method specifically detects whether the target thread group has executed the unified memory instruction by the following steps:

[0081] When the unified memory instruction is a read request instruction, and the memory read data corresponding to the read request instruction is received from the to-be-tested memory unit, it is determined that the target thread group has executed the read request instruction.

[0082] when the uniform access instruction is a write request instruction, issuing a synchronization instruction to the to-be-tested access unit; the synchronization instruction is used to instruct the to-be-tested access unit to feed back synchronization response information corresponding to the synchronization instruction when the target thread group executes the write request instruction completely;

[0083] when the synchronization response information is received, it is determined that the target thread group executes the write request instruction completely.

[0084] Specifically, the uniform access instruction in the embodiment further includes at least one of a read request instruction and a write request instruction. For example, the uniform access instruction can be only a read request instruction to verify the read operation of the to-be-tested access unit; the uniform access instruction can also be only a write request instruction to verify the write operation of the to-be-tested access unit; the uniform access instruction can also include a read request instruction and a write request instruction to fully verify the access operation of the to-be-tested access unit, which is not limited in the embodiment. In order to determine the end time of the execution of the uniform access instruction of each target thread group in time, the detection mode of the read request instruction in the embodiment is that if all memory read data corresponding to the issued read request instruction can be received from the read data interface of the to-be-tested access unit, it is determined that the target thread group executes the read request instruction completely.

[0085] The detection mode of the write request instruction is that the feedback information corresponding to the completion of the write operation is obtained by issuing a synchronization instruction to the to-be-tested access unit. It is worth noting that after the write request instruction is issued completely, the synchronization instruction needs to be issued to the to-be-tested access unit to ensure that the data is written to the preset destination. The synchronization instruction is used to instruct the to-be-tested access unit to feed back the corresponding synchronization response information when the target thread group executes the corresponding write request instruction completely, indicating that the write operation has been completed. Further, by receiving the synchronization response information, the embodiment can determine when the target thread group executes the write request instruction in time and accurately, effectively ensuring the timely acquisition and checking of the to-be-tested access data of the target thread group and ensuring the timely issuance of the subsequent thread group.

[0086] As a preferred solution, the to-be-tested access data generated when the target thread group executes the uniform access instruction completely specifically includes:

[0087] sending a data read request to the to-be-tested access unit; the data read request is used to instruct the to-be-tested access unit to read the memory write data generated when the target thread group executes the write request instruction completely from the memory and return;

[0088] obtaining the memory write data returned by the to-be-tested access unit in response to the data read request;

[0089] determine the to-be-tested memory access data based on the memory read data and the memory write data.

[0090] Specifically, the embodiment adopts a front-door access manner to obtain the memory write data generated when the write request instruction of the target thread group is executed, and first sends a data read request to the to-be-tested memory access unit to instruct it to read the memory write data corresponding to the target thread group from the memory and return. This access manner can simultaneously verify whether the read operation of the to-be-tested memory access unit can be correctly implemented. If all the memory write data can be obtained through the read data interface of the to-be-tested memory access unit, it indicates that the read operation of the to-be-tested memory access unit can be correctly implemented, thereby further improving the sufficiency of the memory access verification of the to-be-tested memory access unit.

[0091] In another preferred embodiment, to obtain the to-be-tested memory access data corresponding to the target thread group, the memory write data generated when the write request instruction of the target thread group is executed can also be directly obtained from the memory of the to-be-tested memory access unit; and the to-be-tested memory access data is determined based on the memory read data and the memory write data.

[0092] It is worth noting that the embodiment adopts a back-door access manner to obtain the memory write data corresponding to the target thread group. Compared with the above-mentioned front-door access manner, the embodiment directly reads the memory write data corresponding to the target thread group from the memory of the to-be-tested memory access unit. Although this manner cannot verify whether the read operation of the to-be-tested memory access unit can be correctly implemented, it is more efficient in obtaining the to-be-tested memory access data, thereby improving the memory access verification efficiency of the to-be-tested memory access unit.

[0093] As a preferred solution, the memory access verification of the to-be-tested memory access unit based on the to-be-tested memory access data specifically includes:

[0094] comparing the to-be-tested memory access data with reference memory access data;

[0095] when the to-be-tested memory access data is inconsistent with the reference memory access data, determining that the memory access verification of the to-be-tested memory access unit fails.

[0096] Specifically, the embodiment realizes the memory access verification of the to-be-tested memory unit by comparing the to-be-tested memory data with the reference memory data. It can be understood that the reference memory data is an expected result output by a reference model, the reference model is a model constructed based on the memory processing operation of the memory unit, the memory processing function of the model is correct and executable, and is used to generate an expected result corresponding to an expected memory operation after inputting the same unified memory instruction. Since the memory instruction issued in the embodiment is predetermined and unified, the reference model can be used to generate the reference memory data corresponding to the unified memory instruction in advance. The reference memory data can also be generated by synchronously inputting into the reference model when the unified memory instruction corresponding to a certain target thread group is issued. The embodiment is not limited specifically herein. The to-be-tested memory data of each target thread group running on the to-be-tested memory unit needs to be compared and verified. As long as the to-be-tested memory data of one target thread group is inconsistent with the reference memory data, it is determined that the memory verification of the to-be-tested memory unit fails. If the to-be-tested memory data of all target thread groups is consistent with the reference memory data, it is determined that the memory verification of the to-be-tested memory unit passes.

[0097] See Figure 3is a flowchart of the chip memory access verification in the embodiment of the present application, first, the context program needs to be issued to the to-be-tested memory access unit according to the execution mode of the context program, in the process, the System Verilog Semaphore mechanism can be used to issue arbitration to each context program, then at least one thread group corresponding to at least one context program currently running is issued to the to-be-tested memory access unit, in the thread group issuing process, for the newly issued thread group, a unified memory access instruction needs to be further issued, then the unified memory access instruction is waited to be executed, and for the remaining thread groups that have been issued, since the unified memory access instruction has been issued to these thread groups before, these thread groups are also waited to execute the unified memory access instruction. For each thread group whose unified memory access instruction is executed, memory access verification is performed based on the to-be-tested memory access data, and the occupied resources of the thread group are recycled, such as the occupied memory address space. Further, if all the thread groups corresponding to the context program currently executed are not executed, the context program switching cannot be performed, and the thread group issuing process is continued; if all the thread groups corresponding to any one context program currently executed are executed, it is needed to judge whether all the to-be-issued context programs pre-configured are issued, if not, the context program issuing process is continued, if yes, after all the context programs are executed, the final state of the to-be-tested memory access unit is checked, for example, whether all the modules in the to-be-tested memory access unit are in an idle state, and whether there is to-be-tested memory access data in the data queue which has not been subjected to memory access verification, if all the modules in the to-be-tested memory access unit are in an idle state, and all the to-be-tested memory access data are subjected to memory access verification, it is determined that the memory access verification process is ended.

[0098] Please refer to Figure 4 The embodiment of the present application also provides a chip memory access verification device, which comprises:

[0099] The unified memory access instruction issuing module 101 is used for issuing the unified memory access instruction corresponding to each target thread group currently to be run to the to-be-tested memory access unit, so as to instruct the to-be-tested memory access unit to run the target thread group to execute the unified memory access instruction; wherein each target thread group corresponds to one or more context programs currently executed by the to-be-tested memory access unit;

[0100] The to-be-tested memory access data acquisition module 102 is used for acquiring the to-be-tested memory access data generated when the target thread group executes the unified memory access instruction;

[0101] The memory access verification module 103 is used for performing memory access verification on the to-be-tested memory access unit based on the to-be-tested memory access data.

[0102] As a preferred solution, before the apparatus issues the uniform memory access instruction corresponding to each target thread group to be executed to the to-be-tested memory access unit, the apparatus is further configured to:

[0103] issue one or more context programs to the to-be-tested memory access unit;

[0104] issue at least one target thread group corresponding to at least one context program to the to-be-tested memory access unit according to a preset thread group issue condition.

[0105] As a preferred solution, the apparatus is configured to issue one or more context programs to the to-be-tested memory access unit, specifically including:

[0106] determine at least two context programs to be issued currently and the execution mode of each context program based on a preconfigured context program group;

[0107] when the execution mode is a serial execution mode and the to-be-tested memory access unit is in an idle state, determine a target context program from each context program to be issued currently and issue it to the to-be-tested memory access unit; repeat this step until each context program in the context program group is issued completely;

[0108] when the execution mode is a parallel execution mode and the number of context programs currently executed by the to-be-tested memory access unit is less than a preset parallel execution number threshold, determine at least one target context program from each context program to be issued currently, which has the same configuration parameters as the context program currently executed by the to-be-tested memory access unit, and issue it to the to-be-tested memory access unit; repeat this step until each context program in the context program group is issued completely.

[0109] As a preferred solution, the thread group issue condition specifically is that the number of thread groups currently issued by the to-be-tested memory access unit is less than a preset thread group issue number threshold, and the available memory address space of the thread group currently executed by the to-be-tested memory access unit is greater than or equal to the memory address space occupied by the target thread group to be issued currently.

[0110] As a preferred solution, the apparatus is further configured to:

[0111] when it is detected that the target thread group has executed the uniform memory access instruction, reissue at least one target thread group corresponding to at least one context program currently executed by the to-be-tested memory access unit to the to-be-tested memory access unit until each target thread group corresponding to each context program currently executed by the to-be-tested memory access unit has executed the uniform memory access instruction.

[0112] As a preferred solution, the apparatus is further configured to:

[0113] when the to-be-tested access data is acquired, recycling the memory address space of the to-be-tested access unit currently occupied by the target thread group.

[0114] As a preferred solution, the apparatus is further configured to:

[0115] when it is detected that each of the target thread groups corresponding to any one of the context programs currently executed by the to-be-tested access unit has executed the unified access instruction, recycling the resources occupied by the any one of the context programs.

[0116] As a preferred solution, the unified access instruction comprises at least one of a read request instruction and a write request instruction.

[0117] The to-be-tested access data acquisition module 102 specifically detects whether the target thread group has executed the unified access instruction by the following steps:

[0118] when the unified access instruction is a read request instruction, and the memory read data corresponding to the read request instruction is received from the to-be-tested access unit, it is determined that the target thread group has executed the read request instruction;

[0119] when the unified access instruction is a write request instruction, issuing a synchronization instruction to the to-be-tested access unit; wherein the synchronization instruction is used to instruct the to-be-tested access unit to feed back the synchronization response information corresponding to the synchronization instruction when the target thread group has executed the write request instruction.

[0120] when the synchronization response information is received, it is determined that the target thread group has executed the write request instruction.

[0121] As a preferred solution, the to-be-tested access data acquisition module 102 is configured to acquire the to-be-tested access data generated when the target thread group has executed the unified access instruction, specifically comprising:

[0122] sending a data read request to the to-be-tested access unit; wherein the data read request is used to instruct the to-be-tested access unit to read the memory write data generated when the target thread group has executed the write request instruction from the memory and return;

[0123] acquiring the memory write data returned by the to-be-tested access unit in response to the data read request;

[0124] or, directly acquiring the memory write data generated when the target thread group has executed the write request instruction from the memory of the to-be-tested access unit;

[0125] Based on the memory read data and the memory write data, the to-be-tested memory data is determined.

[0126] As a preferred solution, the memory verification module 103 is configured to perform memory verification on the to-be-tested memory unit based on the to-be-tested memory data, specifically including:

[0127] comparing the to-be-tested memory data with reference memory data;

[0128] When the to-be-tested memory data is inconsistent with the reference memory data, it is determined that the memory verification of the to-be-tested memory unit fails.

[0129] The chip memory verification apparatus provided by the embodiment of the present application can realize the uniformity of the number of memory instructions and the content of access instructions issued to each target thread group without affecting the memory verification, can detect whether each target thread group has executed the corresponding uniform memory instruction based on the number of memory instructions and the content of access instructions issued by each target thread group, can determine the end time of the execution of the uniform memory instruction by each target thread group, and thus can perform memory verification based on the to-be-tested memory data generated by each target thread group in a timely manner when detecting that the target thread group has executed the uniform memory instruction, thereby fully verifying the memory unit and ensuring the reliability of the memory verification of the memory unit.

[0130] Please refer to Figure 5 The second aspect of the embodiment of the present application provides an electronic device, which includes a memory 202, a processor 201, and a computer program stored in the memory 202 and executable on the processor 201, and the processor 201 implements the chip memory verification method of any one of the first aspect embodiments when executing the computer program.

[0131] For example, the computer program can be divided into one or more modules / units, which are stored in the memory 202 and executed by the processor 201 to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the electronic device.

[0132] The electronic device can include, but is not limited to, the processor 201 and the memory 202. Those skilled in the art can understand that the schematic diagram is only an example of the electronic device and does not limit the electronic device, which can include more or fewer components than the diagram, or combine certain components or different components, for example, the electronic device can also include an input / output device, a network access device, a bus, etc.

[0133] The processor 201 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor 201, etc., and is a control center of the electronic device that connects all parts of the electronic device through various interfaces and lines.

[0134] The memory 202 can be used to store computer programs and / or modules, and the processor 201 realizes various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory 202, and calling data stored in the memory 202. The memory 202 can mainly include a program storage area and a data storage area, wherein the program storage area can store operating systems, at least one application program required by a function (such as a sound playing function, an image playing function, etc.), etc.; and the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory 202 can include a high-speed random access memory, and can also include a non-volatile memory, for example, a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state memory devices.

[0135] The third aspect of the embodiment of the present application provides a computer readable storage medium, the computer readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer readable storage medium is located executes the chip memory verification method of any one of the first aspect.

[0136] The fourth aspect of the embodiment of the present application provides a computer program product, including at least one of a computer program and computer instructions, and when the at least one of the computer program and the computer instructions is executed by a processor, the steps of the chip memory verification method of any one of the first aspect are realized.

[0137] The modules / units integrated in the electronic device, if realized in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by a processor, the steps of each method embodiment can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms, etc. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0138] The above is the preferred embodiment of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which are also considered within the scope of protection of the present application.

Claims

1. A chip memory access verification method, characterized in that, include: Issue one or more context procedures to the memory access unit to be tested; According to the preset thread group issuance conditions, at least one target thread group corresponding to the context program is issued to the memory access unit to be tested. A unified memory access instruction corresponding to each of the target thread groups currently to be run is issued to the memory access unit under test, so as to instruct the memory access unit under test to run the target thread group to execute the unified memory access instruction; wherein, each target thread group corresponds to one or more context programs currently being executed by the memory access unit under test. Obtain the memory access data to be tested generated when the target thread group finishes executing the unified memory access instruction; The memory access data to be tested is used to verify the memory access of the memory access unit to be tested.

2. The chip memory access verification method as described in claim 1, characterized in that, The step of issuing one or more context procedures to the memory access unit under test specifically includes: Based on the pre-configured context program group, determine at least two context programs to be issued and the execution mode of each context program; When the execution mode is serial execution mode and the memory access unit under test is in an idle state, a target context program is determined from each of the context programs to be sent and sent to the memory access unit under test; this step is repeated until all the context programs in the context program group have been sent. When the execution mode is parallel execution mode, and the number of current context programs executed by the memory access unit under test is less than a preset parallel execution number threshold, at least one target context program with the same configuration parameters as the current context program executed by the memory access unit under test is determined from the current context programs to be sent, and sent to the memory access unit under test; this step is repeated until all context programs in the context program group have been sent.

3. The chip memory access verification method as described in claim 1, characterized in that, The specific conditions for issuing the thread group are as follows: the number of thread groups issued by the memory access unit under test is less than the preset threshold for the number of thread groups issued, and the available memory address space of the current thread group of the memory access unit under test is greater than or equal to the memory address space occupied by the target thread group to be issued.

4. The chip memory access verification method as described in claim 1 or 3, characterized in that, The method further includes: When it is detected that the target thread group has completed the execution of the unified memory access instruction, the at least one target thread group corresponding to the at least one context program currently being executed by the memory access unit under test is reissued to the memory access unit under test, until each target thread group corresponding to each context program currently being executed by the memory access unit under test has completed the execution of the unified memory access instruction.

5. The chip memory access verification method as described in claim 1, characterized in that, The method further includes: When the memory access data to be tested is obtained, the memory address space of the memory access unit to be tested currently occupied by the target thread group is reclaimed.

6. The chip memory access verification method as described in claim 1, characterized in that, The method further includes: When it is detected that each of the target thread groups corresponding to any context program currently being executed by the memory access unit under test has completed the execution of the unified memory access instruction, the resources occupied by any context program are reclaimed.

7. The chip memory access verification method as described in claim 1, characterized in that, The unified memory access instruction includes at least one of read request instruction and write request instruction; The method specifically detects whether the target thread group has finished executing the unified memory access instruction through the following steps: When the unified memory access instruction is a read request instruction, and the memory data corresponding to the read request instruction is received from the memory access unit under test, it is determined that the target thread group has completed the execution of the read request instruction; When the unified memory access instruction is a write request instruction, a synchronization instruction is sent to the memory access unit under test; wherein, the synchronization instruction is used to instruct the memory access unit under test to provide feedback on the synchronization response information corresponding to the synchronization instruction when the target thread group finishes executing the write request instruction; When the synchronization response information is received, it is determined that the target thread group has completed the write request instruction.

8. The chip memory access verification method as described in claim 7, characterized in that, The acquisition of the memory access data to be tested generated when the target thread group completes the unified memory access instruction specifically includes: Send a data read request to the memory access unit under test; wherein, the data read request is used to instruct the memory access unit under test to read the memory write data generated when the target thread group finishes executing the write request instruction and return it; Obtain the memory write data returned by the memory access unit under test in response to the data read request; Alternatively, the memory write data generated when the target thread group finishes executing the write request instruction can be directly obtained from the memory of the memory access unit to be tested; Based on the memory read data and the memory write data, the memory access data to be tested is determined.

9. The chip memory access verification method as described in claim 1, characterized in that, The process of verifying the memory access of the unit under test based on the memory access data specifically includes: Compare the memory access data to be tested with the reference memory access data; When the memory access data to be tested is inconsistent with the reference memory access data, the memory access verification of the memory access unit to be tested is determined to be unsuccessful.

10. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the chip memory access verification method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the chip memory access verification method according to any one of claims 1 to 9.

12. A computer program product, characterized in that, The method includes at least one of a computer program and computer instructions, wherein when the computer program and at least one of the computer instructions are executed by a processor, the steps of the chip memory access verification method according to any one of claims 1 to 9 are implemented.

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