Chip, method and electronic device with performance statistics function

Abstract

Embodiments of the present application provide a chip, a method and an electronic device with performance statistics function. The chip comprises a parallel processor and a performance statistics module. The performance statistics module comprises a parameter configuration unit, a performance statistics unit and a readout control unit. The parameter configuration unit is configured to receive a performance statistics parameter, which is used to indicate the identification of N computing units that need to perform performance statistics. The performance statistics unit is configured to obtain N groups of events generated by the N computing units in the parallel processor based on the performance statistics parameter, and obtain corresponding N groups of performance data by statistics. The readout control unit is configured to store the N groups of performance data to an external memory located outside the chip. The chip can improve the flexibility and accuracy of performance statistics of the parallel processor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer hardware, and particularly relates to a chip with performance statistics function, a method and an electronic device. BACKGROUND

[0002] With the development of the fields of artificial intelligence and large-scale scientific calculation, parallel processors become core hardware due to their powerful parallel computing capabilities. When performing complex parallel tasks, computing cores in the processors generate various events and performance data, and the performance data is crucial for locating performance bottlenecks and optimizing programs.

[0003] In the prior art, performance data is collected by performance monitoring software at the operating system level. Since the operating system is at the software abstraction layer and is not directly connected to the hardware structure, it is impossible to capture hardware-level events in real time, and the performance monitoring software needs to switch between the operating system kernel state and the user state, resulting in large resource consumption and limited accuracy. SUMMARY

[0004] The present application provides a chip with performance statistics function, a method and an electronic device, which are used to improve the flexibility and accuracy of performance statistics of parallel processors.

[0005] In a first aspect, an embodiment of the present application provides a chip with performance statistics function, which comprises a parallel processor and a performance statistics module, and the performance statistics module comprises a parameter configuration unit, a performance statistics unit and a readout control unit. The parameter configuration unit is configured to receive performance statistics parameters, and the performance statistics parameters are used to indicate the identities of N computing units that need to be subjected to performance statistics. N is an integer greater than or equal to 1. The performance statistics unit is configured to obtain N groups of events generated by the N computing units in the parallel processor when running based on the performance statistics parameters, and to obtain corresponding N groups of performance data by statistics. The readout control unit is configured to store the N groups of performance data to an external memory located outside the chip.

[0006] The chip with performance statistics function described above is directly connected to the parallel processor, and the identities of the computing units in the performance statistics parameters are configured to flexibly determine the computing units to be subjected to statistics and accurately determine the performance data of the computing units.

[0007] In a possible implementation, the performance statistics module further comprises a storage module, and the performance statistics parameters further comprise a storage slot width; the storage module is configured to store the N groups of performance data according to the storage slot width; the readout control unit is configured to read the N groups of performance data from the storage module and store them in the external memory; and the storage slot width is configured to determine the number of computing units corresponding to the N groups of performance data that can be stored in the storage module.

[0008] The chip with the performance statistics function can be used to separately set a storage module in the performance statistics module to store N groups of performance data corresponding to N computing units that need to be counted.

[0009] In a possible implementation, the performance statistics parameters further comprise a dump mode and a dump time interval; if the dump mode is a single-dump mode, the readout control unit is configured to store the N groups of performance data in the external memory at one time; and if the dump mode is a periodic-dump mode, the readout control unit is configured to periodically store the N groups of performance data in the external memory according to the dump time interval.

[0010] The chip with the performance statistics function can further be configured with the dump mode and the dump time interval in the performance statistics parameters, and if the dump mode is set to the periodic-dump mode, the N groups of performance data can be automatically and periodically stored in the external memory according to the dump time interval, without the need to manually store the N groups of performance data in the external memory multiple times, thereby improving the intelligence of the chip.

[0011] In a possible implementation, the performance statistics parameters further comprise a target dump address; and the target dump address is an address of the external memory.

[0012] In a possible implementation, the parameter configuration unit comprises a plurality of registers, and the plurality of registers are configured to store the performance statistics parameters when and / or before the parallel processor performs a computing task.

[0013] The chip with the performance statistics function can be configured with the performance statistics parameters by external software or a driver when the parallel processor performs a computing task, or the performance statistics parameters can be configured and stored in the registers before the parallel processor performs a computing task, so that the statistics function can be started when the parallel processor runs. In this way, the configuration of the performance statistics parameters can be synchronized with or asynchronous to the computing task of the parallel processor, thereby improving the flexibility of counting performance data.

[0014] In a possible implementation, the performance statistics unit comprises M performance processing units, and at least one performance processing unit performs statistics on a plurality of computing units in the N computing units in a time division multiplexing manner, where N is an integer greater than M.

[0015] With the chip with the performance statistics function, statistics can be performed on more computing units than performance processing units even if the number of performance processing units is small.

[0016] In a possible implementation, the parallel processor comprises M computing units, and the performance statistics unit comprises M performance processing units and a crossbar switch; the M performance processing units correspond to the M computing units one by one; M is an integer greater than or equal to N; and the crossbar switch is configured to control N performance processing units in the M performance processing units to perform statistics according to the performance statistics parameter.

[0017] With the chip with the performance statistics function, the number of performance processing units corresponding to the number of computing units can be set, and comprehensive performance statistics of the parallel processor can be provided.

[0018] In a possible implementation, the performance processing unit comprises P counters, an adder, and a storage unit; each counter is configured to count performance data of a set type of event; the storage unit is configured to store performance data of P types of events; and the adder is configured to sum a value of a first counter and a value of first performance data stored in the storage unit, and update the value of the first performance data in the storage unit to the sum value; where the first counter is any one of the P counters, and the first performance data is performance data of a set type of event corresponding to the first counter.

[0019] With the chip with the performance statistics function, P counters can be set for each computing unit, P types of events generated by one computing unit can be counted separately, and thus performance data of each type of performance event generated by each computing unit can be more accurately obtained.

[0020] In a possible implementation, the performance processing unit further comprises a multiplexer; the performance statistics parameter further comprises a counter mask value of at least one performance processing unit; the counter mask value is P bits; and the multiplexer is configured to control whether to start counting of each counter according to the counter mask value.

[0021] With the chip with the performance statistics function, the counter mask value of the performance processing unit can be set to flexibly control the switch of each counter in the performance processing unit, so as to flexibly control the type of event on which statistics of the computing unit are performed.

[0022] In a possible implementation, the performance processing unit further comprises a performance packaging unit, and the performance statistical parameter further comprises a command control parameter; the performance packaging unit is configured to transfer each performance data stored in the storage unit to a storage module according to the command control parameter; and the performance packaging unit is further configured to clear the storage module according to the command control parameter.

[0023] By setting the command control parameter, the performance data can be flexibly controlled to be cleared or transferred by using the chip with the performance statistical function.

[0024] In a second aspect, an embodiment of the present application provides a performance statistical method, which is used for a chip with a performance statistical function, and the chip comprises a parallel processor and a performance statistical module, the performance statistical module comprises a parameter configuration unit, a performance statistical unit and a readout control unit, and the method comprises the following steps: receiving, by the parameter configuration unit, a performance statistical parameter, the performance statistical parameter being used to indicate the identification of N computing units that need to perform performance statistics; N is an integer greater than or equal to 1; based on the performance statistical parameter, obtaining, by the performance statistical unit, N groups of events generated when the N computing units in the parallel processor run, and obtaining corresponding N groups of performance data by statistics; and transferring the N groups of performance data to an external memory located outside the chip.

[0025] In a possible implementation, the parallel processor comprises M computing units, the performance statistical unit comprises M performance processing units and a crossbar switch, the M performance processing units correspond to the M computing units one by one, and M is an integer greater than N; and the method comprises the following steps: controlling N performance processing units in the M performance processing units to perform statistics according to the performance statistical parameter.

[0026] In a possible implementation, the performance processing unit comprises P counters, an adder and a storage unit, and the method comprises the following steps: counting the performance data of a set type event according to the counters; summing the value of a first counter and the value of a first type of performance data stored in the storage unit according to the adder, and updating the value of the first type of performance data in the storage unit to the sum value; wherein the first counter is any one of the P counters, and the first type of performance data is the performance data of the set type event corresponding to the first counter.

[0027] In a third aspect, an embodiment of the present application provides an electronic device comprising the chip in any possible implementation of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor.

[0029] Figure 1 A structure diagram of a chip with performance statistics function provided by an embodiment of the present application is shown in the figure.

[0030] Figure 2 A structure diagram of another chip with performance statistics function provided by an embodiment of the present application is shown in the figure.

[0031] Figure 3 A detailed diagram of a performance processing unit provided by an embodiment of the present application is shown in the figure.

[0032] Figure 4 A flow diagram corresponding to a performance statistics method provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings. Obviously, the described embodiments only constitute some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0034] A parallel processor refers to a processor that can process multiple operations at a time, and has the characteristic of realizing parallel processing capability through multi-thread technology. The parallel processor can be a multi-core central processing unit (CPU), a graphics processing unit (GPU), a general-purpose computing on graphics processing units (GPGPU), an artificial intelligence chip, a field programmable gate array, an application specific integrated circuit, etc. When the parallel processor executes a complex parallel task, the computing core generates corresponding events and generates corresponding performance data at the same time. The computing core is the smallest hardware unit for realizing parallel computing of the parallel processor, and the parallel processor forms large-scale parallel computing capability by integrating thousands of computing cores. The events generated by the computing core when running can be read-write events, computing events, etc. The performance data is the number of events, such as the number of read-write event A, the number of read-write event B, and the number of computing event C.

[0035] In the performance debugging process of a parallel processor, performance data of events can be used to locate performance bottlenecks of the parallel processor, so as to optimize the kernel program of the parallel processor and improve the performance of the program. For example, by counting performance data, the performance of a parallel computing algorithm can be optimized in GPU computing, the performance index in the deep learning training process can be supervised in artificial intelligence model training, and the performance of large-scale scientific computing applications can be optimized in scientific operation. Therefore, it is important to accurately count the performance data of the parallel processor in practical applications.

[0036] The prior art collects performance data through performance monitoring software at the operating system level. The performance monitoring software is located at the software abstraction layer and does not directly interface with hardware, so the micro-architecture events of the hardware cannot be captured in real time. In addition, the software sampling needs frequent interaction among the operating system kernel, the monitoring process and the hardware, and the sampling request generated by the performance monitoring software also occupies the resources of the central processing unit, resulting in large resource overhead and affecting the accuracy of the collected performance data.

[0037] Therefore, the embodiment of the present application provides a chip with performance statistical function, which can improve the flexibility and accuracy of performance statistics of the parallel processor.

[0038] Figure 1 A structural diagram of a chip with performance statistical function provided by the embodiment of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the chip includes a parallel processor and a performance statistical module, and the performance statistical module includes a parameter configuration unit, a performance statistical unit and a readout control unit. The chip further includes an external memory outside the chip. The parameter configuration unit is configured to receive performance statistical parameters, and the performance statistical parameters are used to indicate the identities of N computing units to be subjected to performance statistics. The performance statistical unit is configured to obtain N groups of events generated by the N computing units in the parallel processor during runtime based on the performance statistical parameters, and to count corresponding N groups of performance data. The readout control unit is configured to transfer the N groups of performance data to the external memory outside the chip.

[0039] Specifically, the parameter configuration unit can receive performance statistics parameters written by software or a driver to the performance statistics module. The performance statistics parameters can include the identification of the N computing units that need to perform performance statistics, or can include the identification of the N computing units that need to perform performance statistics. N is an integer greater than or equal to 1. For example, the identification of the computing units can be determined according to the hardware layout order or chip batch production process information, and the embodiments of the present application do not limit the determination manner of the identification of the computing units. The computing unit is a unit that can perform performance statistics, such as a computing core in a parallel processor. The performance statistics unit obtains N groups of performance data corresponding to the N computing units in the parallel processor. One computing unit generates one group of performance data. The readout control unit can transfer the N groups of performance data to an external storage outside the chip. The external storage can be a host memory, a local disk, a network storage such as a server, a cloud object storage, and the like.

[0040] In a possible implementation, the performance statistics module further includes a storage module, and the performance statistics parameters further include a storage slot width. The storage slot width represents the number of computing units corresponding to the N groups of performance data that can be stored by the storage module. The storage module is configured to store the N groups of performance data according to the storage slot width. Specifically, the storage slot width can be used to determine the number of dump data blocks that can be cached. For example, if the storage slot width is 8, 256 (2 raised to the power of 8) groups of performance data corresponding to 256 computing units can be cached. Further, the readout control unit is further configured to read the N groups of performance data from the storage module and transfer the N groups of performance data to the external storage. The performance data stored in the storage module is read to the external storage in time, which avoids overflow of the performance data in the storage module, and also makes the storage capacity of the storage module not need to be set to be very large, so that the hardware overhead of the chip can be reduced.

[0041] In a possible implementation, the performance statistical parameter further includes a dump mode and a dump time interval, and the dump mode includes a single-dump mode and a periodic-dump mode. If the dump mode is the periodic-dump mode, the performance statistical module always collects performance data corresponding to the N computing units, and the readout control unit can automatically transfer the N groups of performance data to the external memory at a configured dump time interval. For example, if the dump time interval is 1000 ms, the N groups of performance data collected can be transferred to the external memory every 1000 ms, that is, once every 1000 ms. The performance data transferred to the external memory can be subtracted to obtain the performance of each computing unit in a unit time interval. For example, the number of occurrences of a read-write event A is 50 times in the first time, 80 times in the second time, and 120 times in the third time, and the number of occurrences of the read-write event A in a unit time can be obtained as 50 times, 30 times (80 times-50 times), and 40 times (120 times-80 times).

[0042] If the dump mode is the single-dump mode, the readout control unit can transfer the N groups of performance data to the external memory once. In the case of the single-dump mode, the dump time interval parameter is invalid. The single-dump mode can be represented by parameter 0, and the periodic-dump mode can be represented by parameter 1.

[0043] In a possible implementation, the performance statistical parameter further includes a target dump address, and the target dump address is an address of the external memory. The number of target dump addresses can be multiple. For example, if there are M target dump addresses, it means that there are M external memories or M spaces in the external memory, and the M target dump addresses are used to store multiple groups of performance data generated by multiple computing units. Alternatively, the chip can also set a default dump address, and in the case that the performance statistical parameter does not include the target dump address, the N groups of performance data are transferred to the external memory corresponding to the default address.

[0044] In a possible implementation, the parameter configuration unit can include multiple registers, and the multiple registers are used to configure and store the performance statistical parameter. For example, Table 1 is a register specification table provided by an embodiment of the present application, as shown in Table 1.

[0045] Table 1

[0046]

[0047] The bit width of the Dump_interval_config register in Table 1 can be 14 bits, which is configured to configure a 14-bit unsigned integer representing how often to dump data; the bit width of the Storage_slot_cnt register can be 8 bits, which is configured to configure the number of storage slots of the storage module; the bit width of the Dump_mode register can be 1 bit, which is configured to configure the dump mode parameter, for example, 0 represents a single dump mode, and 1 represents a periodic dump mode; the bit width of the Dump_address register can be M N bits, which is configured to configure the target dump address, where M represents that up to M computing units corresponding performance data can be counted, and N represents the bit width of the dump address corresponding to one computing unit; the bit width of the Dump_space_id register can be M bits, which is configured to configure the identifier of the computing unit, and each bit is used to store the identifier of one computing unit; the bit width of the Count_en register can be M P bits, which is configured to configure the mask value of the counter, M represents M performance processing units, and P represents the P-bit counter mask value corresponding to one performance processing unit; the bit width of the Dump_command register can be 2 bits, which is configured to configure the command parameter of the dump, and up to four command control parameters can be stored. The performance statistical parameter can also include the command control parameter, and the four command control parameters can be represented by 00, 01, 10, and 11, each of which corresponds to a control command. For example, 00 represents saving the performance data stored in the storage module; 01 represents emptying the performance data in the storage module; 10 represents reading the performance data in the storage module to the external memory according to a preset format; and 11 represents reading the performance data in the storage module to the external memory according to a preset format and emptying the performance data in the storage module. The function of the performance statistical parameter of the Count_en register is described below. It should be noted that the name of the register and the bit width of the register in Table 1 can be configured as needed, and the embodiments of the present application do not limit the name of the register and the bit width of the register.

[0048] In a possible implementation, the plurality of registers included in the parameter configuration unit are used to store performance statistical parameters when the parallel processor calculates a task and / or before the parallel processor calculates a task. That is, in one case, the register receives the performance statistical parameters configured by the software or the driver when the parallel processor calculates a task, that is, the configuration of the performance statistical parameters is synchronized with the calculation of the task of the parallel processor; in another case, the register receives the performance statistical parameters configured by the software or the driver before the parallel processor calculates a task, and stores the performance statistical parameters in the register, and then triggers the performance counting when the calculation of the task of the parallel processor comes, that is, the configuration of the performance statistical parameters is asynchronous with the calculation of the task of the parallel processor.

[0049] In a possible implementation, the performance statistics unit can include M performance processing units, and at least one performance processing unit performs statistics on a plurality of computing units in the N computing units in a time-division multiplexing manner, where N is an integer greater than M.

[0050] For example, M can be 1, 2, 3, or other values, such as M is 2, the performance statistics parameter is used to indicate that the identities of the computing units on which statistics are to be performed are five, at least one performance processing unit can perform statistics on a plurality of computing units in the five computing units in a time-division multiplexing manner, such as one of the performance processing units can perform statistics on two of the computing units in a time-division multiplexing manner, and the other performance processing unit can perform statistics on the other three computing units in a time-division multiplexing manner.

[0051] Figure 2 Another structure diagram of a chip with a performance statistics function provided by an embodiment of the present application is shown in FIG. 5. Figure 2 In a possible implementation, the parallel processor includes M computing units, the performance statistics unit includes M performance processing units and a crossbar switch, the M performance processing units correspond to the M computing units in the parallel processor one by one, that is, one performance processing unit is used to perform statistics on the performance data of one computing unit, and M is an integer greater than or equal to N. Figure 2 The crossbar switch in FIG. 5 is used to control N performance processing units in the M performance processing units to perform statistics according to the performance statistics parameter. Specifically, according to the identities of the N computing units and the one-to-one correspondence between the performance processing units and the computing units, the N performance processing units in the M performance processing units are controlled to perform statistics on the performance data of the N computing units. It should be noted that, Figure 2 The write control unit in FIG. 5 is used to write the performance data counted by the performance processing unit into the storage module.

[0052] Figure 3 A detailed structure diagram of a performance processing unit provided by an embodiment of the present application is shown in FIG. 6. Figure 3In a possible implementation, the performance processing unit includes P counters, an adder and a storage unit, each of the counters is configured to count performance data of a set type of event, for example, if P is 64, it means that one performance processing unit can count performance data of 64 types of events, and one counter corresponds to performance data of one type of event. The storage unit is configured to store performance data of P types of events counted by the P counters, and the initial value of the performance data of the P types of events stored in the storage unit is 0. The adder is configured to sum a value of a first counter and a value of first performance data stored in the storage unit, and update the value of the first performance data in the storage unit as the sum, where the first counter is any one of the P counters, and the first performance data is performance data of a set type of event corresponding to the first counter. For example, the value of the first performance data stored in the storage unit is 10, and the first counter receives performance data of the first type of event as 1, and then the adder sums the value of the first performance data stored in the storage unit and the performance data received by the first counter as 1 to obtain 11, and updates the value of the first performance data in the storage unit as 11. It should be noted that the adder can sum values of the P counters and values of the P types of performance data stored in the storage unit, and the priority of the P counters is the same for the adder, and the adder can process the value of each counter in a polling manner. The performance data stored in the storage unit is read out to the storage module in time, so as to avoid overflow of the performance data in the storage unit, and also make the storage capacity of the storage unit not need to be set to be large, so as to reduce the hardware overhead of the chip and reduce the area occupied by the performance statistics module on the chip.

[0053] In a possible implementation, the performance processing unit further includes a multiplexer, and the performance statistics parameter further includes a counter mask value of the at least one performance processing unit, the counter mask value is p bits, and the multiplexer is configured to control whether to start each counter according to the counter mask value. The Count_en register described above can configure the counter mask value of the M performance processing units, and each bit of the counter mask value corresponds to the switch of one counter, and indicates whether to start counting performance data of a type of event. For example, one performance processing unit includes four counters, the counter mask value of the performance processing unit is four bits, is 0011, if 0 represents to close the counter and 1 represents to start the counter, then the third and fourth counters in the performance processing unit are in a started state, and the first and second counters are in a closed state, that is, the performance processing unit counts performance data of the third and fourth types of events in the calculation unit corresponding to the performance processing unit.

[0054] As Figure 3In a possible implementation, as shown, the performance processing unit further comprises a performance packing unit, and the performance statistical parameter further comprises a command control parameter. The performance packing unit is configured to transfer the performance data stored in the storage unit to the storage module according to the command control parameter, and clear the storage module according to the command control parameter. The four command control parameters have been described above, and can be stored in the Dump_command register. No further description is given herein.

[0055] As Figure 3 described above, the performance processing unit further comprises a state machine. The state machine is configured to receive the performance statistical parameter sent by the parameter configuration unit, and control the operation of other units or components in the performance processing unit according to the received performance statistical parameter. Specifically, the state machine is a state machine in the first performance processing unit, and the first performance processing unit is configured to count the performance data of the first computing unit in the parallel processor. If the performance statistical parameter contains the identifier of the first computing unit, the state machine controls the first performance processing unit to be in a counting state; if the performance statistical parameter does not contain the identifier of the first computing unit, the state machine controls the first performance processing unit to be in an idle state. Further, if the low bit of the command control parameter included in the performance statistical parameter is 1 and the high bit is 0, the state machine controls the adder to write 0 to the storage unit for P clock cycles, so as to clear the performance data stored in the storage unit; if the high bit of the command control parameter included in the performance statistical parameter is 1 and the low bit is 0, the state machine controls the performance packing unit to periodically extract the performance data stored in the storage unit to the storage module; if the low bit and the high bit of the command control parameter included in the performance statistical parameter are both 1, the state machine controls the performance data to be periodically extracted to the storage module and the storage unit to be cleared; and if the low bit and the high bit of the command control parameter included in the performance statistical parameter are both 0, the state machine controls the performance data to be normally saved. It should be noted that the performance statistical parameter proposed in the embodiments of the present application can be configured on the same bus.

[0056] The embodiments of the present application further provide a performance counting method. The method is used for the chip with the performance counting function described above, and the chip comprises a parallel processor and a performance counting module. The performance counting module comprises a parameter configuration unit, a performance counting unit and a readout control unit. Figure 4 A flowchart corresponding to the performance counting method provided by the embodiments of the present application is shown in Figure 4 .

[0057] In step 401, the chip with the performance counting function receives the performance statistical parameter through the parameter configuration unit.

[0058] Specifically, the performance statistical parameter is used to indicate the identifiers of N computing units which need to perform performance counting, and N is an integer greater than or equal to 1.

[0059] At step 402, the chip with the performance statistics function acquires N groups of events generated by the N computing units in the parallel processor based on the performance statistics parameters through the performance statistics unit, and obtains corresponding N groups of performance data by statistics.

[0060] Specifically, the performance statistics unit can acquire the N groups of events generated by the N computing units by time division multiplexing, and obtain corresponding N groups of performance data. In one possible implementation, the performance statistics unit includes M performance processing units, and the M performance processing units correspond to the M computing units in the parallel processor one by one. According to the identifier of the N computing units included in the performance statistics parameters, N performance processing units of the M performance processing units are started, and the N performance processing units are caused to perform statistics according to the performance statistics parameters.

[0061] In one possible implementation, one performance processing unit includes P counters, an adder and a storage unit. The P counters are used to count performance data of P types of events generated by one computing unit, and one counter is used to count performance data of one type of event in one computing unit. The storage unit is used to store performance data of P types of events, and the adder is used to sum a value of a first counter and a value of first performance data stored in the storage unit, and update the value of the first performance data in the storage unit as the sum. Wherein, the first counter is any one of the P counters, and the first performance data is performance data of the set type of event corresponding to the first counter.

[0062] At step 403, the chip with the performance statistics function stores the N groups of performance data to an external storage located outside the chip.

[0063] Specifically, after the N groups of performance data corresponding to the N computing units are obtained, the N groups of performance data are stored to the external storage located outside the chip.

[0064] Embodiments of the present application provide an electronic device, which includes a chip with a performance statistics function.

[0065] Those skilled in the art should understand that embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can be in the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0066] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0067] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0068] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0069] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A chip having a performance statistics function, characterized by comprising: The chip comprises a parallel processor and a performance statistics module, and the performance statistics module comprises a parameter configuration unit, a performance statistics unit and a readout control unit; The parameter configuration unit is configured to receive a performance statistics parameter, wherein the performance statistics parameter is used to indicate the identification of N computing units which need to perform performance statistics, and N is an integer greater than or equal to 1; The performance statistics unit is configured to obtain N groups of events generated by the N computing units in the parallel processor during runtime based on the performance statistics parameter, and obtain corresponding N groups of performance data by statistics; The readout control unit is configured to store the N groups of performance data to an external memory outside the chip; The parallel processor comprises M computing units, and the performance statistics unit comprises M performance processing units and a crossbar switch; the M performance processing units correspond to the M computing units one by one; M is an integer greater than or equal to N; The crossbar switch is configured to control N performance processing units in the M performance processing units to perform statistics according to the performance statistics parameter.

2. The chip according to claim 1, characterized in that, The performance statistics module further comprises a storage module, and the performance statistics parameter further comprises a storage slot width; The storage module is configured to store the N groups of performance data according to the storage slot width; The readout control unit is configured to read the N groups of performance data from the storage module and store them to the external memory; The storage slot width is used to determine the number of computing units corresponding to the groups of performance data that can be stored in the storage module.

3. The chip of claim 1, wherein The performance statistics parameter further comprises a dump mode and a dump time interval; If the dump mode is a single dump mode, the readout control unit is configured to store the N groups of performance data to the external memory once; If the dump mode is a periodic dump mode, the readout control unit is configured to periodically store the N groups of performance data to the external memory according to the dump time interval.

4. The chip of claim 1, wherein The performance statistics parameter further comprises a target dump address; and the target dump address is an address of the external memory.

5. The chip of claim 1, wherein The parameter configuration unit comprises a plurality of registers, and the plurality of registers are used to store the performance statistics parameter when and / or before the parallel processor performs a computing task.

6. The chip according to any one of claims 1 to 5, wherein, The performance statistics unit comprises M performance processing units, and at least one performance processing unit adopts a time division multiplexing manner to perform statistics on a plurality of computing units in the N computing units, and N is an integer greater than M.

7. The chip according to any one of claims 1 to 5, wherein The performance processing unit comprises P counters, an adder and a storage unit; Each counter is configured to count performance data of a set type event; The storage unit is configured to store performance data of P types of events; The adder is configured to sum the value of a first counter and the value of first performance data stored in the storage unit, and update the value of the first performance data in the storage unit as the sum; wherein the first counter is any one of the P counters, and the first performance data is performance data of a set type event corresponding to the first counter.

8. The chip of claim 7, wherein, The performance processing unit further comprises a multiplexer; the performance statistical parameter further comprises a counter mask value of at least one performance processing unit; the counter mask value is P bits; The multiplexer is configured to control whether to start counting of each counter according to the counter mask value.

9. The chip of claim 7, wherein, The performance processing unit further comprises a performance packaging unit, and the performance statistical parameter further comprises a command control parameter; The performance packaging unit is configured to transfer each performance data stored in the storage unit to a storage module according to the command control parameter; The performance packaging unit is further configured to clear the storage module according to the command control parameter.

10. A performance statistics method, characterized by, The method is used for a chip with a performance statistical function, and the chip comprises a parallel processor and a performance statistical module, the performance statistical module comprises a parameter configuration unit, a performance statistical unit and a readout control unit, and the method comprises the following steps: The performance statistical parameter is received by the parameter configuration unit, and the performance statistical parameter is used to indicate an identification of N computing units that need to perform performance statistics; N is an integer greater than or equal to 1; Based on the performance statistical parameter, the performance statistical unit acquires N groups of events generated when the N computing units in the parallel processor run, and obtains corresponding N groups of performance data by statistics; The N groups of performance data are transferred to an external memory outside the chip; The parallel processor comprises M computing units, the performance statistical unit comprises M performance processing units and a crossbar switch, the M performance processing units correspond to the M computing units one by one, M is an integer greater than N, and the method comprises the following steps: According to the performance statistical parameter, N performance processing units in the M performance processing units are controlled to perform statistics.

11. The method of claim 10, wherein, The performance processing unit comprises P counters, an adder and a storage unit, and the method comprises the following steps: The performance data of a set type event is counted according to the counter; The value of a first counter and the value of first performance data stored in the storage unit are summed according to the adder, and the value of the first performance data in the storage unit is updated to the sum value; wherein the first counter is any one of the P counters, and the first performance data is performance data of a set type event corresponding to the first counter.

12. An electronic device, comprising: The chip comprises the chip as claimed in any one of claims 1 to 9.

Images