Inductance simulation method, device and equipment of superconducting quantum interference device, medium and product

Abstract

The invention discloses an inductance simulation method, device and equipment of a superconducting quantum interference device, a medium and a product. The method comprises the following steps: obtaining a layout of the superconducting quantum interference device and a basic module in the layout, wherein the basic module comprises a Josephson junction and a superconducting inductor assembly; determining the penetration depth of a target inductance line through simulation processing of the basic module; constructing a first simulation model of the superconducting quantum interference device based on the layout of the superconducting quantum interference device, the penetration depth of the target inductance line and simulation input parameters of a set type; and determining inductance data of at least one detection part in the superconducting quantum interference device through simulation processing of the first simulation model. According to the technical scheme, the inductance simulation precision of the superconducting quantum interference device is improved by introducing the penetration depth of the inductance line.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of quantum device, and particularly relate to an inductance simulation method, device, equipment, medium and product of a superconducting quantum interference device. BACKGROUND

[0002] Superconducting parametric amplifiers exhibit key application values in quantum computing, weak signal detection and other fields due to their extremely low noise characteristics, and superconducting quantum interference devices (SQUID, Superconducting Quantum Interference Device) as their core components

[0003] The performance of the superconducting parametric amplifier depends on the nonlinear inductance characteristics of the Josephson junction in the superconducting quantum interference device. The Josephson junction can be equivalent to a nonlinear inductor in the circuit, and the inductance value changes with the phase difference, and even can present a negative value. The parametric amplification process is based on this nonlinearity to realize the amplification operation of the signal. For example, a superconducting quantum interference device composed of two Josephson junctions has a typical input saturation power of-115dBm; when a superconducting quantum interference device composed of 10 Josephson junctions is used, the input saturation power can be increased to-90dBm. From the application point of view, the larger input saturation power has obvious advantages, allowing higher power to read the signal, which is helpful to further improve the signal-to-noise ratio, and is crucial to the performance optimization of quantum state reading and weak magnetic signal detection.

[0004] The superconducting quantum interference device composed of multiple Josephson junctions has a sharp increase in parameter scale due to the increase in the number of junctions. The characteristic parameters of each Josephson junction and the interaction parameters between the junctions need to be accurately considered, which makes it difficult to accurately simulate them, especially when the inductance related parameters are involved, the complexity increases exponentially.

[0005] Currently, for the superconducting quantum interference device composed of multiple Josephson junctions, due to the above problems of complex parameters, special inductance characteristics and strict error tolerance, there is a lack of effective accurate simulation means. SUMMARY

[0006] Embodiments of the present application provide an inductance simulation method, device, equipment, medium and product of a superconducting quantum interference device to realize high-precision simulation of inductance in a superconducting quantum interference device.

[0007] According to an aspect of the present application, an inductance simulation method of a superconducting quantum interference device is provided, comprising:

[0008] Obtaining a layout of a superconducting quantum interference device and a basic module in the layout, the basic module including a Josephson junction and a superconducting inductor component;

[0009] determine a target inductance line penetration depth through simulation processing of the basic module;

[0010] construct a first simulation model of the superconducting quantum interference device based on the layout of the superconducting quantum interference device, the target inductance line penetration depth, and simulation input parameters of a set type;

[0011] determine inductance data of at least one detection site in the superconducting quantum interference device through simulation processing of the first simulation model.

[0012] According to another aspect of the present application, there is provided an inductance simulation device for a superconducting quantum interference device, comprising:

[0013] an acquisition module configured to acquire a layout of a superconducting quantum interference device and a basic module in the layout, the basic module comprising a Josephson junction and a superconducting inductance component;

[0014] a target inductance line penetration depth determination module configured to determine a target inductance line penetration depth through simulation processing of the basic module;

[0015] a simulation model construction module configured to construct a first simulation model of the superconducting quantum interference device based on the layout of the superconducting quantum interference device, the target inductance line penetration depth, and simulation input parameters of a set type;

[0016] a simulation module configured to determine inductance data of at least one detection site in the superconducting quantum interference device through simulation processing of the first simulation model.

[0017] According to another aspect of the present application, there is provided an electronic device, comprising:

[0018] at least one processor; and

[0019] a memory in communication connection with the at least one processor; wherein

[0020] the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the inductance simulation method for a superconducting quantum interference device according to any one of the embodiments of the present application.

[0021] According to another aspect of the present application, there is provided a computer readable storage medium storing computer instructions for enabling a processor to perform the inductance simulation method for a superconducting quantum interference device according to any one of the embodiments of the present application.

[0022] According to another aspect of the present application, there is provided a computer program product, which, when executed by a processor, implements the method for simulating inductance of a superconducting quantum interference device as described in any of the embodiments of the present application.

[0023] The technical solution provided by the embodiments of the present application determines the influencing factor in the simulation process of the superconducting quantum interference device, i.e., the target inductance line penetration depth, introduces the target inductance line penetration depth in the simulation process of the superconducting quantum interference device, restores the real distribution of the superconducting current in the simulation process, avoids the distortion of the current distribution, so that the magnetic field coupling and quantum effects can be accurately simulated in the simulation process, the inductance simulation precision is improved, and the reliability of the simulation process is improved.

[0024] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0026] Figure 1 is a flowchart of a method for simulating inductance of a superconducting quantum interference device according to an embodiment of the present application;

[0027] Figure 2 is an example diagram of a superconducting quantum interference device composed of two Josephson junctions provided by an embodiment of the present application;

[0028] Figure 3 is an example diagram of a superconducting quantum interference device composed of multiple Josephson junctions provided by an embodiment of the present application;

[0029] Figure 4 is a layout diagram of a basic module provided by an embodiment of the present application;

[0030] Figure 5 is a circuit diagram of an equivalent circuit of a basic module provided by an embodiment of the present application;

[0031] Figure 6 is a schematic diagram of a modulation curve of output voltage with respect to field current provided by an embodiment of the present application

[0032] Figure 7It is a structure schematic view of an inductance simulation device of a superconducting quantum interference device in an embodiment of the present application.

[0033] Figure 8 It is a structure schematic view of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the present application.

[0035] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0036] It can be understood that, before using the technical solutions disclosed in the embodiments of the present application, the type, use range, use scenario, etc. of the personal information involved in the present application should be informed to the user and the authorization of the user should be obtained according to relevant laws and regulations.

[0037] Figure 1 A flowchart of an inductance simulation method of a superconducting quantum interference device provided in an embodiment of the present application, the present embodiment can be applicable to the case of accurately simulating the inductance of at least one detection object in a SQUID, the method can be executed by an inductance simulation device of a superconducting quantum interference device in an embodiment of the present application, the device can be realized in the form of software and / or hardware, and the device can be integrated in an electronic device such as a computer device, a server and a mobile terminal. As shown in the figure, the method specifically includes the following steps: Figure 1

[0038] S110, obtaining a layout of a superconducting quantum interference device and a basic module in the layout, the basic module including a Josephson junction and a superconducting inductor component. ​

[0039] S120, determining a target inductance line penetration depth through simulation processing on the basic module.

[0040] S130, constructing a first simulation model of the superconducting quantum interference device based on a layout of the superconducting quantum interference device, the target inductance line penetration depth, and a simulation input parameter of a set type.

[0041] S140, determining inductance data of at least one detection site in the superconducting quantum interference device through simulation processing on the first simulation model.

[0042] Referring to Figure 2 and Figure 3 , Figure 2 An example diagram of a superconducting quantum interference device composed of two Josephson junctions provided by an embodiment of the present disclosure, Figure 3 An example diagram of a superconducting quantum interference device composed of multiple Josephson junctions provided by an embodiment of the present disclosure. Figure 2 and Figure 3 In the above-mentioned "X" represents a Josephson junction, which is a superconductor-insulator-superconductor structure. The superconductor connecting the Josephson junction is represented by a straight line, which may, for example, include a superconducting wire and a superconducting ring. The superconductor has a certain inductance value and can be equivalent to an inductor.

[0043] The layout of the superconducting quantum interference device can be understood as a layout design diagram of the physical structure of the superconducting quantum interference device on a plane. Different superconducting quantum interference devices correspond to different layouts. The layout of the superconducting quantum interference device includes components that make up the superconducting quantum interference device, such as Josephson junctions and inductors. The inductor here is a superconducting inductor.

[0044] It should be noted that the superconducting inductor is different from the conventional inductor. The superconducting inductor is related to the inductance line penetration depth, and the simulation method of the conventional inductor cannot accurately simulate the superconducting inductor. The inductance line penetration depth can be understood as the characteristic length of the exponential decay of the magnetic field and the current inside the superconductor. When any magnetic flux is introduced into the superconductor, a superconducting shielding current will be formed on the surface of the superconductor, and its range of action is defined as the inductance line penetration depth. The inductance line penetration depth is the maximum penetration depth of the magnetic field that can penetrate the superconductor, and is also the maximum depth of the current that can exist. To solve the above problem, in the simulation process of the superconducting quantum interference device, the inductance line penetration depth is introduced, the target inductance line penetration depth is determined to provide an accurate inductance line penetration depth for the simulation of the superconducting quantum interference device, and the simulation accuracy of the superconducting quantum interference device is improved.

[0045] In this embodiment, the target inductance line penetration depth is obtained by simulating a basic module in the layout of the superconducting quantum interference device, and the target inductance line penetration depth is used to represent the maximum penetration depth of the magnetic field penetrating the superconductor when the superconductor in the superconducting quantum interference device passes through the magnetic flux. The basic module is a local layout in the layout of the superconducting quantum interference device, including a Josephson junction and an inductor. Optionally, the basic module includes two Josephson junctions and an inductor, and the inductor is arranged between the two Josephson junctions. For example, refer to Figure 4 , Figure 4 is a layout schematic diagram of a basic module provided by an embodiment of the present disclosure. The basic module has a simple structure, a small amount of calculation in the simulation process, and is beneficial to improve the simulation efficiency.

[0046] In some embodiments of the present disclosure, optionally, the target inductance line penetration depth is determined by simulating the basic module, including: obtaining a measured inductance value of a to-be-tested inductor in the basic module, the to-be-tested inductor being at least part of the superconducting inductor component in the basic module; obtaining an inductance line penetration depth range, constructing a second simulation model of the basic module based on an optional inductance line penetration depth in the inductance line penetration depth range and the simulation input parameter of the set type; simulating the second simulation model to obtain a simulation inductance value corresponding to each optional inductance line penetration depth of the to-be-tested inductor; comparing the measured inductance value of the to-be-tested inductor and the simulation inductance value corresponding to each optional inductance line penetration depth, and determining the target inductance line penetration depth from the multiple optional inductance line penetration depths based on the comparison result.

[0047] In this embodiment, the inductor in the basic module can be taken as a whole as a to-be-tested inductor, or the inductor in the basic module can be divided into multiple local inductors, and any local inductor can be taken as a to-be-tested inductor. Figure 4 In the basic module, the inductor is divided into three local inductors L1, L2 and L3, and the local inductor L1 is taken as a to-be-tested inductor. It can be explained that the local inductors L1, L2 and L3 can be taken as to-be-tested inductors respectively to determine the target inductance line penetration depth. Optionally, the multiple local inductors obtained by dividing the inductor in the basic module increase in turn, for example, the lengths of the multiple local inductors increase in turn, refer to the local inductors L1, L2 and L3 in Figure 4 It can be understood that the number of local inductors in the basic module can be determined according to the simulation accuracy, and the greater the number of local inductors, the higher the simulation accuracy and the greater the calculation intensity.

[0048] The measured inductance value of the to-be-tested inductance can be understood as the real inductance value of the to-be-tested inductance obtained by a measurement method. The simulated inductance value of the to-be-tested inductance can be understood as the inductance value of the to-be-tested inductance obtained by simulating the second simulation model of the basic module under the condition of setting a selected inductance line penetration depth. Due to the influence of the selected inductance line penetration depth, the simulated inductance value of the to-be-tested inductance and the measured inductance value can be different. The accuracy of the selected inductance line penetration depth can be represented by the difference between the simulated inductance value and the measured inductance value of the to-be-tested inductance. The greater the difference between the simulated inductance value and the measured inductance value of the to-be-tested inductance, the worse the accuracy of the selected inductance line penetration depth. The smaller the difference between the simulated inductance value and the measured inductance value of the to-be-tested inductance, the higher the accuracy of the selected inductance line penetration depth. By using a plurality of selected inductance line penetration depths in the inductance line penetration depth range, the second simulation model of the basic module is simulated to obtain different simulated inductance values of the to-be-tested inductance under a plurality of selected inductance line penetration depths. The different simulated inductance values of the to-be-tested inductance under a plurality of selected inductance line penetration depths are compared with the measured inductance value to obtain a comparison result. The comparison result includes the difference between the measured inductance value of the to-be-tested inductance and the simulated inductance value corresponding to each selected inductance line penetration depth. Correspondingly, the target inductance line penetration depth is determined in a plurality of selected inductance line penetration depths based on the comparison result, including: determining the selected inductance line penetration depth corresponding to the minimum difference as the target inductance line penetration depth.

[0049] On the basis of the above-mentioned embodiments, the selected inductance line penetration depth is selected in the inductance line penetration depth range. Optionally, the selected inductance line penetration depth is obtained by sampling based on a preset interval in the inductance line penetration depth range. The inductance line penetration depth range is a numerical range formed by the upper and lower limits of the inductance line penetration depth. In the inductance line penetration depth range, n selected inductance line penetration depths are sampled based on a uniform interval. The number of selected inductance line penetration depths is negatively correlated with the preset interval. Optionally, the selected inductance line penetration depth is obtained by random sampling in the inductance line penetration depth range.

[0050] Optionally, the optional inductance wire penetration depth is obtained by adjusting the tested optional inductance wire penetration depth based on the comparison result corresponding to the tested optional inductance wire penetration depth. Based on the comparison result corresponding to the tested optional inductance wire penetration depth, the change trend of the comparison result with the inductance wire penetration depth is determined, the adjustment direction of the optional inductance wire penetration depth is determined according to the change trend, the tested optional inductance wire penetration depth is adjusted based on the adjustment direction of the inductance wire penetration depth, a new optional inductance wire penetration depth is obtained, the second simulation model is simulated again based on the new optional inductance wire penetration depth and the simulation input parameters of the set type, a simulation inductance value corresponding to the new optional inductance wire penetration depth is obtained, and a comparison result of the simulation inductance value and the measured inductance value is obtained, and the process is repeated. For example, according to the change trend of the comparison result with the inductance wire penetration depth, if the difference between the simulation inductance value and the measured inductance value of the to-be-tested inductance increases with the increase of the inductance wire penetration depth, the adjustment direction of the optional inductance wire penetration depth is to decrease; if the difference between the simulation inductance value and the measured inductance value of the to-be-tested inductance decreases with the increase of the inductance wire penetration depth, the adjustment direction of the optional inductance wire penetration depth is to increase. Optionally, the single adjustment amount of the tested optional inductance wire penetration depth can be a fixed value; optionally, the single adjustment amount of the tested optional inductance wire penetration depth can be determined according to the adjustment times, the single adjustment amount is negatively correlated with the adjustment times, the coarse-grained adjustment of the optional inductance wire penetration depth is first performed to speed up the processing efficiency, and then the fine-grained adjustment is performed to realize the fine adjustment of the optional inductance wire penetration depth and improve the accuracy of the selection of the optional inductance wire penetration depth. In the case where the difference between the simulation inductance value and the measured inductance value in the comparison result corresponding to the tested optional inductance wire penetration depth is less than a set threshold, it is determined that the simulation process is completed, and the optional inductance wire penetration depth corresponding to the minimum difference between the simulation inductance value and the measured inductance value is determined as the target inductance wire penetration depth.

[0051] On the basis of the above embodiment, the measured inductance value of the to-be-tested inductance is obtained by pre-measurement. Optionally, the measured inductance value of the to-be-tested inductance in the base module is obtained by: for the equivalent circuit of the base module, obtaining the output voltage of the equivalent circuit under the condition that the bias current and the excitation current are applied to the equivalent circuit; determining the current period based on the change trend of the output voltage with the excitation current; determining the measured inductance value of the to-be-tested inductance based on the magnetic flux sub and the current period.

[0052] The base module is converted into an equivalent circuit based on the connection relationship of the components in the base module, and the measured inductance value of the to-be-tested inductance is obtained through the test process of the equivalent circuit. For example, referring to Figure 5 , Figure 5is a circuit diagram of an equivalent circuit of a basic module provided by an embodiment of the present disclosure. It can be understood that the inductance in the basic module is divided into multiple local inductances, and each local inductance is equivalent to a superconducting wire to be tested. For the basic module shown in FIG. 1, three local inductances correspond to three superconducting wires to be tested, that is, L1, L2 and L3 in FIG. 1. Among them, the length of the superconducting wire to be tested in the equivalent circuit can be the same as the length of each local inductance in the basic module. Figure 4 Figure 5

[0053] Based on the equivalent circuit diagram of the basic module, an equivalent circuit is built, and a bias current and an excitation current are applied to the equivalent circuit. The bias current I bias is used to adjust the working current of a superconducting quantum interference device to be near the critical current, which is the maximum current at which a superconductor maintains a superconducting state. When the working current of the superconducting quantum interference device is near the critical current, the superconducting quantum interference device is most sensitive to the change of magnetic flux, ensuring that the change of magnetic flux generated by the superconducting wire to be tested can be accurately detected by the superconducting quantum interference device and converted into an observable output voltage. The value of the bias current I bias may be a calibrated value of the superconducting quantum interference device, and the calibration process of the bias current is not described here.

[0054] The excitation current is applied to both ends of the superconducting wire to be tested in the equivalent circuit, that is, I Figure 5 in FIG. 1. + magnetic I - magnetic I + magnetic I - magnetic represent the input and output of the excitation current. The excitation current is a variable current, and the current range of the excitation current can be between -n and +n. The superconducting wire to be tested generates a magnetic flux due to the change of the excitation current, and the magnetic flux is coupled into the superconducting quantum interference device. Since the superconducting quantum interference device is in a high sensitivity state, it can accurately detect the change of the magnetic flux and convert it into an output voltage. The corresponding relationship between the output voltage and the excitation current is recorded, and a periodic modulation curve of the output voltage changing with the excitation current is drawn based on the corresponding relationship, which is used to represent the trend of the output voltage changing with the excitation current. For example, see Figure 6 , Figure 6 is a schematic diagram of a modulation curve of the output voltage changing with the excitation current provided by an embodiment of the present disclosure.

[0055] ​​Based on the schematic diagram of the modulation curve of the output voltage with respect to the change of the field current, a current period is identified, which can be understood as the current change amount corresponding to one periodic fluctuation of the output voltage in the modulation curve of the output voltage with respect to the change of the field current, wherein one periodic fluctuation of the output voltage can be understood as the fluctuation between one wave crest and the next wave crest, or the fluctuation between one wave trough and the next wave trough.

[0056] Optionally, the determining the current period based on the change trend of the output voltage with respect to the field current comprises: determining a modulation curve of the output voltage with respect to the change of the field current based on the output voltage and the field current, wherein the modulation curve represents the change trend of the output voltage with respect to the field current; determining the current period based on the current interval between at least one wave crest and / or the current interval between at least one wave trough in the modulation curve, which can be represented as .

[0057] For example, a first wave crest located on the left side of the set current value and a second wave crest located on the right side of the set current value are identified in the modulation curve, and the current interval between the first current value corresponding to the first wave crest and the second current value corresponding to the second wave crest is determined as the current period.

[0058] For another example, a first wave trough located on the left side of the set current value and a second wave trough located on the right side of the set current value are identified in the modulation curve, and the current interval between the third current value corresponding to the first wave trough and the fourth current value corresponding to the second wave trough is determined as the current period. The set current value may, for example, be 0, which is not limited in this case.

[0059] For another example, a plurality of wave crests in the modulation curve are identified, the current interval between adjacent wave crests is determined, and the average of the current intervals between the plurality of adjacent wave crests is determined as the current period.

[0060] For another example, a plurality of wave troughs in the modulation curve are identified, the current interval between adjacent wave troughs is determined, and the average of the current intervals between the plurality of adjacent wave troughs is determined as the current period.

[0061] For another example, the current interval between a plurality of adjacent wave troughs in the modulation curve and the average of the current intervals between the plurality of adjacent wave troughs are determined as the current period.

[0062] In this embodiment, the magnetic flux quantum is the smallest quantum unit of the magnetic flux in a superconductor, which can be marked as

[0063] Correspondingly, the measured inductance value of the to-be-measured inductance can be determined based on the ratio of the magnetic flux quantum to the current period, which can be marked as .

[0064] Based on the above embodiments, the simulation process of the second simulation model can be as follows: display the constructed second simulation model in the interactive interface of the simulation software, respond to the attribute configuration operation, set the optional inductance line penetration depth and the set type of simulation input parameters corresponding to the second simulation model, execute the electromagnetic simulation process on the second simulation model after parameter configuration, and obtain the simulated inductance value of the inductor to be tested.

[0065] Optionally, the simulation input parameters for the specified type may include inductor structure parameters and parasitic inductance caused by the contact surface. The inductor structure parameters include at least one of the superconducting thin film size, thickness, and ground thickness. The inductor structure parameters are the geometric and physical parameters of the superconducting inductor component. The superconducting thin film size can be understood as the length and width of the superconducting thin film within the screen; the superconducting thin film thickness can be understood as the thickness of the superconducting thin film perpendicular to the current direction; and the ground thickness can be understood as the thickness of the ground layer beneath the superconducting inductor component. The parasitic inductance caused by the contact surface can be understood as the inductance generated in the contact area between the superconducting inductor component and external circuitry (e.g., clicks or leads) due to non-ideal current distribution. The specific values ​​of the inductor structure parameters and the parasitic inductance caused by the contact surface can be pre-acquired.

[0066] In this embodiment, by using the penetration depth of the inductor line as a variable, the second simulation model corresponding to the basic model is simulated for multiple selectable inductor line penetration depths to obtain the simulated inductance value of the inductor to be tested. By comparing the simulated inductance value of the inductor to be tested obtained based on multiple selectable inductor line penetration depths with the test inductance value, the target inductor line penetration depth is determined, providing accurate data support for the simulation of superconducting quantum interference devices.

[0067] In some embodiments of this disclosure, the inductor in the basic module includes multiple inductors to be tested. For each inductor to be tested, a measured inductance value is obtained, and a simulated inductance value corresponding to the penetration depth of each selectable inductor line is obtained through simulation. For example, Figure 4 Any one of the inductors L1, L2, and L3 can be used as the inductor under test. Simulation processing is performed for each of these inductors. For example, multiple optional inductor line penetration depths are obtained. For the inductor under test L1, the test inductance value of inductor under test L1 is obtained. The second simulation model is then simulated for each of the multiple optional inductor line penetration depths to obtain the simulated inductance value of inductor under test L1. For the inductor under test L2, the test inductance value of inductor under test L2 is obtained. The second simulation model is then simulated for each of the multiple optional inductor line penetration depths to obtain the simulated inductance value of inductor under test L2. For the inductor under test L3, the test inductance value of inductor under test L3 is obtained. The second simulation model is then simulated for each of the multiple optional inductor line penetration depths to obtain the simulated inductance value of inductor under test L3.

[0068] For each of the optional inductance line penetration depths, a comparison result of a measured inductance value of each of the inductances under test (inductances L1, L2 and L3) and a simulated inductance value corresponding to the optional inductance line penetration depth is determined, and a comprehensive comparison result is determined based on the comparison results corresponding to the inductances under test respectively; and a target inductance line penetration depth is determined from the optional inductance line penetration depths based on the comprehensive comparison results corresponding to the optional inductance line penetration depths respectively.

[0069] For example, for the optional inductance line penetration depth A1, a first comparison result of the measured inductance value and the simulated inductance value of the inductance L1 is obtained, i.e. a difference value of the measured inductance value and the simulated inductance value; a second comparison result of the measured inductance value and the simulated inductance value of the inductance L2 is obtained; a third comparison result of the measured inductance value and the simulated inductance value of the inductance L3 is obtained; and the average or weighted value of the first, second and third comparison results is taken as the comprehensive comparison result corresponding to the optional inductance line penetration depth A1, i.e. a comprehensive difference value. Similarly, the comprehensive comparison result corresponding to the optional inductance line penetration depth A2 is determined, and so on.

[0070] The optional inductance line penetration depths corresponding to the optional inductance line penetration depths are compared to determine the target inductance line penetration depth, for example, the optional inductance line penetration depth corresponding to the minimum comprehensive comparison result (i.e. the minimum comprehensive difference value) is determined as the target inductance line penetration depth.

[0071] The embodiments of the present disclosure determine the target inductance line penetration depth based on the simulation process of multiple inductances under test, avoid accidental errors of the simulation process of a single inductance under test, and improve the accuracy of the target inductance line penetration depth.

[0072] On the basis of the above embodiments, the target inductance line penetration depth is introduced in the simulation process of the superconducting quantum interference device to improve the simulation accuracy of the superconducting quantum interference device. Specifically, the simulation process can include: drawing unit modules included in the superconducting quantum interference device in an interactive interface of simulation software, for example, Josephson junctions and superconducting inductor components, etc., and the superconducting inductor components can include superconducting rings, superconducting wires and microstrip lines, etc.; performing parameter configuration, for example, setting the target inductance line penetration depth and setting type simulation input parameters, etc., to obtain a first simulation model; configuring a physical field and a solver of electromagnetic simulation, wherein if the superconducting quantum interference device works in a microwave / high frequency band, the physical field selects a frequency domain electromagnetic simulation; if transient response (such as pulse excitation) is concerned, the physical field selects a time domain simulation, and the solver can use a finite element method, for example; applying excitation and constraints to the first simulation model to simulate a working scenario; running simulation and post-processing to extract inductance data of at least one detection site in the superconducting quantum interference device.

[0073] The detection site can be at least one of a Josephson junction and at least one superconducting inductor component.

[0074] The technical scheme of the embodiment determines an influencing factor in the simulation process of the superconducting quantum interference device, that is, the target inductor line penetration depth, introduces the target inductor line penetration depth in the simulation process of the superconducting quantum interference device, restores the real distribution of the superconducting current in the simulation process, avoids current distribution distortion, so that the magnetic field coupling and quantum effects can be accurately simulated in the simulation process, the inductance simulation precision is improved, and the reliability of the simulation process is improved.

[0075] Figure 7 A structural schematic diagram of an inductance simulation device of a superconducting quantum interference device is provided in the embodiment of the application. The device can be integrated in any device providing simulation processing functions, such as a computer. Figure 7 As shown in the figure, the device specifically includes an acquisition module 210, a target inductor line penetration depth determination module 220, and a simulation module 230.

[0076] The acquisition module 210 is configured to acquire a layout of the superconducting quantum interference device and a basic module in the layout, and the basic module includes a Josephson junction and a superconducting inductor component.

[0077] The target inductor line penetration depth determination module 220 is configured to determine the target inductor line penetration depth through simulation processing of the basic module.

[0078] The simulation module 230 is configured to construct a first simulation model of the superconducting quantum interference device based on the layout of the superconducting quantum interference device, the target inductor line penetration depth, and a simulation input parameter of a set type, and determine inductance data of at least one detection site in the superconducting quantum interference device through simulation processing of the first simulation model.

[0079] The technical scheme of the embodiment determines an influencing factor in the simulation process of the superconducting quantum interference device, that is, the target inductor line penetration depth, introduces the target inductor line penetration depth in the simulation process of the superconducting quantum interference device, restores the real distribution of the superconducting current in the simulation process, avoids current distribution distortion, so that the magnetic field coupling and quantum effects can be accurately simulated in the simulation process, the inductance simulation precision is improved, and the reliability of the simulation process is improved.

[0080] On the basis of the above-mentioned embodiments, optionally, the target inductance wire penetration depth determination module 220 is configured to: acquire a measured inductance value of a to-be-tested inductance in the basic module, the to-be-tested inductance being at least part of the superconducting inductance assembly in the basic module; acquire an inductance wire penetration depth range, construct a second simulation model of the basic module based on an optional inductance wire penetration depth in the inductance wire penetration depth range and the simulation input parameter of the set type; perform simulation processing on the second simulation model to obtain a simulation inductance value corresponding to each optional inductance wire penetration depth of the to-be-tested inductance; compare the measured inductance value of the to-be-tested inductance with the simulation inductance value corresponding to each optional inductance wire penetration depth, and determine a target inductance wire penetration depth from the optional inductance wire penetration depths based on a comparison result.

[0081] Optionally, the target inductance wire penetration depth determination module 220 is further configured to: for an equivalent circuit of the basic module, acquire an output voltage of the equivalent circuit under the condition that a bias current and an excitation current are applied to the equivalent circuit; determine a current period based on a variation trend of the output voltage with the excitation current; and determine the measured inductance value of the to-be-tested inductance based on a magnetic flux quantum and the current period.

[0082] Optionally, the target inductance wire penetration depth determination module 220 is further configured to: determine a modulation curve of the output voltage with the excitation current based on the output voltage and the excitation current, wherein the modulation curve represents the variation trend of the output voltage with the excitation current; and determine the current period based on a current interval between at least one wave crest and / or a current interval between at least one wave trough in the modulation curve.

[0083] Optionally, the optional inductance wire penetration depths are obtained based on a set interval in the inductance wire penetration depth range.

[0084] Optionally, the optional inductance wire penetration depths are obtained by adjusting the tested optional inductance wire penetration depths based on comparison results corresponding to the tested optional inductance wire penetration depths.

[0085] Optionally, the comparison result includes a difference between the measured inductance value of the to-be-tested inductance and the simulation inductance value corresponding to each optional inductance wire penetration depth.

[0086] The target inductance wire penetration depth determination module 220 is further configured to: determine the optional inductance wire penetration depth corresponding to the minimum difference value as the target inductance wire penetration depth.

[0087] Optionally, the inductances in the basic module include a plurality of to-be-tested inductances, and for each to-be-tested inductance, a measured inductance value is measured and a simulation inductance value corresponding to each optional inductance wire penetration depth is simulated respectively.

[0088] The target inductor penetration depth determination module 220 is further configured to: for each of the optional inductor penetration depths, determine the comparison result between the measured inductance value of each inductor under test and the simulated inductance value corresponding to the optional inductor penetration depth; determine a comprehensive comparison result based on the comparison results corresponding to the multiple inductors under test; and determine the target inductor penetration depth among the multiple optional inductor penetration depths based on the comprehensive comparison results corresponding to the multiple optional inductor penetration depths.

[0089] Optionally, the simulation input parameters of the set type include inductance structure parameters and parasitic inductance caused by the contact surface, wherein the inductance structure parameters include at least one of the superconducting thin film size, thickness, and grounding thickness.

[0090] The aforementioned inductance simulation device for superconducting quantum interference devices can execute the inductance simulation method for superconducting quantum interference devices provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0091] Figure 8 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0092] like Figure 8 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0093] A plurality of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0094] The processor 11 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as the inductance simulation method of a superconducting quantum interference device.

[0095] In some embodiments, the inductance simulation method of a superconducting quantum interference device can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded onto the RAM 13 and executed by the processor 11, one or more steps of the inductance simulation method of a superconducting quantum interference device described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the inductance simulation method of a superconducting quantum interference device by any other appropriate means, such as by means of firmware.

[0096] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0097] Computer programs for implementing the methods of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer program, when executed, enables the functions / acts specified in the flowcharts and / or block diagrams to be implemented. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package and partially on a remote machine or entirely on a remote machine or server.

[0098] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0099] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0100] The systems and techniques described herein can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described herein), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0101] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, and solves the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0102] It should be understood that the various forms of flow shown above can be used to reorder, add, or delete steps. For example, the steps described in the present application can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, and the present application is not limited herein.

[0103] The embodiment of the present application further provides a computer program product, comprising a computer program, wherein the computer program is used to implement the inductance simulation method of the superconducting quantum interference device according to any one of the embodiments of the present application when executed by a processor.

[0104] Computer program products can be written in any one of a number of programming languages or combinations thereof including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0105] The specific embodiments described above are not intended to limit the scope of the application, which is defined by the appended claims. Those of skill in the art will understand that modifications, combinations, sub-combinations, and alternatives can be made to the specific embodiments without departing from the spirit and principles of the application, which is defined by the claims.

Claims

1. A method of simulating an inductance of a superconducting quantum interference device, the method comprising: The method comprises: obtaining a layout of a superconducting quantum interference device and a basic module in the layout, wherein the basic module comprises a Josephson junction and a superconducting inductor component; determining a target inductor line penetration depth through simulation processing of the basic module; constructing a first simulation model of the superconducting quantum interference device based on the layout of the superconducting quantum interference device, the target inductor line penetration depth and a simulation input parameter of a set type; determining inductance data of at least one detection site in the superconducting quantum interference device through simulation processing of the first simulation model.

2. The method of claim 1, wherein, The method for determining a target inductor line penetration depth through simulation processing of the basic module comprises: obtaining a measured inductance value of a to-be-tested inductor in the basic module, wherein the to-be-tested inductor is at least part of the superconducting inductor component in the basic module; obtaining an inductor line penetration depth range, constructing a second simulation model of the basic module based on a selectable inductor line penetration depth in the inductor line penetration depth range and the simulation input parameter of the set type; performing simulation processing on the second simulation model to obtain a simulation inductance value corresponding to each selectable inductor line penetration depth for the to-be-tested inductor; comparing the measured inductance value of the to-be-tested inductor with the simulation inductance value corresponding to each selectable inductor line penetration depth, and determining a target inductor line penetration depth from the selectable inductor line penetration depths based on a comparison result.

3. The method of claim 2, wherein, The method for obtaining a measured inductance value of a to-be-tested inductor in the basic module comprises: for an equivalent circuit of the basic module, obtaining an output voltage of the equivalent circuit under the condition that a bias current and an excitation current are applied to the equivalent circuit; determining a current period based on a change trend of the output voltage with respect to the excitation current; determining the measured inductance value of the to-be-tested inductor based on a magnetic flux quantum and the current period.

4. The method of claim 3, wherein, The method for determining a current period based on a change trend of the output voltage with respect to the excitation current comprises: determining a modulation curve of the output voltage with respect to the excitation current based on the output voltage and the excitation current, wherein the modulation curve represents the change trend of the output voltage with respect to the excitation current; determining the current period based on a current interval between at least one wave crest and / or a current interval between at least one wave trough in the modulation curve.

5. The method of claim 2, wherein, The selectable inductor line penetration depths are obtained based on a set interval within the inductor line penetration depth range. Alternatively, the selectable inductor line penetration depths are obtained by adjusting tested selectable inductor line penetration depths based on a comparison result corresponding to the tested selectable inductor line penetration depths.

6. The method of claim 2, wherein, The comparison result comprises a difference between the measured inductance value of the to-be-tested inductor and the simulation inductance value corresponding to each selectable inductor line penetration depth. The method for determining a target inductor line penetration depth from the selectable inductor line penetration depths based on a comparison result comprises: determining a selectable inductor line penetration depth corresponding to a minimum difference as the target inductor line penetration depth.

7. The method of claim 2, wherein, The inductance in the basic module includes a plurality of to-be-tested inductances, and for each to-be-tested inductance, a measured inductance value is measured and a simulated inductance value corresponding to each optional inductive line penetration depth is simulated respectively; The method further includes: For each optional inductive line penetration depth, determining a comparison result of the measured inductance value of each to-be-tested inductance and the simulated inductance value corresponding to the optional inductive line penetration depth, and determining a comprehensive comparison result based on the comparison results respectively corresponding to the plurality of to-be-tested inductances; Based on the comprehensive comparison results respectively corresponding to the plurality of optional inductive line penetration depths, determining a target inductive line penetration depth in the plurality of optional inductive line penetration depths.

8. The method of claim 1, wherein, The simulation input parameters of the set type include inductance structure parameters and contact surface induced parasitic inductance, and the inductance structure parameters include at least one of superconducting thin film size, thickness, and ground thickness.

9. An inductance simulation device for a superconducting quantum interference device, characterized by It includes: An acquisition module is configured to acquire a layout of a superconducting quantum interference device and a basic module in the layout, wherein the basic module includes a Josephson junction and a superconducting inductance component; A target inductive line penetration depth determination module is configured to determine a target inductive line penetration depth through simulation processing of the basic module; A simulation model construction module is configured to construct a first simulation model of the superconducting quantum interference device based on the layout of the superconducting quantum interference device, the target inductive line penetration depth, and simulation input parameters of a set type; A simulation module is configured to determine inductance data of at least one detection site in the superconducting quantum interference device through simulation processing of the first simulation model.

10. An electronic device, comprising: The electronic device includes: at least one processor; and a memory connected to the at least one processor in communication; wherein The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the inductance simulation method of the superconducting quantum interference device according to any one of claims 1-9.

11. A computer readable storage medium characterized by, The computer readable storage medium stores computer instructions for causing the processor to execute the inductance simulation method of the superconducting quantum interference device according to any one of claims 1-9.

12. A computer program product, characterised in that, The computer program product includes a computer program that, when executed by a processor, implements the inductance simulation method of the superconducting quantum interference device according to any one of claims 1-9.

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