Design rule checking method for chip layout and related equipment

Abstract

The invention belongs to the technical field of semiconductor design automation, and provides a design rule checking method for a chip layout and related equipment. The method comprises the following steps: acquiring a to-be-processed chip layout comprising at least one graphic layer; a process rule interval of a target graph layer in the chip layout and factor weights of the target graph layer on a plurality of process risk factors are obtained, the process rule interval is the minimum graph interval meeting process production, and the factor weights are used for representing the interference degree of the corresponding process risk factors on chip manufacturing; calling a conflict quantification model to calculate a conflict risk value of each adjacent graph in the target graph layer based on the process rule spacing, the factor weight and the actual spacing of each adjacent graph in the target graph layer; and based on the conflict risk value, carrying out design rule check on the target graph layer. Through the technical scheme provided by the invention, the precision of chip layout design verification can be improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor design automation, and particularly relates to a design rule checking method for a chip layout and a related device. BACKGROUND

[0002] In the field of semiconductor design automation (EDA), the design quality of a chip layout directly determines the performance, yield and reliability of chip manufacturing. Design rule checking is a key link in the chip layout design process, and its core purpose is to verify whether the chip layout meets various requirements of semiconductor process production, and to identify and exclude design defects that may cause manufacturing failure in advance.

[0003] A chip layout is composed of multiple graphic layers, and the spacing of adjacent graphics in each graphic layer is one of the core parameters affecting manufacturing feasibility. Traditional design rule checking methods usually take a fixed process rule spacing as the judgment standard, that is, when the actual spacing of adjacent graphics is less than the preset process rule spacing, it is determined that there is a violation.

[0004] However, as the semiconductor process node continues to evolve, especially after entering the advanced process node, the chip layout verified by the traditional design rule checking method may still have manufacturing defects such as graphic distortion, short circuit or open circuit in the later chip production process, resulting in a significant decrease in chip yield. Based on this, how to improve the accuracy of chip layout design verification has become a technical problem to be solved. SUMMARY

[0005] Embodiments of the present application provide a design rule checking method, device, computer program product, computer readable storage medium and electronic device for a chip layout, thereby improving the accuracy of chip layout design verification to a certain extent.

[0006] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0007] According to a first aspect of the embodiments of the present application, a design rule checking method for a chip layout is provided. The method comprises: obtaining a chip layout to be processed, the chip layout comprising at least one pattern layer; obtaining a process rule spacing of a target pattern layer in the chip layout and factor weights of the target pattern layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing meeting a process production, and the factor weights being used to represent interference degrees of the corresponding process risk factors on chip manufacturing; calling a conflict quantification model to calculate a conflict risk value of each adjacent pattern in the target pattern layer based on the process rule spacing, the factor weights, and an actual spacing of each adjacent pattern in the target pattern layer; and performing design rule checking on the target pattern layer based on the conflict risk values of the adjacent patterns in the target pattern layer.

[0008] In some embodiments of the present application, based on the foregoing scheme, the conflict quantification model comprises: wherein, represents a conflict risk value of any adjacent pattern; represents the process rule spacing of the target pattern layer, which is a constant; respectively represent the factor weights of the target pattern layer on the n process risk factors, which are constants; , which is a constant; represents an actual spacing of the any adjacent pattern in the target pattern layer, which is a variable.

[0009] In some embodiments of the present application, based on the foregoing scheme, the process risk factors comprise one or more of a lithography risk factor, a pattern feature factor, an etching deviation factor, a deposition deviation factor, and a superposition mask error factor.

[0010] In some embodiments of the present application, based on the foregoing scheme, if the target pattern layer is applied to a single pattern process, the performing of the design rule checking on the target pattern layer based on the conflict risk values of the adjacent patterns in the target pattern layer comprises: obtaining a first risk value threshold set for the target pattern layer; and determining, as a violation pattern, an adjacent pattern in the target pattern layer whose conflict risk value exceeds the first risk value threshold.

[0011] In some embodiments of the present application, based on the foregoing scheme, if the target pattern layer is applied to a double patterning process, the design rule checking of the target pattern layer based on the conflict risk values of the adjacent patterns in the target pattern layer comprises: obtaining a second risk value threshold set for the target pattern layer, and defining the adjacent patterns in the target pattern layer with conflict risk values exceeding the second risk value threshold as conflict pattern pairs; constructing a conflict graph in the target pattern layer by taking the patterns in the conflict pattern pairs as nodes and the conflict relationship between the patterns as connecting edges; detecting odd cycles in the conflict graph, and determining the patterns corresponding to the odd cycles as violation patterns, wherein the odd cycles are closed loops formed by an odd number of patterns through connecting edges in sequence.

[0012] In some embodiments of the present application, based on the foregoing scheme, the method further comprises: dividing the target pattern layer into a plurality of first regions with similar number of odd cycles, wherein the number of odd cycles in each first region is less than or equal to a set number; dividing each first region into at least two second regions with similar region size, and defining the second regions as correction regions. The odd cycles in the correction regions are eliminated in parallel, and the step of invoking the conflict quantification model to calculate the conflict risk values of each adjacent pattern in the target pattern layer is executed until there is no odd cycle in the conflict graph.

[0013] In some embodiments of the present application, based on the foregoing scheme, the dividing of the target pattern layer into a plurality of first regions with similar number of odd cycles comprises: sequentially traversing the grid regions in the target pattern layer in a set traversal order; whenever a current grid region is traversed, counting the total number of odd cycles of the grid regions that have been traversed, and if the total number of odd cycles exceeds a set number, marking the grid regions that have been traversed before the current grid region as a first region, and resetting the grid regions that have been traversed and the total number of odd cycles; taking the current grid region as the first grid region that has not been traversed, repeating the traversal process of the grid regions until all grid regions are traversed.

[0014] In some embodiments of the present application, based on the foregoing scheme, the elimination of the odd cycles in the correction region comprises: determining at least one target connecting edge to be eliminated in the correction region; performing shift processing and / or cutting processing on one of the patterns associated with each target connecting edge to eliminate the odd cycle to which the target connecting edge belongs.

[0015] In some embodiments of the present application, based on the foregoing scheme, the determining at least one target connection edge to be resolved in the modified region comprises: traversing each connection edge in the modified region, recording the corresponding relationship between each connection edge and the odd ring to which the connection edge belongs in a temporary table; in the temporary table, counting the connection edge with the largest number of odd rings as a pending connection edge, and determining the pending connection edge as the target connection edge to be resolved; hiding the odd ring to which the pending connection edge belongs in the temporary table, and returning to execute the step of counting the connection edge with the largest number of odd rings in the temporary table until all the odd rings recorded in the temporary table are hidden.

[0016] According to a second aspect of embodiments of the present application, a chip layout design rule checking device is provided. The device comprises: a first obtaining unit configured to obtain a chip layout to be processed, the chip layout comprising at least one pattern layer; a second obtaining unit configured to obtain a process rule spacing of a target pattern layer in the chip layout and a factor weight of the target pattern layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing meeting process production, and the factor weight being used to represent a degree of interference of a corresponding process risk factor on chip manufacturing; a calling unit configured to call a conflict quantization model to calculate a conflict risk value of each adjacent pattern in the target pattern layer based on the process rule spacing, the factor weight, and an actual spacing of each adjacent pattern in the target pattern layer; and a checking unit configured to perform design rule checking on the target pattern layer based on the conflict risk values of the adjacent patterns in the target pattern layer.

[0017] According to a third aspect of embodiments of the present application, a computer program product is provided. The computer program product comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor, so that a computer device having the processor performs operations implemented by the method according to the first aspect described above.

[0018] According to a fourth aspect of embodiments of the present application, a computer readable storage medium is provided. The computer readable storage medium stores at least one computer program instruction. The at least one computer program instruction is loaded and executed by a processor to implement operations performed by the method according to the first aspect described above.

[0019] According to a fifth aspect of embodiments of the present application, an electronic device is provided. The electronic device comprises one or more processors and one or more memories. The one or more memories store at least one computer program instruction. The at least one computer program instruction is loaded and executed by the one or more processors to implement operations performed by the method according to the first aspect described above.

[0020] Based on the technical scheme provided in the present application, the limitation of traditional methods of binary judgment based on fixed process rule spacing is broken through, the process rule spacing, the weight of multiple process risk factors and the actual spacing of adjacent patterns are fused through a conflict quantization model to replace the traditional compliance or non-compliance judgment with a quantitative risk value, the interference of multiple process risk factors can be fully considered to realize accurate quantitative evaluation of the conflict risk of adjacent patterns, the risk status in the actual manufacturing process can be more accurately reflected, the designer can be assisted to distinguish high-risk and low-risk areas, the risk omission or excessive correction caused by a single judgment standard can be avoided, the comprehensiveness and accuracy of the design rule check are significantly improved, the chip layout check of multiple process types and different process nodes can be applied, good universality and adaptability are achieved, the application range of the design rule check method is widened, the whole check process has clear logic and clear steps, can be seamlessly connected with the existing electronic design automation design process, is convenient for engineering application, more potential manufacturing defects can be excluded in advance through accurate conflict risk evaluation and comprehensive violation identification, the failure probability in the chip manufacturing process is reduced, and the chip manufacturing yield is significantly improved.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0022] The drawings herein are incorporated into the specification and form part of the specification, show embodiments consistent with the present application, and together with the specification serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings: Figure 1 A flowchart of a design rule check method for a chip layout in an embodiment of the present application is shown; Figure 2 A schematic diagram of a target pattern layer in a chip layout in an embodiment of the present application is shown; Figure 3 A schematic diagram of a target pattern layer in a chip layout in an embodiment of the present application is shown; Figure 4 A schematic diagram of a target pattern layer in a chip layout in an embodiment of the present application is shown; Figure 5 A block diagram of a design rule check device for a chip layout in an embodiment of the present application is shown; Figure 6 A structural schematic diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described, obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the protection scope of the present application.

[0024] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to give a full understanding of the embodiments of the present application. However, one skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0025] The block diagrams shown in the drawings are only functional entities, which do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. It should be noted that in the drawings, in order to ensure the simplicity of the drawings, some components in the drawings are omitted, which do not affect the explanation of the technical solutions of the present application.

[0026] The flowcharts shown in the drawings are only exemplary illustrations, which do not necessarily include all contents and operations / steps, and are not necessarily executed in the described order. For example, some operations / steps can be further divided, and some operations / steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0027] In the description of the present application, it should be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0028] In order for those skilled in the art to better understand the present application, first, the technical concepts and application background related to the present application are briefly described.

[0029] Integrated Circuit (IC): Integrated Circuit, also known as microchip or chip, refers to a microelectronic device with specific circuit functions, which is formed by concentrating a large number of transistors, diodes, resistors, capacitors, inductors and interconnections between these components on one or more semiconductor wafers (usually silicon wafers), insulating substrates and other carriers through semiconductor manufacturing processes (such as photolithography, etching, doping, deposition, etc.), and packaging in an outer shell.

[0030] Chip Layout: Chip layout, also known as chip physical layout, is the core intermediate carrier in the transition from logic design to physical manufacturing in the semiconductor chip design process, which converts the logic function and circuit structure of the chip into a two-dimensional / three-dimensional graphical description file that meets the requirements of semiconductor process manufacturing, and is also the direct basis for chip manufacturing and packaging testing.

[0031] Design Rule Check (DRC): Design rule check is a core verification link in the automatic process of semiconductor chip design, and its core purpose is to fully check the physical design of the chip layout according to the production requirements of a specific semiconductor process, identify and eliminate design defects that may cause manufacturing failure, performance degradation or reliability decline in advance, ensure that the chip layout can adapt to the actual manufacturing process, and protect the manufacturability, yield and stability of the chip.

[0032] At present, with the continuous evolution of semiconductor process nodes, especially after entering the advanced process nodes, the chip layout verified by the traditional design rule check method may still have manufacturing defects such as pattern distortion, short circuit or open circuit in the later chip production process, resulting in a significant decrease in chip yield.

[0033] The present inventors found that the traditional design rule check method only uses fixed process rule spacing as the basis for judgment, ignores the interference of multiple process risk factors on chip manufacturing, does not design differentiated check logic for the differences between single pattern process and double pattern process, uses binary judgment logic of "compliance / non-compliance" to quantify the conflict risk of adjacent patterns, and lacks a scientific screening mechanism in the odd ring processing of double pattern process, resulting in low odd ring resolution efficiency and easy to cause new conflicts. In this case, the present application proposes a design rule check scheme for chip layout to meet the high precision, comprehensiveness and process adaptability requirements of advanced semiconductor process for chip layout design verification.

[0034] The implementation details of the technical solutions of the embodiments of the present application are described below: Reference Figure 1, a flow chart of a design rule checking method of a chip layout in the embodiments of the present application is shown, which can be executed by a device with computing processing function. Referring to Figure 1 The design rule checking method of the chip layout at least includes steps 110 to 140, which are described in detail as follows: As shown in Figure 1 In step 110, a chip layout to be processed is acquired, which includes at least one pattern layer.

[0035] In the present application, the chip layout to be processed is patterned data formed after chip design is completed, which contains at least one pattern layer. Each pattern layer can correspond to one physical layer (such as metal layer, via layer, dielectric layer, etc.) in the chip manufacturing process. In the subsequent design rule checking process, the design rule checking method proposed in the present application can be executed independently for each pattern layer to ensure that the design of each physical layer meets the corresponding process requirements.

[0036] Continuing to refer to Figure 1 In step 120, the process rule spacing of a target pattern layer in the chip layout and the factor weight of the target pattern layer on multiple process risk factors are acquired, the process rule spacing being the minimum pattern spacing meeting the process production, and the factor weight being used to represent the interference degree of the corresponding process risk factor on chip manufacturing.

[0037] In the present application, the process rule spacing can be the minimum pattern spacing meeting the production of a specific semiconductor process, which is a quantitative parameter determined based on factors such as equipment capacity, material characteristics, and manufacturing process of the specific semiconductor process. The process rule spacing of different process nodes and different pattern layers is different, for example, the process rule spacing of the metal layer of the 14nm process can be 0.12μm, and the process rule spacing of the metal layer of the 7nm process can be 0.08μm.

[0038] In the present application, the factor weight is used to represent the interference degree of each process risk factor on chip manufacturing, which is a quantitative parameter. The process risk factor is a key factor affecting the effect of chip manufacturing, which can be preset according to the specific process type and manufacturing requirements.

[0039] In the present application, the process risk factor can include one or more of the lithography risk factor, the pattern feature factor, the etching deviation factor, the deposition deviation factor, and the overlay mask error factor. Each risk factor corresponds to a weight value, and the greater the weight value, the higher the interference degree of the factor on the manufacturing process.

[0040] In the present application, different process risk factors will interfere with the actual manufacturing effect of the adjacent pattern spacing from different angles. The specific description is as follows: For the lithography risk factor, it can represent the risk of pattern distortion caused by factors such as light source characteristics, photoresist performance, exposure dose control, etc. in the lithography process. The lithography process is a key step to transfer the layout pattern to the wafer, and the pattern distortion will directly cause the deviation of the actual pattern pitch from the design pitch.

[0041] For the pattern feature factor, it can represent the influence of the self-pattern characteristics (such as pattern size, shape, density, etc., or such as metal layer, via layer, etc.) of each pattern layer in the chip layout on manufacturing, for example, high-density fine line patterns are more prone to deformation during manufacturing, leading to pitch deviation.

[0042] For the etching deviation factor, it can represent the risk of pattern sidewall tilt, line width deviation, etc. caused by factors such as uneven etching rate, insufficient mask selectivity, etc. in the etching process. The etching process is used to transfer the pattern formed by lithography to the underlying material, and the deviation will affect the actual pitch of adjacent patterns; For the deposition deviation factor, it can represent the pattern height deviation caused by factors such as uneven thin film deposition rate, poor thickness consistency, etc. in the deposition process, which in turn affects the insulation performance or connection reliability between adjacent patterns, and indirectly affects the manufacturing effect related to the pitch; For the overlay mask error factor, it can represent the risk of alignment error in the multi-mask overlay process, especially in processes such as double pattern process that require multiple mask exposure. Alignment errors will directly cause pattern pitch deviation and trigger manufacturing conflicts.

[0043] Continue to refer to Figure 1 In step 130, based on the process rule pitch, the factor weight, and the actual pitch of each adjacent pattern in the target pattern layer, a conflict quantization model is called to calculate the conflict risk value of each adjacent pattern in the target pattern layer.

[0044] In this application, based on the obtained process rule pitch, factor weight, and actual pitch of each adjacent pattern in the target pattern layer, a conflict quantization model is called to calculate the conflict risk value of each adjacent pattern. The conflict quantization model can fully integrate the influence of process rule requirements and multiple process risk factors, and can accurately reflect the risk degree of conflict (such as short circuit, open circuit, etc.) of adjacent patterns in the actual manufacturing process.

[0045] Specifically, in this application, the conflict quantization model can be as shown in formula (1): (1) Wherein, represents the conflict risk value of any adjacent pattern; represents the process rule pitch of the target pattern layer, which is a quantitative value; respectively represent the factor weight of the target pattern layer on the process risk factor, n is quantitative; represents the actual spacing of the arbitrary adjacent patterns in the target pattern layer, and is a variable.

[0046] In practical applications, one or more process risk factors can be selected according to the type of the target pattern layer in the chip layout and / or the specific semiconductor process type and manufacturing requirements to be included in the conflict quantification model, so as to ensure that the model can accurately reflect the risk situation in the actual manufacturing process.

[0047] For example, for a metal layer of a certain 10nm advanced process, the pattern density of the process is high, the difficulty of the photolithography and etching process is great, and the thickness uniformity of the deposition process has a significant impact on the insulation performance between metal lines, so four process risk factors, i.e., the photolithography risk factor, the etching deviation factor, the deposition deviation factor and the pattern feature factor, can be selected, and the factor weights are set to K1=0.15, K2=0.15, K3=0.08 and K4=0.05 respectively according to the actual manufacturing data of the process, so as to comprehensively cover the main manufacturing risks.

[0048] For example, for a certain mature 28nm single pattern process of a dielectric layer, the photolithography, etching and other processes of the process are relatively stable, and the main risk comes from the overlay mask error, so only the overlay mask error factor can be selected as the process risk factor, and the factor weight K1=0.15 is set, so as to simplify the inspection model while ensuring that the core risk is considered.

[0049] For example, for the manufacture of a doped layer, it mainly involves photolithography and ion implantation processes, and the pattern features (such as the size and shape of the doped region) have a greater impact on the uniformity of the doping concentration, so the photolithography risk factor and the pattern feature factor can be selected as the process risk factors.

[0050] For example, for a via layer, its manufacture mainly involves deposition, photolithography, etching and multiple mask overlay processes, and there are many risk factors, so the photolithography risk factor, the etching deviation factor, the deposition deviation factor and the overlay mask error factor can be selected as the process risk factors.

[0051] ​Based on the above scheme, the specific types of process risk factors of each key link in semiconductor manufacturing are determined. The physical meaning of these process risk factors is clear and closely related to the actual process principle of semiconductor manufacturing. The manufacturing risk characteristics of different processes and different pattern layers can be fully reflected to ensure the comprehensiveness of the conflict risk assessment. Meanwhile, the process risk factors can be flexibly combined and selected. Designers can select a single risk factor to simplify the model for simple processes or select multiple risk factors for comprehensive evaluation for complex processes according to actual process requirements, effectively balancing the evaluation accuracy and calculation efficiency, and making the technical scheme of the present application more operable.

[0052] In the present application, the conflict quantification model can be expressed by an exponential function part which comprehensively reflects the superimposed interference effect of process rule requirements and multiple process risk factors. The process rule spacing is larger, indicating that the process requirement for the spacing is more relaxed, and the risk base value is lower. The weight of each process risk factor is larger, the value of is larger, the result of the exponential part is larger, and the risk base value is higher. Then, the actual spacing of the adjacent patterns is subtracted , which can take the influence of the actual spacing into account. The actual spacing is smaller, indicating that the adjacent patterns are more dense, and the conflict risk is higher.

[0053] In order to make the person skilled in the art better understand the conflict quantification model shown in formula (1), the following specific embodiments are described: In an embodiment of the present application, it is assumed that the process rule spacing of a pattern layer is , the actual spacing of adjacent patterns is , and two process risk factors are selected.

[0054] When the factor weight , ; When the factor weight , , .

[0055] It can be seen that when the process rule spacing and the actual spacing are the same, the weight of the process risk factor is larger (the interference degree is higher), and the conflict risk value is larger, which can accurately reflect the influence law of the process risk factor on the manufacturing conflict risk.

[0056] In another embodiment of the present application, it is assumed that the process rule spacing of a pattern layer is , and two process risk factors are selected, with the factor weights being , .

[0057] When the actual spacing , ; When the actual spacing , .

[0058] It can be seen that, under the condition that the process rule spacing and the factor weight are the same, the smaller the actual spacing of adjacent patterns, the greater the conflict risk value, and the smaller the compliance spacing, the more likely it is to occur in the actual situation of manufacturing conflict.

[0059] In the present application, based on the above conflict quantification model, the nonlinear superposition of risk factors can be realized through the exponential function, which can more accurately reflect the influence of the interaction between various factors on the conflict risk, and has higher evaluation accuracy compared with the linear model. At the same time, the comprehensive influence of the process rule spacing, the multi-process risk factor weight and the actual spacing of adjacent patterns on the conflict risk can be accurately quantified, the correlation of the quantification result with the actual manufacturing risk is strong, and each parameter in the model can be flexibly configured according to the specific process characteristics, which can adapt to the inspection needs of different process nodes and different pattern layers, has good flexibility and expansibility, and the model calculation process is simple, a large number of conflict risk values of adjacent patterns can be quickly calculated, and the efficiency requirement of chip layout design rule inspection can be met.

[0060] Continuing to refer to Figure 1 , in step 140, based on the conflict risk values of each adjacent pattern in the target pattern layer, the target pattern layer is subjected to design rule checking.

[0061] In the present application, according to the process type (single pattern process or double pattern process) applied by the target pattern layer, combined with the conflict risk values of each adjacent pattern, the corresponding design rule checking process can be performed to identify and correct the violation patterns. The manufacturing principles and requirements of different process types are different, so the differentiated checking logic can be designed to ensure the accuracy and applicability of the checking result.

[0062] Based on the technical solutions of steps 110 to 140, the limitations of traditional methods of binary judgment based only on fixed process rule spacing are broken through. The process rule spacing, multi-process risk factor weights, and actual spacing of adjacent patterns are fused through a conflict quantification model to replace the traditional compliance or non-compliance judgment with a quantified risk value. This can fully consider the interference of various process risk factors and realize precise quantitative evaluation of the conflict risk of adjacent patterns, more accurately reflect the risk status in the actual manufacturing process, assist designers in distinguishing high-risk and low-risk areas, avoid risk omissions or excessive corrections caused by a single judgment standard, significantly improve the comprehensiveness and accuracy of design rule checking, and is suitable for chip layout checking of various process types and different process nodes, has good universality and adaptability, widens the application range of the design rule checking method, and the entire checking process has clear logic and clear steps, which can seamlessly connect with the existing electronic design automation design process, facilitate engineering application, and through precise conflict risk evaluation and comprehensive violation identification, more potential manufacturing defects can be excluded in advance, the failure probability in the chip manufacturing process is reduced, and the chip manufacturing yield is significantly improved.

[0063] In the present application, if the target pattern layer is applied to a single pattern process, the design rule checking of the target pattern layer based on the conflict risk values of the adjacent patterns in the target pattern layer can be performed according to the following steps 141 to 142: Step 141, obtaining a first risk value threshold set for the target pattern layer.

[0064] Step 142, determining the adjacent patterns in the target pattern layer whose conflict risk values exceed the first risk value threshold as violation patterns.

[0065] In the present application, the single pattern process is a relatively basic process type in semiconductor manufacturing, and its design rule checking process is relatively direct. First, according to the specific requirements of the single pattern process, chip reliability standards, manufacturing experience and other factors, a first risk value threshold is set in advance, which is a key standard for judging whether the adjacent patterns are violation patterns. The setting of the first risk value threshold needs to consider the stability of the process, the application scene of the chip and other factors to ensure that high-risk patterns that may cause manufacturing defects can be effectively identified, and excessive correction caused by too low threshold setting does not affect design efficiency. Then, the conflict risk values of each adjacent pattern in the target pattern layer calculated by the conflict quantification model are compared with the first risk value threshold. If the conflict risk value exceeds the threshold, it means that the probability of conflict in the manufacturing process of this adjacent pattern is relatively high, which may cause manufacturing defects such as short circuit and open circuit, so it is determined as a violation pattern, and the designer can modify the spacing adjustment and other correction processing for these violation patterns.

[0066] In the present application, the first risk value threshold can be set to 0, -0.001 or 0.01, and the setting of the threshold needs to balance the design efficiency and manufacturing reliability. If the threshold is too high, it may lead to missing high-risk points, affecting the chip yield. If the threshold is too low, it may lead to excessive violation patterns, increasing the workload of the design personnel and reducing the design efficiency. It can be understood that the first risk value threshold can be set according to the actual situation, and the present application does not make too many restrictions on this.

[0067] In the present application, after obtaining the first risk value threshold set for the target pattern layer, the conflict risk values of all adjacent patterns in the target pattern layer can be compared with the first risk value threshold. If the conflict risk value of a certain adjacent pattern exceeds the first risk value threshold, the adjacent pattern is directly determined as a violation pattern. Design personnel can correct the violation patterns by adjusting the pattern position to increase the actual spacing, optimizing the pattern shape, and other ways to reduce the conflict risk.

[0068] In order to enable those skilled in the art to better understand the above steps 141 to 142, the following will be described in combination with Figure 2 A specific embodiment is described.

[0069] Referring to Figure 2 , a schematic diagram of a target pattern layer in a chip layout in an embodiment of the present application is shown.

[0070] As Figure 2 shown, it is assumed that the target pattern layer is applied to a single pattern process, and the conflict risk values of each adjacent pattern are as shown in Table 1.

[0071] Table 1: Conflict risk value example table of adjacent patterns In the present embodiment, it is assumed that the first risk value threshold is set to 0. Then, based on Table 1, the violation patterns in the target pattern layer can be determined as A-B, A-F, A-G, A-H, B-C, B-H, C-D, D-E, D-G, E-F and E-G.

[0072] Based on the technical solutions of steps 141 to 142, a simple and efficient checking process is designed for the characteristics of the single-pattern process, and the violation patterns are directly determined based on the comparison of the conflict risk values and the threshold values, which is simple to operate, small in calculation amount, high in checking efficiency, and suitable for the design requirements of the single-pattern process. The first risk value threshold value can be flexibly adjusted according to the process requirements, which can balance the design efficiency and the manufacturing reliability, meet the quality requirements of different chip products, and accurately identify the adjacent patterns with high conflict risk in the single-pattern process, thereby excluding potential manufacturing defects in advance, effectively improving the chip manufacturing yield, and intuitively identifying the violation patterns, which is convenient for designers to quickly locate the problem area and make corrections, thereby reducing the design iteration cost.

[0073] In the present application, if the target pattern layer is applied to a double-pattern process, the design rule checking of the target pattern layer based on the conflict risk values of the adjacent patterns in the target pattern layer can be performed according to the following steps 143 to 145: Step 143, a second risk value threshold value set for the target pattern layer is obtained, and the adjacent patterns with conflict risk values exceeding the second risk value threshold value in the target pattern layer are defined as conflict pattern pairs.

[0074] Step 144, the conflict graph is constructed in the target pattern layer by taking the patterns in the conflict pattern pairs as nodes and the conflict relationship between the patterns as connecting edges.

[0075] Step 145, the odd ring is detected in the conflict graph, and the patterns corresponding to the odd ring are determined as violation patterns. The odd ring is a closed loop formed by an odd number of patterns through connecting edges.

[0076] In the present application, the double-pattern process is a commonly used technology in advanced semiconductor processes, and its design rule checking process is relatively complex, and the identification of the odd ring structure needs to be focused on. This process can realize smaller pattern spacing by splitting the single-layer layout pattern onto two masks for exposure, but the requirements for pattern layout are more stringent, so a second risk value threshold value needs to be set separately according to its characteristics. The threshold value is different from the first risk value threshold value of the single-pattern process, and needs to be adjusted in combination with the mask splitting requirements, alignment accuracy and other factors of the double-pattern process, and fully consider the additional risks brought by multiple mask stacking and pattern splitting.

[0077] In the design rule checking of the double patterning process, first, adjacent patterns in the target pattern layer whose conflict risk values exceed a second risk value threshold are defined as conflict pattern pairs, and such pattern pairs have a high conflict risk in the manufacturing process and are the basis for constructing a conflict graph; then, each pattern in the conflict pattern pair is taken as a node, and the conflict relationship between the patterns is taken as a connecting edge, and a conflict graph is constructed in the target pattern layer, which is an abstract graphical representation and can intuitively reflect the association relationship between the conflict patterns; finally, odd cycles are detected in the conflict graph, and the odd cycle is a closed loop formed by an odd number of patterns through connecting edges, and such a structure will cause the mask splitting in the double patterning process to fail, so the patterns corresponding to the odd cycle need to be determined as violation patterns to provide a clear target for subsequent odd cycle elimination.

[0078] In order to make the person skilled in the art better understand the above steps 143 to 145, the following will continue to combine Figure 2 with a specific embodiment for description.

[0079] As Figure 2 shown, it is assumed that the target pattern layer is applied to the double patterning process, and the conflict risk values of each adjacent pattern are as shown in Table 1.

[0080] In this embodiment, it is assumed that the second risk value threshold is set to 0, so based on Table 1, the conflict pattern pairs in the target pattern layer can be determined as: A-B, A-F, A-G, A-H, B-C, B-H, C-D, D-E, D-G, E-F, E-G. The conflict graph 200 is constructed in the target pattern layer by taking the patterns in the conflict pattern pairs as nodes and the conflict relationship between the patterns as connecting edges. As can be seen, the odd cycles included in the conflict graph 200 specifically include: A-B-H-A, A-B-C-D-G-A, A-B-C-D-G-E-F-A, A-H-B-C-D-E-F-A, D-E-G-D, D-E-F-A-G-D.

[0081] Based on the technical solutions of the above steps 143 to 145, the violation identification process based on the conflict graph and the odd cycle detection is proposed according to the particularity of the double patterning process, which accurately solves the technical pain points that the traditional method cannot effectively identify the odd cycle violation in the double patterning process. The second risk value threshold is set according to the characteristics of the double patterning process, which ensures the accuracy of the conflict pattern pair screening and provides a reliable basis for subsequent odd cycle detection, and the construction of the conflict graph visualizes the conflict relationship between the patterns, which facilitates the rapid and accurate detection of the odd cycle structure and can significantly improve the efficiency and accuracy of violation identification.

[0082] The flow defines the definition and detection method of the odd loop, makes the exception identification process more operable, provides clear target objects for subsequent odd loop resolution, helps to improve the efficiency and accuracy of odd loop resolution, effectively avoids mask splitting failure caused by odd loop through accurate identification of odd loop, ensures the smooth progress of chip manufacturing process, and improves chip manufacturing yield and design efficiency.

[0083] In the present application, after step 145, i.e., after detecting the odd loop in the conflict graph, the following steps 151 to 153 can be performed: Step 151, divide the target graphic layer into a plurality of first regions with similar number of odd loops, and the number of odd loops in each first region is less than or equal to a set number.

[0084] Step 152, divide each first region into at least two second regions with similar region size, and define the second regions as correction regions.

[0085] Step 153, resolve the odd loops in the plurality of correction regions in parallel, and return to perform the step of calling the conflict quantification model to calculate the conflict risk value of each adjacent graphic in the target graphic layer until there is no odd loop in the conflict graph.

[0086] In the present application, odd loop resolution is a key link of double graphic process design rule checking, and this step can improve the efficiency of odd loop resolution through reasonable region division and parallel processing.

[0087] Specifically, first, the target graphic layer can be divided into a plurality of first regions with similar number of odd loops, and the number of odd loops in each first region is less than a set number. The purpose of this division is to divide the large-scale chip layout into a plurality of regions with moderate size, avoiding the problem of large number of odd loops in a single region leading to difficult resolution and low efficiency. Then, each first region is divided into at least two second regions with similar region size, and the second regions are defined as correction regions. The purpose of this step is to further refine the region division, so that the size of each correction region is moderate, facilitating parallel processing and improving the overall efficiency of odd loop resolution. Finally, for a plurality of correction regions, odd loop resolution is performed in parallel, i.e., the odd loop resolution tasks of the plurality of correction regions can be executed simultaneously on different processing threads or processors, greatly shortening the total time of odd loop resolution.

[0088] Further, after completing a round of odd cycle resolution, return to perform the above step 130, i.e., return to perform the step of "calling the conflict risk quantification model to calculate the conflict risk value of each adjacent graph in the target graph layer", reconstruct the conflict graph and detect the odd cycle until there is no odd cycle in the conflict graph, and complete the design rule check of the dual graph process. The purpose of the iterative check is to verify whether new odd cycles are generated during the resolution process, to ensure that all odd cycles are completely resolved, and to ensure that the chip layout meets the manufacturing requirements of the dual graph process.

[0089] To better enable those skilled in the art to understand the above steps 151 to 153, the following will be described in combination with a specific embodiment. Figure 3 A specific embodiment will be described.

[0090] Referring to Figure 3 , a schematic diagram of a target graph layer in a chip layout according to an embodiment of the present application is shown.

[0091] As shown in Figure 3 , assuming that the metal layer graph 300 of a certain dual graph process contains 120 odd cycles, and the number of odd cycles in each first region is set to be no more than 45, the layout is divided into three first regions FR1, FR2, and FR3 by a region division algorithm, and the number of odd cycles in each region is 42, 41, and 37, respectively. Then, the first regions FR1, FR2, and FR3 are divided into the second region FR1-1 and the second region FR1-2, the second region FR2-1 and the second region FR2-2, and the second region FR3-1 and the second region FR3-2, respectively, as correction regions, and the number of odd cycles in each correction region is between 18 and 22, and the region size is similar, providing a basis for parallel resolution. Subsequently, the odd cycle resolution tasks of the six correction regions are assigned to six processing threads for parallel execution, and each thread is responsible for the odd cycle resolution of one correction region. Compared with serial processing, the total resolution time is shortened to about 1 / 6 of the original. After the first round of parallel resolution, the conflict risk value is recalculated, the conflict graph is reconstructed, and the odd cycle is detected. Assuming that there are 10 odd cycles in the six correction regions that have not been completely resolved, and 2 new odd cycles are generated, the total number of odd cycles is 12, then the second round of resolution is performed, and after the resolution, there are 3 remaining odd cycles, and no new odd cycle is generated, and the third round of resolution is continued, and finally there is no odd cycle in the conflict graph, and the odd cycle resolution is completed.

[0092] Based on the technical solutions of steps 151 to 153, by using the phased regional division strategy, the large-scale chip layout, i.e., the target pattern layer, is divided into multiple correction regions with moderate size and uniform odd ring distribution, which can effectively reduce the difficulty of odd ring elimination of a single region, support parallel elimination processing of multiple correction regions, greatly improve the overall efficiency of odd ring elimination, and avoid the problem of low elimination efficiency caused by concentrated odd ring distribution or excessively large region in the traditional method. The iterative checking mechanism can ensure the thoroughness of odd ring elimination, avoid missing uneliminated odd rings, discover and process new odd rings generated in the elimination process in a timely manner, ensure the elimination effect, avoid manufacturing risks caused by incomplete single elimination, and the logic of regional division and parallel processing is clear, which can be combined with existing parallel computing technology, facilitating engineering implementation, and having good practicability. Efficient and thorough elimination of odd rings helps to ensure the smooth progress of mask splitting in the double pattern process, improve the success rate of chip manufacturing, shorten the chip design cycle, and improve the chip design efficiency and manufacturing yield.

[0093] In the present application, in step 151, the division of the target pattern layer into multiple first regions with similar odd ring numbers can be performed according to steps 1511 to 1513 as follows: Step 1511: According to a set traversal order, the grid regions that have not been traversed are traversed in the target pattern layer one by one.

[0094] Step 1512: When the current grid region is traversed, the total odd ring number of the accumulated traversed grid regions is counted. If the total odd ring number exceeds a set number, the grid regions accumulated before the current grid region are marked as a first region, and the accumulated grid regions and the total odd ring number are reset.

[0095] Step 1513: The current grid region is regarded as the first grid region that has not been traversed, and the grid region traversal process is repeated until all grid regions are traversed.

[0096] In the present application, the core of the region division method is to ensure that the number of odd loops in each first region is similar and does not exceed a certain number, providing a good foundation for subsequent odd loop elimination. Specifically, first, a certain traversal order can be determined, and the selection of the traversal order can be determined according to factors such as the shape of the target pattern layer, the pattern distribution characteristics, etc., such as from left to right, from top to bottom, or from the center to the periphery, etc., to ensure that the traversal process can cover the entire grid area of the target pattern layer. Then, according to the traversal order, the untraversed grid areas are traversed in turn, and in the traversal process, the total number of odd loops of the cumulative traversed grid areas is counted in real time. When the total number of odd loops counted exceeds the set number, it means that the number of odd loops in the cumulative traversed grid areas is relatively large, and if subsequent grid areas are added, it will lead to too large difficulty in the elimination of the odd loops in the region, so the cumulative traversed grid areas before the current grid area are marked as a first region, and the cumulative traversed grid areas and the total number of odd loops are reset, and a new region division is started. Finally, the current grid area is taken as the first untraversed grid area, and the above traversal and counting process is repeated until all grid areas are traversed, and the division of the first region is completed.

[0097] For example, in a specific embodiment, the target pattern layer is divided into 5 μm x 5 μm grid areas, and the number of odd loops in each first region is set to not exceed 40, and the traversal order is from left to right and from top to bottom. After starting traversal, the (1, 1), (1, 2), …, (1, 5) grid areas are traversed in turn, and the total number of odd loops of the cumulative traversed grid areas is 38, which does not exceed the set number 40; continue to traverse the (1, 6) grid area, and the total number of odd loops is 42, which exceeds the set number 40. At this time, the (1, 1) - (1, 5) grid areas are marked as the first region 1, and the cumulative traversed grid areas and the total number of odd loops are reset. Then, the (1, 6) grid area is taken as the first untraversed grid area, and the (1, 7), (1, 8) and other grid areas are continued to be traversed, and the above counting and marking process is repeated. When the (5, 10) grid area is traversed, the cumulative number of odd loops reaches 40, and the corresponding cumulative traversed grid areas are marked as the first region n. Continue to traverse the remaining grid areas until all 100 grid areas are traversed, and finally the target pattern layer is divided into multiple first regions with similar number of odd loops.

[0098] Based on the technical solutions of steps 1511-1513, the number of odd loops in each first region is ensured to be less than the set value and the number of odd loops in each region is similar by setting the traversal order and the real-time statistical mechanism to traverse the grid region and count the number of odd loops, so that the division result is uniform and reasonable, and the difficulty of resolution caused by the excessive concentration of odd loops in some regions is avoided. Meanwhile, the traversal order can be flexibly set to adapt to chip layouts of different shapes and different pattern distributions, and has good adaptability. The division process is highly automated and does not require manual intervention, and can quickly and accurately complete the first region division of a large-scale chip layout, is convenient for programming and implementation, and can be directly integrated into an electronic design automation tool, and has good engineering application prospects. Uniform region division also helps to divide each first region into correction regions of similar size, providing good conditions for parallel odd loop resolution, which can further improve the efficiency of odd loop resolution and shorten the chip design cycle.

[0099] In step 153, for each correction region, the odd loop in the correction region is resolved, which can be performed according to steps 1531-1532 as follows: Step 1531, determining at least one target connection edge to be resolved in the correction region.

[0100] Step 1532, performing shift processing and / or cutting processing on one of the patterns associated with each target connection edge to eliminate the odd loop to which the target connection edge belongs.

[0101] In this application, the core of odd loop resolution is to break the closed structure of the odd loop by processing the pattern associated with the target connection edge, so as to eliminate the odd loop. First, the target connection edge to be resolved can be determined in the correction region. The selection of the target connection edge is crucial, and reasonable selection can reduce the number of correction iterations and avoid causing new conflicts. The target connection edge is a connection edge that plays a key supporting role in the structure of the odd loop, and deleting or modifying the connection edge can effectively break the odd loop. Then, shift processing and / or cutting processing can be performed on one of the patterns associated with each target connection edge. Shift processing refers to moving the pattern a certain distance in the plane to change the position of the pattern and adjust the distance between adjacent patterns. Cutting processing refers to cutting part of the region of the pattern to reduce the size of the pattern, and then changing the relative position and distance between adjacent patterns. Through these processes, the closed loop of the odd loop can be broken, the odd loop structure can be eliminated, and the mask splitting in the double pattern process can be ensured to proceed smoothly.

[0102] In addition, shift processing and cutting processing can also be used simultaneously according to the layout characteristics and manufacturing requirements of the pattern to achieve better resolution effect.

[0103] In order for those skilled in the art to better understand the above steps 1531-1532, the following will be described in combination withFigure 4 With a specific embodiment as an example.

[0104] Referring to Figure 4 , a schematic diagram of a target pattern layer in a chip layout according to an embodiment of the present application is shown.

[0105] As shown in Figure 4 , in the target pattern layer 400, a singular ring is formed between the pattern I, the pattern J and the pattern K. For example Figure 4 , as shown in subgraph (a) thereof, by performing cutting processing on the pattern K, the singular ring is eliminated, and a target pattern layer as shown in subgraph (b) of Figure 4 is obtained. For another example Figure 4 , as shown in subgraph (c) thereof, by performing displacement processing on the pattern K, the singular ring is eliminated, and a target pattern layer as shown in subgraph (d) of Figure 4 is obtained. For another example Figure 4 , as shown in subgraph (e) thereof, by performing cutting processing and displacement processing on the pattern K simultaneously, the singular ring is eliminated, and a target pattern layer as shown in subgraph (f) of Figure 4 is obtained.

[0106] Based on the technical solutions of steps 1531 to 1532 described above, by determining the target connection edge and performing displacement processing and / or cutting processing on the associated pattern, the target connection edge can be effectively disconnected, and the singular ring structure in the correction region can be quickly eliminated, meeting the mask splitting requirements of the double pattern process. Compared with the traditional way of randomly selecting a connection edge for correction, this method can accurately locate the key connection edge, reduce the number of correction iterations, improve the efficiency of singular ring elimination, support flexible selection and combination of multiple processing methods, adapt to the singular ring elimination requirements of different pattern layouts and different manufacturing constraints according to the specific conditions of the pattern, has good flexibility, and the processing process is only performed on a single pattern associated with the target connection edge, has less impact on the surrounding patterns, can reduce the risk of new conflicts in the elimination process, and can ensure the design quality of the chip layout. This processing method is simple and efficient, does not require complex pattern reconstruction, can further improve the overall efficiency of design rule checking, helps the smooth implementation of the double pattern process, and improves the yield and reliability of chip manufacturing.

[0107] In step 1531 described above, the at least one target connection edge to be eliminated in the correction region can be determined according to the following steps 15311 to 15313: Step 15311: Traverse each connection edge in the correction region, and record the corresponding relationship between each connection edge and the singular ring to which it belongs in a temporary table.

[0108] Step 15312, counting the connection edge belonging to the odd ring with the largest number of odd rings in the temporary table as a pending connection edge, and determining the pending connection edge as a target connection edge to be eliminated.

[0109] Step 15313, hiding the odd ring to which the pending connection edge belongs in the temporary table, and returning to execute the step of counting the connection edge belonging to the odd ring with the largest number of odd rings in the temporary table until all the odd rings recorded in the temporary table are hidden.

[0110] In this application, the number of odd rings to which each connection edge belongs is counted in the temporary table, the connection edge belonging to the odd ring with the largest number of odd rings is selected as a pending connection edge, and the pending connection edge is determined as a target connection edge to be eliminated. The connection edge with the largest number of odd rings is preferentially selected because eliminating the connection edge can eliminate multiple odd rings at the same time, reduce the number of elimination iterations, and improve the elimination efficiency. Then, all the odd rings to which the pending connection edge belongs (i.e., the odd ring formed by the connection edge no longer participates in the subsequent statistics) are hidden in the temporary table, and the selection process of "counting the connection edge belonging to the odd ring with the largest number of odd rings in the temporary table" is returned to execute until all the odd rings recorded in the temporary table are hidden, i.e., all the odd rings have found the corresponding target connection edge.

[0111] Based on the above embodiments, it is not difficult to understand that the determination method of the target connection edge proposed in this application can preferentially select the connection edge that plays a key role in multiple odd rings for modification, thereby improving the efficiency of odd ring elimination. First, each connection edge in the modified region is traversed to determine the odd ring to which each connection edge belongs, and the correspondence between the connection edge and the odd ring is recorded in the temporary table, which can clearly reflect the association between the connection edge and the odd ring. Then, the number of odd rings to which each connection edge belongs is counted in the temporary table, the connection edge belonging to the odd ring with the largest number of odd rings is selected as a pending connection edge, and the pending connection edge is determined as a target connection edge to be eliminated. Because this type of connection edge belongs to multiple odd rings at the same time, modifying it can break the structure of multiple odd rings at the same time, reduce the number of modifications, and improve the elimination efficiency. Then, the odd rings to which the pending connection edge belongs are hidden in the temporary table, i.e., these odd rings no longer participate in the subsequent statistics and selection process. Then, the step of counting the connection edge belonging to the odd ring with the largest number of odd rings is executed again to select the target connection edge from the remaining connection edges and odd rings, and the above process is repeated until all the odd rings recorded in the temporary table are hidden, i.e., all the odd rings are covered by the corresponding target connection edge, providing a clear object for subsequent odd ring elimination.

[0112] In order for those skilled in the art to better understand the above steps 15311 to 15313, the following will continue to combine the above Figure 2 A specific embodiment is described.

[0113] As Figure 2As shown, the correction region 200 includes: odd ring 1: A-B-H-A; odd ring 2: A-B-C-D-G-A; odd ring 3: A-B-C-D-G-E-F-A; odd ring 4: A-H-B-C-D-E-F-A; odd ring 5: D-E-G-D; and odd ring 6: D-E-F-A-G-D. The correspondence between each connection edge in the correction region 200 and the odd ring to which the connection edge belongs is recorded in a temporary table, as shown in Table 2 below: Table 2: Correspondence table between connection edges and odd rings to which the connection edges belong According to the above step logic, based on the temporary table as shown in Table 2, it can be determined that the connection edges D-G and B-H can be determined as target connection edges to be resolved, or the connection edges D-G and A-H can be determined as target connection edges to be resolved.

[0114] Based on the technical solutions of steps 15311 to 15313 described above, by recording the correspondence between the connection edges and the odd rings in the temporary table, and based on the number of odd rings to which the connection edges belong, the connection edge that plays a key role in multiple odd rings, i.e., the connection edge that belongs to the most odd rings, is preferentially selected as the target connection edge, which can realize simultaneous resolution of multiple odd rings, reduce the number of correction iterations, and greatly improve the efficiency of odd ring resolution. Compared with the traditional random selection of connection edges, this method is more targeted and scientific, avoids low efficiency and the generation of new conflicts caused by blind correction, reduces the risk of generating new conflicts during resolution, improves the stability and reliability of odd ring resolution, and at the same time, the selection process logic is clear and simple to operate. The use of the temporary table makes the correspondence between the connection edges and the odd rings more clear, facilitating statistics and selection, and the determination of the target connection edge can be quickly completed, meeting the demand for efficient checking. Moreover, the selection method has good universality, is suitable for different numbers and structures of odd ring combinations, and can be applied to various odd ring resolution scenarios of double pattern processes, providing efficient and accurate basis for subsequent odd ring resolution, ensuring the smooth progress of odd ring resolution, and further improving the chip design efficiency and manufacturing yield.

[0115] The device embodiment of the present application is described below, which can be used to execute the design rule checking method of the chip layout in the embodiments of the present application. For details not disclosed in the device embodiment of the present application, please refer to the embodiments of the design rule checking method of the chip layout described above.

[0116] Referring to Figure 5 , a block diagram of a design rule checking device of a chip layout in an embodiment of the present application is shown.

[0117] As Figure 5As shown, the chip layout design rule checking device 500 according to the embodiment of the present application comprises a first obtaining unit 501, a second obtaining unit 502, a calling unit 503 and a checking unit 504.

[0118] The first obtaining unit 501 is configured to obtain a chip layout to be processed, the chip layout comprising at least one graphic layer; the second obtaining unit 502 is configured to obtain a process rule spacing of a target graphic layer in the chip layout and factor weights of the target graphic layer on a plurality of process risk factors, the process rule spacing being a minimum graphic spacing meeting process production, and the factor weights being used to represent interference degrees of the corresponding process risk factors on chip manufacturing; the calling unit 503 is configured to call a conflict quantification model to calculate a conflict risk value of each adjacent graphic in the target graphic layer based on the process rule spacing, the factor weights and an actual spacing of each adjacent graphic in the target graphic layer; and the checking unit 504 is configured to perform design rule checking on the target graphic layer based on the conflict risk values of the adjacent graphics in the target graphic layer.

[0119] In some embodiments of the present application, based on the foregoing scheme, the conflict quantification model comprises: wherein, represents a conflict risk value of any adjacent graphic; represents the process rule spacing of the target graphic layer, which is a constant; respectively represent the factor weights of the target graphic layer on the n process risk factors, which is a constant; represents an actual spacing of the any adjacent graphic in the target graphic layer, which is a variable.

[0120] In some embodiments of the present application, based on the foregoing scheme, the process risk factors comprise one or more of a lithography risk factor, a graphic feature factor, an etching deviation factor, a deposition deviation factor and a superposition mask error factor.

[0121] In some embodiments of the present application, based on the foregoing scheme, the checking unit 504 is configured to, if the target graphic layer is applied to a single graphic process, obtain a first risk value threshold set for the target graphic layer; and determine adjacent graphics in the target graphic layer with conflict risk values exceeding the first risk value threshold as violation graphics.

[0122] In some embodiments of the present application, based on the foregoing scheme, the checking unit 504 is configured to: if the target pattern layer is applied to a double patterning process, obtain a second risk value threshold set for the target pattern layer, and define adjacent patterns in the target pattern layer with a conflict risk value exceeding the second risk value threshold as a conflict pattern pair; construct a conflict graph in the target pattern layer by taking patterns in the conflict pattern pair as nodes and a conflict relationship between patterns as a connecting edge; detect an odd ring in the conflict graph, and determine a pattern corresponding to the odd ring as a violation pattern, the odd ring being a closed loop formed by sequentially associating odd-numbered patterns through connecting edges.

[0123] In some embodiments of the present application, based on the foregoing scheme, the device further comprises a resolution unit configured to: divide the target pattern layer into a plurality of first regions with similar odd ring numbers, the number of odd rings in each first region being less than or equal to a set number; divide each first region into at least two second regions with similar region sizes, and define the second regions as correction regions; and resolve the odd rings in the correction regions in parallel, and return to execute the step of invoking the conflict quantification model to calculate the conflict risk value of each adjacent pattern in the target pattern layer until there is no odd ring in the conflict graph.

[0124] In some embodiments of the present application, based on the foregoing scheme, the resolution unit is configured to: sequentially traverse untraversed grid regions in the target pattern layer according to a set traversal order; each time a current grid region is traversed, count the total number of odd rings of the grid regions that have been traversed, and if the total number of odd rings exceeds a set number, mark the grid regions that have been traversed before the current grid region as a first region, and reset the grid regions that have been traversed and the total number of odd rings; take the current grid region as the first untraversed grid region, and repeat the traversal process of the grid regions until all grid regions are traversed.

[0125] In some embodiments of the present application, based on the foregoing scheme, the resolution unit is configured to: determine at least one target connecting edge to be resolved in the correction region; perform a shift processing and / or a cutting processing on one of the patterns associated with each target connecting edge to eliminate the odd ring to which the each target connecting edge belongs.

[0126] In some embodiments of the present application, based on the foregoing scheme, the elimination unit is configured to: traverse each connecting edge in the modified region, record the corresponding relationship between each connecting edge and the odd ring to which the connecting edge belongs in a temporary table; count the connecting edge with the largest number of odd rings in the temporary table as a pending connecting edge, and determine the pending connecting edge as a target connecting edge to be eliminated; hide the odd ring to which the pending connecting edge belongs in the temporary table, and return to execute the step of counting the connecting edge with the largest number of odd rings in the temporary table until all the odd rings recorded in the temporary table are hidden.

[0127] Based on the same inventive concept, the embodiments of the present application provide a computer program product, which comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device having the processor to perform operations performed by the chip layout design rule checking method as described above.

[0128] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium, which stores at least one computer program instruction, and the at least one computer program instruction is loaded and executed by a processor to enable the processor to perform operations performed by the chip layout design rule checking method as described above.

[0129] Based on the same inventive concept, the embodiments of the present application further provide an electronic device, which is shown in Figure 6 , a structural schematic diagram of an electronic device in the embodiments of the present application is shown, the electronic device comprises one or more memories 604, one or more processors 602, and at least one computer program (computer program instructions) stored in the memory 604 and executable on the processor 602, and the processor 602 implements the chip layout design rule checking method as described above when executing the computer program.

[0130] In the above embodiments of the present application, the processor 602 is configured to execute the computer program instructions to perform the operations of the chip layout design rule checking method as described above. Figure 6In particular embodiments, a bus architecture, represented generally by the bus 600, can include any number of interconnected buses and bridges, the bus 600 linking together various circuits including the processor 602, represented by one or more processors, and the memory 604, represented by the memory. The bus 600 can also link various other circuits together, such as peripheral devices, voltage stabilizers and power management circuits, which are well known in the art, and thus, not further described herein. The bus interface 605 provides an interface between the bus 600 and the receiver 601 and the transmitter 603. The receiver 601 and the transmitter 603 can be the same element, i.e., a transceiver, providing a means for communicating with various other apparatuses over a transmission medium. The processor 602 is responsible for managing the bus 600 and general processing, while the memory 604 can be used for storing data used by the processor 602 in executing operational processes.

[0131] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as technology evolves, the "functionalities" described herein can be implemented by various combinations of digital and / or analog hardware, and / or software.

[0132] In several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other manners. The described device embodiments are merely illustrative, for example, the division of units can be different, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, and can be in electrical, or other forms.

[0133] The units described as separate components can or can not be physically separate, and the components of the control device can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0134] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer program instructions.

[0135] The above only describes the embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the scope of the claims of the present application.

Claims

1. A method of design rule checking for a chip layout, characterized by, The method comprises: acquiring a chip layout to be processed, the chip layout comprising at least one pattern layer; acquiring a process rule spacing of a target pattern layer in the chip layout and factor weights of the target pattern layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing meeting process production, and the factor weights being used to represent interference degrees of the corresponding process risk factors on chip manufacturing; based on the process rule spacing, the factor weights, and an actual spacing of each adjacent pattern in the target pattern layer, calling a conflict quantization model to calculate a conflict risk value of each adjacent pattern in the target pattern layer; based on the conflict risk values of the adjacent patterns in the target pattern layer, performing design rule checking on the target pattern layer.

2. The method of claim 1, wherein, The conflict quantization model comprises: wherein, represents a conflict risk value of any adjacent pattern; represents a process rule pitch of the target pattern layer, which is a constant; respectively represent factor weights of the target pattern layer on n process risk factors, which are constants; , which is a constant; represents an actual pitch of the any adjacent pattern in the target pattern layer, which is a variable.

3. The method according to claim 1 or 2, characterized in that, The process risk factors comprise one or more of a lithography risk factor, a pattern feature factor, an etching deviation factor, a deposition deviation factor, and a superimposed mask error factor.

4. The method according to claim 1 or 2, characterized in that, If the target pattern layer is applied to a single pattern process, the design rule checking on the target pattern layer based on the conflict risk values of the adjacent patterns in the target pattern layer comprises: acquiring a first risk value threshold set for the target pattern layer; determining, as a violation pattern, an adjacent pattern in the target pattern layer whose conflict risk value exceeds the first risk value threshold.

5. The method according to claim 1 or 2, characterized in that, If the target pattern layer is applied to a double pattern process, the design rule checking on the target pattern layer based on the conflict risk values of the adjacent patterns in the target pattern layer comprises: acquiring a second risk value threshold set for the target pattern layer, and defining, as a conflict pattern pair, an adjacent pattern in the target pattern layer whose conflict risk value exceeds the second risk value threshold; constructing a conflict graph in the target pattern layer by taking patterns in the conflict pattern pair as nodes and a conflict relationship between the patterns as a connecting edge; detecting an odd ring in the conflict graph, and determining, as a violation pattern, a pattern corresponding to the odd ring, the odd ring being a closed loop formed by an odd number of patterns through connecting edges.

6. The method of claim 5, wherein, The method further comprises: dividing the target pattern layer into a plurality of first regions with similar odd ring numbers, an odd ring number in each first region being less than or equal to a set number; dividing each first region into at least two second regions with similar region sizes, and defining the second regions as correction regions; parallelizing odd ring elimination in the correction regions, and returning to the step of calling the conflict quantization model to calculate the conflict risk values of the adjacent patterns in the target pattern layer until there is no odd ring in the conflict graph.

7. The method of claim 6, wherein, The division of the target pattern layer into the plurality of first regions with similar odd ring numbers comprises: traversing grid regions in the target pattern layer in a set traversal order in sequence; whenever a current grid region is traversed, counting a total odd ring number of the grid regions traversed cumulatively, and if the total odd ring number exceeds a set number, marking the grid regions traversed cumulatively before the current grid region as a first region, and resetting the grid regions traversed cumulatively and the total odd ring number; The current grid region is taken as the first grid region which has not been traversed, and the grid region traversal process is repeated until all grid regions are traversed.

8. The method of claim 6, wherein, The odd ring in the correction region is eliminated, including: At least one target connection edge to be eliminated is determined in the correction region; A shift processing and / or a cutting processing are performed on each target connection edge to eliminate the odd ring to which the target connection edge belongs.

9. The method of claim 8, wherein, The at least one target connection edge to be eliminated in the correction region includes: Each connection edge in the correction region is traversed, and a corresponding relationship between the connection edge and an odd ring to which the connection edge belongs is recorded in a temporary table; A connection edge with the largest number of odd rings is counted as a pending connection edge in the temporary table, and the pending connection edge is determined as the target connection edge to be eliminated; The odd ring to which the pending connection edge belongs is hidden in the temporary table, and the step of counting the connection edge with the largest number of odd rings in the temporary table is returned to be executed until all odd rings recorded in the temporary table are hidden.

10. A design rule checking apparatus for a chip layout, characterized by, The device includes: A first obtaining unit configured to obtain a chip layout to be processed, the chip layout including at least one pattern layer; A second obtaining unit configured to obtain a process rule spacing of a target pattern layer in the chip layout and a factor weight of the target pattern layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing meeting process production, and the factor weight being used to represent an interference degree of a corresponding process risk factor on chip manufacturing; A calling unit configured to call a conflict quantization model to calculate a conflict risk value of each adjacent pattern in the target pattern layer based on the process rule spacing, the factor weight, and an actual spacing of each adjacent pattern in the target pattern layer; An inspection unit configured to perform a design rule inspection on the target pattern layer based on the conflict risk value of each adjacent pattern in the target pattern layer.

11. A computer program product, characterised in that, The computer program product includes computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the method of any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program code, and the at least one program code is loaded and executed by the processor to implement the operations performed by the method of any one of claims 1 to 9.

13. An electronic device, comprising: The electronic device includes one or more processors and one or more memories, and the one or more memories store at least one program code, and the at least one program code is loaded and executed by the one or more processors to implement the method of any one of claims 1 to 9.

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