Chip layout correction method based on double patterning process and related device

Abstract

The application belongs to the technical field of semiconductor design automation, and proposes a chip layout correction method based on double pattern technology and related equipment. The method comprises: obtaining a chip layout to be processed, and determining a pair of patterns with conflicts in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to double pattern technology; constructing a conflict graph in the target metal layer by taking patterns in the pair of patterns as nodes and a conflict relationship between the patterns as a connection edge, and detecting an odd cycle in the conflict graph; if an odd cycle is detected in the conflict graph, dividing the target metal layer into multiple correction regions; and eliminating the odd cycles in the multiple correction regions in parallel, and returning to execute the step of determining a pair of patterns with conflicts in the target metal layer of the chip layout until there is no odd cycle in the constructed conflict graph. The technical scheme provided by the application can improve the correction efficiency of the chip layout.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor design automation, and particularly relates to a chip layout correction method based on double patterning technology and a related device. BACKGROUND

[0002] In the field of semiconductor chip manufacturing, with the continuous improvement of chip integration and the continuous reduction of transistor feature size, the traditional photolithography process has been difficult to meet the demand of high-precision pattern preparation. As a key technology to break through the resolution limit of photolithography, double patterning technology effectively reduces the pattern spacing and improves the precision and density of pattern preparation by dividing the target metal layer of the chip layout into two sub-metal layers for photolithography and etching, and has become one of the core technologies in advanced process chip manufacturing.

[0003] In the practical application of double patterning technology, the metal layer of the chip layout needs to meet strict process rule requirements, and the pattern spacing is a key factor affecting the process feasibility and yield. If the spacing of adjacent patterns does not meet the process rule, it will cause pattern distortion, bridging and other defects in the photolithography process, which seriously affects the performance and reliability of the chip. Therefore, before applying double patterning technology, the chip layout must be corrected to ensure the feasibility of the divided layout and ensure that all patterns meet the process rule requirements, and the correction efficiency of the chip layout directly determines the research and development cycle and manufacturing cost of the chip. SUMMARY

[0004] Embodiments of the present application provide a chip layout correction method based on double patterning technology, device, computer program product, computer readable storage medium and electronic equipment, which can improve the correction efficiency of the chip layout to a certain extent.

[0005] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0006] According to a first aspect of the embodiments of the present application, a chip layout correction method based on double patterning technology is provided, the method comprising: obtaining a chip layout to be processed, and determining a pair of conflicting patterns in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to double patterning technology; taking patterns in the pair of conflicting patterns as nodes and a conflict relationship between the patterns as a connection edge, constructing a conflict graph in the target metal layer, and detecting an odd ring in the conflict graph, the odd ring being a closed loop formed by an odd number of patterns through connection edges; if an odd ring is detected in the conflict graph, dividing the target metal layer into a plurality of correction regions; and parallelly eliminating the odd rings in the plurality of correction regions, and returning to execute the step of determining a pair of conflicting patterns in the target metal layer of the chip layout until there is no odd ring in the constructed conflict graph.

[0007] In some embodiments of the present application, based on the foregoing scheme, the determining of the pair of conflicting patterns in the target metal layer of the chip layout comprises: obtaining a process rule spacing of the target metal layer, the process rule spacing being a minimum pattern spacing satisfying a process production condition; and determining any adjacent patterns in the target metal layer as the pair of conflicting patterns if an actual spacing of the any adjacent patterns is less than a set multiple of the process rule spacing.

[0008] In some embodiments of the present application, based on the foregoing scheme, the determining of the pair of conflicting patterns in the target metal layer of the chip layout comprises: obtaining a process rule spacing of the target metal layer, and a factor weight of the target metal layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing satisfying a process production condition; calculating a conflict risk value of any adjacent patterns in the target metal layer under double pattern process by a conflict quantification model based on the process rule spacing, the factor weight, and an actual spacing of the any adjacent patterns; and determining the any adjacent patterns as the pair of conflicting patterns if the conflict risk value is greater than a set risk value.

[0009] In some embodiments of the present application, based on the foregoing scheme, the conflict quantification model comprises:

[0010]

[0011] wherein, represents the conflict risk value of the any adjacent patterns under double pattern process; represents a process rule spacing set for the target metal layer, being a constant; represents a factor weight of photolithography risk, being a constant; represents a factor weight of pattern type, being a constant; represents an actual spacing of the any adjacent patterns in the target metal layer, being a variable.

[0012] In some embodiments of the present application, based on the foregoing scheme, the detecting of the odd ring in the conflict graph comprises: calling a graph theory loop extraction algorithm to traverse each closed loop in the conflict graph, and counting a node number of the each closed loop; and determining a closed loop with an odd node number as the odd ring.

[0013] In some embodiments of the present application, based on the foregoing scheme, the dividing the target metal layer into multiple correction regions comprises: dividing the target metal layer into multiple first regions with similar number of odd loops, and the number of odd loops in each first region is less than a set number; dividing each first region into at least two second regions with similar size, and defining the second regions as the correction regions.

[0014] In some embodiments of the present application, based on the foregoing scheme, the dividing the target metal layer into multiple first regions with similar number of odd loops comprises: sequentially traversing the grid regions in the target metal layer in a set traversal order; whenever a current grid region is traversed, counting the total number of odd loops of the grid regions that have been traversed, and if the total number of odd loops exceeds a set number, marking the grid regions that have been traversed before the current grid region as a first region, and resetting the grid regions that have been traversed and the total number of odd loops; taking the current grid region as the first grid region that has not been traversed, and repeating the traversal process of the grid regions until all grid regions are traversed.

[0015] In some embodiments of the present application, based on the foregoing scheme, the eliminating the odd loops in the correction regions comprises: determining at least one target connection edge to be repaired in the correction regions; performing shift processing and / or cutting processing on one of the graphs associated with each target connection edge to eliminate the odd loop to which the each target connection edge belongs.

[0016] In some embodiments of the present application, based on the foregoing scheme, the determining at least one target connection edge to be repaired in the correction regions comprises: traversing each connection edge in the correction regions, and recording the correspondence between each connection edge and the odd loop to which the each connection edge belongs in a temporary table; in the temporary table, counting the connection edge with the largest number of odd loops as the target connection edge to be repaired; in the temporary table, hiding the odd loop to which the target connection edge belongs, and returning to the step of counting the connection edge with the largest number of odd loops in the temporary table until all odd loops recorded in the temporary table are hidden.

[0017] In some embodiments of the present application, based on the foregoing scheme, the method further comprises: if the connection edge with the largest number of odd loops counted in the temporary table includes multiple connection edges, obtaining the actual distance between the adjacent graphs associated with each of the multiple connection edges; and determining the connection edge corresponding to the adjacent graphs with the largest actual distance as the target connection edge.

[0018] According to a second aspect of the embodiments of the present application, a chip layout correction device based on a double patterning process is provided, the device comprising: an obtaining unit configured to obtain a chip layout to be processed, and determine a pair of conflicting patterns in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to the double patterning process; a detecting unit configured to construct a conflict graph in the target metal layer by taking the patterns in the pair of conflicting patterns as nodes and the conflict relationship between the patterns as connecting edges, and detect an odd cycle in the conflict graph, the odd cycle being a closed loop formed by odd-numbered patterns through connecting edges in sequence; a dividing unit configured to divide the target metal layer into a plurality of correction regions if there is an odd cycle in the conflict graph; and a resolving unit configured to resolve the odd cycles in the plurality of correction regions in parallel, and return to perform the step of determining a pair of conflicting patterns in the target metal layer of the chip layout until there is no odd cycle in the conflict graph.

[0019] According to a third aspect of the embodiments of the present application, a computer program product is provided, the computer program product comprising computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform operations to implement the operations performed by the method according to the first aspect.

[0020] According to a fourth aspect of the embodiments of the present application, a computer readable storage medium is provided, the computer readable storage medium storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by a processor to implement the operations performed by the method according to the first aspect.

[0021] According to a fifth aspect of the embodiments of the present application, an electronic device is provided, the electronic device comprising one or more processors and one or more memories, the one or more memories storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by the one or more processors to implement the operations performed by the method according to the first aspect.

[0022] Based on the technical scheme provided in the present application, through the complete process of constructing a conflict graph, detecting odd cycles, partitioning and parallel resolving, and cyclic iteration, the orderliness and integrity of the chip layout correction process can be guaranteed. Among them, the partitioning and parallel processing mode can fully exert the parallel computing capability of modern computing devices, and can decompose the correction task of a large-scale layout into multiple sub-tasks to be pushed forward synchronously, compared with the traditional overall serial processing mode, the data processing amount and the correction time can be greatly reduced, and the rapid correction demand of a large-scale chip layout can be met, and the correction efficiency of the chip layout is improved. In addition, the odd cycle detection carried out by the conflict graph in the present application can accurately locate the object to be corrected, and provide a clear target for the subsequent resolution operation, reduce invalid operations, and enhance the stability and reliability of the correction. After each odd cycle resolution, the conflict detection is carried out again, which can timely find and handle new conflicts and new odd cycles generated in the resolution process, avoid missing potential problems, and significantly improve the reliability of the chip layout correction, and ensure that the final chip layout completely meets the process rule requirements.

[0023] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0024] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application. It is apparent that the drawings described below are only some embodiments of the present application, and other drawings can be obtained according to these drawings without creative labor for those skilled in the art. In the drawings:

[0025] Figure 1 A flowchart of a chip layout correction method based on a double patterning process in an embodiment of the present application is shown;

[0026] Figure 2 A schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown;

[0027] Figure 3 A schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown;

[0028] Figure 4 A schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown;

[0029] Figure 5 A block diagram of a chip layout correction device based on a double patterning process in an embodiment of the present application is shown;

[0030] Figure 6 A structural schematic diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0032] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will recognize that the technical solutions of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0033] The block diagrams shown in the drawings are only functional entities, which do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices. It should be noted that in the drawings, in order to ensure the simplicity of the drawings, some components in the drawings are omitted, which do not affect the explanation of the technical solutions of the present application.

[0034] The flowcharts shown in the drawings are only exemplary illustrations, which do not necessarily include all contents and operations / steps, and are not necessarily executed in the described order. For example, some operations / steps can be further divided, and some operations / steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0035] In the description of the present application, it should be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0036] In order for those skilled in the art to better understand the present application, first, the technical concepts and application background related to the present application are briefly described.

[0037] Integrated Circuit (IC): Integrated circuit, also known as microchip or chip, refers to a microelectronic device with specific circuit functions, which is formed by concentrating a large number of transistors, diodes, resistors, capacitors, inductors and interconnections between these components on one or more semiconductor wafers (which can be silicon wafers), insulating substrates and other carriers through semiconductor manufacturing processes (such as photolithography, etching, doping, deposition, etc.), and packaging in an outer shell.

[0038] Chip Layout (CL): Chip layout, also known as chip physical layout, is the core intermediate carrier in the transition from logic design to physical manufacturing in the semiconductor chip design process, which converts the logic function and circuit structure of the chip into a two-dimensional / three-dimensional graphical description file that meets the requirements of semiconductor process manufacturing, and is also the direct basis for chip manufacturing and packaging testing.

[0039] Double Patterning Technology (DPT): Double patterning technology is a core process technology developed in the field of semiconductor chip manufacturing to break through the resolution limit of traditional photolithography, i.e. Deep Ultraviolet Lithography (DUV), and meet the high-precision pattern preparation needs of advanced process chips. The core logic is to divide the complex high-density patterns of the same metal layer (such as metal wiring layer, dielectric layer, etc.) in the chip layout into two independent sub-metal layers (sub-layouts), and then through two independent photolithography and etching processes, the two sub-metal layers are transferred to the wafer surface, and finally the high-precision, small-pitch target pattern that cannot be achieved by single photolithography is formed by superposition.

[0040] The applicant found that in the prior art, after the metal layer wiring is completed, the odd ring resolution efficiency is low, and as the size of the chip layout expands, the number of odd rings increases and the distribution is complex. The traditional correction method adopts a whole processing method to resolve the odd ring, which leads to excessive data processing amount and long correction period in the correction process, and cannot meet the rapid correction needs of large-scale chip layout, and in the odd ring resolution process, the prior art randomly selects the connection edge to be resolved, which leads to the need for multiple repeated resolution operations, increases the complexity of the correction process, greatly affects the correction efficiency of the chip layout, and may cause excessive deformation of the pattern due to unreasonable connection edge processing, affecting the original design function of the chip layout, further reducing the overall correction efficiency. Under this circumstance, the present application proposes a chip layout correction scheme based on double patterning technology to improve the correction efficiency of the chip layout.

[0041] The implementation details of the technical solutions of the embodiments of the present application are described below:

[0042] Referring to Figure 1 , a flow chart of a chip layout modification method based on a double patterning process in an embodiment of the present application is shown, which can be executed by a device with computing processing function. Referring to Figure 1 , the chip layout modification method based on a double patterning process includes at least steps 110 to 140, which are described in detail as follows:

[0043] Referring to Figure 1 , in step 110, a chip layout to be processed is obtained, and a pair of conflicting patterns in a target metal layer of the chip layout is determined, the target metal layer being a metal layer to be applied to a double patterning process.

[0044] In an actual chip manufacturing process, the target metal layer is a key layer for realizing a specific electrical function of a chip, such as a metal wiring layer for realizing signal connection between transistors in a 12 nm process logic chip. Determining a pair of conflicting patterns is the basis for subsequent modification work, and the core purpose is to accurately identify a pattern combination that can cause a lithography defect.

[0045] In an embodiment of the present application, the determination of a pair of conflicting patterns in the target metal layer of the chip layout can be performed according to the following steps 111 to 112:

[0046] Step 111, a process rule spacing of the target metal layer is obtained, the process rule spacing being a minimum pattern spacing that meets process production conditions.

[0047] Step 112, if an actual spacing of any adjacent patterns in the target metal layer is less than a set multiple of the process rule spacing, the any adjacent patterns are determined as a pair of conflicting patterns.

[0048] In the present application, the process rule spacing is a minimum pattern spacing that meets process production conditions. Specifically, the process rule spacing is a key parameter determined by a chip manufacturing process, and different processes and different metal layers have different process rule spacings. For example, the process rule spacing of a 14 nm process metal layer can be 50 nm, and the process rule spacing of a 7 nm process metal layer can be reduced to 30 nm. This parameter can be determined by a chip manufacturer according to the performance of its lithography equipment, etching process level and other factors. Further, if an actual spacing of any adjacent patterns in the target metal layer is less than a set multiple of the process rule spacing, the any adjacent patterns are determined as a pair of conflicting patterns. Wherein,

[0049] In the embodiment, the set multiple is a flexible adjustable parameter, and the value of the set multiple needs to comprehensively consider factors such as process stability and precision redundancy of the photolithography equipment. The set multiple can be set to be between 1-1.5, for example, for a mature process with high manufacturing process stability, the set multiple can be set to 1.1. For an advanced process with high process difficulty, the set multiple can be set to 1.5. The core logic of the determination mode of the conflict pattern pair can be that when the actual spacing of the adjacent patterns is less than the set multiple of the process rule spacing, the risk of pattern distortion, bridge connection and other defects in the photolithography process is significantly increased, and therefore the conflict pattern pair needs to be determined and corrected subsequently.

[0050] Based on the technical solutions of steps 111-112, only two parameters, the process rule spacing and the actual spacing of the adjacent patterns, need to be obtained, and the conflict determination can be completed through simple multiplication and size comparison operations, without complex model calculation, so that the calculation amount is small, the implementation difficulty and the calculation complexity of the algorithm are reduced, the algorithm is convenient to integrate into various chip layout design verification tools, large-scale chip layout data can be quickly processed, and the conflict screening of all adjacent patterns can be completed in a short time, so that time is saved for subsequent odd ring detection and elimination, and the overall layout correction efficiency is improved. The determination mode has high flexibility and practicability, and the adjustability of the set multiple enables the determination mode to adapt to chip layout correction requirements of different manufacturing processes, equipment conditions, processes and reliability requirements. The set multiple can be low in mature processes to improve the correction efficiency, and the set multiple can be high in advanced processes to improve the manufacturing reliability. When the process level is improved and the precision of the photolithography equipment is improved, the set multiple can be appropriately reduced to reduce unnecessary correction operations. When the process stability is insufficient, the set multiple can be increased to ensure that all potential conflict risks can be identified. In addition, the determination result has high reliability. The process rule spacing is the minimum safe spacing determined based on the actual production conditions, the introduction of the set multiple reserves a certain redundancy space for process execution, can accurately identify the explicit conflict caused by too small spacing, effectively avoids manufacturing defects such as photolithography distortion and bridge connection caused by small process fluctuations, layout measurement errors and the explicit conflict, ensures the basic manufacturing feasibility of the chip, and improves the yield of chip manufacturing.

[0051] In another embodiment of the present application, the determination of the conflict pattern pair existing in the target metal layer of the chip layout can also be performed according to steps 113-115 as follows:

[0052] In step 113, the process rule spacing of the target metal layer and the factor weight of the target metal layer on a plurality of process risk factors are obtained. The process rule spacing is the minimum pattern spacing that meets the process production conditions.

[0053] Step 114, based on the process rule spacing, the factor weight, and the actual spacing of any adjacent patterns in the target metal layer, the conflict risk value of the any adjacent patterns under the double patterning process is calculated by a conflict quantification model.

[0054] Step 115, if the conflict risk value is greater than a set risk value, the any adjacent patterns are determined as a conflict pattern pair.

[0055] In the embodiment, another more accurate conflict pattern pair determination method is provided, which comprehensively considers the process rule spacing and multiple process risk factors, and realizes the accurate identification of conflict pattern pairs through quantitative calculation.

[0056] Specifically, in the embodiment, in addition to the basic parameter of process rule spacing, multiple process risk factors are introduced, which are key factors affecting the quality of lithography and the feasibility of process. For example, it can include a lithography risk factor and a pattern type factor. Among them, the lithography risk factor reflects the risk degree of pattern distortion caused by factors such as equipment precision and light intensity uniformity in the lithography process. The pattern type factor is related to the geometric shape, size ratio and the like of the pattern, for example, the lithography difficulty of an elongated pattern is usually higher than that of a rectangular pattern, and the lithography difficulty of a metal line pattern is usually higher than that of a metal via pattern. The factor weight is a quantitative representation of the importance of each process risk factor, and its value range can be between 0-1, and the greater the weight value, the greater the influence of the factor on the conflict risk. The determination of the factor weight needs to be based on a large amount of process experimental data and statistical analysis, such as studying the influence degree of different factors on the lithography defect rate by orthogonal experiment method, and then determining the reasonable weight distribution.

[0057] In the embodiment, the conflict quantification model is the core of the embodiment scheme, which can establish a correlation between the process rule spacing, the factor weight, and the actual spacing and the conflict risk value through a mathematical formula, and can realize the quantitative evaluation of the conflict risk. The design of the model can fully consider the internal logical relationship between the parameters, and can comprehensively and objectively reflect the actual conflict risk of the pattern pair.

[0058] In the embodiment, the set risk value is a critical value for distinguishing whether there is an actual conflict risk of the pattern pair, and its determination needs to comprehensively consider factors such as the performance requirements, manufacturing costs, and yield targets of the chip. For example, for a chip with high performance and high reliability requirements, the set risk value can be set to a lower level (such as between -0.001 and 0.001) to strictly control the conflict risk. For a chip with low performance and low reliability requirements, the set risk value can be appropriately increased (such as between 0.001 and 0.1) to reduce the subsequent layout modification cost on the premise of ensuring basic performance.

[0059] In the embodiment, after the conflict risk value of any adjacent pattern under the double pattern process is calculated, the calculated conflict risk value is compared with the set risk value. If the conflict risk value is greater than the set risk value, it indicates that the adjacent pattern has a higher actual conflict risk in the manufacturing process, and is determined as a pattern pair with conflict.

[0060] Based on the technical solutions of steps 113 to 115, the process rule spacing, multiple key process risk factors, and actual spacing and other factors can be comprehensively considered. The process risk factors and spacing parameters are organically combined through a quantitative model, which can more comprehensively and objectively evaluate the actual conflict risk of the pattern pair, effectively avoid the missed judgment of potential conflicts and the misjudgment of patterns without actual risk, for example, for a pattern pair with an actual spacing slightly greater than the set multiple of the process rule spacing but a higher lithography risk, the conflict risk value after model calculation may exceed the set threshold and be accurately determined as a conflict pattern pair. For a pattern pair with a smaller actual spacing but a simple pattern type and a very low lithography risk, the conflict risk value may be lower than the set threshold, thereby avoiding unnecessary modification operations. The determination method is suitable for complex process scenarios, introduces multiple process risk factors and their weights, can fully consider the influence of various factors on manufacturing conflicts, and is consistent with the characteristics of complex process risks in advanced processes, improving the pertinence and effectiveness of conflict determination. It is flexible, and the factor weight and the set risk value can be flexibly adjusted and individually configured according to different process requirements, chip types, performance targets, and reliability requirements, etc. The lithography risk factor weight can be increased and the determination standard can be strictly determined in a high-risk advanced process with a higher lithography process difficulty, or the set risk value can be appropriately increased and the standard can be relaxed in a low-risk scene with a higher cost control requirement, balancing the modification efficiency and manufacturing reliability. At the same time, accurate conflict determination can clearly determine the modification object, provide a more reliable basis for subsequent conflict graph construction and odd ring detection, avoid modification process confusion caused by false conflicts or missed conflicts, reduce the complexity of the modification process, ensure that the modification resources are concentrated for processing pattern pairs with real risks, improve the overall modification efficiency, and the calculation result of the conflict risk value can also provide data support for chip manufacturing process optimization. By analyzing the conflict risk value distribution of different pattern pairs, the weak links in the process can be identified, and the lithography process parameters or pattern design rules can be optimized, thereby fundamentally reducing the conflict risk.

[0061] Specifically, in the embodiment, the conflict quantification model can be as shown in formula (1):

[0062] (1)

[0063] wherein, represents the conflict risk value of the arbitrary adjacent pattern under the double pattern process; represents the process rule spacing set for the target metal layer, and is a constant; represents the factor weight of the lithography risk, and is a constant; represents the factor weight of the pattern type, and is a constant; represents the actual spacing of any adjacent patterns in the target metal layer, and is a variable.

[0064] In the present application, for the above conflict quantification model, the process rule requirement and the comprehensive requirement of various risk factors on the pattern spacing can be comprehensively reflected, and can be regarded as the equivalent safety spacing considering the risk factors; the difference between the equivalent safety spacing and the actual spacing is converted by an exponential function, and then 1 is subtracted to obtain the conflict risk value. When the difference is positive, the result of the exponential function is greater than 1, greater than 0, and the greater the difference, the greater the value, indicating that the conflict risk is higher; when the difference is negative or zero, the result of the exponential function is less than or equal to 1, less than or equal to 0, indicating that the conflict risk is low or there is no conflict risk.

[0065] In the present application, in order to enable those skilled in the art to better understand the conflict quantification model shown in formula (1), the following will be described in combination with several specific embodiments:

[0066] In an embodiment of the present application, assuming that a logic chip of a 7nm process, the process rule spacing of the target metal layer is According to the lithography process conditions of the chip, the lithography risk factor weight is determined, since the patterns of the layer are mainly regular rectangles, the pattern type factor weight is determined. The actual spacing of adjacent patterns N and O is , which is substituted into the model for calculation:

[0067]

[0068] If the risk value is set to 0, then is much greater than the set risk value, and it can be determined that the patterns N and O are a conflict pattern pair.

[0069] In an embodiment of the present application, assuming that a radio frequency chip of a 14nm process, the target metal layer , the lithography equipment precision is high, , and the patterns are all regular squares, . The actual spacing of adjacent patterns R and S is , substitute into the model to calculate:

[0070]

[0071] If the risk value is set to 0, then If the risk value is less than the set risk value, it can be determined that the patterns R and S do not constitute a conflict pair.

[0072] As can be seen from the above examples, the greater the factor weight of the process risk factor, the greater the equivalent safety distance calculated, and the higher the conflict risk value under the same actual distance.

[0073] Based on the above conflict quantification model, the process rule distance and the weights of the two process risk factors are nonlinearly fused by an exponential function, which can sensitively reflect the comprehensive influence of each factor. Compared with the linear model, it is more in line with the law of risk accumulation in actual manufacturing. At the same time, the process rule distance, multiple process risk factors and actual distance are organically combined. Abstract conflict risk is converted into specific numerical value, so that conflict judgment is upgraded from qualitative judgment to quantitative analysis, which greatly improves the scientificity and accuracy of conflict judgment. In addition, the characteristics of the exponential function also enable the model to respond significantly to changes in the comprehensive risk coefficient. Even a small change in the weight of the process risk factor or the actual distance can be reflected in the conflict risk value, effectively distinguishing different degrees of conflict risk, and further improving the accuracy and sensitivity of risk assessment.

[0074] The calculation process of the above conflict quantification model is relatively simple, only involving basic four arithmetic operations and exponential operation, without complex matrix operation or iterative solution, the calculation complexity is moderate, which can quickly process large-scale chip layout data while ensuring the evaluation accuracy, meet the rapid calculation demand, and will not affect the overall correction efficiency due to excessive calculation amount. The conflict risk value calculated by the model can objectively and quantitatively reflect the conflict risk of adjacent pattern pairs, providing a scientific and unified standard for conflict pattern pair judgment, avoiding the uncertainty brought by subjective judgment. At the same time, by analyzing the influence degree of each parameter in the model on the risk value, data support can also be provided for the optimization of chip manufacturing process and the improvement of pattern design rules, which can evaluate the influence effect of different process improvement measures on conflict risk and provide guidance for process optimization direction.

[0075] Continuing to refer to Figure 1 In step 120, a conflict graph is constructed in the target metal layer by taking the patterns in the pattern pair as nodes and the conflict relationship between the patterns as connecting edges, and an odd cycle is detected in the conflict graph. The odd cycle is a closed loop formed by an odd number of patterns through connecting edges.

[0076] In the present application, the odd ring is a closed loop formed by an odd number of patterns through connection edges. The conflict graph is a visualized abstraction of the conflict relationship between patterns, and each node represents an independent pattern. The existence of the connection edge indicates that there is a process conflict risk between the two patterns. The detection of the odd ring is a key link of the modification work, because this kind of closed loop composed of an odd number of patterns cannot meet the process requirements through the conventional double pattern segmentation method, and must be processed through a special modification means.

[0077] In the present application, the detection of the odd ring in the conflict graph can be performed according to the following steps 121 to 122:

[0078] Step 121, calling a graph theory loop extraction algorithm to traverse each closed loop in the conflict graph, and counting the number of nodes of each closed loop.

[0079] Step 122, determining the closed loop with an odd number of nodes as an odd ring.

[0080] In the present application, the graph theory loop extraction algorithm is a kind of algorithm specially used for identifying closed loops in patterns, and common ones include depth-first search (DFS) algorithm, breadth-first search (BFS) algorithm, etc. In the present application, a suitable algorithm can be selected according to the size and complexity of the conflict graph. For example, for a conflict graph with small size and relatively simple structure, the BFS algorithm can be used, which has the advantages of fast traversal speed and low memory occupation; for a conflict graph with large size and complex loop structure, the DFS algorithm can be used, which is more advantageous in the integrity of loop identification. In the traversal process, the algorithm starts from an arbitrary node of the conflict graph, and successively visits other nodes along the connection edges. When it returns to the starting node again, a closed loop is formed. At the same time, the number of nodes contained in each loop is recorded during the traversal process, which provides a basis for the subsequent odd ring judgment.

[0081] Further, the closed loop with an odd number of nodes can be determined as an odd ring. The core feature of the odd ring is a closed loop formed by an odd number of nodes (patterns) through connection edges (conflict relationships), which is the fundamental reason why the odd ring cannot meet the process requirements through the conventional double pattern segmentation method. By counting the number of nodes of each closed loop, the odd ring can be quickly and accurately screened out, and the target for the subsequent elimination operation is clear.

[0082] In order to enable those skilled in the art to better understand the above steps 121 to 122, a specific embodiment is described below. Figure 2

[0083] Referring to Figure 2 , a schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown. In the conflict graph shown in​Figure 2 In the target metal layer shown, assume that the conflict risk values of each adjacent pattern are as shown in Table 1.

[0084] Table 1: Example table of conflict risk values of adjacent patterns

[0085]

[0086] In this embodiment, assume that the set risk value is set to 0, then based on Table 1, it can be determined that the pattern pairs in which there is a conflict in the target metal layer 200 are A-B, A-F, A-G, A-H, B-C, B-H, C-D, D-E, D-G, E-F, and E-G.

[0087] Further, in the conflict graph, the patterns in the conflict pattern pair are nodes, and the conflict relationship between the patterns is a connecting edge. The conflict graph is constructed in the target metal layer. Then, a graph theory loop extraction algorithm is called to traverse each closed loop in the conflict graph, and the number of nodes in each closed loop is counted. The closed loop in which the number of nodes is odd is determined as an odd loop, such as Figure 2 As shown, the determined odd loop specifically includes:

[0088] Odd loop 1: A-B-H-A;

[0089] Odd loop 2: A-B-C-D-G-A;

[0090] Odd loop 3: A-B-C-D-G-E-F-A;

[0091] Odd loop 4: A-H-B-C-D-E-F-A;

[0092] Odd loop 5: D-E-G-D;

[0093] Odd loop 6: D-E-F-A-G-D.

[0094] Based on the technical solutions in steps 121-122, the graph theory loop extraction algorithm is used to detect odd loops, which can systematically and comprehensively traverse all closed loops in the conflict graph, accurately count the number of nodes in each loop, and filter out odd loops, thereby effectively avoiding the omission or misjudgment problems that may occur in manual detection or simple logical judgment, ensuring the accuracy of the odd loop detection result and providing accurate targets for subsequent odd loop resolution. For conflict graphs of different sizes and complexities, suitable algorithms such as depth-first search and breadth-first search can be selected for this graph theory loop extraction algorithm. For large-scale conflict graphs, optimization strategies such as pruning parallel traversal and the use of marked array queue management can be used to improve traversal speed and reduce redundant calculations, allowing the detection to be completed within a reasonable time and meeting the efficiency requirements of large-scale chip layout modification. In addition, this method can also clearly identify the nodes and connecting edges included in each odd loop, providing clear target information for subsequent modification region division and target connecting edge selection, and can clearly identify the key objects for subsequent modification, avoid waste of modification resources, and improve the effectiveness of subsequent modification operations and the efficiency of the overall modification process.

[0095] With reference to the above Figure 1 In step 130, if an odd loop is detected in the conflict graph, the target metal layer is divided into multiple modification regions.

[0096] In this application, reasonable region division is the premise of parallel processing. By dividing a large-scale target metal layer into multiple independent modification regions, the computing resources of multi-threading and multi-processor can be fully utilized, and the efficiency bottleneck caused by overall processing can be avoided.

[0097] In this application, the division of the target metal layer into multiple modification regions can be performed according to the following steps 131-132:

[0098] Step 131: The target metal layer is divided into multiple first regions with similar number of odd loops, and the number of odd loops in each first region is less than a set number.

[0099] Step 132: Each first region is divided into at least two second regions with similar sizes, and the second regions are defined as the modification regions.

[0100] In the present application, the number of settings is a critical value determined according to the computing power of the computing device, the correction efficiency target and other factors, such as being set to 35-45. The core purpose of this step is to relatively evenly distribute the odd rings in each first region, avoiding excessive concentration of odd rings in a certain region, which leads to excessive difficulty in correction. At the same time, it ensures that the number of odd rings in each first region is within a controllable range, laying a foundation for subsequent subdivision and parallel processing. During the division process, factors such as the distribution position of the odd ring and the adjacent relationship need to be considered to ensure that the division of the first region does not damage the integrity of the odd ring, which is convenient for subsequent processing.

[0101] Further, each first region can be divided into at least two second regions with similar region sizes, and the second regions are defined as the correction regions. The purpose of this step is to further reduce the number of odd rings that a single thread needs to process, while achieving the balance of correction region size, ensuring that the number of graphics and the area size of each correction region are relatively consistent, so that the correction workload of each region is equivalent when parallel processing, avoiding the situation that some regions are still in long-time processing after the correction of other regions is completed, and fully exerting the efficiency advantage of parallel processing.

[0102] In order to enable those skilled in the art to better understand the above steps 131 to 132, the following is described in combination with a specific embodiment. Figure 3 A specific embodiment is described.

[0103] Referring to Figure 3 , a schematic diagram of a target metal layer in a chip layout in the embodiment of the present application is shown.

[0104] As shown in Figure 3 , the metal layer pattern 300 of a certain double pattern process contains 120 odd rings, and the number of odd rings in each first region is set to not more than 45. The layout is divided into three first regions FR1, FR2 and FR3 by a region division algorithm, and the number of odd rings in each region is 42, 41 and 37 respectively. Then the first regions FR1, FR2 and FR3 are divided into second regions FR1-1 and FR1-2, second regions FR2-1 and FR2-2, and second regions FR3-1 and FR3-2 respectively as correction regions, and the number of odd rings in each correction region is between 18 and 22, and the region size is similar, providing a basis for parallel elimination.

[0105] Based on the technical solutions of steps 121-122, the two-stage division method lays a good foundation for parallel processing. The first-stage division divides the target metal layer into multiple first regions with similar odd loop numbers and each region having an odd loop number less than a set number, achieving balanced odd loop distribution, avoiding excessive concentration of odd loops in a single region, and ensuring that the correction workload of each region is within a controllable range, thereby reducing the overall correction difficulty. The second-stage division divides each first region into second regions of similar size, i.e., the final correction regions, making the number of patterns in each correction region relatively consistent and ensuring that the correction time of each region is similar and the load of each processing unit is balanced during subsequent parallel processing. This can significantly improve the overall efficiency of odd loop elimination and avoid low parallel efficiency caused by large differences in region size or odd loop number, thereby significantly shortening the overall correction period. Meanwhile, this balanced region division can improve resource utilization, avoid situations where some regions have insufficient correction resources while others have idle resources, maximize the effectiveness of hardware processing resources, and make the correction difficulty of each correction region relatively balanced, thereby avoiding correction failure or excessive pattern distortion caused by excessive correction difficulty in a single region and improving the stability and reliability of the overall correction process. In addition, the division method has clear logic and simple operation, with the first stage focusing on balanced odd loop distribution and the second stage focusing on balanced region size, making the operation process easy to implement and control. Moreover, the division parameters such as the set number and the number of second regions can be flexibly adjusted according to actual conditions, making the method suitable for various chip layouts from small to large scales and having strong versatility and flexibility.

[0106] In step 131, the target metal layer can be divided into multiple first regions with similar odd loop numbers according to steps 1311-1312 as follows:

[0107] Step 1311: Traverse the untraversed grid regions in the target metal layer in a set traversal order.

[0108] Step 1312: When a current grid region is traversed, count the total number of odd loops in the traversed grid regions. If the total number of odd loops exceeds a set number, mark the grid regions traversed before the current grid region as a first region and reset the traversed grid regions and the total number of odd loops.

[0109] Step 1313: Take the current grid region as the first untraversed grid region and repeat the grid region traversal process until all grid regions are traversed.

[0110] In the present application, the target metal layer is divided into multiple uniform grid regions according to a preset grid size. The setting of the grid size needs to comprehensively consider the area, pattern density and odd loop distribution of the target metal layer. For example, for a target metal layer with a large area and high pattern density, the grid size can be set to 50 μm x 50 μm; for a target metal layer with a small area and low pattern density, the grid size can be set to 100 μm x 100 μm. The traversal order can be row priority traversal from left to right and top to bottom, or column priority traversal from top to bottom and left to right. When selecting the traversal order, it is necessary to ensure that all grid regions can be fully and orderly covered, and omission is avoided.

[0111] In the traversal process, the number of odd loops in each grid region is added to the total number of odd loops every time a grid region is traversed. When the total number of odd loops exceeds the set number, it indicates that the number of odd loops contained in the currently accumulated grid regions has reached a reasonable range, and these grid regions need to be divided into an independent first region. Then, the list of accumulated traversed grid regions and the total number of odd loops are reset, and the accumulation is restarted from the current grid region, ensuring that the subsequent divided first regions also meet the odd loop number requirement. After that, the current grid region can be taken as the first grid region that has not been traversed, and the grid region traversal process is repeated until all grid regions are traversed. This step can ensure that all grid regions can be orderly divided into various first regions, avoiding the omission of grid regions. For the last part of the grid regions, if the accumulated number of odd loops does not exceed the set number, they are still marked as an independent first region, ensuring that all odd loops are contained in the first region.

[0112] For example, in a specific embodiment, the target metal layer is divided into 100 μm x 100 μm grid regions, and the number of odd loops in each first region is set to not exceed 40. The traversal order is from left to right and top to bottom. After starting the traversal, the (1,1), (1,2), …, (1,5) grid regions are traversed in turn. At this time, the total number of odd loops of the accumulated traversed grid regions is 38, which does not exceed the set number 40. Continue to traverse the (1,6) grid region, and the total number of odd loops becomes 42, which exceeds the set number 40. At this time, the (1,1)-(1,5) grid regions are marked as first region 1, and the accumulated traversed grid regions and the total number of odd loops are reset. Then, the (1,6) grid region is taken as the first grid region that has not been traversed, and the (1,7), (1,8) and other grid regions are continued to be traversed, and the above statistical and marking process is repeated. When the (5,10) grid region is traversed, the accumulated number of odd loops reaches 40, and the corresponding accumulated traversed grid regions are marked as first region n. Continue to traverse the remaining grid regions until all 100 grid regions are traversed, and finally the target metal layer is divided into multiple first regions with similar number of odd loops.

[0113] Based on the technical solutions of steps 1311 to 1313, the division is performed in a grid traversal manner, which can be operated according to a preset traversal order and rule, so that the division process has good order and standard, and problems such as chaotic region boundary of uneven odd loop distribution caused by manual division or simple random division can be effectively avoided. The method can automatically complete the division of the first region by setting the traversal order and the statistical rule, without manual intervention, and has high automation, which reduces the operation complexity and improves the division efficiency. In the division process, the number of accumulated odd loops is counted in real time, and the region is divided when the number exceeds the set number, so that the number of odd loops in each first region can be accurately controlled, the number of odd loops in each first region is ensured to be less than the set number and the overall distribution is similar, the problem of too concentrated or too sparse odd loops in some regions is avoided, the balance of odd loop distribution is realized, the correction difficulty of a single region is reduced, and the traversal order can be flexibly selected to adapt to chip layouts of different shapes and odd loops of different distribution densities, so that the comprehensiveness and rationality of the division process are ensured.

[0114] In addition, the grid traversal manner can quickly cover the entire target metal layer, and the calculation process of the accumulated number of odd loops is simple and efficient, without complex analysis and judgment, so that the division efficiency is high, the first region division can be quickly completed, the efficiency requirement of large-scale chip layout correction is met, and the steps of the method are clear and explicit. The setting of the traversal order of the grid region and the statistics of the number of odd loops are easy to program and implement, and the operability is strong, so that the method can be quickly integrated into a chip layout correction tool. The process of the division method is based on clear rules and steps, and the same result can be obtained by dividing the same target metal layer each time, so that the division result has good consistency and repeatability, and provides a stable basis for subsequent correction operations. The division of the first region based on the grid region has a clear and regular boundary, and the uniform division of the first region also provides a good foundation for the second-level region division, so that the second-level division can more easily realize the balance of the region size, further guarantee the efficiency of parallel processing, and ensure the rationality and efficiency of the entire correction region division.

[0115] Continuing with reference to Figure 1 In step 140, the odd loops in the plurality of correction regions are resolved in parallel, and the step of determining the existence of a pair of conflicting patterns in the target metal layer of the chip layout is performed until there is no odd loop in the constructed conflict graph.

[0116] In the present application, parallel resolution can greatly shorten the correction time, and the process of cyclic iteration ensures that all potential odd loop conflicts can be completely eliminated, and finally a chip layout that meets the process rule requirements is obtained.

[0117] In the present application, specifically, the odd cycle in the modification region can be eliminated according to the following steps 141 to 142:

[0118] Step 141, determining at least one target connection edge to be repaired in the modification region.

[0119] Step 142, performing shift processing and / or cutting processing on one of the graphs associated with each target connection edge to eliminate the odd cycle to which each target connection edge belongs.

[0120] In the present application, the core of the odd cycle elimination is to break the closed structure of the odd cycle by processing the graphs associated with the target connection edge, so as to eliminate the odd cycle. First, the target connection edge to be eliminated can be determined in the modification region. The target connection edge refers to the connection edge that plays a key role in the elimination of the odd cycle, which can be the connection edge that belongs to multiple odd cycles and can eliminate multiple odd cycles through a single processing. Determining the target connection edge is a key link in the elimination of the odd cycle, and the core purpose is to eliminate the most odd cycles by processing the least connection edges, improve the modification efficiency, and reduce the deformation of the graph.

[0121] Further, shift processing and / or cutting processing can be performed on one of the graphs associated with each target connection edge. The shift processing refers to moving the graph in a specific direction (such as the horizontal direction or the vertical direction) by a certain distance, increasing or adjusting the spacing between the graphs, and eliminating the conflict relationship. The cutting processing refers to cutting the edge of the graph, reducing the size of the graph, and thus increasing the spacing between adjacent graphs, and eliminating the conflict relationship. According to the shape, position and conflict situation of the graph, the shift processing alone, the cutting processing alone, or the combination of the two processing methods can be selected. For example, for the graph with a large adjustable space, the shift processing can be used; for the graph with limited space for position adjustment but with redundant size, the cutting processing can be used; for the conflict situation, the shift and cutting processing can be used at the same time to achieve better elimination effect.

[0122] In order to enable those skilled in the art to better understand the above steps 141 to 142, the following will be described in conjunction with Figure 4 a specific embodiment.

[0123] Referring to Figure 4 , a schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown.

[0124] As shown in Figure 4 , in the target metal layer 400, an odd cycle is formed between the graph I, the graph J and the graph K. For example Figure 4 , as shown in subgraph (a), by cutting the graph K, the odd cycle is eliminated, and the graph I, the graph J and the graph K are obtained as shown in Figure 4the target metal layer shown in subgraph (b) in FIG. 12B. Also for example Figure 4 as shown in subgraph (c) in FIG. 12C, by performing shift processing on the pattern K, the odd loop is eliminated, and a target metal layer as shown in subgraph (d) in FIG. 12D is obtained. Figure 4 as shown in subgraph (c) in FIG. 12C, by performing shift processing on the pattern K, the odd loop is eliminated, and a target metal layer as shown in subgraph (d) in FIG. 12D is obtained. Figure 4 as shown in subgraph (e) in FIG. 12E, by performing both cutting and shift processing on the pattern K, the odd loop is eliminated, and a target metal layer as shown in subgraph (f) in FIG. 12F is obtained. Figure 4 as shown in subgraph (e) in FIG. 12E, by performing both cutting and shift processing on the pattern K, the odd loop is eliminated, and a target metal layer as shown in subgraph (f) in FIG. 12F is obtained.

[0125] Based on the technical solutions of steps 141-142 described above, by determining the target connection edge and processing the pattern associated with the target connection edge, the closed structure of the odd loop can be directly broken. The method provides three processing methods of shift cutting and combination, and the appropriate processing method can be selected according to the actual situation of the pattern, that is, the shape, size, periphery layout, and other specific conditions of the pattern. The method can adapt to patterns of different shapes, positions, and conflict degrees, adapt to the elimination needs of different types of odd loops, and improve the adaptability and effectiveness of odd loop elimination. In the pattern processing layer, both shift processing and cutting processing are local and small adjustments to the pattern, and the processing process is only performed on a single pattern associated with the target connection edge. The processing range and degree can be accurately controlled. Compared with the method of overall reconstructing the pattern or simultaneously adjusting multiple patterns, the original design features and size ratio of the pattern can be maximally preserved, the degree of pattern deformation is further reduced, the influence of pattern deformation on the performance of the chip is reduced, and the original design function of the pattern is preserved. The determination of the target connection edge and the selection of the processing method of the method are based on clear logic and rules. In the processing process, the processing direction, distance, and range can also be reasonably selected according to the layout of the surrounding pattern, avoiding the uncertainty caused by random processing, effectively avoiding new conflicts or pattern function failure caused by improper processing, reducing the risk of new conflicts, and ensuring the controllability and stability of the elimination process, improving the stability and reliability of the correction.

[0126] In step 141 described above, the at least one target connection edge to be repaired in the correction area can be executed according to steps 1411-1413 as follows:

[0127] Step 1411: Each connection edge in the correction area is traversed, and the corresponding relationship between each connection edge and the odd loop to which it belongs is recorded in a temporary table.

[0128] Step 1412: The connection edge with the largest number of odd loops in the temporary table is counted as the target connection edge to be repaired.

[0129] Step 1413, hide the odd ring to which the target connection edge belongs in the temporary table, and return to execute the step of counting the connection edge with the most number of belonging odd rings in the temporary table until all the odd rings recorded in the temporary table are hidden.

[0130] In this application, first, each connection edge in the correction area can be traversed, and the corresponding relationship between each connection edge and the odd ring to which it belongs is recorded in the temporary table, which is a data structure for storing connection edge and odd ring association information, and its fields can include connection edge identifier, belonging odd ring identifier list, etc. For example, the belonging odd ring identifier list of connection edge A-B is odd ring 1 and odd ring 3, which means that connection edge AB belongs to odd ring 1 and odd ring 3 at the same time. Each connection edge is checked one by one during the traversal process to determine all the odd rings to which it belongs, ensuring that the relevant information is accurately recorded and that no association between the connection edge and the odd ring is missed.

[0131] Then, the connection edge with the most number of belonging odd rings is counted in the temporary table and is taken as the target connection edge to be repaired. The number of belonging odd rings is a key indicator for measuring the importance of the connection edge. The more this value, the greater the influence of the connection edge on the elimination of odd rings. Therefore, this type of connection edge needs to be determined as the target connection edge first. When counting, the number of belonging odd rings of each connection edge is counted, and then the connection edge with the most number of belonging odd rings is selected. If there are multiple connection edges with the same number of belonging odd rings and the number is the most, these connection edges can be listed as candidate target connection edges first, and the final target connection edge can be determined through further rule screening.

[0132] Finally, the odd ring to which the selected target connection edge belongs is hidden in the temporary table. Hiding the odd ring means removing the corresponding odd ring from the odd ring list in the temporary table so that it no longer participates in the subsequent counting of the number of belonging odd rings of the connection edge. This is because the odd ring to which the target connection edge belongs will be eliminated after the target connection edge is processed, and there is no need to consider other connection edges corresponding to these odd rings. Then, the step of counting the connection edge with the most number of belonging odd rings in the temporary table is executed again. Through the iterative execution of the selection and hiding process, the connection edge that plays a key role in the elimination of the remaining odd rings is continuously selected until all the odd rings recorded in the temporary table are hidden, that is, all the odd rings can be eliminated through the selected target connection edge.

[0133] In order to better understand the above steps 1411 to 1413, the following will continue to combine the above Figure 2 A specific embodiment is described.

[0134] As Figure 2 shown, the correction area 200 includes:

[0135] Odd ring 1: A-B-H-A;

[0136] Odd ring 2: A-B-C-D-G-A;

[0137] Odd ring 3: A-B-C-D-G-E-F-A;

[0138] Odd ring 4: A-H-B-C-D-E-F-A;

[0139] Odd ring 5: D-E-G-D;

[0140] Odd ring 6: D-E-F-A-G-D.

[0141] The correspondence between each connection edge in the correction area 200 and the odd ring to which it belongs is recorded in a temporary table, as shown in Table 2 below:

[0142] Table 2: Correspondence between connection edges and the odd rings to which they belong

[0143]

[0144] According to the above step logic, based on the temporary table as shown in Table 2, it can be determined that the connection edges D-G and B-H can be determined as target connection edges to be eliminated, or the connection edges D-G and A-H can be determined as target connection edges to be eliminated.

[0145] Based on the technical solutions of steps 1411 to 1413 described above, by counting the number of odd rings to which a connection edge belongs, the connection edges that play a key role in odd ring elimination can be processed in a targeted manner, especially those connection edges that belong to multiple odd rings. After processing, multiple odd rings can be eliminated at the same time. Compared with the traditional overall adjustment method, the elimination efficiency is higher and the targeting is stronger. The number of elimination operations can be reduced, the efficiency of odd ring elimination can be improved, and the efficient odd ring elimination method reduces the number of elimination operations and the amplitude of graphic adjustment, reduces the complexity of the correction process, saves time for subsequent loop iteration correction, and helps to shorten the correction period of the overall chip layout.

[0146] The method can continuously filter out connection edges that play a key role in the remaining odd rings by iteratively performing the step of selecting and hiding, ensuring that all odd rings can be covered, and ultimately eliminating all odd rings by processing the selected target connection edges. This avoids missing odd rings. At the same time, the logic of preferentially processing key connection edges can reduce the number of elimination operations and the number of subsequent loop iterations, avoid repeated elimination and invalid operations caused by random selection of connection edges, not only reduce the complexity of the overall correction process, but also reduce the risk of accumulated graphic distortion and new conflicts caused by multiple operations.

[0147] The process of selecting the target connection edge of the method has good operability and repeatability, the statistics and screening process based on the temporary table has clear steps and rules, is simple to operate and is not affected by human factors, the same target connection edge selection result can be obtained for the same correction area each time, ensuring the repeatability and stability of the selection process, and the steps are clear, the construction of the temporary table, the statistics of the number of odd loops and the selection of the target connection edge are easy to program and realize, and can be quickly integrated into the automatic correction tool to realize the automatic processing of the odd loop elimination.

[0148] In addition, the determined target connection edge clearly determines the conflict relationship to be processed, provides a clear target for subsequent displacement and cutting processing, improves the pertinence and effectiveness of subsequent processing, and by selectively selecting the target connection edge, the influence on non-critical connection edges and graphics can be minimized while ensuring the elimination of odd loops, thereby ensuring the original design function and manufacturing precision of the chip layout.

[0149] In step 141 of the present application, the following steps 1414 to 1415 can also be performed:

[0150] In step 1414, if the connection edge with the most number of odd loops in the temporary table includes multiple connection edges, the actual distance between the adjacent graphics associated with each of the multiple connection edges is obtained.

[0151] In step 1415, the connection edge corresponding to the adjacent graphics with the largest actual distance is determined as the target connection edge.

[0152] In the present application, when the connection edge with the most number of odd loops in the temporary table includes multiple connection edges, the actual distance between the adjacent graphics associated with each of the multiple connection edges is first obtained. The actual distance between the adjacent graphics associated with the connection edge refers to the actual distance between the two graphics corresponding to the connection edge, which can be directly obtained from the chip layout data by a layout measurement tool and is an important indicator reflecting the conflict degree between graphics.

[0153] Then, the connection edge corresponding to the adjacent graph pair with the largest actual distance is determined as the target connection edge. The logical basis for selecting the connection edge with the largest actual distance as the target connection edge is that the graph pair with the larger actual distance has a relatively low conflict risk, and the conflict relationship can be eliminated by a small amount of displacement or cutting processing of one of the graphs, and the degree of graph deformation is smaller; while the graph pair with a smaller actual distance has a higher conflict risk, and a large amount of graph adjustment may be required to eliminate the conflict, which is easy to cause excessive graph deformation. Therefore, preferentially selecting the connection edge with the largest actual distance as the target connection edge can eliminate the odd ring while minimizing the graph deformation and ensuring the original design function of the chip layout. At the same time, it is also less likely to cause new conflicts with the surrounding graphs.

[0154] For example, based on the above embodiment, the actual distance between graph B and graph H associated with connection edge B-H is 45nm, and the actual distance between graph A and graph H associated with connection edge A-H is 48nm. Then, connection edges D-G and A-H can be selected as the final target connection edges to be eliminated.

[0155] Based on the technical solutions of steps 1414 to 1415, the selection of the target connection edge can be further optimized and the rationality of the selection can be improved. In the case that the number of odd rings to which a plurality of connection edges belong is the same, by introducing the actual distance as a supplementary screening standard, comparing the actual distances of the graphs associated with the connection edges and selecting the connection edge with the largest distance as the target connection edge, it can be ensured that the graph pair corresponding to the selected connection edge has a relatively low conflict risk and requires a smaller amount of graph adjustment, which can minimize the adjustment amount of the correction processing on the graph, thereby minimizing the graph deformation and ensuring the original design characteristics and original design function of the chip layout. At the same time, the graph pair with a larger actual distance only needs a small amount of adjustment to eliminate the conflict relationship, and the adjustment amount required during displacement or cutting processing is small, which is less likely to cause new overlapping or too small distance problems with the surrounding graphs. This can not only avoid the problems of excessive graph deformation and function failure that may be caused by a large amount of adjustment of a graph pair with a small actual distance, but also reduce the probability of new conflicts, improve the safety and reliability of the correction process, and further improve the reliability of odd ring elimination.

[0156] The screening scheme is simple, clear and easy to implement, only needs to obtain the actual distance of the connection edge associated graph and compare, so as to determine the final target connection edge, without complex calculation or analysis, the screening process is simple and efficient, and is convenient to integrate into the overall correction process. The target connection edge selected by the screening scheme can minimize the graph deformation while eliminating the odd ring, the minimized graph adjustment can maximize the original layout and size accuracy of the chip layout, and the correction efficiency and correction quality are considered, so as to ensure the performance and reliability of the final chip layout, and also ensure that the corrected chip layout meets the manufacturing requirements of the double pattern process, and ensures the manufacturing precision and performance of the chip. In addition, the screening scheme provides a clear solution for the case of multiple candidate connection edges, avoids the uncertainty caused by random selection, makes the selection process of the target connection edge more perfect, enhances the adaptability and flexibility of the overall correction method, and makes the selection of the target connection edge more scientific and accurate.

[0157] The device embodiment of the present application is introduced below, which can be used to execute the chip layout correction method based on the double pattern process in the above-mentioned embodiments of the present application. For details not disclosed in the device embodiment of the present application, please refer to the above-mentioned embodiments of the chip layout correction method based on the double pattern process.

[0158] Referring to Figure 5 , a block diagram of a chip layout correction device based on a double pattern process in an embodiment of the present application is shown.

[0159] As Figure 5 shown, the chip layout correction device 500 based on a double pattern process according to an embodiment of the present application includes an acquisition unit 501, a detection unit 502, a division unit 503 and an elimination unit 504.

[0160] The acquisition unit 501 is configured to acquire a chip layout to be processed, and determine a pair of conflicting graphs in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to a double pattern process. The detection unit 502 is configured to construct a conflict graph in the target metal layer by taking graphs in the pair of conflicting graphs as nodes and a conflict relationship between the graphs as connection edges, and detect an odd ring in the conflict graph, the odd ring being a closed loop formed by an odd number of graphs associated in sequence through connection edges. The division unit 503 is configured to divide the target metal layer into a plurality of correction regions if there is an odd ring in the conflict graph. The elimination unit 504 is configured to eliminate the odd ring in the plurality of correction regions in parallel, and return to execute the step of determining a pair of conflicting graphs in a target metal layer of the chip layout until there is no odd ring in the conflict graph.

[0161] In some embodiments of the present application, based on the foregoing scheme, the acquisition unit 501 is configured to: acquire a process rule spacing of the target metal layer, the process rule spacing being a minimum pattern spacing that meets process production conditions; and determine any adjacent patterns in the target metal layer as a conflicting pattern pair if an actual spacing of the any adjacent patterns is less than a set multiple of the process rule spacing.

[0162] In some embodiments of the present application, based on the foregoing scheme, the acquisition unit 501 is configured to: acquire a process rule spacing of the target metal layer, and a factor weight of the target metal layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing that meets process production conditions; calculate a conflict risk value of any adjacent patterns in the target metal layer under double pattern process by a conflict quantification model based on the process rule spacing, the factor weight, and an actual spacing of the any adjacent patterns; and determine the any adjacent patterns as a conflicting pattern pair if the conflict risk value is greater than a set risk value.

[0163] In some embodiments of the present application, based on the foregoing scheme, the conflict quantification model comprises:

[0164]

[0165] wherein, represents the conflict risk value of the any adjacent patterns under double pattern process; represents the process rule spacing set for the target metal layer, which is a constant; represents a factor weight of photolithography risk, which is a constant; represents a factor weight of pattern type, which is a constant; represents the actual spacing of the any adjacent patterns in the target metal layer, which is a variable.

[0166] In some embodiments of the present application, based on the foregoing scheme, the detection unit 502 is configured to: call a graph theory loop extraction algorithm to traverse each closed loop in the conflict graph, and count a number of nodes of each closed loop; and determine a closed loop with an odd number of nodes as an odd loop.

[0167] In some embodiments of the present application, based on the foregoing scheme, the division unit 503 is configured to: divide the target metal layer into a plurality of first regions with similar numbers of odd loops, the number of odd loops in each first region being less than a set number; divide each first region into at least two second regions with similar region sizes, and define the second regions as the correction regions.

[0168] In some embodiments of the present application, based on the foregoing scheme, the dividing unit 503 is configured to: traverse the grid regions in the target metal layer in sequence according to a set traversal order; whenever a current grid region is traversed, count the total number of odd loops of the grid regions that have been traversed cumulatively, and if the total number of odd loops exceeds a set number, mark the grid regions that have been traversed cumulatively before the current grid region as a first region, and reset the grid regions that have been traversed cumulatively and the total number of odd loops; take the current grid region as the first grid region that has not been traversed, and repeat the traversal process of the grid regions until all the grid regions are traversed.

[0169] In some embodiments of the present application, based on the foregoing scheme, the resolving unit 504 is configured to: determine at least one target connection edge to be repaired in the correction region; and perform a shift processing and / or a cutting processing on one of the graphs associated with each target connection edge to resolve the odd loop to which the each target connection edge belongs.

[0170] In some embodiments of the present application, based on the foregoing scheme, the resolving unit 504 is configured to: traverse each connection edge in the correction region, and record the correspondence between the each connection edge and the odd loop to which the each connection edge belongs in a temporary table; count the connection edge with the largest number of odd loops in the temporary table as a target connection edge to be repaired; hide the odd loop to which the target connection edge belongs in the temporary table, and return to the step of counting the connection edge with the largest number of odd loops in the temporary table until all the odd loops recorded in the temporary table are hidden.

[0171] In some embodiments of the present application, based on the foregoing scheme, the resolving unit 504 is configured to: if the connection edge with the largest number of odd loops counted in the temporary table includes multiple connection edges, obtain the actual distance between the adjacent graphs associated with each of the multiple connection edges; and determine the connection edge corresponding to the adjacent graphs with the largest actual distance as the target connection edge.

[0172] Based on the same inventive concept, the embodiments of the present application provide a computer program product, which comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device having the processor to perform the operations performed by the chip layout correction method based on the double-pattern process as described above.

[0173] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium, which stores at least one computer program instruction, and the at least one computer program instruction is loaded and executed by a processor to enable the processor to perform the operations performed by the chip layout correction method based on the double-pattern process as described above.

[0174] Based on the same inventive concept, the embodiments of the present application also provide an electronic device, which is shown in the structural schematic diagram of the electronic device in the embodiments of the present application, and includes one or more memories 604, one or more processors 602, and at least one computer program (computer program instructions) stored in the memory 604 and executable on the processor 602, and the processor 602 implements the chip layout correction method based on the double patterning process as described above when executing the computer program. Figure 6 , shows a structural schematic diagram of an electronic device in the embodiments of the present application, and the electronic device includes one or more memories 604, one or more processors 602, and at least one computer program (computer program instructions) stored in the memory 604 and executable on the processor 602, and the processor 602 implements the chip layout correction method based on the double patterning process as described above when executing the computer program.

[0175] In the above method, the chip layout correction method based on the double patterning process includes the following steps. Figure 6 In the above method, the chip layout correction method based on the double patterning process includes the following steps. The bus architecture (represented by the bus 600) can include any number of interconnected buses and bridges, the bus 600 links various circuits including one or more processors represented by the processor 602 and the memory represented by the memory 604. The bus 600 can also link various other circuits such as peripheral devices, voltage stabilizers and power management circuits, etc., which are well known in the art, and therefore, they will not be further described herein. The bus interface 605 provides an interface between the bus 600 and the receiver 601 and the transmitter 603. The receiver 601 and the transmitter 603 can be the same element, i.e. the transceiver, which provides a unit for communicating with various other devices on the transmission medium. The processor 602 is responsible for managing the bus 600 and general processing, while the memory 604 can be used to store data used by the processor 602 in performing operations.

[0176] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred over a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Multiple functions described above can be implemented as a single function, multiple functions, or any combination thereof. Further, functions can be implemented in hardware, software, or any combination thereof.

[0177] In several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. Among them, the above-mentioned device embodiments are only schematic, such as the division of the units, which can be a logical function division, and actual implementation can have another division manner, such as a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between units or modules, which can be electrical or other forms.

[0178] The units described as separate components can or can not be physically separated, and the components of the control device can or can not be physical units, i.e. can be located in one place, or can be distributed to multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0179] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or all or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions to make a computer device (which can be a personal computer, a server or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various computer program instruction storage media.

[0180] The above is only an embodiment of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the scope of claims of the present application.

Claims

1. A method for correcting a chip layout based on a double patterning process, characterized in that, The method comprises: acquiring a chip layout to be processed, and determining a pair of conflicting patterns in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to a double pattern process; constructing a conflict graph in the target metal layer by taking patterns in the pair of conflicting patterns as nodes and a conflict relationship between the patterns as a connecting edge, and detecting an odd cycle in the conflict graph, the odd cycle being a closed loop formed by an odd number of patterns through the connecting edge; if an odd cycle is detected in the conflict graph, sequentially traversing a grid region that has not been traversed in the target metal layer according to a set traversal order; each time a current grid region is traversed, counting a total number of odd cycles of the grid regions that have been traversed, if the total number of odd cycles exceeds a set number, marking the grid regions that have been traversed before the current grid region as a first region, and resetting the grid regions that have been traversed and the total number of odd cycles; taking the current grid region as a first grid region that has not been traversed, repeating the traversal process of the grid regions until all the grid regions are traversed; dividing each first region into at least two second regions of similar region size, and defining the second regions as correction regions; simultaneously resolving the odd cycles in the correction regions, and returning to the step of determining a pair of conflicting patterns in a target metal layer of the chip layout until no odd cycle exists in the constructed conflict graph.

2. The method of claim 1, wherein, The step of determining a pair of conflicting patterns in a target metal layer of the chip layout comprises: acquiring a process rule spacing of the target metal layer, the process rule spacing being a minimum pattern spacing that meets a process production condition; if an actual spacing of any adjacent patterns in the target metal layer is less than a set multiple of the process rule spacing, determining the any adjacent patterns as the pair of conflicting patterns.

3. The method of claim 1, wherein, The step of determining a pair of conflicting patterns in a target metal layer of the chip layout comprises: acquiring a process rule spacing of the target metal layer and a factor weight of the target metal layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing that meets a process production condition; based on the process rule spacing, the factor weight, and an actual spacing of any adjacent patterns in the target metal layer, calculating a conflict risk value of the any adjacent patterns under a double pattern process through a conflict quantification model; if the conflict risk value is greater than a set risk value, determining the any adjacent patterns as the pair of conflicting patterns.

4. The method of claim 3, wherein, The conflict quantification model comprises: wherein, represents the conflict risk value of the arbitrary adjacent pattern under the double patterning process; represents the process rule spacing set for the target metal layer, which is a constant; represents the factor weight of the lithography risk, which is a constant; represents the factor weight of the pattern type, which is a constant; represents the actual spacing of the arbitrary adjacent pattern in the target metal layer, which is a variable.

5. The method of claim 1, wherein, The step of detecting an odd cycle in the conflict graph comprises: calling a graph theory loop extraction algorithm to traverse each closed loop in the conflict graph, and counting a number of nodes of the each closed loop; determining the closed loop with an odd number of nodes as the odd cycle.

6. The method of claim 1, wherein, The step of resolving the odd cycle in the correction region comprises: determining at least one target connecting edge to be repaired in the correction region; performing a shift processing and / or a cutting processing on one of the patterns associated with each target connecting edge to resolve the odd cycle to which the each target connecting edge belongs.

7. The method of claim 6, wherein, The method comprises the following steps: The method comprises the following steps: The method comprises the following steps: The method comprises the following steps:

8. The method of claim 7, wherein, The method comprises the following steps: The method comprises the following steps: The device comprises:

9. A device for modifying a chip layout, characterized by The device comprises: The device comprises: The device comprises: The computer program product comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor, so that a computer device with the processor executes the method as claimed in any one of claims 1 to 8. The computer readable storage medium stores at least one program code, which is loaded and executed by the processor to realize the operations performed by the method as claimed in any one of claims 1 to 8.

10. A computer program product, characterised in that, The computer readable storage medium stores at least one program code, which is loaded and executed by the processor to realize the operations performed by the method as claimed in any one of claims 1 to 8.

11. A computer readable storage medium, characterized in that, ​ 12. An electronic device, comprising: The electronic device includes one or more processors and one or more memories having at least one program code stored therein, the at least one program code being loaded and executed by the one or more processors to implement the method of any one of claims 1 to 8.

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