Preparation process of multilayer circuit board with thermoelectric separation substrate

Abstract

The invention relates to the field of circuit board technology and integrated circuit manufacturing, and particularly discloses a preparation process of a multilayer circuit board with a thermoelectric separation substrate, which comprises the following steps of: preparing and laminating an FR4 multilayer board at one time; and finally, through secondary pressing, the red copper plate boss is accurately embedded into the groove of the FR4 plate and is electrically connected with the circuit bonding pad, so that a thermoelectric separation integrated structure is realized. The method is suitable for packaging and heat dissipation requirements of high-power integrated circuits and semiconductor devices, and particularly can be used for producing high-density and high-heat-dissipation circuit modules in semiconductor device special equipment such as a special photoetching machine and an etching machine. The obtained product has the high-density wiring advantage of the FR4 multilayer board and the high heat dissipation performance of the metal substrate, the lowest thermal resistance path to the heat dissipation substrate is achieved through direct connection of the bosses, meanwhile, the reliability and the electrical insulation performance of the overall structure are guaranteed, the stability of electronic equipment under the high-temperature and high-power working conditions is remarkably improved, and the service life of the electronic equipment under the high-temperature and high-power working conditions is remarkably prolonged.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board and integrated circuit manufacturing, in particular to a multilayer circuit board preparation process with thermoelectric separation substrate. BACKGROUND

[0002] In the field of electronic devices, especially high-power LEDs, power supply modules, automotive electronics, and integrated circuit manufacturing, power semiconductor packaging, etc., high-efficiency heat dissipation performance is the key to ensuring the reliability and life of the device. The traditional printed circuit board substrate such as FR4 has poor thermal conductivity, which is difficult to meet the heat dissipation needs of high-power density integrated circuits and semiconductor devices. With the development of semiconductor manufacturing equipment (such as lithography machines and etching machines) towards high precision and high integration, the internal circuit modules also face increasingly severe heat dissipation challenges.

[0003] At present, Chinese patent application No. CN202211103297.5 discloses a manufacturing method of a double-sided patch multilayer thermoelectric separation circuit board and a PCB, which comprises the following steps: multilayer FR4 substrate manufacturing; multilayer FR4 substrate slotting; boss manufacturing; copper plate slotting; filler block manufacturing; riveting; assembling filler block; layout and pressing; removing filler block to complete pressing; filling the manufacturing technology gap of the double-sided patch thermoelectric separation circuit board; and at the same time, under the premise of ensuring the double-sided patch, the phenomenon of structure overhanging surface not being recessed can be met at the same time.

[0004] However, the preparation process route of the prior art is long and complicated, involves precise assembly and secondary operation of multiple components, which not only increases the manufacturing cost and working hours, but also introduces multiple mechanical interface interfaces, which easily affects the connection reliability, thermal resistance stability and long-term durability, and is difficult to meet the strict requirements of integrated circuit manufacturing and high-end semiconductor equipment on high reliability, high heat dissipation efficiency and long-term stability of the circuit board. SUMMARY

[0005] The present application aims to provide a multilayer circuit board preparation process with thermoelectric separation substrate to solve the problems raised in the background art, especially to meet the needs of high-efficiency heat dissipation and high-density interconnection integration in the field of integrated circuit manufacturing and semiconductor power device packaging.

[0006] In order to achieve the above-mentioned purpose, the present application adopts the following technical scheme: a multilayer circuit board preparation process with thermoelectric separation substrate, comprising the following steps:

[0007] S1, preparing an inner layer core board: providing at least two double-sided copper-clad FR4 core boards, respectively forming L2 / L3 and L4 / L5 layer circuit patterns through inner layer circuit manufacturing and etching, and performing brown oxidation treatment to prevent delamination during subsequent pressing;

[0008] S2, one-time pressing: the inner layer core board after the brown treatment is laminated with prepreg to perform one-time pressing to form an FR4 panel with multiple inner layer circuits, and to ensure that the thickness of the panel after one-time pressing is a first predetermined thickness;

[0009] S3, first outer layer circuit manufacturing: drilling, copper sinking, electroplating, outer layer circuit manufacturing and etching are performed on a surface of the FR4 panel to form a first outer layer circuit pattern;

[0010] S4, copper substrate preparation: a red copper plate is provided, and a boss pattern is formed on a surface thereof through a dry film masking, exposure, development and etching process;

[0011] S5, two-time pressing: the FR4 panel with the first outer layer circuit pattern and the boss is laminated and pressed with the red copper plate through the prepreg, one surface of the FR4 panel with the first outer layer circuit pattern faces one surface of the red copper plate with the boss, so that the boss is embedded in the prepreg and electrically connected with the pads on the first outer layer circuit pattern, while the remaining part of the red copper plate is insulated from the circuit of the FR4 panel through the prepreg, realizing thermal and electrical separation, the copper thickness of the red copper plate after pressing is 10OZ, and the total thickness after pressing is a second predetermined thickness;

[0012] S6, second outer layer circuit manufacturing: outer layer circuit manufacturing and etching are performed on another surface of the FR4 panel to form a second outer layer circuit pattern;

[0013] S7, post-processing: resist, character, surface treatment and molding processes are sequentially performed to obtain the multilayer circuit board.

[0014] Preferably, in step S3, after the first outer layer circuit pattern is formed, a slotting step is further included: panel slots and PP slots corresponding to the positions of the bosses of the subsequently pressed red copper plate are slotted on the FR4 panel, the size of the PP slots is larger than that of the panel slots, which provides accurate space for the embedding of the bosses, avoids the damage of the FR4 circuit caused by the extrusion of the bosses during pressing, and the larger size of the PP slots can better accommodate the prepreg glue flow to prevent the glue powder from penetrating into the panel slots to contaminate the pads, ensuring the reliability of the metal contact between the bosses and the pads.

[0015] Preferably, in step S4, the thickness of the red copper plate is 2.5mm±0.05mm, and the etching height tolerance of the boss is the thickness of the panel±0.05mm, which accurately controls the thickness of the copper substrate and the height of the boss, ensuring the consistency of the total thickness of the product after two-time pressing, and the sufficiency and uniformity of the contact between the boss and the pad, thereby ensuring excellent heat conduction and electrical conductivity.

[0016] Preferably, after the secondary pressing in step S5, the thickness of the insulating layer between the red copper plate and the FR4 panel is greater than or equal to 100 microns, which ensures sufficient and reliable insulation strength and voltage resistance between the copper substrate and the internal circuit, and fully meets the electrical safety standards in high-power application scenarios.

[0017] Preferably, the outer layer circuit in step S3 and / or step S6 is made by a laser direct imaging process, with a minimum line spacing of 0.1 mm, which avoids the size deviation caused by thermal expansion and contraction of traditional film, improves the precision and yield of circuit production, and meets the design requirements of high-density interconnection circuit.

[0018] Preferably, the surface treatment in step S7 includes gold plating treatment on the surface where the second outer layer circuit pattern is located, with a gold layer thickness of 1.5 microns and a nickel layer thickness of 120 microns; and wire drawing and organic solder mask treatment on the exposed surface of the red copper plate, forming an extremely thin protective film on the surface of the copper substrate, which can prevent copper oxidation without affecting its heat dissipation performance.

[0019] Preferably, the hole drilled through the FR4 panel in step S3 is treated by plugging the hole with an aluminum sheet in the solder mask process of step S7, which can achieve the flattening of the hole height, avoid problems such as ink entering the hole or incomplete plugging, and provide an extremely flat pad surface for subsequent surface treatment and component mounting.

[0020] Preferably, after the forming process in step S7, a V-CUT process is further included: V-CUT is performed from one side of the FR4 panel, with a depth of at least V through the insulating layer to the red copper plate, and a remaining thickness controlled within 0.5-0.6 mm, which facilitates the splitting operation of the panel, accurately controls the depth and remaining thickness, ensures easy breaking during splitting, avoids damaging the copper substrate as the main structure support, and guarantees the mechanical strength of the unit panel.

[0021] Preferably, the thickness of the panel after the first pressing in step S2 is 0.565 mm±0.1 mm, and the finished thickness after the second pressing in step S5 is 2.5 mm±0.2 mm, to ensure that the final product meets the design size, satisfies the structural assembly requirements and heat dissipation performance.

[0022] In addition, the application also provides a multilayer circuit board prepared by the above multilayer circuit board preparation process with thermoelectric separation substrate, which comprises:

[0023] an FR4 multilayer panel body having at least four inner layer circuits and first and second outer layer circuits arranged on two opposite surfaces thereof;

[0024] a red copper substrate combined with one surface of the FR4 multilayer panel body through an insulating layer;

[0025] The red copper substrate is integrally formed with a boss protruding towards the FR4 multilayer board body, the boss is directly electrically connected with the pad on the first outer layer circuit through the insulating layer, and the rest of the red copper substrate is electrically insulated from the FR4 multilayer board body.

[0026] The product prepared by the above process has a structure that realizes efficient "thermal-electric separation": heat from the heat-generating element → the second outer layer circuit → the via → the first outer layer circuit pad → the boss → the red copper substrate, the heat resistance of this path is extremely low, and the heat dissipation efficiency far exceeds that of traditional insulating metal substrates. At the same time, reliable insulation between the large-area red copper substrate and the circuit, excellent heat dissipation performance, electrical performance, and high reliability.

[0027] Compared with the prior art, the present application has the following advantages:

[0028] The present application successfully constructs a thermal-electric separation structure through the unique boss design of the red copper substrate and the secondary pressing process. The heat from the heat-generating element (such as an integrated circuit chip or a power semiconductor device) can be directly and efficiently conducted to the large-area red copper substrate through the boss for rapid dissipation, greatly improving the heat dissipation efficiency. At the same time, the red copper substrate body and the circuit system are reliably isolated by the insulating layer, ensuring the signal integrity and safety of the circuit, and perfectly solving the technical problem of the mutual contradiction between heat dissipation and insulation of high-power integrated circuits and semiconductor devices.

[0029] The red copper substrate and the boss thereon of the present application are integrally made, avoiding the risks of high connection interface thermal resistance, poor mechanical strength, and easy aging and falling caused by assembling multiple parts. The entire preparation process integrates the combination process of multilayer FR4 circuit and metal substrate in an orderly manner, with compact structure and stable connection, significantly improving the long-term reliability and service life of the product in harsh industrial environments and long-term continuous operation (such as inside semiconductor manufacturing equipment).

[0030] While providing excellent heat dissipation performance, the present application still retains the advantages of traditional FR4 multilayer circuit boards, enabling the layout of high-density, fine lines and complex multilayer interconnection, and various surface treatments such as gold plating, OSP, etc., meeting the comprehensive requirements of modern integrated circuits, semiconductor modules, and high-end electronic equipment (including production-specific photolithography machines, etching machines, and other semiconductor device-specific equipment) for circuit function, size, heat dissipation, and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 The figure is a preparation process flow diagram of the multilayer circuit board of the present application;

[0032] Figure 2 The figure is a structure diagram of the multilayer circuit board of the present application. DETAILED DESCRIPTION

[0033] To further explain the technical solutions of the present application, the following will be described in detail through specific examples. The preparation process provided by the present application is particularly suitable for the manufacture of integrated circuit substrates, power semiconductor module carriers, and electronic device circuit boards with high heat dissipation requirements.

[0034] Please refer to Figure 1 and Figure 2 , the present application provides a multilayer circuit board preparation process with a thermoelectrically separated substrate, the main technical solutions of the preparation process include: preparing an inner layer core board and performing brown oxidation; first pressing to form an FR4 multilayer board; making a first outer layer circuit pattern on one side of the first pressed FR4 panel; etching a boss on a red copper panel; combining the FR4 panel with the red copper panel through secondary pressing, embedding the boss and connecting it with the solder pad of the first outer layer circuit pattern, and at the same time, the rest of the red copper panel is insulated by a prepreg, thereby realizing thermoelectric separation; then making a second outer layer circuit pattern on the other side of the FR4 panel; finally, post-processing to obtain the finished product.

[0035] The technical solutions mainly include the following technical features:

[0036] The above preparation process can further include the step of forming panel slots and PP slots of different sizes to reserve space for the boss after forming the first outer layer circuit; the thickness of the red copper panel can be 2.5mm±0.05mm, and the boss height tolerance can be controlled to be the panel thickness±0.05mm; the insulation layer thickness after secondary pressing can be≥100μm; the outer layer circuit can be made by using the laser direct imaging (LDI) process, and the minimum line distance can be 0.1mm; the surface treatment can include nickel plating and gold plating (nickel layer thickness 120 micro inches, gold layer thickness 1.5 micro inches) on the circuit surface, and wire drawing and OSP treatment on the copper base surface; the via hole can be plugged with an aluminum sheet; the step of V-CUT to the copper substrate with a remaining thickness of 0.5-0.6mm can be included; the board thickness after first pressing can be 0.565mm±0.1mm, and the finished product board thickness can be 2.5mm±0.2mm.

[0037] The multilayer circuit board prepared by the above process has a structure including an FR4 multilayer board main body and a red copper substrate combined by an insulation layer, and a boss integrally formed on the red copper substrate directly electrically connected with the solder pad on the first outer layer circuit through the insulation layer, thereby realizing high-efficiency thermoelectric separation performance.

[0038] The following will be further described in detail in combination with specific examples. It should be noted that the following examples are only used to explain the present application, and are not used to limit the scope of the present application.

[0039] Example 1:

[0040] This example prepares a six-layer structure of a circuit board with a thermoelectrically separated substrate, and the preparation process includes the following steps:

[0041] 1. Preparation of inner core boards:

[0042] Two pieces of qualified halogen-free FR4 double-sided copper clad laminates were provided as inner core boards. The first piece of core board was used to make the second layer (L2) and third layer (L3) circuits, with a cutting size of 440mm x 410mm, a copper thickness of 1oz (35μm), an insulating dielectric layer thickness of 75μm, and a board thickness tolerance controlled within ±0.025mm. The core board was baked in an oven at 150±5°C for 2 hours to remove moisture, and then dry films were attached to both sides of the core board. Using a negative film process, a film with the number T13P620C23474A0.L2 / L3 was exposed and developed by LDI laser direct imaging technology, with a minimum line width of 0.15mm for the L2 layer and 0.1mm for the L3 layer. Acid etching was then performed with an etching tolerance controlled within ±20%, to form the final L2 / L3 layer circuit pattern. After that, 100% scanning inspection of the circuit was performed using an AOI optical detection device to ensure that there were no defects such as film peeling, incomplete etching, open circuits, short circuits, and line gaps. Finally, the formed circuit layer was subjected to a brown oxidation treatment to increase the bonding force between the copper surface and the prepreg.

[0043] Similarly, the second piece of core board was used to make the fourth layer (L4) and fifth layer (L5) circuits, with the same cutting size, copper thickness, and board type as the first piece. Using a film with the number T13P620C23474A0.L4 / L5, the same baking, film attaching, exposure, etching, AOI detection, and brown oxidation treatment were performed, with a minimum line width of 0.16mm for the L4 layer and 0.14mm for the L5 layer, to complete the fabrication of the L4 / L5 layer circuit pattern.

[0044] 2. First pressing:

[0045] The two inner core boards subjected to the brown oxidation treatment were combined with the corresponding prepregs according to the predetermined layer structure. Pressing was performed at high temperature and high pressure, so that the prepregs melted and solidified, firmly combining the layers into a whole. After pressing, the thickness of the obtained multilayer FR4 panel was controlled to be 0.565mm with a tolerance of ±0.1mm. Subsequently, target holes were milled as needed to provide positioning references for the subsequent drilling process.

[0046] 3. First outer layer circuit fabrication and processing:

[0047] The panel after the first lamination is drilled with a drill press and a drill file numbered T13P620C23474A0-440x410.drl. At the same time, aluminum pieces for the subsequent via holes are drilled (T13P620C23474A0.sai). The walls of the drilled holes are treated with copper deposition and copper plating: first, the walls of the holes are chemically deposited with a thickness of about 15 μm of chemical copper, and then the hole copper is thickened by 25 μm by full-plate plating, ensuring that the final hole copper thickness is ≥ 18 μm, and the copper thickness is ≥ 35 μm. After plating is complete, the plate thickness is 0.6 ± 0.1 mm.

[0048] Next, the outer layer circuit is made on the bottom surface of the panel (i.e., the surface defined as GBL later). The top surface (GTL surface) is protected with dry film, and dry film is attached only on the bottom surface. Using a negative film process, using the film T13P620C23474A0.GBL, the pattern is transferred by LDI technology, and the minimum line distance of the outer layer pattern is 0.1 mm. Then etching is performed with an etching tolerance of ± 20%, and the first outer layer (GBL) circuit pattern is formed. After completion, AOI detection is performed again to ensure the quality of the circuit.

[0049] Subsequently, grooving is performed. According to the file numbered T13P620C23474A0.GKO-1, first, the panel groove is grooved on the bottom surface (copper foil surface facing up), and then the PP groove with a size of 0.1 mm larger than the panel groove is grooved at the same position. This step is intended to reserve space for the subsequent lamination of the copper substrate boss and prevent the semi-cured sheet resin from seeping into the groove and affecting the electrical connection. Finally, the entire panel is browned.

[0050] 4. Preparation of the copper substrate:

[0051] A T2 red copper plate is provided as a substrate for thermoelectric separation, and its supplier is Nan Ye, with a copper content of 99% and a thickness of 2.5 mm, with a tolerance of ± 0.05 mm. Dry film is attached to one side of the red copper plate, and a negative film process is used to expose and develop the film numbered T13P620C23474A0.LJ, defining the boss pattern. Since this plate is a thick copper plate, it needs to be confirmed to be qualified before mass production. Then etching is performed, and the etching depth is accurately controlled to control the height tolerance of the boss within the range of (FR4 panel thickness ± 0.05 mm). After stripping, the red copper plate with the boss is browned.

[0052] 5. Second lamination:

[0053] The FR4 panel treated in Step 3 is laminated with the red copper plate treated in Step 4. The laminated structure is: the side of the FR4 panel with the GBL circuit pattern and the PP slot faces the side of the red copper plate with the boss, and the prepreg is used for bonding in the middle. During the lamination process, the boss on the red copper plate is precisely embedded into the PP slot and the panel slot of the FR4 panel, and forms a close mechanical contact and electrical connection with the corresponding pads on the GBL layer. The non-boss area of the red copper plate is insulated from the FR4 panel through the prepreg, thereby realizing a perfect "thermal-electric separation" structure. After lamination, the total thickness of the circuit board is 2.5 mm, the copper thickness of the copper substrate surface is 1 oz, and the lamination tolerance is ±0.1 mm. After lamination, the thickness of the insulating layer (i.e. the thickness of the cured prepreg) between the red copper plate and the FR4 panel is ≥100 μm. After lamination, new target holes are milled according to the target hole pattern after secondary lamination.

[0054] 6. Second outer layer circuit manufacturing:

[0055] The top surface (GTL surface) of the FR4 panel after secondary lamination is subjected to outer layer circuit manufacturing. Dry film and negative film process are used, and the film T13P620C23474A0.GTL is used to manufacture the pattern by LDI technology, and the minimum line distance of this surface is 0.1 mm. After etching with a tolerance of ±20% and AOI detection, the second outer layer (GTL) circuit pattern is formed.

[0056] 7. Post-processing:

[0057] Firstly, solder mask processing is performed. Solder mask ink is printed only on the GTL surface, and the color is black, and the halogen-free ink KSM-S6189-EK25A of Guangxin Company is used. The film T13P620C23474A0.GTS is used for exposure and development, and the pad windowing is realized by using the outer windowing method. The through hole is processed by using the aluminum sheet (T13P620C23474A0.sai) hole plugging process;

[0058] Then, white characters are printed on the GTL surface, and the IJR-4000 CW100 ink of Taiyang Company is used, and the computer sealing method is used, and the film number is T13P620C23474A0.GTO;

[0059] Then, surface treatment is performed: the windowed pads on the GTL surface are subjected to chemical nickel-gold plating treatment, wherein the thickness of the nickel layer is 120 micro inches (about 3.05 μm), and the thickness of the gold layer is 1.5 micro inches (about 0.038 μm). The exposed red copper substrate surface is subjected to wire drawing treatment, and then OSP film is sprayed, and the thickness is 0.2-0.5 μm, so as to prevent the oxidation of the copper surface;

[0060] After that, flying probe test is performed to ensure that the circuit has no electrical defects such as open circuit and short circuit;

[0061] Then, drilling and slotting: according to the corresponding file, non-conductive holes (NPTH) are drilled, back flat countersunk holes are drilled, and back flat countersunk grooves are milled;

[0062] Then, computer V-CUT: V-CUT is performed from the circuit surface (GTL surface), the depth needs to V-pass the insulating layer to the copper plate, and the remaining thickness is controlled at 0.5-0.6mm;

[0063] Finally, according to the forming file numbered T13P620C23474A0.GKO, the profile processing is performed by a numerical control milling machine (computer milling), and the inner groove tolerance is strictly controlled at +0.1mm.

[0064] 8. Inspection and packaging:

[0065] The finished board is subjected to final inspection, and the plate thickness tolerance (2.5mm±0.2mm), warpage rate (≤0.75%) and the like are checked. After passing, the product is packaged into the warehouse by vacuum packaging, and a delivery report is attached.

[0066] The multilayer circuit board prepared by the above process has a structure including an FR4 multilayer board main body integrating L2-L5 inner layer circuits and GTL / GBL outer layer circuits, and a copper base plate combined with the main body through an insulating layer. The boss integrally formed on the copper base plate passes through the insulating layer and is directly electrically connected with the pad on the GBL layer, so as to realize the separation of high-efficiency heat dissipation and circuit insulation. The product is particularly suitable for high-power LED, power module, automobile electronics, server power supply, and heat dissipation substrate, semiconductor device packaging pad and the like in the field of integrated circuit manufacturing, and can also be used as an ideal carrier for high-power and high-density circuit modules in the internal high-power and high-density circuit modules of special photolithography machines, etching machines and other semiconductor device special equipment, and has broad application prospects in high-end equipment manufacturing industry.

[0067] The above only describes the preferred examples of the present application and is not used to limit the present application, although the present application is described in detail with reference to the foregoing examples, and those skilled in the art can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features. Any modification, equivalent replacement, improvement and the like made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A multilayer circuit board manufacturing process with thermoelectrically separated substrates, suitable for integrated circuit fabrication and semiconductor packaging, characterized by, The method comprises the following steps: S1, preparing an inner core plate: providing at least two double-sided copper-clad FR4 core plates, respectively forming L2 / L3 and L4 / L5 layer circuit patterns through inner layer circuit manufacturing and etching, and performing brown processing; S2, first pressing: laminating the inner core plate after brown processing with a prepreg to perform first pressing, forming an FR4 panel with multiple inner layer circuits, and ensuring that the thickness of the panel after first pressing is a first predetermined thickness; S3, first outer layer circuit manufacturing: performing drilling, copper plating, electroplating, outer layer circuit manufacturing and etching on one surface of the FR4 panel to form a first outer layer circuit pattern; S4, preparing a copper substrate: providing a red copper plate, and forming a boss pattern on one surface thereof through dry film masking, exposure, development and etching processes; S5, second pressing: laminating the FR4 panel with the first outer layer circuit pattern and the boss and the red copper plate through a prepreg, with one surface of the FR4 panel facing one surface of the red copper plate with the boss, so that the boss is embedded in the prepreg and electrically connected to the pads on the first outer layer circuit pattern, while the remaining part of the red copper plate is insulated from the circuit of the FR4 panel through the prepreg, achieving thermal and electrical separation, and the copper thickness of the red copper plate after pressing is 10OZ, and the finished panel thickness is a second predetermined thickness; S6, second outer layer circuit manufacturing: performing outer layer circuit manufacturing and etching on the other surface of the FR4 panel to form a second outer layer circuit pattern; S7, post-processing: sequentially performing solder mask, character, surface treatment and molding processes to obtain the multi-layer circuit board.

2. The process for manufacturing a multilayer circuit board with thermoelectrically separated substrates according to claim 1, characterized in that, In step S3, after forming the first outer layer circuit pattern, a slotting step is further included: slotting a panel slot and a PP slot on the FR4 panel corresponding to the position of the boss of the subsequently pressed red copper plate, and the size of the PP slot is greater than that of the panel slot.

3. The process for manufacturing a multilayer circuit board with thermoelectrically separated substrates according to claim 1, characterized in that, In step S4, the thickness of the red copper plate is 2.5mm±0.05mm, and the etching height tolerance of the boss is panel thickness±0.05mm.

4. The process for manufacturing a multilayer circuit board with thermoelectrically separated substrates according to claim 1, characterized in that, In step S5, after the second pressing, the thickness of the insulating layer between the red copper plate and the FR4 panel is≥100μm.

5. The process for manufacturing a multilayer circuit board with thermoelectrically separated substrates according to claim 1, wherein In step S3 and / or step S6, the outer layer circuit is made by a laser direct imaging process, and the minimum line distance is 0.1mm.

6. The process for manufacturing a multilayer circuit board with thermoelectrically separated substrates according to claim 1, wherein In step S7, the surface treatment includes: performing gold plating on the surface where the second outer layer circuit pattern is located, with a gold layer thickness of 1.5μin and a nickel layer thickness of 120μin; and performing wire drawing and organic solder mask film treatment on the exposed surface of the red copper plate.

7. The process for manufacturing a multilayer circuit board with thermoelectrically separated substrates according to claim 1, wherein In step S3, the holes drilled through the FR4 panel are plugged in the solder mask process of step S7 by using an aluminum sheet to plug the holes.

8. The process for manufacturing a multilayer circuit board with thermally separated substrates according to claim 1, wherein After the molding process in step S7, a V-CUT process is further included: performing V-CUT from one side of the FR4 panel, with a depth of at least V penetrating the insulating layer to the red copper plate, and a remaining thickness controlled within 0.5-0.6mm.

9. The process for manufacturing a multilayer circuit board with thermally separated substrates according to claim 1, wherein, In step S2, the thickness of the panel after first pressing is 0.565mm±0.1mm; and in step S5, the finished panel thickness after second pressing is 2.5mm±0.2mm.

10. A multilayer circuit board, characterized by, A multilayer circuit board with a thermoelectric separation substrate prepared by the process of any one of claims 1-9, comprising: an FR4 multilayer board body having at least four inner layers of circuitry and first and second outer layers of circuitry disposed on opposite surfaces thereof; a red copper substrate bonded to one face of the FR4 multilayer board body by an insulating layer; a boss integrally formed on the red copper substrate and projecting toward the FR4 multilayer board body, the boss being directly electrically connected to a pad on the first outer layer of circuitry through the insulating layer, while the remainder of the red copper substrate is electrically isolated from the FR4 multilayer board body.

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