Ferroelectric tunnel junction, memory and ferroelectric tunnel junction preparation method

Abstract

The invention relates to the technical field of integrated circuits, and provides a ferroelectric tunnel junction, a memory and a ferroelectric tunnel junction preparation method, the ferroelectric tunnel junction comprises an electrode layer, a ferroelectric layer, a conductive function layer and a semiconductor layer, the ferroelectric layer is located between the electrode layer and the conductive function layer, and the semiconductor layer is located between the electrode layer and the conductive function layer. The semiconductor layer is located on the side, away from the ferroelectric layer, of the conductive functional layer, and the thickness of the conductive functional layer is smaller than or equal to 10 nm. According to the ferroelectric tunnel junction, the conductive function layer is introduced into the ferroelectric tunnel junction with the structure, so that the switching ratio and the stability of the ferroelectric tunnel junction are improved, and the problem of high power consumption caused by relatively high reading voltage is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a ferroelectric tunnel junction, a memory and a ferroelectric tunnel junction preparation method. BACKGROUND

[0002] The ferroelectric tunnel junction is a kind of memory device using ferroelectric material to store information, which can be applied to high-density storage. The hafnium-zirconium-oxygen-based ferroelectric tunnel junction has the advantages of high-speed switching, non-destructive readout, and compatibility with CMOS process. However, the hafnium-zirconium-oxygen-based ferroelectric tunnel junction has the following problems: the traditional ferroelectric tunnel junction (metal-ferroelectric layer-metal structure) uses the asymmetric shielding of the metal counter electrode to realize different resistance states before and after polarization reversal, thereby realizing binary storage. However, due to the limited difference in the shielding characteristics of the metal, the switching ratio of the hafnium-zirconium-oxygen-based ferroelectric tunnel junction has a relatively large disadvantage compared with the two-terminal memory such as RRAM.

[0003] In order to improve the switching ratio of the ferroelectric tunnel junction, the mainstream research uses metal-insulating layer-ferroelectric layer-metal and semiconductor-insulating layer-ferroelectric layer-metal two structures, but these structures bring many problems to the device:

[0004] (1) The highly asymmetric structure can indeed improve the switching ratio of the device, but the highly asymmetric structure will also introduce a relatively large depolarization field, which will damage the stability (retention performance and endurance performance) of the device. At the same time, the defects on the surface of the dielectric layer caused by the asymmetric interface pin the ferroelectric dipole, which limits the device's ability to resist erasing.

[0005] (2) These structures inevitably increase the potential barrier and reduce the on-state current, which limits the miniaturization application of the device and increases the necessity of the current amplifier, which makes the ferroelectric tunnel junction device lose the expected density advantage.

[0006] In order to improve the on-state current, many studies have focused on reducing the thickness of the ferroelectric layer, which also brings many problems. First, the ferroelectric hafnium-zirconium-oxygen will also decrease with the decrease of the thickness, which will weaken the switching ratio. The process requirements of the low-thickness ferroelectric tunnel junction for the ferroelectric hafnium-zirconium-oxygen are relatively harsh. Second, although there are currently studies that have achieved ferroelectricity in 1nm thick hafnium-zirconium-oxygen and prepared a ferroelectric tunnel junction, the stability of the device is very poor, which is due to the decrease of the ferroelectric layer thickness greatly increasing the depolarization field.

[0007] In addition, there are almost no studies focusing on improving the opening speed of the ferroelectric tunnel junction, so the ferroelectric tunnel junction needs to be read at a relatively high voltage, which will increase the power consumption of the device in the actual work of the memory.

[0008] In summary, the existing ferroelectric tunnel junction has low switching, poor stability and high reading voltage, which causes power consumption problems. SUMMARY

[0009] The present application provides a ferroelectric tunnel junction, a memory and a ferroelectric tunnel junction preparation method to solve the problems of low switching, poor stability and slow opening speed of the existing ferroelectric tunnel junction.

[0010] The present application provides a ferroelectric tunnel junction, comprising: an electrode layer, a ferroelectric layer, a conductive functional layer and a semiconductor layer, the ferroelectric layer is located between the electrode layer and the conductive functional layer, the semiconductor layer is located on the side of the conductive functional layer away from the ferroelectric layer, and the thickness of the conductive functional layer is less than or equal to 10nm.

[0011] According to the ferroelectric tunnel junction provided by the present application, a first insulating layer is further included, and the first insulating layer is located between the electrode layer and the ferroelectric layer.

[0012] According to the ferroelectric tunnel junction provided by the present application, a first insulating layer is further included, and the first insulating layer is located between the ferroelectric layer and the conductive functional layer.

[0013] According to the ferroelectric tunnel junction provided by the present application, a first insulating layer is further included, and the first insulating layer is located between the conductive functional layer and the semiconductor layer.

[0014] According to the ferroelectric tunnel junction provided by the present application, a first insulating layer is further included, and the ferroelectric layer includes a first ferroelectric sublayer and a second ferroelectric sublayer, and the first insulating layer is located between the first ferroelectric sublayer and the second ferroelectric sublayer.

[0015] According to the ferroelectric tunnel junction provided by the present application, the thickness of the first insulating layer is less than 10nm.

[0016] According to the ferroelectric tunnel junction provided by the present application, a second insulating layer is further included, and the second insulating layer is located on the side of the semiconductor layer facing the conductive functional layer.

[0017] According to the ferroelectric tunnel junction provided by the present application, the material of the semiconductor layer is: doped Si, Ge or two-dimensional material.

[0018] The present application also provides a memory device, comprising: the ferroelectric tunnel junction of any one of the above.

[0019] The present application also provides a ferroelectric tunnel junction preparation method, comprising:

[0020] forming a semiconductor layer;

[0021] Forming an electrically conductive functional layer, a ferroelectric layer and an electrode layer on the semiconductor layer in sequence to obtain the ferroelectric tunnel junction.

[0022] The application provides a ferroelectric tunnel junction, a memory and a preparation method of the ferroelectric tunnel junction. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0024] Figure 1 is one of the structure schematic diagrams of the ferroelectric tunnel junction provided by the application;

[0025] Figure 2 is a ferroelectric property schematic diagram of the ferroelectric layer when the ferroelectric tunnel junction is Ptype-Si(SiO2)-TiN(1-3nm)-HZO(8nm)-electrode(Al, Pt, TiN or W) specific structure;

[0026] Figure 3 is one of the performance schematic diagrams of the ferroelectric tunnel junction when the ferroelectric tunnel junction is Ptype-Si(SiO2)-TiN(1-3nm)-HZO(8nm)-electrode(Al, Pt, TiN or W) specific structure;

[0027] Figure 4 is the second performance schematic diagram of the ferroelectric tunnel junction when the ferroelectric tunnel junction is Ptype-Si(SiO2)-TiN(1-3nm)-HZO(8nm)-electrode(Al, Pt, TiN or W) specific structure;

[0028] Figure 5 is the third performance schematic diagram of the ferroelectric tunnel junction when the ferroelectric tunnel junction is Ptype-Si(SiO2)-TiN(1-3nm)-HZO(8nm)-electrode(Al, Pt, TiN or W) specific structure;

[0029] Figure 6is the fourth performance schematic diagram of the ferroelectric tunnel junction when the ferroelectric tunnel junction provided by the application is Ptype-Si (SiO2) -TiN (1-3nm) -HZO (8nm) -electrode (Al, Pt, TiN or W) specific structure;

[0030] Figure 7 is the second structure schematic diagram of the ferroelectric tunnel junction provided by the application;

[0031] Figure 8 is the third structure schematic diagram of the ferroelectric tunnel junction provided by the application;

[0032] Figure 9 is the fourth structure schematic diagram of the ferroelectric tunnel junction provided by the application;

[0033] Figure 10 is the fifth structure schematic diagram of the ferroelectric tunnel junction provided by the application;

[0034] Figure 11 is the first performance schematic diagram of the ferroelectric tunnel junction when the ferroelectric tunnel junction provided by the application is Ptype-Si (SiO2) -TiN (1-3nm) -HZO (8nm) -electrode (Al, Pt, TiN or W) specific structure and the first insulating layer is introduced;

[0035] Figure 12 is the second performance schematic diagram of the ferroelectric tunnel junction when the ferroelectric tunnel junction provided by the application is Ptype-Si (SiO2) -TiN (1-3nm) -HZO (8nm) -electrode (Al, Pt, TiN or W) specific structure and the first insulating layer is introduced;

[0036] Figure 13 is the third performance schematic diagram of the ferroelectric tunnel junction when the ferroelectric tunnel junction provided by the application is Ptype-Si (SiO2) -TiN (1-3nm) -HZO (8nm) -electrode (Al, Pt, TiN or W) specific structure and the first insulating layer is introduced;

[0037] Figure 14 is the fourth performance schematic diagram of the ferroelectric tunnel junction when the ferroelectric tunnel junction provided by the application is Ptype-Si (SiO2) -TiN (1-3nm) -HZO (8nm) -electrode (Al, Pt, TiN or W) specific structure and the first insulating layer is introduced;

[0038] Figure 15 is the sixth structure schematic diagram of the ferroelectric tunnel junction provided by the application;

[0039] Reference signs:

[0040] 1: Electrode layer; 2: Ferroelectric layer; 3: Conductive functional layer; 4: Semiconductor layer; 5: First insulating layer; 6: Second insulating layer; 21: First ferroelectronic layer; 22: Second ferroelectronic layer. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0042] Ferroelectric tunnel structure according to embodiments of the present invention Figure 1 As shown, the device includes: an electrode layer 1, a ferroelectric layer 2, a conductive functional layer 3, and a semiconductor layer 4. The ferroelectric layer 2 is located between the electrode layer 1 and the conductive functional layer 3, and the semiconductor layer 4 is located on the side of the conductive functional layer 3 facing away from the ferroelectric layer 1. The thickness of the conductive functional layer 3 is less than or equal to 10 nm. The conductive functional layer 3 is a material layer with conductive properties. The materials of the conductive functional layer 3 include: elemental metals (e.g., nickel, platinum, Ti, gold, silver, and copper), compound conductive materials (e.g., TiN, TaN, and ITO), and materials that exhibit conductive characteristics under specific structures, such as graphene. When the conductive functional layer 3 is thin, i.e., less than or equal to 10 nm, its conductivity may be low or even weak, but this will not affect the device performance because its current flows perpendicular to the surface of the metal thin film.

[0043] The ferroelectric tunnel junction of the embodiment introduces the conductive functional layer 3, thereby improving the on-off ratio, stability and low-voltage reading operation of the ferroelectric tunnel junction, and avoiding the power consumption problem caused by relatively high reading voltage. The principle is that the introduction of the conductive functional layer 3 can reduce the interface resistance and increase the probability of tunneling, thereby improving the on-state current, increasing the speed of current opening, and reducing the reading voltage. At the same time, due to the existence of the semiconductor layer 4, the off-state current is still high due to the high interface potential barrier caused by the semiconductor band bending. The introduction of the conductive functional layer can further suppress the leakage current caused by defects in the ferroelectric layer 2, reduce the off-state current, and increase the on-off ratio. At the same time, for some electrodes such as TiN and W, there is another mechanism, the conductive functional layer 3 can introduce defect energy levels at the forbidden band of the ferroelectric layer 2, which can improve the tunneling probability, thereby obtaining a higher on-state current at a lower reading voltage, avoiding the power consumption problem caused by a relatively high reading voltage. The stability is increased for two reasons. On the one hand, the introduction of the conductive functional layer 3 can effectively reduce the interface defects. On the other hand, the structure can play a role in screening high-energy particles and delaying the degradation of the ferroelectric layer 2. However, the conductive functional layer 3 needs to be less than a certain range (less than or equal to 10 nm). First, if the conductive functional layer 3 is too thick, the properties of the ferroelectric tunnel junction will be consistent with the traditional MFM (metal layer-ferroelectric layer-metal layer) layer structure device, and the effect of the semiconductor layer 4 on the ferroelectric tunnel junction will disappear, resulting in that the ferroelectric tunnel junction is difficult to have a large on-off ratio. Secondly, for the conductive functional layer 3 (TiN, W, etc.) that is prone to cause defects, the excessive thickness of the conductive functional layer 3 will cause the number of defects to increase rapidly, resulting in that the ferroelectric tunnel junction is easy to be broken down.

[0044] In the embodiment, the electrode layer 1 and the conductive functional layer 3 can be any conductive material (such as Al, Pt, TiN, W, etc.), including: metal, metal oxide, conductive polymer or conductive two-dimensional material (for example: graphene, etc.), and the thickness of the electrode layer 1 can reach the conductive standard. The ferroelectric layer 2 can be hafnium-zirconium oxide (HZO), or any other ferroelectric material (for example: PbTiO3, etc.), and the ferroelectric layer 2 can be of any thickness. The semiconductor layer 4 can be P-Si, i.e. P-type Si, or any doping type and doping concentration of Si, in addition to Ge or two-dimensional semiconductor materials.

[0045] In this embodiment, a ferroelectric tunnel junction with a P-type-Si(SiO2)-TiN(1-3nm)-HZO(8nm)-electrode (Al, Pt, TiN, or W) structure is used as an example for detailed performance description. The electrode layer 1 is made of TiN, the ferroelectric layer 2 is made of HZO with a thickness of 8nm, the conductive functional layer 3 is also made of TiN with a thickness of 1-3nm, and the semiconductor layer 4 is made of P-type-Si and SiO2. The fabrication process can be as follows: using highly doped P-type silicon, a layer of SiO2 is naturally oxidized to form the semiconductor layer 4. Then, 1-3nm TiN (titanium nitride), 8nm HZO, and 60nm TiN are prepared using ALD (atomic layer deposition). The 60nm TiN is patterned to form electrode layer 1. After forming electrode layer 1, rapid annealing is performed using a rapid annealing furnace (550℃, 30s heating, 30s cooling, and 1min holding).

[0046] The ferroelectricity of ferroelectric layer 2 in the above structure is as follows: Figure 2 As shown, its 2Pr (twice the remanent polarization) value is at 30 μC / cm. 2 Based on this, the overall performance of the ferroelectric tunnel structure described above is as follows: Figures 3-6 As shown. Figure 3 In this process, by inserting a conductive functional layer 3 (e.g., TiN), an on / off ratio of up to 2580 is achieved, such as... Figure 4 As shown, the on-state current is 1.6 A / cm. 2 The ferroelectric tunnel junction maintains an on / off ratio exceeding 100 times at 0.1V and over 1000 times at 0.4V, enabling readout operations at low voltages. Figure 5 As shown, the stability of the ferroelectric tunnel junction was tested, and it was found that it could still maintain an on / off ratio of over 1000 times after 10000s. Furthermore, the epitaxial curves of both the high-resistivity and low-resistivity states indicate that the ferroelectric tunnel junction can maintain a service life of 10 years. Figure 6 As shown, the ferroelectric tunnel junction is subjected to ±10 10 Even after a pulse, it can still maintain a discrete electrical state, thus possessing excellent erasure and rewrite resistance.

[0047] In some embodiments, such as Figure 7 As shown, the ferroelectric tunnel junction further includes a first insulating layer 5, which is located between the electrode layer 1 and the ferroelectric layer 2.

[0048] In some embodiments, such as Figure 8 As shown, the ferroelectric tunnel junction further includes a first insulating layer 5, which is located between the ferroelectric layer 2 and the conductive functional layer 3.

[0049] In some embodiments, as shown in FIG. 1, the ferroelectric tunnel junction further comprises a first insulating layer 5, which is located between the conductive functional layer 3 and the semiconductor layer 4. Figure 9 In some embodiments, as shown in FIG. 1, the ferroelectric tunnel junction further comprises a first insulating layer 5, which is located between the conductive functional layer 3 and the semiconductor layer 4.

[0050] In some embodiments, as shown in FIG. 1, the ferroelectric tunnel junction further comprises a first insulating layer 5, which is located between the conductive functional layer 3 and the semiconductor layer 4. Figure 10 In some embodiments, as shown in FIG. 1, the ferroelectric tunnel junction further comprises a first insulating layer 5, which is located between the conductive functional layer 3 and the semiconductor layer 4.

[0051] In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies.

[0052] In some embodiments, the thickness of the first insulating layer 5 is less than 10 nm, because if the thickness of the first insulating layer 5 is too thick, it will reduce the working current of the entire ferroelectric tunnel junction, and the resistance of the first insulating layer 5 will exceed the resistance of the ferroelectric layer 2, so that there is no switching ratio before and after the ferroelectric reversal.

[0053] In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies. Figure 7 In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies. Figures 11-14 In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies. Figure 11 In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies. Figure 12 In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies. 2 In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies. Figure 13 In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies. Figure 14 In some embodiments, the material of the first insulating layer 5 can be MgO, Al2O3 or SiO2, etc. By introducing the first insulating layer 5 between the electrode layer 1, the ferroelectric layer 2, the conductive functional layer 3 and the semiconductor layer 4, or between the first ferroelectric sublayer 21 and the second ferroelectric sublayer 22, the switching ratio and stability of the ferroelectric tunnel junction can be further improved. The reason is that the large band gap of the first insulating layer 5 can effectively suppress the leakage current caused by oxygen vacancies. 10The ferroelectric tunnel junction can still maintain a discrete electrical state after a subsequent pulse, thus having superior resistance to erasing.

[0054] In some embodiments, as shown in FIG. 1, the ferroelectric tunnel junction further comprises a first insulating layer 5, which is located on the semiconductor layer 4 and faces the conductive functional layer 3. Figure 15 The first insulating layer 5 can be present simultaneously with the second insulating layer 6, and the first insulating layer 5 is located above the second insulating layer 6.

[0055] In some embodiments, the material of the semiconductor layer 4 can be doped Si, Ge or a two-dimensional material. When the material of the semiconductor layer 4 is a two-dimensional material, the second insulating layer 6 will not be generated in the process of preparing the semiconductor layer 4, so that the overall structure of the ferroelectric tunnel junction is simpler.

[0056] The application also provides a preparation method of a ferroelectric tunnel junction, which can be used to prepare the ferroelectric tunnel junctions in the above embodiments.

[0057] Step one: forming a semiconductor layer. In this step, the semiconductor layer can be a highly doped P-type silicon, and a layer of SiO2 is naturally oxidized to form the semiconductor layer.

[0058] Step two: sequentially forming a conductive functional layer, a ferroelectric layer and an electrode layer on the semiconductor layer to obtain the ferroelectric tunnel junction. For example, 1-3 nm of TiN (titanium nitride) and 8 nm of HZO and 60 nm of TiN are prepared by ALD (atomic layer deposition) respectively, and the 60 nm of TiN is patterned to form an electrode layer 1. After the formation of the electrode layer 1, rapid annealing is performed by using a rapid annealing furnace (550 DEG C, 30 seconds of temperature rise, 30 seconds of temperature drop, and 1 minute of holding).

[0059] In some embodiments, step two specifically comprises:

[0060] sequentially forming a conductive functional layer, a ferroelectric layer, a first insulating layer and an electrode layer on the semiconductor layer.

[0061] or sequentially forming a conductive functional layer, a first insulating layer, a ferroelectric layer and an electrode layer on the semiconductor layer.

[0062] or sequentially forming a first insulating layer, a conductive functional layer, a ferroelectric layer and an electrode layer on the semiconductor layer.

[0063] Or, a conductive functional layer, a second ferrie layer, a first insulating layer, a first ferrie layer and an electrode layer are sequentially formed on the semiconductor layer.

[0064] The application also provides a memory including the ferroelectric tunnel junction of any of the above embodiments. The memory of the application also has the advantages of high on-off ratio, high stability and low power consumption due to the use of the ferroelectric tunnel junction of the above embodiments.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the application, and not to limit it; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A ferroelectric tunnel junction, characterized by, Comprising: an electrode layer, a ferroelectric layer, a conductive functional layer and a semiconductor layer, the ferroelectric layer is between the electrode layer and the conductive functional layer, the semiconductor layer is on the side of the conductive functional layer away from the ferroelectric layer, the thickness of the conductive functional layer is less than or equal to 10 nm.

2. The ferroelectric tunnel junction of claim 1, wherein, Further comprising: a first insulating layer, the first insulating layer is between the electrode layer and the ferroelectric layer.

3. The ferroelectric tunnel junction of claim 1, wherein, Further comprising: a first insulating layer, the first insulating layer is between the ferroelectric layer and the conductive functional layer.

4. The ferroelectric tunnel junction of claim 1, wherein, Further comprising: a first insulating layer, the first insulating layer is between the conductive functional layer and the semiconductor layer.

5. The ferroelectric tunnel junction of claim 1, wherein, Further comprising: a first insulating layer, the ferroelectric layer comprises a first ferroelectric sub-layer and a second ferroelectric sub-layer, the first insulating layer is between the first ferroelectric sub-layer and the second ferroelectric sub-layer.

6. The ferroelectric tunnel junction of any one of claims 1-5, wherein, The thickness of the first insulating layer is less than 10 nm.

7. The ferroelectric tunnel junction of any one of claims 1-5, wherein, Further comprising: a second insulating layer, the second insulating layer is on the side of the semiconductor layer facing the conductive functional layer.

8. The ferroelectric tunnel junction of any one of claims 1-5, wherein, The material of the semiconductor layer is: Si, Ge with doping or two-dimensional material.

9. A memory, comprising: Comprising: the ferroelectric tunnel junction of any one of claims 1 to 8.

10. A method for preparing a ferroelectric tunnel junction, characterized in that, A method for preparing the ferroelectric tunnel junction of any one of claims 1 to 8, the method comprising: forming a semiconductor layer; forming a conductive functional layer, a ferroelectric layer and an electrode layer on the semiconductor layer in sequence to obtain the ferroelectric tunnel junction.

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