Preparation method of semiconductor structure facing advanced node and semiconductor structure
Efficient and precise pattern fabrication was achieved in advanced nodes of integrated circuits by using remote plasma etching machines and stacking processes. This solved the problems of insufficient photolithography resolution and complexity and edge quality caused by multiple patterning, thus improving fabrication efficiency and pattern quality.
Patent Information
- Application Number
- CN202511295079.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-10
- Publication Date
- 2026-01-20
AI Technical Summary
In advanced nodes of integrated circuits, lithography resolution cannot meet the requirements of small size. Multiple patterning techniques lead to a surge in the complexity of process steps and deterioration of pattern edge quality, affecting device performance.
Isotropic dry etching is performed using a remote plasma etching machine, combined with a stacked process, to form a pattern of the target size in one photolithography-etching cycle, which simplifies the process flow and improves the pattern quality.
It significantly improves preparation efficiency, reduces process time, improves pattern quality, and meets the requirements of advanced nodes for high precision and high consistency.
Smart Images
Figure CN121368346A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a manufacturing method of a semiconductor structure for an advanced node and the semiconductor structure. BACKGROUND
[0002] In the advanced node of integrated circuits, the core challenge of small size patterning is derived from the contradiction between the physical limit of lithography resolution and the demand for small size, which further leads to a series of derivative problems, which can be summarized as follows: The lithography resolution cannot directly meet the size demand: using EUV lithography with a wavelength of 13.5 nm, the theoretical resolution (about 13-16 nm) is still lower than the pattern size demand (for example, 10-20 nm) of the key structure (for example, gate, contact hole) related to the 3 nm node, so multiple patterning technology must be relied on to realize smaller size patterns, including LELE (lithography-etch-lithography-etch), SADP (self-aligned double patterning), SAQP (self-aligned quadruple patterning), etc.
[0003] However, multiple patterning technology directly leads to an explosive increase in process flow steps and complexity: to break through the resolution limit of lithography, multiple patterning needs to realize pattern reduction step by step through multiple lithography-etch cycles, which causes two key problems: one is the strict requirement for overlay accuracy, and any slight thermal / mechanical fluctuation will cause pattern misplacement failure; the second is that the process steps, cost and defect rate increase exponentially with the number of cycles.
[0004] In addition, multiple pattern transfer aggravates edge quality deterioration: in multiple patterning, the pattern needs to go through multiple transfer cycles of "photoresist→mask→target layer", and each transfer cycle will accumulate line edge roughness and edge placement error, eventually leading to pattern deformation and affecting device performance. SUMMARY
[0005] The purpose of the present application is to provide a manufacturing method of a semiconductor structure for an advanced node and the semiconductor structure, for improving the manufacturing efficiency and pattern quality of the semiconductor structure for an advanced node.
[0006] In order to achieve the above purpose, the present application provides the following technical scheme: In a first aspect, the present application provides a manufacturing method of a semiconductor structure for an advanced node, comprising: forming a stack on a bottom structure; the stack comprises a stop layer, a target layer and a mask layer from bottom to top; forming an initial pattern on the surface of the mask layer, and transferring the initial pattern to the mask layer and the target layer to form an initial structured pattern of the target layer on the target layer, the size of which is consistent with that of the initial pattern; The remote plasma etching machine is used to isotropically etch the initial structured pattern of the target layer, so as to reduce the initial structured pattern of the target layer to a target size pattern; wherein the ratio of the preset etching rate of the target layer to the stop layer is greater than or equal to a preset ratio; Based on the target layer with the target size pattern formed by etching, a target semiconductor structure is formed.
[0007] Optionally, the remote plasma etching machine at least includes a reaction cavity; The remote plasma etching machine is used to isotropically etch the initial structured pattern of the target layer, so as to reduce the initial structured pattern of the target layer to a target size pattern, including: The main gas and the carrier gas are introduced into the reaction cavity, and the sidewall of the initial structured pattern of the target layer is isotropically dry etched based on the ratio of the preset etching rate; wherein the main gas is one of 、 and ; the carrier gas is one or more of and ; When the preset time is reached, the etching is stopped; the preset time is the time to reach the target size pattern.
[0008] Optionally, the remote plasma etching machine further includes a remote plasma generating unit; the remote plasma generating unit is connected with the reaction cavity through a sealed gas channel; The remote plasma generating unit at least includes an inductively coupled plasma etching cavity and two layers of charged ion filtering screens, and the two layers of the charged ion filtering screens are fixedly arranged between the inductively coupled plasma etching cavity and the sealed gas channel.
[0009] Optionally, the target semiconductor structure is a contact hole; Based on the target layer with the target size pattern formed by etching, a target semiconductor structure is formed, including: For the target layer with the target size pattern formed by etching, taking the stop layer as a base, a dielectric is filled in the gap between the target size patterns, and a chemical mechanical polishing process is used to make the surface of the dielectric flush with the top of the initial structured pattern of the target layer; the material of the dielectric is the same as that of the stop layer; The target size pattern formed by etching the target layer is removed; The local stop layer directly below the position of the target size pattern is removed to form a contact hole opening; The metal is filled in the contact hole opening and polished to form the contact hole.
[0010] Optionally, the gap between the target size patterns is filled with dielectric, comprising: A HDP process is used to deposit dielectric on the whole area including the gap; wherein the deposition range covers the gap and the surface of the target size patterns.
[0011] Optionally, the gap between the target size patterns is filled with dielectric, comprising: The mask layer remaining on top of the target size patterns is removed, and an ALD process is used to perform dielectric filling on the gap.
[0012] Optionally, an initial pattern is formed on the surface of the mask layer, comprising: Based on a photolithography process, photoresist is coated on the surface of the mask layer; The photoresist is exposed and developed through a mask, and the photoresist in the exposed area is removed to form the initial pattern.
[0013] Optionally, the initial pattern is transferred to the mask layer and the target layer, and an initial structured pattern of the target layer with the same size as the initial pattern is formed on the target layer, comprising: Using the photoresist as a mask, a first etching gas is used to etch the mask layer based on a first preset plasma power, and a mask pattern is formed; The photoresist is retained, and a second etching gas is used to etch the target layer based on a second preset plasma power, using the mask pattern as an auxiliary mask, and etching to a stop layer to form the initial structured pattern of the target layer.
[0014] Optionally, the first etching gas includes F-based gas; and the second etching gas includes Based gas.
[0015] Compared with the prior art, the preparation method of the semiconductor structure for the advanced node provided by the present application forms the initial structured pattern of the target layer with the same size as the initial pattern first, and then uses a remote plasma etching machine for isotropic dry etching to realize one-time pattern precise reduction, which eliminates the multiple photolithography, mask adjustment or step etching steps that may be required in the traditional process, greatly simplifies the process flow, reduces the process time, and significantly improves the preparation efficiency.
[0016] Meanwhile, since the ratio of the etching rate of the target layer to the stop layer meets the preset requirement, the bottom layer structure can be effectively protected from excessive etching damage during the etching process, the isotropic characteristics of the remote plasma etching are combined, the pattern reduction range can be accurately controlled and the sidewall smoothness is ensured, and problems such as pattern size deviation and edge roughness that are prone to occur in the prior art are avoided, so that the pattern quality is significantly improved while the efficiency is improved, and the requirements of high precision and high consistency of the semiconductor structure of the advanced node are better met.
[0017] In a second aspect, the present application further provides a semiconductor structure prepared by the preparation method of the semiconductor structure for advanced nodes. BRIEF DESCRIPTION OF DRAWINGS
[0018] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application. In the drawings: Figure 1 Flowchart of the preparation method of the semiconductor structure for advanced nodes provided by an embodiment of the present application; Figures 2 to 11 Preparation flow of the contact hole in the first embodiment of the present application.
[0019] Reference signs: 1-bottom layer structure; 2-stop layer; 3-target layer; 4-mask layer; 5-photoresist pattern; 6-metal. DETAILED DESCRIPTION
[0020] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second", etc. For example, the first threshold value and the second threshold value are only used to distinguish different threshold values, and do not limit the order. Those skilled in the art can understand that "first", "second", etc. do not limit the number and execution order, and "first", "second", etc. also do not necessarily mean different.
[0021] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of "exemplary" or "for example" is intended to present concepts in a concrete manner. The words "first", "second", etc. are used to distinguish different items or similar items with basically the same functions and effects.
[0022] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships.
[0023] like Figure 1 As shown, embodiments of the present invention provide a method for fabricating semiconductor structures for advanced nodes, which may include: Step 100: Form a stack on the underlying structure; the stack includes a stop layer, a target layer and a mask layer from bottom to top; Specifically, advanced nodes refer to advanced process nodes (such as 3nm, 5nm, etc.) used in integrated circuit manufacturing. They are characterized by extremely small sizes of key structures such as transistors and contact holes in the chip (typically 20nm and below), aiming to improve chip performance, reduce power consumption, and increase integration density by shrinking device size. However, the fabrication of advanced nodes faces challenges such as insufficient lithographic resolution and a surge in process complexity. This invention is a solution proposed to address these challenges.
[0024] For example, if a contact hole needs to be formed, then the stop layer and the mask layer can be... The target layer can be amorphous silicon. .
[0025] In one optional embodiment, step 100 may specifically include: A stop layer is formed on the underlying structure using a thermo-oxidative process; The target layer is formed on the stop layer using a low-pressure chemical vapor deposition (LPCVD) process; A mask layer is formed on the target layer using atomic layer deposition (ALD).
[0026] In this embodiment, the thermal oxidation, LPCVD, and atomic layer deposition processes used in step 100 for the stop layer, target layer, and mask layer, respectively, are not simply film formation choices, but rather a collaborative design that combines the core requirements of small size, high precision, and process compatibility in the fabrication of advanced node semiconductor structures. Its technical effects are reflected in the following aspects:
[0027] A stop layer formed using a thermal oxidation process is used to construct a high-selectivity protective substrate, thus mitigating the risk of damage to the underlying layers. Specifically, the stop layer serves as a protective barrier for the subsequent 300-step isotropic dry etching process. Its core requirement is to form a stable high etching selectivity with the target layer (such as polysilicon or amorphous silicon) to prevent accidental damage to sensitive underlying structures (such as source / drain regions and gate oxide layers) during the etching process.
[0028] Thermo-oxidation process generates by direct oxidation on the surface of the underlying silicon substrate. Thin films possess three key advantages: firstly, they have extremely high component purity and near-ideal stoichiometry. ( (2:1), no impurities (such as carbon, hydrogen) that may be introduced by the deposition process, ensuring chemical stability during etching; second, the interface bonding force with the underlying silicon substrate is extremely strong, avoiding the risk of film peeling; third, it can stably achieve an etching selectivity ratio of ≥10:1 (much better than 5:1 or less for a single deposition process). In step 300, the etching gas preferentially reacts with the target layer, with almost no etching of the thermal oxide The stop layer fundamentally guarantees the integrity of the underlying sensitive structure, providing a reliable protective foundation for the precise etching and shrinking of the target layer.
[0029] The target layer uses the LPCVD process to ensure uniformity and stability, which is suitable for small-size etching requirements. Specifically, as the carrier of the initial structured pattern, the thickness uniformity and structural density of the target layer directly determine the consistency of the target size pattern after isotropic etching in step 300. The LPCVD process perfectly matches this requirement: LPCVD deposits the target layer in a low-pressure environment (typically 10-100 Pa). On the one hand, the film uniformity is excellent, with a thickness deviation controlled within ±1 nm. Even if there are slight bumps and hollows (such as fin structure edges and trench textures) of 3 nm on the surface of the stop layer, it can achieve consistent thickness coverage in the entire area, ensuring that the sidewalls of the initial structured pattern can be uniformly reduced during step 300 etching, and finally forming a target pattern with a size deviation of ≤0.5 nm. On the other hand, the deposition density is high (polysilicon density ≥2.3 g / cm³), avoiding defects such as sidewall sagging and pattern collapse caused by loose structure during etching, which is suitable for the structural stability requirements of small-size patterns in advanced nodes (such as 15-20 nm). At the same time, the deposition temperature of LPCVD (typically 500-600°C) is compatible with the thermal stability of the underlying thermal oxide , without causing interface diffusion or lattice distortion, meeting the implicit requirement of low thermal budget for advanced nodes.
[0030] The mask layer uses an atomic layer deposition process to ensure pattern transfer accuracy. Specifically, the mask layer is the core template for the initial pattern transfer in step 200, and its thickness deviation and shape retention will directly cause size deviation or edge distortion in the transferred pattern. The single-atomic layer control characteristics of the atomic layer deposition process perfectly solve this problem: Atomic layer deposition realizes nanometer thickness control (accuracy ±0.1 nm) through a cycle mode of alternating input of reaction gas-adsorption-reaction-purge, can accurately control the mask layer thickness (usually 5-20 nm) according to the target pattern requirement, avoids incomplete etching caused by too thick thickness and mask failure caused by too thin thickness; secondly, it has strong conformality and can completely cover the fine structure of the target layer surface (such as the small protrusions and grooves at the edge of the target layer), ensuring that the mask layer is completely attached to the target layer surface without blind area; thirdly, the film composition is uniform, and there is no problem of uneven etching rate caused by local composition difference. Such high-precision mask layer can control the transfer error of the initial pattern of the target layer to be within ±0.3 nm, thereby guaranteeing the size accuracy of the subsequent etching shrinkage from the source, and meeting the demand of advanced nodes for pattern zero distortion.
[0031] Step 200: forming an initial pattern on the surface of the mask layer, and transferring the initial pattern to the mask layer and the target layer to form an initial structured pattern of the target layer with the same size as the initial pattern on the target layer; Step 300: using a remote plasma etching machine to perform isotropic dry etching on the sidewall of the initial structured pattern of the target layer, and reducing the initial structured pattern of the target layer to a target size pattern; wherein the ratio of the etching rate of the target layer to the stop layer is greater than or equal to a preset ratio; For example, the preset ratio is 8:1.
[0032] For example, for a contact hole, the preset ratio is 10:1.
[0033] It should be particularly pointed out that the related art uses an electrically conductive coupled plasma process to prepare a semiconductor technology: an RF power source is used to directly generate plasma in a reaction chamber, the plasma directly contacts the sample, and a bias power can cause certain physical bombardment, although it can achieve isotropic etching, but the etching selectivity control is weak.
[0034] The embodiment of the application specially uses a remote plasma etching machine: the plasma is generated in an area far away from the reaction chamber, and active particles are introduced into the chamber through a carrier gas, which avoids direct bombardment of the sample by the plasma, the etching process is more gentle, the uniformity of isotropic etching is higher, and the etching rate ratio can be accurately controlled.
[0035] Therefore, the embodiment of the application specially uses a remote plasma etching machine, which has the following advantages: 1) Higher etching selectivity: accurately control the etching rate ratio of the target layer and the stop layer, reduce the damage to the bottom layer structure, and the process stability is higher, while the electrically conductive coupled plasma process in the related art may cause device defects due to insufficient selectivity.
[0036] 2) Better edge quality: the combination of the gentle characteristics of remote plasma etching and single pattern transfer enables the control of gate sidewall roughness (LER) within 1.2 nm, which is improved compared to multiple patterning techniques, and the related art cannot solve the edge quality deterioration problem caused by multiple pattern transfer.
[0037] In summary, the embodiment realizes smaller size, higher precision and more stable performance in advanced node gate preparation through precise control of the remote plasma etching machine, high-selectivity etching and synergistic layer process, which can better meet the technical requirements of 3nm and other advanced nodes compared to the inductively coupled plasma process in the related art.
[0038] Step 400: forming a target semiconductor structure based on the target layer with the target size pattern formed by etching.
[0039] For example, the target semiconductor structure is a contact hole.
[0040] Beneficial effect analysis of the embodiment: the embodiment realizes the following technical effects by the core process of layer construction (step 100) → initial pattern transfer (step 200) → single etching reduction (step 300) → formation of the final structure (step 400) for the inherent defects of multiple patterning techniques in advanced node semiconductor structure preparation: 1) Solve the problem of complicated steps and cost explosion.
[0041] The embodiment completes the transfer of the initial pattern to the mask layer and the target layer through one lithography-etching cycle, and only single pattern transfer is needed to form the initial structured pattern of the basic size, without repeated steps such as multiple photoresist coating, exposure, development, etc. The sidewall of the initial structured pattern is isotropically dry etched by a remote plasma etching machine, and the pattern size is directly reduced from the basic value (e.g. 45nm) to the target value (e.g. 15nm) through single etching, without additional lithography steps throughout the process.
[0042] This single pattern transfer combined with single etching reduction reduces the total process steps by more than 60%, not only reducing equipment investment and time cost, but also completely avoiding the strict requirement of nanoscale precision caused by multiple overlay in multiple patterning, reducing the risk of pattern misplacement caused by thermal / mechanical fluctuations, and improving process stability.
[0043] 2) Solve the problem of pattern edge quality deterioration.
[0044] The step 200 only performs one-time pattern transfer of "photoresist→mask layer→target layer", avoiding the accumulation of line edge roughness (LER) and edge placement error (EPE) caused by multiple transfers in the traditional technology; the step 300 directly performs uniform trimming on the sidewall of the target layer through isotropic etching to reduce the size, rather than realizing size reduction through new pattern transfer, so as not to introduce additional edge error.
[0045] The measured data show that the pattern edge roughness prepared by the method can be controlled within 1.2 nm, which is higher than that of the multiple patterning technology (usually 3-5 nm), significantly improves the edge consistency of key structures such as contact holes, and reduces the performance risks such as device leakage and abnormal contact resistance.
[0046] In summary, the embodiment fundamentally overcomes the bottleneck of multiple patterning technology by simplifying the process and optimizing the pattern processing method, and provides a feasible solution for efficient and high-precision preparation of advanced node semiconductor structures such as 3 nm.
[0047] In an alternative embodiment, the remote plasma etching machine at least includes a reaction chamber and a remote plasma generation unit; the remote plasma generation unit is connected with the reaction chamber through a sealed gas channel; the remote plasma generation unit at least includes an inductively coupled plasma (ICP) etching chamber and two layers of charged ion filtering screens (grids), and the two layers of charged ion filtering screens are fixedly arranged between the inductively coupled plasma etching chamber and the sealed gas channel to form a separated structure of 'plasma generation-filtering-delivery'. Among them, the two layers of charged ion filtering screens are used to filter the charged ions in the plasma generated by the inductively coupled plasma etching chamber, and only allow neutral etching active particles to enter the reaction chamber through the sealed gas channel.
[0048] Based on the above structure of the remote plasma etching machine, the step 300 uses the remote plasma etching machine to perform isotropic etching on the initial structured pattern of the target layer, and reduces the initial structured pattern of the target layer to a target size pattern, including: Passing the main gas and the carrier gas into the reaction chamber, based on the preset etching rate ratio, performing isotropic dry etching on the sidewall of the initial structured pattern of the target layer; wherein the main gas is , and one of them; the carrier gas is and one or more.
[0049] When the preset time is reached, stop etching; the preset time is the time to reach the target size pattern.
[0050] The embodiment has the following technical effects: 1) The embodiment fixes the ICP etching cavity and the sealing gas channel between the two layers of charged ion filtering screens and selects the etching gas, which together ensures that the etching rate ratio of the target layer to the stop layer is greater than or equal to a preset ratio, thereby fundamentally protecting the bottom layer structure. From the structure: The two layers of grid precisely filter the high-energy charged ions (such as , ) generated by the ICP etching cavity, allowing only neutral etching active particles to pass through the sealing channel into the reaction cavity. The neutral particles only react with the target layer through chemical action (such as generating volatile ), and almost do not react with the stop layer (such as , ), thereby avoiding the false damage to the stop layer in the traditional mixed mode of ion bombardment and chemical etching.
[0051] From the gas selection: The main gas (one of ) is a highly efficient etchant for the target layer (such as NF3, which has an etching rate for amorphous silicon that is more than 10 times that of ), and the carrier gas further adjusts the reaction atmosphere to suppress the weak reaction of neutral particles with the stop layer, thereby double-protecting the target layer from etching and the bottom layer from damage.
[0052] 2) The embodiment realizes the precise reduction of the initial structured pattern of the target layer to the target size (such as 10-20 nm) through the separated structure and the preset time control speed, thereby solving the bottleneck of insufficient photolithography resolution: From the etching uniformity: The separated structure of plasma generation (ICP), filtering (grid), and delivery (sealed channel) makes the neutral active particles more uniformly diffuse in the reaction cavity, which can uniformly reduce the target layer initial pattern along the entire sidewall, thereby avoiding the size deviation caused by local over-reduction or under-reduction in traditional etching, and ensuring that the size deviation of the reduced pattern is less than or equal to 0.5 nm.
[0053] From the end point control: The preset time equal to the time to reach the target size is a quantitative parameter based on the previous process verification (such as 15s to reduce 45nm pattern to 20nm when the etching rate is stable), which does not require additional multiple photolithography-etching cycles (instead of traditional multiple patterning technology), thereby directly realizing single etching reduction, avoiding the size cumulative error of multiple overlay, and meeting the precision requirements of advanced nodes 3-20nm key dimensions.
[0054] 3) The structure and etching mode of the embodiment fundamentally solve the problem of edge roughness and edge placement error deterioration caused by multiple pattern transfer in the prior art: The mild etching characteristics of the neutral particles: no high-energy ion bombardment, no lattice distortion, burr, depression and other defects on the sidewall of the target layer during the etching process, combined with the uniform reduction of isotropic etching, the pattern edge roughness can be controlled within 1.2 nm, which is higher than the traditional multiple patterning technology; No additional pattern transfer step: this embodiment completes size control through initial pattern transfer (1 time) combined with single etching reduction, avoids the EPE accumulation caused by traditional photoresist→mask→target layer multiple transfer (for example, each transfer error is 0.5 nm, 3 times of transfer is 1.5 nm error), ensures the consistency of the pattern edge, and reduces the performance risk of device leakage (sidewall roughness causes electric field concentration) and abnormal contact resistance (size deviation causes poor interconnection).
[0055] 4) The remote plasma etching scheme of this embodiment directly replaces the complex process of traditional advanced node preparation which relies on multiple patterning, achieving efficiency improvement: Reduce process steps: traditional multiple patterning needs to be realized through 2-4 times of photolithography-etching cycle to achieve small size pattern (such as reducing 45 nm to 20 nm needs 4 times of etching), while this embodiment only needs 1 time of initial pattern transfer and 1 time of remote plasma etching to complete size reduction, which reduces the total process steps by more than 50%, saving the time-consuming links such as photoresist coating, exposure, development, mask replacement, etc. Shorten the process cycle: the separated structure of remote plasma etching supports the synchronization of plasma generation and etching (without waiting for the plasma to stabilize before putting the sample), and the etching process can be continuous (carrier gas continuously delivers active particles), which shortens the single batch process time, and at the same time avoids the pollution risk caused by exposing the sample to air in multiple processes (sealed channel and closed loop operation of reaction cavity), further improving the production efficiency.
[0056] In an optional embodiment, the target semiconductor structure is a contact hole; when the target semiconductor structure is a contact hole, step 400: forming a target semiconductor structure based on the target layer with a target size pattern formed by etching, comprises: For the target layer with a target size pattern formed by etching, taking the stop layer as the base, filling the dielectric in the gap between the target size patterns, and using chemical mechanical polishing process (CMP) to make the surface of the dielectric flush with the top of the initial structured pattern of the target layer; the material of the dielectric is the same as that of the stop layer; Removing the target size pattern formed by etching the target layer; Removing the local stop layer directly below the position of the target size pattern to form a contact hole opening; Filling metal in the contact hole opening and polishing to form a contact hole.
[0057] Specifically, the dielectric in the dielectric fill refers to a material with insulating properties, which is filled in the gap between the target size pattern (amorphous silicon), and its role is to isolate adjacent structures and avoid short circuits during subsequent metal filling. Since its material is the same as the stop layer (for example ), it can ensure the compatibility of the fill layer and the substrate, and reduce the interface stress.
[0058] Chemical mechanical polishing is a process that combines chemical corrosion and mechanical grinding to polish the surface of the filled dielectric to the top of the initial structured pattern of the target layer. The key is to control the polishing rate and endpoint to ensure surface flatness (for example, 3nm node requires global flatness ≤1nm), providing a smooth operating surface for subsequent removal of the target layer and formation of the contact hole opening.
[0059] The target layer removal process is described. When removing the etched target size pattern (amorphous silicon), a selective etching technique (such as dry etching using fluorine-containing gas) is used to remove only amorphous silicon without damaging the surrounding dielectric and stop layer, ensuring the integrity of the dielectric fill structure and providing accurate boundaries for the positioning of the contact hole opening.
[0060] Local stop layer removal and contact hole opening formation. When removing the local stop layer directly below the target size pattern, positioning is based on the isolation wall formed by the previous dielectric fill. After defining the opening area by photolithography, dry etching is used to accurately remove the local , forming a contact hole opening that communicates with the underlying structure (such as the source / drain region), with an opening size error ≤2nm to avoid poor contact.
[0061] Regarding metal filling and polishing, when filling metal (such as tungsten, cobalt) in the contact hole opening, physical vapor deposition or chemical vapor deposition is usually used to ensure that the metal is completely filled to the bottom of the opening (avoiding voids); subsequent polishing removes excess metal on the surface, making the top of the metal flush with the dielectric surface, forming a contact hole that is electrically connected to other parts of the device.
[0062] Beneficial effect analysis of the embodiment: 1) Contact hole size precision and positioning accuracy. Through the process of target layer etching reduction → dielectric filling positioning → local stop layer precise removal, the contact hole opening size can strictly match the target size pattern, and the position deviation is ≤1 nm, solving the contact hole positioning deviation problem caused by multiple patterning in traditional process, ensuring effective contact with the bottom source / drain region. 2) Interface compatibility and structural stability. The dielectric and the stop layer material are the same, avoiding interface reactions (such as diffusion, stress cracking) between different materials; the flat surface ensured by the CMP process reduces defects (such as insufficient metal accumulation at the step) in subsequent etching and metal filling, improving the structural stability of the contact hole. 3) Process simplification and cost reduction. Compared with the "multiple photolithography-etching-filling" cycle in traditional contact hole preparation, this process realizes positioning through one target layer etching reduction and one dielectric filling, reducing process steps, reducing equipment investment and time cost, and avoiding error accumulation caused by multiple processes. 4) Optimization of electrical performance. The integrity of the metal filling and the precise size of the contact hole opening reduce the contact resistance and reduce the power consumption of the device; at the same time, the good insulation of the dielectric avoids the risk of leakage between adjacent contact holes, improving the reliability of the device.
[0063] In an alternative embodiment, the dielectric is filled in the gap between the target size patterns, comprising: The HDP process is used to deposit dielectric on the entire area including the gap; wherein the deposition range covers the gap and the surface of the target size pattern.
[0064] Specifically, HDP (High Density Plasma) is a dielectric deposition technology that combines chemical deposition and physical bombardment. The core is to generate high-density plasma (ion concentration usually ) through a high-frequency power supply, which simultaneously performs chemical deposition of dielectric (such as ) and real-time compaction of the deposition layer using high-energy ions (such as ) in the plasma. Its core feature is that the deposition layer has extremely high density, and by adjusting the plasma power and gas flow, it can achieve uniform coverage of the entire area including the gap and the surface of the target size pattern, especially suitable for filling the gap with low aspect ratio in advanced nodes (such as the gap with an aspect ratio ≤8:1 in the preparation of contact holes in the 3nm node), avoiding the gap or local loose problems caused by uneven coverage in traditional deposition. During the deposition process, the reaction gas (such as , , ) is introduced in a predetermined ratio, and react chemically to generate dielectric, Ions bombard the generated layer, extruding the pores in the layer, ensuring that the dielectric completely fills the gap and has no internal cavities.
[0065] In this embodiment, the dielectric filling method is specifically as follows: directly using the HDP process to perform dielectric deposition on the entire area containing the gap between the target size patterns, and the deposition range not only covers the inside of the gap, but also completely covers the top surface of the target size pattern (such as amorphous silicon, polysilicon). This process does not need to remove the mask layer that may be left on the top of the target size pattern in advance, and gap filling and surface coverage can be completed by a single deposition, which is suitable for scenarios with high requirements for process step simplification and production efficiency; subsequently, the dielectric layer covering the surface of the target size pattern needs to be polished to be flush with the top of the target size pattern by a chemical mechanical polishing process, and at the same time, the residual mask layer can be removed, finally forming a flat dielectric substrate.
[0066] Beneficial effect analysis of the embodiment: 1) High density filling, avoiding subsequent process defects. The ion bombardment compaction characteristics of the HDP process make the deposited dielectric density higher than that of the traditional PECVD process, which not only can completely fill the gap between the target size patterns, but also can avoid the presence of small cavities or loose areas in the gap, which can effectively prevent poor contact or resistance difference caused by cavities during subsequent metal filling, and adapt to the strict requirements of 3nm nodes for defect-free dielectric layers.
[0067] 2) Improved deposition uniformity and interface stability. The high-density plasma density uniformity error of the HDP process is ≤3%, which can ensure that the deposition thickness deviation of the dielectric inside the gap and the surface of the target size pattern is controlled within ±1nm, avoiding uneven subsequent CMP polishing caused by local over-thickness or over-thin; at the same time, ion bombardment can enhance the interface bonding force between the dielectric and the target layer and the stop layer, and reduce the interface stress cracking caused by the difference in material thermal expansion coefficient.
[0068] 3) Simplify the process flow and improve production efficiency. This filling method does not need to remove the residual mask layer on the top of the target size pattern in advance, and directly realizes whole piece deposition, which reduces 1 etching process compared with the scheme of removing the mask first and then filling, and simplifies the process steps; at the same time, the deposition rate of the HDP process is relatively fast, the deposition time of a single batch of wafers is shortened, which significantly improves the production efficiency of advanced node semiconductor structures, and solves the problem of complicated traditional process steps and long time consumption.
[0069] In an alternative embodiment, the dielectric filling between the target size patterns comprises: removing the residual mask layer on the top of the target size pattern, and performing dielectric filling on the gap by using an atomic layer deposition (ALD) process.
[0070] Specifically, the atomic layer deposition process is a thin film deposition technology based on surface chemical reaction. Two or more reaction gases (precursors) are alternately introduced into a reaction chamber, so that the gas molecules are self-limitedly adsorbed and reacted on the surface of the substrate, thereby realizing the growth of thin film with single atomic layer precision.
[0071] The beneficial effects of the embodiment are: 1) for a small gap with a depth-to-width ratio of ≥10:1 in the scenario of a 3nm node contact hole, the self-limiting growth characteristics of the atomic layer deposition process can uniformly deposit dielectric from the bottom and sidewall of the gap, completely avoiding the keyhole effect that easily occurs in HDP process at high depth-to-width ratio, and ensuring 100% gap filling without voids, 2) ALD can accurately control the thickness of the dielectric (deviation ±0.1nm) through the number of cycles, and only fill the gap without covering the surface of the target layer, and the thickness uniformity is improved.
[0072] In an alternative embodiment, the metal is filled in the contact hole opening, comprising: When the feature size of the target size pattern is less than or equal to 20nm, the atomic layer deposition process is used to fill the metal.
[0073] In the embodiment, the specific process can be: when filling metal (such as tungsten, cobalt) in the contact hole opening, first introduce the metal precursor (such as tungsten hexafluoride ), the molecules of which will be adsorbed on the inner wall surface of the contact hole opening (forming a monolayer); then introduce the reaction gas (such as hydrogen ), which reacts with the adsorbed precursor to form metal elements (such as tungsten W) and release by-products (such as HF); finally, the unreacted gas and by-products are removed by purging with inert gas (such as argon ), completing one deposition cycle. By repeating the above cycle, the metal layer will gradually grow from the bottom and sidewall of the contact hole opening "from bottom to top and from inside to outside", until the opening is completely filled.
[0074] Adaptability of feature size ≤20nm: when the feature size (such as diameter or width) of the contact hole opening is ≤20nm, its depth-to-width ratio is usually high (up to 15:1 or more for a 3nm node). Traditional physical vapor deposition (PVD) or chemical vapor deposition (CVD) is prone to shadow effect, resulting in the opening top closing first and the formation of voids inside; while the self-limiting growth characteristics of atomic layer deposition can ensure that the metal uniformly covers every surface of the opening (including the bottom corner and sidewall), avoiding filling defects caused by too small size.
[0075] The beneficial effects of the embodiment are: 1) Void-free filling of ultra-small contact holes. For contact hole openings with feature size < 20 nm, atomic layer deposition can completely eliminate defects such as voids and gaps in traditional processes through single-atom layer level precision control, with a metal filling rate of 100%. This is crucial for advanced node devices, as voids can cause a sharp increase in contact resistance, while defect-free filling can ensure the electrical conductivity of the contact hole.
[0076] 2) Precise control of metal layer thickness and uniformity. Atomic layer deposition can grow a fixed thickness of metal layer (e.g. 0.1-0.5 nm / cycle) with each cycle, and by controlling the number of cycles, the metal layer thickness deviation on the inner wall of the contact hole can be controlled within ±0.2 nm. This uniformity avoids local metal thinness leading to uneven resistance, or excessive thickness leading to opening blockage, ensuring the consistency of contact hole electrical performance.
[0077] 3) Excellent step coverage. For the possible small steps and corners in the contact hole opening (such as the connection between the bottom and the sidewall), atomic layer deposition can achieve a step coverage rate close to 100% (traditional CVD is usually only 60%-80%), ensuring the continuity and integrity of the metal layer on the complex topography surface, reducing the risk of electromigration (metal atoms migrate to form voids under the action of current, leading to device failure) caused by insufficient local coverage.
[0078] 4) Process compatibility and thermal budget control. The reaction temperature of atomic layer deposition is usually low (e.g. 200-400°C), which will not cause thermal damage to the dielectric or sensitive structures (such as the dopant distribution of the source and drain region) around the contact hole, meeting the stringent requirements of advanced nodes such as 3nm for low thermal budget processes (to avoid material diffusion or lattice distortion caused by high temperature).
[0079] In an alternative embodiment, step 200 comprises: Step S1: based on the photolithography process, coating photoresist on the surface of the mask layer; For example, uniformly coat photoresist (a polymer material sensitive to light) on the surface of the mask layer, control the thickness of the photoresist (about 50-100 nm for 3 nm nodes) through the spin coating process (rotation speed usually 3000-6000 rpm), ensure that the coating is flat and bubble-free, and provide a uniform photosensitive substrate for subsequent exposure.
[0080] Step S2: expose and develop the photoresist through the mask, remove the photoresist in the exposed area, and form the initial pattern.
[0081] For example, use a mask (a quartz plate with a pre-designed pattern) to expose the photoresist to ultraviolet light (such as When the laser is irradiated onto the photoresist surface, the photoresist in the exposed area changes in chemical properties (after positive photoresist exposure, it can be dissolved by a developer, and negative photoresist is the opposite); during development, the photoresist in the exposed area is removed by a specific developer (such as a tetramethylammonium hydroxide solution), and an initial pattern consistent with the mask is formed on the surface of the photoresist, and the pattern size needs to match the design size of the initial structured pattern of the target layer (such as 45 nm).
[0082] Step S2 comprises: Step S21: using the photoresist as a mask, based on a first preset plasma power, using a first etching gas to etch the mask layer, and forming a mask pattern; wherein the first etching gas can include F-based gas, for example, the first etching gas is Or .
[0083] For example, using the photoresist as a mask, a mixed gas of the first etching gas (providing fluorine ions, etching the mask layer or ) and the carrier is introduced, and the gas is ionized into active ions by a first preset plasma excitation power of 50-200W, so as to dry etch the mask layer not covered by the photoresist, transfer the initial pattern on the photoresist to the mask layer, and form the mask pattern.
[0084] Key parameter description: The flow ratio (such as 3:1) of needs to be adjusted according to the mask material to ensure the etching rate and selectivity, and to avoid excessive etching damage to the bottom target layer.
[0085] Step S22: retaining the photoresist, using the mask pattern as an auxiliary mask, using a second etching gas to etch the target layer based on a second preset plasma power, and etching to a stop layer to form an initial structured pattern of the target layer. Wherein the second etching gas can include based gas, for example, the second etching gas is .
[0086] In a specific implementation, the photoresist is retained, and the second etching gas is switched to, and a second preset plasma excitation power of 100-300W is used to excite the plasma, and at the same time, the mask pattern is used as an auxiliary mask (the photoresist + the mask form a double mask protection), and the target layer is etched to a preset depth of 50-200nm to form an initial structured pattern consistent with the mask pattern size.
[0087] Etching stop condition: when a preset etching stop time is reached, etching is stopped.
[0088] Beneficial effect analysis of the embodiment: 1)Pattern transfer accuracy improvement. Double mask etching target layer with photoresist and mask, etch resistance of mask layer is better than photoresist, can reduce the deformation of mask pattern in etching process (such as photoresist edge wear), make the size deviation of initial structured pattern of target layer controlled within ±1nm, improve the accuracy compared with single photoresist mask, provide reliable basic pattern for subsequent etching shrinkage step 300.
[0089] 2)Etching selectivity and surface quality optimization. Mask etching uses gas, high etching selectivity of mask layer and photoresist (for example ≥10:1), avoid excessive consumption of photoresist; target layer etching uses gas, high etching selectivity of polysilicon / amorphous silicon and mask layer (for example ≥8:1), ensure etching only target layer without damaging mask pattern.
[0090] The plasma parameters of the second preset power (such as lower bias) can reduce the physical bombardment on the surface of the target layer, so that the sidewall roughness of the initial structured pattern is controlled within 2nm, laying a foundation for uniform shrinkage of subsequent isotropic etching.
[0091] 3)Process step simplification and efficiency improvement. Retain photoresist and use mask pattern as auxiliary mask, save the step of removing photoresist→recoating, reduce process time; at the same time, mask layer etching and target layer etching are carried out continuously in the same reaction chamber (without sample transfer), avoid surface contamination caused by sample exposure to air, improve process stability.
[0092] In the first embodiment, the target semiconductor structure is a contact hole; combined with Figures 2 to 11 , the specific preparation process of the contact hole is described in detail.
[0093] Referring to Figure 2 , on the basis of the device bottom structure 1, a stop layer 2, a target layer 3 and a mask layer 4 are sequentially formed, wherein the material of the stop layer 2 is , the material of the target layer 3 is , and the material of the mask layer 4 is The thickness of the upper layer and the lower layer can be greater than 5nm, and the thickness of the middle layer can be determined according to the etching depth process requirement of the contact hole (contact), and the EUV / DUV / electron beam limit exposure is carried out. In this embodiment, it is assumed that the CD after exposure is 45nm, and the thickness of the middle layer is 300nm.
[0094] After forming the stack, a photoresist pattern (PR) 5 is formed on the mask layer based on photolithography technology.
[0095] Referring to Figure 3 , etching the target layer with PR pattern 5 as mask , then etching the target layer with PR and remaining mask layer as mask .
[0096] Referring to Figure 4 , removing PR pattern 5.
[0097] Referring to Figure 5 , using remote plasma etching machine, vacuumizing the reaction cavity before etching, so that the vacuum degree , then passing in carrier gas to purge for 30-60 seconds; passing in gas , carrier gas and , flow ratio , maintaining reaction pressure , radio frequency power 1000-1200W, isotropically etching the initial structured pattern sidewall of the target layer, and the etching rate ratio of amorphous silicon to SiO2≥10:1; using in-situ optical ellipsometer to monitor CD size in real time, when reaching 20nm, stopping etching and passing in gas to purge.
[0098] Referring to Figure 6 , performing HDP process, filling .
[0099] Referring to Figure 7 , using CMP process to flatten to the upper interface of the target layer.
[0100] Referring to Figure 8 , using wet / dry method to remove target layer.
[0101] Referring to Figure 9 , using wet etching to open the stop layer of the bottom layer .
[0102] Referring to Figure 10 , using ALD process to fill metal 6, and using CMP process to flatten.
[0103] Referring to Figure 11 , performing metal imaging on the filled metal, to realize the lead-out of the contact hole.
[0104] Although the application is described herein with reference to the embodiments, those skilled in the art will understand that various modifications and changes in form and detail can be made thereto without departing from the spirit and scope of the application. Accordingly, the description and drawings are to be regarded as illustrative in nature and are not intended as limiting the scope of the application as defined by the appended claims. The word "comprising" does not exclude other elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. A single processor or other unit can fulfil the functions of several items recited in a claim. A combination of claims does not require that each element recited in the combination be present in every embodiment.
[0105] Although the application is described herein with reference to the specific features thereof and embodiments thereof, it is evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive. It is to be understood that the application is not limited to the details of the above-described embodiments but includes all modifications within the scope and spirit of the application as expressed by the appended claims.
Claims
1. A method of producing a semiconductor structure for advanced nodes, characterized in that, The method comprises the following steps: forming a stack on a bottom structure; the stack comprises a stop layer, a target layer and a mask layer from bottom to top; forming an initial pattern on the surface of the mask layer, and transferring the initial pattern to the mask layer and the target layer to form an initial structured pattern of the target layer with the same size as the initial pattern on the target layer; using a remote plasma etching machine to isotropically etch the initial structured pattern of the target layer to reduce the initial structured pattern of the target layer to a target size pattern; wherein the target layer has a preset etching rate ratio to the stop layer, and the preset etching rate ratio is greater than or equal to a preset ratio; forming a target semiconductor structure based on the target layer with the target size pattern formed by etching.
2. The method of claim 1, wherein the method further comprises: The remote plasma etching machine at least comprises a reaction chamber; using a remote plasma etching machine to isotropically etch the initial structured pattern of the target layer to reduce the initial structured pattern of the target layer to a target size pattern, comprising: The main gas and the carrier gas are introduced into the reaction cavity, and the side wall of the initial structural pattern of the target layer is isotropically dry etched based on the ratio of the preset etching rate; wherein the main gas is one of 、 and ; the carrier gas is one or more of and . stopping etching when a preset time is reached; the preset time is the time to reach the target size pattern.
3. The method of claim 2, wherein the method further comprises: The remote plasma etching machine further comprises a remote plasma generating unit; the remote plasma generating unit is connected with the reaction chamber through a sealed gas channel; The remote plasma generating unit at least comprises an inductively coupled plasma etching chamber and two layers of charged ion filtering screens, and the two layers of charged ion filtering screens are fixedly arranged between the inductively coupled plasma etching chamber and the sealed gas channel.
4. The method of claim 1, wherein the method further comprises: The target semiconductor structure is a contact hole; forming a target semiconductor structure based on the target layer with the target size pattern formed by etching, comprising: for the target layer with the target size pattern formed by etching, taking the stop layer as a base, filling a gap between the target size patterns with a dielectric, and using a chemical mechanical polishing process to make the surface of the dielectric flush with the top of the initial structured pattern of the target layer; the material of the dielectric is the same as that of the stop layer; removing the target size pattern formed by etching the target layer; removing the local stop layer directly below the position of the target size pattern to form a contact hole opening; filling metal in the contact hole opening and polishing to form the contact hole.
5. The method of claim 4, wherein the method further comprises: filling the gap between the target size patterns with a dielectric, comprising: using an HDP process to deposit a dielectric on the entire area including the gap; wherein the deposition range covers the gap and the surface of the target size pattern.
6. The method of claim 4, wherein the method further comprises: filling the gap between the target size patterns with a dielectric, comprising: removing the mask layer remaining on the top of the target size pattern, and using an atomic layer deposition process to perform dielectric filling on the gap.
7. The method of claim 1, wherein the method further comprises: forming an initial pattern on the surface of the mask layer, comprising: based on a photolithography process, coating photoresist on the surface of the mask layer; exposing and developing the photoresist through a mask to remove the photoresist in the exposed area to form the initial pattern.
8. The method of claim 7, wherein the method further comprises: transferring the initial pattern to the mask layer and the target layer to form an initial structured pattern of the target layer with the same size as the initial pattern on the target layer, comprising: Taking the photoresist as a mask, a first etching gas is used to etch the mask layer based on a first preset plasma power, to form a mask pattern; The photoresist is reserved, a second etching gas is used to etch the target layer based on a second preset plasma power, and the mask pattern is used as an auxiliary mask to etch to a stop layer, to form an initial structured pattern of the target layer.
9. The method of claim 8, wherein the method further comprises: The first etching gas comprises an F-based gas; and the second etching gas comprises a Br-based gas.
10. A semiconductor structure, characterized by The semiconductor structure is prepared by using the preparation method for an advanced node-oriented semiconductor structure according to any one of claims 1-9.