Large-area silicon nano pattern structure and preparation method thereof

Abstract

The invention provides a large-area silicon nano pattern structure and a preparation method thereof, and the preparation method comprises the steps: firstly, sequentially forming a sacrificial layer and a photoresist layer on the surface of a substrate; secondly, patterning the photoresist layer to form a plurality of first microstructures which are arranged in an array; thirdly, the sacrificial layer is etched with the first microstructures as masks, and a plurality of second microstructures corresponding to the first microstructures one to one are formed on the sacrificial layer; thirdly, forming a metal layer on the surface of the substrate and the plurality of first microstructures; thirdly, synchronously removing the second microstructure, the first microstructure and a part of the metal layer on the first microstructure through a stripping process, and forming a plurality of third microstructures arranged in an array on the residual metal layer; thirdly, performing metal-assisted chemical etching on the substrate by taking the third microstructure as a template, so that the third microstructure is completely embedded into the substrate; and finally, removing the third microstructure embedded in the substrate, and forming a large-area silicon nano pattern structure on the surface of the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of micro-nano processing manufacturing, and particularly relates to a large-area silicon nano pattern structure and a preparation method thereof. BACKGROUND

[0002] Silicon nanomaterial is one of the research hotspots and core application materials in the field of semiconductors. As a typical one-dimensional silicon nanomaterial, silicon nanorod / silicon nanowire has high specific surface area, excellent light absorption performance and good photoconductivity, and exhibits outstanding application value and development potential in the field of micro-nano optoelectronic devices (such as photodetectors and solar cells), and has become a key research direction in this field.

[0003] At present, the preparation methods of silicon nanorod / silicon nanowire mainly include laser ablation, chemical vapor deposition (CVD) and chemical etching. Among them, the laser ablation method melts and evaporates the silicon source quickly by high-energy laser ablation, and forms the target structure along a specific direction after cooling and crystallization; the chemical vapor deposition method generates solid silicon deposits by chemical reaction of gaseous precursors at the reaction interface and grows into a structure. However, the above two methods generally have problems such as high cost of instrument and equipment, harsh process conditions (such as temperature and pressure), poor controllability of product structure, and are difficult to meet the demand of low-cost large-scale preparation. The chemical etching method is one of the mainstream technical paths due to its simple operation and low cost. The most commonly used method in this method is a mixed solution system of hydrofluoric acid and silver nitrate: silver ions are reduced to silver single element on the surface of the silicon wafer, which is used as an etching catalyst to selectively etch the surrounding silicon matrix, thereby forming silicon nanorod / silicon nanowire. However, the silver single element is randomly distributed on the surface of the silicon wafer, which leads to poor uniformity of the prepared silicon nanostructure, low controllability of the size and array arrangement, and is difficult to meet the requirements of high-precision structure for devices.

[0004] In order to solve the above problems, Chinese patent CN114132890A discloses a silicon nanowire array preparation method based on micro-nano mesh anodic aluminum oxide (AAO) template combined with chemical wet etching. However, the anodic aluminum oxide template used in this method has obvious defects: on the one hand, the template is prone to cracks or even peeling due to deformation, thermal expansion and contraction of the substrate, and such defects are more prominent in high-temperature environment; on the other hand, the preparation cost of the anodic aluminum oxide template is high, and the pattern morphology of the final silicon nanowire array is completely determined by the template, which cannot be flexibly adjusted according to actual needs, and limits its application in diversified devices.

[0005] Therefore, there is an urgent need for a large-area silicon nano pattern structure and a preparation method thereof to solve the above technical problems. SUMMARY

[0006] The present application aims to solve the technical problems of high instrument cost, harsh process conditions, poor structure uniformity, poor structure controllability and flexible pattern morphology control of the existing large-area silicon nano pattern structure.

[0007] To solve the above technical problems, the present application first provides a preparation method of a large-area silicon nano pattern structure, comprising: S10, sequentially forming a sacrificial layer and a photoresist layer on the surface of a substrate; S20, performing a patterning treatment on the photoresist layer to form a plurality of first microstructures arranged in an array; S30, etching the sacrificial layer with the first microstructures as a mask to form a plurality of second microstructures corresponding to the first microstructures one by one; the orthographic projection of the second microstructures on the substrate coincides with the orthographic projection of the first microstructures on the substrate; S40, forming a metal layer on the surface of the substrate and the plurality of first microstructures; S50, synchronously removing the second microstructures, the first microstructures and part of the metal layer located on the first microstructures by a stripping process, and the remaining metal layer forms a plurality of third microstructures arranged in an array; S60, performing metal-assisted chemical etching on the substrate with the third microstructures as a template to embed the third microstructures completely inside the substrate; S70, removing the third microstructures embedded inside the substrate to form a large-area silicon nano pattern structure on the surface of the substrate.

[0008] Preferably, the S10 step specifically comprises: S101, sequentially performing cleaning and drying treatment on the substrate to obtain a pretreated substrate; S102, sequentially coating the sacrificial layer and the photoresist layer on the surface of the pretreated substrate.

[0009] Preferably, the cleaning treatment of the S101 step comprises: first performing ultrasonic treatment on the substrate, then soaking the substrate in a Piranha solution at 250℃, and finally blowing the substrate dry with nitrogen.

[0010] Preferably, in the S10 step: the substrate is an n-type <100> single crystal silicon wafer, the sacrificial layer is an LOR 1A type photoresist, and the photoresist layer is an SU-8 2000.5 type negative photoresist.

[0011] Preferably, the patterning treatment of the S20 step specifically comprises: exposing the photoresist layer to a coherent light source, and then sequentially performing baking and developing treatment; Wherein, the exposure wavelength is 266nm, the full power of the coherent light source is 100-120mW, and the exposure time is 8-12s.

[0012] Preferably, in the step S40, an electron beam evaporation process is adopted to deposit a metal layer on the substrate surface and the plurality of first microstructures, and the metal layer comprises a first metal layer and a second metal layer which are arranged in a bottom-to-top manner.

[0013] Preferably, the first metal layer comprises titanium and has a thickness of 2-3 nm, and the second metal layer comprises gold and has a thickness of 15-25 nm.

[0014] Preferably, the stripping process in the step S50 comprises: soaking and ultrasonic treating the sacrificial layer with a stripping liquid to dissolve and strip the sacrificial layer.

[0015] Preferably, in the metal-assisted chemical etching treatment in the step S60, the etching method is wet etching, the etching liquid is a mixed solution of 4.6 M hydrofluoric acid and 0.4 M hydrogen peroxide, the etching catalyst is the third microstructure, and the etching time is 5 s-3 min.

[0016] Correspondingly, the application also provides a large-area silicon nano pattern structure prepared by the preparation method of any one of the above large-area silicon nano pattern structures. The large-area silicon nano pattern structure is a silicon nanorod or a silicon nanowire, and the processing area size of the large-area silicon nano pattern structure reaches a centimeter level.

[0017] The application has the following beneficial effects: Different from the prior art, the application provides a large-area silicon nano pattern structure and a preparation method thereof. The preparation method comprises the following steps: firstly, forming a sacrificial layer and a photoresist layer on a substrate surface in sequence; secondly, performing a patterning treatment on the photoresist layer to form a plurality of first microstructures arranged in an array; thirdly, etching the sacrificial layer to form a plurality of second microstructures corresponding to the first microstructures, with the first microstructures as a mask; fourthly, forming a metal layer on the substrate surface and the plurality of first microstructures; fifthly, simultaneously removing the second microstructures, the first microstructures and part of the metal layer located on the first microstructures by a stripping process, and forming a plurality of third microstructures arranged in an array with the remaining metal layer; sixthly, performing a metal-assisted chemical etching on the substrate with the third microstructures as a template, so that the third microstructures are completely embedded in the substrate; and finally, removing the third microstructures embedded in the substrate to form a large-area silicon nano pattern structure on the substrate surface. The preparation method of the application precisely defines the microstructure array through photoresist patterning, forms a controllable metal template by combining the sacrificial layer etching and stripping process, and realizes the precise forming of the silicon nano pattern through the metal-assisted chemical etching. The preparation method of the application not only solves the problems of poor structure uniformity and low controllability in the prior art, but also avoids the defects of easy damage of the template, high cost and difficulty in flexible regulation of the pattern. Moreover, the preparation method of the application is compatible with mature micro-nano processing technology, is suitable for large-area preparation, and can efficiently obtain a silicon nano pattern structure with high precision and high uniformity. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A preparation method flow chart of the large-area silicon nano pattern structure provided by the embodiment of the present application is provided. Figures 2A to 2G A structure schematic diagram corresponding to each step in the preparation method of the large-area silicon nano pattern structure provided by the embodiment of the present application is provided. Figure 3 A scanning electron microscope image of the gold film on the surface of the substrate after the sacrificial layer is peeled off in the preparation method of the large-area silicon nano pattern structure provided by the embodiment 1 is provided. Figures 4 to 6 A scanning electron microscope overhead view of the large-area silicon nano pattern structure prepared by using different metal assisted chemical etching processing time in the embodiment 1 is provided. Figures 7 to 8 A scanning electron microscope cross-sectional view of the large-area silicon nano pattern structure prepared by using different metal assisted chemical etching processing time in the embodiment 1 is provided. In the description of the drawings: 100-large-area silicon nano pattern structure; 10-substrate; 101-large-area silicon nano pattern structure; 20-sacrificial layer; 201-second microstructure; 30-photoresist layer; 301-first microstructure; 40-metal layer; 401-third microstructure. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0020] In order to overcome the defects and deficiencies of the prior art, the purpose of the present application is to provide a preparation method of large-area silicon nano column / line. The method is to form a sacrificial layer and a photoresist film on the surface of a substrate in sequence, to dry etch the sacrificial layer with the exposed photoresist film as a mask, to form a patterned gold film by depositing a gold film and peeling off and removing the sacrificial layer, to perform metal assisted chemical etching, and to remove the gold film, so as to finally obtain a large-area silicon nano column / line structure. By flexibly adjusting the exposed photoresist pattern, the flexible regulation and control of the silicon nano column / line pattern in the horizontal direction can be realized.

[0021] In order to achieve the above technical purpose, the present application adopts the following technical solutions: In the first aspect, please refer to Figure 1 、 Figures 2A to 2G , Figure 1 A preparation method flow chart of the large-area silicon nano pattern structure 101 provided by the embodiment of the present application is provided. Figures 2A to 2GThe preparation method of the large-area silicon nano pattern structure 101 provided in the embodiment of the present application comprises the following steps: S10, sequentially forming a sacrificial layer 20 and a photoresist layer 30 on the surface of the substrate 10.

[0022] Specifically, the S10 step further comprises the following steps. S101, sequentially performing cleaning and drying treatment on the substrate 10 to obtain a pretreated substrate 10. S102, sequentially coating the sacrificial layer 20 and the photoresist layer 30 on the surface of the pretreated substrate 10 by using a spin coating method, as shown in FIG. 2. Figure 2A

[0023] Specifically, the cleaning treatment in the S101 step comprises the following steps: first, rinsing the substrate 10 with water; then, performing ultrasonic treatment on the substrate 10 with an acetone and ethanol solution; then, immersing the substrate 10 in a 250℃ "piranha" solution; finally, drying the substrate 10 with nitrogen and using a hot plate to dry the substrate 10. The substrate 10 is an n-type <100> single crystal silicon wafer, the sacrificial layer 20 is an LOR 1A type photoresist, the photoresist layer 30 is an SU-8 2000.5 type negative photoresist, the polymer molecules of the photoresist layer 30 are epoxy resins, the acid generator is diphenyl sulfonium hexafluoroantimonate, and the "piranha" solution is a mixture of a 30% hydrogen peroxide solution and a 98% sulfuric acid solution with a volume ratio of 1:3.

[0024] Further, the S10 step can completely remove the pollutants on the surface of the substrate 10 by using a multi-step cooperative cleaning process (water rinsing, acetone / ethanol ultrasonic oil removal, high-temperature "piranha" solution for deep removal of organic residues and oxidation of surface impurities, nitrogen blowing and hot plate drying to ensure drying), while optimizing the surface energy of the substrate 10, significantly improving the adhesion and coating uniformity of the subsequent sacrificial layer 20 and photoresist layer 30; the n-type <100> single crystal silicon wafer is selected as the substrate 10, which is suitable for the conventional semiconductor processing technology; the LOR 1A type photoresist is used as the sacrificial layer 20, which forms a matching interlayer structure with the SU-8 2000.5 type negative photoresist, providing good material compatibility for subsequent patterning, etching and stripping processes, and improving the process stability and repeatability as a whole, laying a foundation for high-precision microstructure forming.

[0025] S20, performing patterning treatment on the photoresist layer 30 to form a plurality of first microstructures 301 arranged in an array.

[0026] Specifically, the S20 step further comprises the following steps. The photoresist layer 30 is exposed by using a coherent light source, and then baking and developing treatment are sequentially performed to form a plurality of first microstructures 301 arranged in an array, as shown in FIG. 3. Figure 2B ​As shown; wherein the exposure wavelength is 266 nm, the full power of the coherent light source is 100-120 mW (preferably 110 mW), and the exposure time is 8-12 s (preferably 10 s).

[0027] Further, the S20 step uses a coherent light source (high coherence, directivity) combined with a 266 nm deep ultraviolet exposure wavelength, which takes advantage of the weak diffraction effect of short-wavelength light to significantly improve the pattern resolution, facilitating the formation of fine micro-nano scale first microstructures 301; by optimizing the exposure parameters, both sufficient photosensitive crosslinking of the SU-8 negative photoresist and avoidance of pattern edge blurring or deformation caused by overexposure can be achieved, ensuring uniformity and stability of exposure; the synergistic effect of subsequent baking and development processing can accurately convert the latent image formed by exposure into a physical structure, ultimately obtaining a first microstructure 301 with controllable size, regular array arrangement, and clear edge, providing a high-precision template for subsequent etching of the sacrificial layer 20, ensuring the accuracy of the entire pattern transfer chain and improving the overall controllability and repeatability of the process.

[0028] S30, etching the sacrificial layer 20 using the first microstructure 301 as a mask to form a plurality of second microstructures 302 corresponding to the first microstructure 301; the orthographic projection of the second microstructure 302 on the substrate 10 coincides with the orthographic projection of the first microstructure 301 on the substrate 10, as shown. Figure 2C

[0029] Specifically, in the S30 step: dry etching the sacrificial layer 20 using the first microstructure 301 as a mask; using the characteristics of strong anisotropy, high etching precision, and good pattern transfer fidelity of dry etching, the pattern of the first microstructure 301 can be accurately transferred to the sacrificial layer 20, ensuring that the second microstructure 302 formed is highly consistent with the first microstructure 301 in size, shape, and array arrangement.

[0030] Specifically, the design of "the orthographic projection of the second microstructure 302 on the substrate 10 coincides with the orthographic projection of the first microstructure 301 on the substrate 10" further ensures the accurate correspondence of the spatial positions of the two, avoiding pattern shift or deformation. This accurate pattern transfer provides a reliable template for the selective retention of the metal layer 40 in the subsequent peeling process, ensuring the array regularity and size controllability of the subsequent third microstructure 401 from the source, significantly improving the pattern transfer accuracy and structural consistency of the entire preparation process.

[0031] S40, forming a metal layer 40 on the surface of the substrate 10 and the plurality of first microstructures 301.

[0032] Specifically, the S40 step further includes: using an electron beam evaporation process to deposit a metal layer 40 on the surface of the substrate 10 and the plurality of first microstructures 301, as shown in​Figure 2D As shown in FIG. 4B, the metal layer 40 includes a first metal layer (as a primer layer) and a second metal layer stacked from bottom to top, wherein the first metal layer includes titanium and has a thickness of 2-3 nm, and the second metal layer includes gold and has a thickness of 15-25 nm.

[0033] Further, the S40 step ensures uniform and firm coverage of the metal layer 40 on the substrate 10 and the first microstructure 301 by the electron beam evaporation process. The 2-3 nm titanium primer layer enhances the adhesion between the metal and the substrate. The 15-25 nm gold thin film layer ensures the subsequent etching efficiency due to its excellent stability and catalytic activity. The reasonable thickness design avoids material waste and reserves the structure profile for precise peeling. The overall high-quality metal layer 40 provides a foundation for forming regular third microstructures 401, ensuring the stability and reliability of subsequent processes.

[0034] In S50, the second microstructure 302, the first microstructure 301, and part of the metal layer 40 on the first microstructure 301 are removed by a peeling process, and the remaining metal layer 40 forms a plurality of third microstructures 401 arranged in an array.

[0035] Specifically, the S50 step further includes: The sacrificial layer 20 is soaked and ultrasonically treated with a peeling solution (such as an organic solvent like acetone) to dissolve and peel off the sacrificial layer 20 (the second microstructure 302), thereby indirectly removing the first microstructure 301 on the sacrificial layer 20 and part of the metal layer 40 on the first microstructure 301, and the remaining metal layer 40 forms a plurality of third microstructures 401 arranged in an array, as shown in FIG. 4C. Figure 2E

[0036] Further, the S50 step uses acetone and other mild organic solvents as the peeling solution, which does not damage the substrate 10 and the target metal layer 40 on the surface of the substrate 10, but can selectively dissolve the sacrificial layer 20 (the second microstructure 302). The process is compatible with the material selection. Through the synergistic treatment of soaking and ultrasonics, soaking can make the peeling solution fully penetrate and dissolve the sacrificial layer 20, and ultrasonics can accelerate the peeling process to ensure that the sacrificial layer 20, the first microstructure 301, and the metal layer 40 above are efficiently and completely removed, avoiding the influence of residual impurities on subsequent processes. This method of "dissolving the sacrificial layer 20 to indirectly remove the upper structure" can accurately preserve the metal layer 40 on the surface of the substrate 10, ultimately forming third microstructures 401 arranged in an array, with clear edges and controllable sizes. This provides a high-quality catalytic template for subsequent metal-assisted chemical etching. The acetone and other peeling solutions are low in cost and easy to handle, making the process economical and operable, and ensuring the precision and stability of the overall preparation process.

[0037] ​S60, metal-assisted chemical etching is performed on the substrate 10 with the third microstructure 401 as a template, so that the third microstructure 401 is completely embedded in the substrate 10, as shown in Figure 2F

[0038] Specifically, in the metal-assisted chemical etching process of S60, the etching method is wet etching, the etching solution is a mixed solution of 4.6M hydrofluoric acid and 0.4M hydrogen peroxide, and the etching catalyst is the third microstructure 401. The third microstructure 401 is stable in chemical properties and is not consumed, which can ensure that the etching is accurately performed along the patterning area at all times.

[0039] Further, the specific etching process of the above-mentioned metal-assisted chemical etching is as follows: Catalytic oxidation stage: the third microstructure 401 acts as a catalyst, and its surface can accelerate the reduction reaction of hydrogen peroxide - hydrogen peroxide obtains electrons on the metal surface and decomposes to generate strong oxidizing species such as hydroxyl, which oxidizes the silicon substrate 10 (Si) directly below and around the third microstructure 401 into silicon dioxide; Dissolution etching stage: the hydrofluoric acid in the etching solution will quickly react with the generated silicon dioxide to generate water-soluble fluorosilicic acid, so that the oxidized silicon dioxide is continuously dissolved, and a recess is formed on the surface of the silicon substrate 10; Embedding process: as the oxidation-dissolution reaction continues, the silicon below the third microstructure 401 is gradually etched, and the third microstructure 401 gradually sinks as the etching depth increases, and finally completely embeds in the silicon substrate 10, while forming a preliminary silicon nano pattern profile on the surface of the substrate 10 corresponding to the array of the third microstructure 401.

[0040] Further, the arrayed third microstructure 401 is used as a precise catalytic template in S60, so that the metal-assisted chemical etching only occurs locally under the metal, effectively avoiding the problem of uneven structure caused by random distribution of catalysts in traditional etching, and ensuring high precision and high uniformity of the silicon nano pattern; the optimized ratio of 4.6M hydrofluoric acid and 0.4M hydrogen peroxide can accurately control the oxidation-dissolution rate, ensure that the third microstructure 401 is completely embedded in the substrate 10, and avoid excessive or insufficient etching; the wet etching operation is simple and the equipment cost is low, without harsh process conditions, which is suitable for large-area processing requirements, and the embedded third microstructure 401 provides a clear template for subsequent removal of the metal catalyst and formation of complete silicon nano structures, ensuring the continuity and reliability of the entire preparation process.

[0041] S70, the third microstructure 401 embedded in the substrate 10 is removed, and a large-area silicon nano pattern structure 101 is formed on the surface of the substrate 10.

[0042] Specifically, S70 further includes: ​The third microstructure 401 embedded inside the substrate 10 is dissolved by aqua regia to form a large-area silicon nano pattern structure 101 on the surface of the substrate 10, as shown in Figure 2G

[0043] Correspondingly, the application further provides a large-area silicon nano pattern structure 101 prepared by the preparation method of the large-area silicon nano pattern structure 101 according to any one of the above. The large-area silicon nano pattern structure 101 is a silicon nanorod or a silicon nanowire, and the processing area size of the large-area silicon nano pattern structure 101 reaches centimeters.

[0044] Specifically, the structure type of the large-area silicon nano pattern structure 101 is a silicon nanorod or a silicon nanowire, both of which are typical one-dimensional silicon nano materials and naturally have high specific surface area, excellent light absorption performance and good photoconductivity, can accurately match the performance requirements of core functional structures of micro-nano optoelectronic devices (such as photodetectors and solar cells), and lay a foundation for efficient operation of the devices; secondly, the processing area size reaches centimeters, which breaks through the limitation that some existing preparation methods (such as an anodic aluminum oxide template method) are difficult to realize large-area processing, can meet the demand of large-scale device production for "large-area structure", and improves the industrial application potential; thirdly, relying on the foregoing high-precision preparation method, the structure inherits the characteristics of "array arrangement is regular, size is controllable, and uniformity is high", avoids the defects of random distribution of structures in traditional chemical etching method and uncontrolled morphology in template method, can adapt to the strict requirements of high-precision devices for structure consistency, and at the same time, the structure preparation process is compatible with mature micro-nano processing technology, has strong repeatability, and further reduces the production difficulty and cost in actual application.

[0045] The application discloses a preparation method of a large-area silicon nano pattern structure 101, and relates to the field of nano devices and micro-nano manufacturing and processing.The preparation method comprises the following steps: coating a sacrifice layer 20 and a photoresist layer 30 on the surface of a silicon wafer substrate 10 which has been cleaned and dried, patterning the photoresist layer 30 after exposure, and etching the sacrifice layer 20 by taking the patterned photoresist layer 30 as a mask; then depositing a gold film and stripping the sacrifice layer 20 to pattern the gold film; then etching the substrate 10 by taking the gold film as an etching catalyst; and finally removing the gold film to obtain the large-area silicon nano pattern structure 101. The method can be used for preparing silicon nanorods / lines in a large area and in a large quantity, and the length-diameter ratio of the structure is controllable. The prepared large-area silicon nanorod / line structure is expected to be used in micro-nano electronic devices and has a good prospect.

[0046] The technical solutions of the application will be further described in combination with specific embodiments.

[0047] Embodiment 1 This embodiment 1 provides a large-area silicon nano-pattern structure 101 and a method for preparing the same. The large-area silicon nano-pattern structure 101 is a silicon nano-pillar / line, and the specific preparation method is as follows: Step one, clean the substrate 10 and dry it: first, rinse the substrate 10 (such as an n-type <100> single crystal silicon wafer) with water, and then ultrasonically treat it in acetone and ethanol solutions, respectively. Subsequently, prepare an "piranha" solution by mixing 30% hydrogen peroxide and 98% concentrated sulfuric acid at a volume ratio of 1:3, and immerse the substrate 10 at 250°C. Then rinse and dry the substrate 10 with ultra-pure water and nitrogen. Then, dry the substrate 10 to remove residual water stains.

[0048] Step two, coat the sacrificial layer 20 and the photoresist film: as shown in Figure 2A , use a spin coater to spin coat the sacrificial layer 20 (such as LOR1A) and the photoresist layer 30 (such as SU-8 2000.5) on the surface of the substrate 10 in turn. Then, use a hot plate to bake the substrate 10 to volatilize the solvents in the sacrificial layer 20 and the photoresist layer 30.

[0049] Step three, exposure: use an exposure system to expose the substrate 10 to light, and pattern the photoresist layer 30. Then, use a hot plate to bake the substrate 10 to induce a cascade reaction in the photoresist layer 30. Then, develop the substrate 10 with a developing solution to obtain a photoetching pattern (first microstructure 301) on the surface of the substrate 10, as shown in Figure 2B . Finally, rinse and dry the substrate 10 with ultra-pure water and nitrogen.

[0050] Step four, dry etching of the sacrificial layer 20: as shown in Figure 2C , use the patterned photoresist layer 30 as a mask to dry etch the sacrificial layer 20. The etched sacrificial layer 20 has the same pattern as the photoresist layer 30.

[0051] Step five, deposition of a gold film: use electron beam evaporation to deposit a 20 nm thick gold film on the surface of the substrate 10. Before depositing the gold film, a very thin (such as 3 nm) titanium adhesion layer is first deposited. The gold film is mainly deposited on the surface of the photoresist film layer and the surface layer of the substrate 10 exposed after etching, as shown in Figure 2D .

[0052] Step six, stripping of the sacrificial layer 20: soak and ultrasonically treat the substrate 10 with an organic solvent such as acetone to dissolve and strip the sacrificial layer 20 above the substrate 10. The photoresist layer 30 and the gold film attached to the sacrificial layer 20 also collapse. Only the gold film deposited on the surface layer of the substrate 10 remains, as shown in Figure 2E . The morphology of the remaining gold film is exactly complementary to that of the first microstructure 301 used as a mask in Figure 2B , Figure 3A scanning electron microscope image of the gold thin film layer after the sacrificial layer 20 is peeled off is shown.

[0053] Step seven, metal-assisted chemical etching: a mixed solution of 4.6M hydrofluoric acid and 0.4M hydrogen peroxide is used as the etching solution to etch the gold thin film on the surface of the substrate 10 after the sacrificial layer 20 is peeled off as a template, and the substrate 10 is subjected to metal-assisted chemical etching, as shown in Figure 2F .

[0054] Step eight, removing the gold thin film: aqua regia (a mixture of concentrated nitric acid and concentrated hydrochloric acid in a volume ratio of 1:3) is used to dissolve and remove the gold thin film etched into the substrate 10, obtaining a silicon nanocolumn / line array pattern.

[0055] Please refer to Figures 4 to 8 , Figures 4 to 6 is a scanning electron microscope top view of a large-area silicon nano pattern structure 101 prepared by different metal-assisted chemical etching processing times in this embodiment 1. Figures 7 to 8 is a scanning electron microscope cross-sectional view of a large-area silicon nano pattern structure 101 prepared by different metal-assisted chemical etching processing times in this embodiment 1. Figure 7 The metal-assisted chemical etching processing time of Figure 8 is 2min.

[0056] As can be seen from Figures 4 to 8 : with the extension of the metal-assisted chemical etching processing time, the aspect ratio of the silicon nanocolumn / line gradually increases; when the etching time is too long, the aspect ratio of the silicon nanocolumn / line exceeds the critical value, and the finally prepared large-area silicon nano pattern structure 101 will show obvious tilting or even collapse.

[0057] Compared with the prior art, the present application has the following significant advantages: (1) The present application directly prepares a gold thin film etching template on the surface of a silicon substrate 10 through a photoresist patterning and sacrificial layer 20 peeling process, and then obtains a large-area silicon nano pattern structure 101 by combining metal-assisted chemical wet etching. This design directly combines the etching template with the silicon substrate 10, fundamentally overcoming the defects of "poor combination of the template with the substrate 10 and random drifting of the template on the surface of the substrate 10" in the traditional template method, ensuring the stability of the template position and the accuracy of pattern transfer.

[0058] (2) Compared with the silver single catalyst used in traditional chemical wet etching, the gold thin film used in the present application has better chemical stability: on the one hand, it can avoid the problem of uneven etching caused by the random distribution of silver single on the surface of the substrate 10, and on the other hand, it can maintain the stability of the catalytic activity for a long time, significantly improving the array uniformity and size consistency of the large-area silicon nano pattern structure 101.

[0059] (3) The present application can realize the preparation of a centimeter-level processing area silicon nano-pattern, and the structure is highly ordered arrangement, which breaks through the limitation of traditional methods (such as silver catalytic etching, anodic aluminum oxide template method) that it is difficult to balance "large area" and "high order degree", and meets the mass production demand of core structure of large-scale micro-nano optoelectronic device production.

[0060] (4) The present application can obtain different morphology of photoresist pattern by adjusting exposure parameters (such as exposure pattern, exposure time, etc.), and then flexibly control the array arrangement, size and spacing of large-area silicon nano-pattern structure 101 in the horizontal direction. Compared with the traditional process which depends on fixed template (such as anodic aluminum oxide template), this control path does not need to replace the template, and the operation is more simple, flexible and efficient, which can quickly adapt to the structure design demand of diversified devices.

[0061] In summary, unlike the prior art, the present application provides a large-area silicon nano-pattern structure 101 and a preparation method thereof. The preparation method comprises the following steps: first, forming a sacrificial layer 20 and a photoresist layer 30 on the surface of a substrate 10 in sequence; second, performing patterned processing on the photoresist layer 30 to form a plurality of first microstructures 301 arranged in an array; third, etching the sacrificial layer 20 using the first microstructure 301 as a mask, so that the sacrificial layer 20 forms a plurality of second microstructures 302 corresponding to the first microstructure 301; fourth, forming a metal layer 40 on the surface of the substrate 10 and the plurality of first microstructures 301; fifth, synchronously removing the second microstructure 302, the first microstructure 301 and part of the metal layer 40 located on the first microstructure 301 by a stripping process, and the remaining metal layer 40 forms a plurality of third microstructures 401 arranged in an array; sixth, performing metal-assisted chemical etching on the substrate 10 using the third microstructure 401 as a template, so that the third microstructure 401 is completely embedded in the substrate 10; and finally, removing the third microstructure 401 embedded in the substrate 10 to form a large-area silicon nano-pattern structure 101 on the surface of the substrate 10. The preparation method of the present application precisely defines the microstructure array through photoresist patterning, forms a controllable metal template by combining the etching and stripping processes of the sacrificial layer 20, and then realizes the precise forming of the silicon nano-pattern through metal-assisted chemical etching. Not only does it solve the problems of poor structure uniformity and low controllability in existing methods, but it also avoids the defects of easily damaged template, high cost and difficult flexible control of pattern. Moreover, the process is compatible with mature micro-nano processing technology, suitable for large-area preparation, and can efficiently obtain a silicon nano-pattern structure with high precision and high uniformity.

[0062] It should be noted that the above embodiments all belong to the same inventive concept, and the description of each embodiment has its own emphasis. If not fully described in an individual embodiment, the description can be referred to in other embodiments.

[0063] The above embodiments only express the implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing large-area silicon nanopatterned structures, characterized in that, include: S10, a sacrificial layer and a photoresist layer are sequentially formed on the substrate surface; S20, the photoresist layer is patterned to form a plurality of first microstructures arranged in an array; S30, using the first microstructure as a mask, the sacrificial layer is etched to form a plurality of second microstructures that correspond one-to-one with the first microstructure; The orthographic projection of the second microstructure onto the substrate coincides with the orthographic projection of the first microstructure onto the substrate; S40, a metal layer is formed on the substrate surface and on the plurality of first microstructures; S50, the second microstructure, the first microstructure, and part of the metal layer located on the first microstructure are removed simultaneously by a stripping process, and the remaining metal layer forms a plurality of third microstructures arranged in an array. S60, using the third microstructure as a template, perform metal-assisted chemical etching on the substrate to completely embed the third microstructure into the substrate; S70, the third microstructure embedded inside the substrate is removed, and a large-area silicon nanopattern structure is formed on the surface of the substrate.

2. The method for preparing large-area silicon nanopatterned structures according to claim 1, characterized in that, The S10 step specifically includes: S101, the substrate is sequentially cleaned and dried to obtain a pretreated substrate; S102, the sacrificial layer and the photoresist layer are sequentially coated on the surface of the pretreated substrate.

3. The method for preparing large-area silicon nanopatterned structures according to claim 2, characterized in that, The cleaning process in step S101 includes: first, ultrasonically treating the substrate, then immersing the substrate in a "piranha" solution at 250°C, and finally drying the substrate with nitrogen gas.

4. The method for preparing large-area silicon nanopatterned structures according to claim 2, characterized in that, In step S10: the substrate is n-type. <100> The single-crystal silicon wafer has a sacrificial layer made of LOR 1A type photoresist and a photoresist layer made of SU-82000.5 type negative photoresist.

5. The method for preparing large-area silicon nanopatterned structures according to claim 1, characterized in that, The patterning process in step S20 specifically includes: exposing the photoresist layer with a coherent light source, followed by baking and development processes in sequence; The exposure wavelength is 266nm, the full power of the coherent light source is 100~120mW, and the exposure time is 8~12s.

6. The method for preparing large-area silicon nanopatterned structures according to claim 1, characterized in that, In step S40: the metal layer is deposited on the substrate surface and the plurality of first microstructures using an electron beam evaporation process, the metal layer comprising a first metal layer and a second metal layer stacked from bottom to top.

7. The method for preparing large-area silicon nanopatterned structures according to claim 6, characterized in that, The first metal layer comprises titanium and has a thickness of 2-3 nm; the second metal layer comprises gold and has a thickness of 15-25 nm.

8. The method for preparing large-area silicon nanopatterned structures according to claim 1, characterized in that, The stripping process in step S50 includes: soaking the sacrificial layer in a stripping solution and ultrasonically treating it to dissolve and strip the sacrificial layer.

9. The method for preparing large-area silicon nanopatterned structures according to claim 1, characterized in that, In the metal-assisted chemical etching process of step S60: the etching method is wet etching, the etching solution is a mixed solution of 4.6M hydrofluoric acid and 0.4M hydrogen peroxide, the etching catalyst is the third microstructure, and the etching time is 5s~3min.

10. A large-area silicon nanopattern structure, characterized in that, It is prepared by the method for preparing large-area silicon nanopatterned structures as described in any one of claims 1 to 9; The large-area silicon nanopattern structure is a silicon nanopillar or silicon nanowire, and the processing area size of the large-area silicon nanopattern structure reaches the centimeter level.

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