Clock configuration integration method and apparatus, electronic device, medium, and program product

Abstract

The application provides a clock configuration integration method and device, electronic equipment, medium and program product, and relates to the technical field of integrated circuits.The method comprises the following steps: obtaining a multi-level structured configuration file; constructing a global clock structured data model based on the multi-level structured configuration file; the global clock structured data model is used to represent the cross-level association relationship between clock entities; based on the global clock structured data model, integrating the relevant configuration data corresponding to each clock entity to obtain reorganized data corresponding to each clock entity; and performing format conversion on the reorganized data corresponding to all clock entities to obtain a standardized clock file.The application can improve the global consistency, accuracy, iteration efficiency and traceability of clock configuration.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a clock configuration integration method, apparatus, electronic device, medium, and program product. Background Technology

[0002] In SoC (System on Chip) chip design, a layered architecture consisting of a Tile layer, a Subsys layer, and a Chip layer is mostly adopted. Each layer needs to independently maintain its own clock configuration information.

[0003] Currently, the main approach relies on manual interpretation and aggregation of files from different sources, or the writing of temporary, targeted scripts, to generate configuration files for subsequent verification processes. However, manual aggregation has the following problems: (1) Cross-level manual or semi-automatic aggregation is prone to inconsistencies in configuration data due to information errors and omissions, resulting in poor chip design consistency and verification accuracy; (2) Any change in the design of the underlying modules requires a large amount of manpower to synchronize the modification of the upper-level configuration, resulting in low design iteration efficiency; (3) The configuration data is relatively scattered, and the traceability of any clock signal is weak. Therefore, how to improve the global consistency, accuracy, iteration efficiency, and traceability of clock configuration is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This invention provides a clock configuration integration method, apparatus, electronic device, medium, and program product to address the shortcomings of existing manual configuration methods, which suffer from low consistency, accuracy, iteration efficiency, and traceability.

[0005] This invention provides a clock configuration integration method, comprising the following steps.

[0006] Obtain multi-level structured configuration files;

[0007] A global clock structured data model is constructed based on a multi-level structured configuration file; the global clock structured data model is used to represent the cross-level association relationships between clock entities;

[0008] Based on the global clock structured data model, the relevant configuration data corresponding to each clock entity is integrated to obtain the recombined data corresponding to each clock entity;

[0009] The recombined data corresponding to all clock entities is converted into a standardized clock file.

[0010] According to the clock configuration integration method provided by the present invention, the construction of a global clock structured data model based on a multi-level structured configuration file includes:

[0011] Based on a multi-level structured configuration file, multiple clock entities are identified, including ports and clock sources;

[0012] Based on a multi-level structured configuration file, a hierarchical relationship tree and a directed connection graph between ports are constructed; the directed connection graph is used to represent the propagation path of the clock signal between ports; the hierarchical relationship tree is used to represent the hierarchical relationship between levels;

[0013] Based on the port attributes, clock associations, and clock sources in the multi-level structured configuration file, the corresponding ports are bound to attributes.

[0014] Based on the directed connection graph, the hierarchical relationship tree, and the ports after attribute binding, the global clock structured data model is constructed.

[0015] According to the clock configuration integration method provided by the present invention, the step of integrating the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain the recombined data corresponding to each clock entity includes:

[0016] Based on the aforementioned global clock structured data model, the master clock source point is anchored;

[0017] Starting from the master clock source point, retrieve the relevant configuration data corresponding to the master clock source point in the global clock structured data model;

[0018] Based on the multi-level structured configuration file and the directed connection graph, the master clock source and the related configuration data are integrated to obtain the recombined data corresponding to each clock entity.

[0019] According to the clock configuration integration method provided by the present invention, the step of anchoring the master clock source point based on the global clock structured data model includes:

[0020] Based on the global clock structured data model, the source point type of each clock source is determined;

[0021] When the source point type is a physical pin, the source point corresponding to the clock source is determined as the master clock source point;

[0022] When the source point type is a logical port, the clock source at the highest level in the hierarchical relationship tree is determined as the master clock source point.

[0023] According to the clock configuration integration method provided by the present invention, the integration of the master clock source and the related configuration data based on the multi-level structured configuration file and the directed connection graph to obtain recombined data corresponding to each clock entity includes:

[0024] Based on the multi-level structured configuration file, the clock attributes corresponding to the master clock source are determined, and the clock attributes corresponding to the master clock source are filled into the top-level configuration.

[0025] Traverse each port downstream of the master clock source point in the directed connection graph, determine the attributes corresponding to the port based on the multi-level structured configuration file, and fill the attributes corresponding to the port into the container corresponding to the child element; until all ports have been traversed, a hierarchical container is obtained.

[0026] Based on the mode parameters and process angle parameters of the master clock source point in different modes in the multi-level structured configuration file, a multi-mode scenario structure is generated.

[0027] The uncertainty parameters in the directed connection graph, the top-level configuration, the hierarchical container, and the multi-mode scenario structure are determined as the recombined data corresponding to each clock entity.

[0028] According to the clock configuration integration method provided by the present invention, the multi-level structured configuration file includes: chip design layer configuration file, subsystem layer configuration file and chip top-level design layer configuration file.

[0029] The present invention also provides a clock configuration integration device, comprising the following modules.

[0030] The acquisition module is used to acquire multi-level structured configuration files;

[0031] A building module is used to construct a global clock structured data model based on a multi-level structured configuration file; the global clock structured data model is used to represent the cross-level association relationships between clock entities;

[0032] An integration module is used to integrate the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain the recombined data corresponding to each clock entity.

[0033] The format conversion module is used to convert the recombined data corresponding to all clock entities into a standardized clock file.

[0034] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the clock configuration integration method as described above.

[0035] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the clock configuration integration method as described above.

[0036] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the clock configuration integration method as described above.

[0037] The clock configuration integration method, apparatus, electronic device, medium, and program products provided by this invention construct a global clock structured data model to represent the cross-level relationships between clock entities through multi-level structured configuration files. Based on this global clock structured data model, relevant configuration data corresponding to each clock entity is integrated to obtain recombined data for each clock entity. The recombined data is then format-converted to obtain a standardized clock file. In this invention, discrete cross-level structured configuration files are parsed and automatically integrated into a global clock structured data model. This global clock structured data model allows for tracing the complete path of any clock from its source to the user port, significantly improving clock traceability. The entire clock configuration process reduces manual intervention and script writing, avoiding SDC errors caused by manual data aggregation, and ensuring the accuracy and consistency of the global configuration data. Furthermore, during design changes, only targeted modifications to the structured configuration files at each level are needed to automatically update the global configuration based on the existing configuration structure, significantly improving design iteration efficiency. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0039] Figure 1 This is a flowchart illustrating the clock configuration integration method provided in an embodiment of the present invention.

[0040] Figure 2 This is a schematic diagram of the structure of the global clock structured data model provided in an embodiment of the present invention.

[0041] Figure 3 This is a schematic diagram of the structure of recombined data provided in an embodiment of the present invention.

[0042] Figure 4 This is a schematic diagram of the clock configuration integration device provided in an embodiment of the present invention.

[0043] Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0045] To address the issues of low consistency, accuracy, iteration efficiency, and traceability in existing manual configuration methods, this invention provides a clock configuration integration method. Figure 1 This is a flowchart illustrating the clock configuration integration method provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes steps 110 to 140.

[0046] Step 110: Obtain multi-level structured configuration files.

[0047] Specifically, for SoC (System-on-Chip) chips employing a layered design architecture including Tile, Subsys, and Chip layers, structured configuration files for each layer are collected uniformly, and each layer's structured configuration file follows predefined specifications. It should be noted that the Tile layer is a chip design module (Harden design); the Subsys (Subsystem) layer is a higher-level structure than the Tile layer and is a subsystem comprising multiple Tile instances; the Chip layer is a higher-level structure than the Subsys layer, belonging to the chip's top-level design layer, and includes at least one Subsys and / or at least one Tile.

[0048] It should be noted that this multi-level structured configuration file includes: chip design layer configuration file, subsystem layer configuration file, and chip top-level design layer configuration file. Among them:

[0049] (1) The chip design layer configuration file is the structured configuration file for the Tile layer. The chip design layer configuration file includes: a Clock Config worksheet and a Tile Interface worksheet. The Clock Config worksheet includes clock relationships, which include clock name, clock definition point, and clock attributes. The clock attributes include period, frequency, clock grouping, whether to divide, source point type, source point name, etc. The Tile Interface worksheet includes attributes for the Tile layer to interface with other layers, such as port name, direction, and associated clock.

[0050] (2) The configuration file for this subsystem layer is the structured configuration file for the Subsys layer. This subsystem layer configuration file includes: a Clock Config worksheet, a Tile Connection worksheet, a Tile Interface worksheet, and a Hierarchy worksheet. The Clock Config worksheet for the Subsys layer is similar to the Clock Config worksheet for the Tile layer, and the Tile Interface worksheet for the Subsys layer is similar to the Tile Interface worksheet for the Tile layer. The Tile Connection worksheet includes source block, source port, source associated clock, end block, end port, and end associated clock. The Hierarchy worksheet is used to record the hierarchical relationships of the Tile layers within this Subsys layer.

[0051] (3) The chip top-level design layer configuration file is the structured configuration file of the Chip layer. This chip top-level design layer configuration file includes: Default Config worksheet, Clock Config worksheet, Tile Connection worksheet, Hierarchy worksheet, and Mode_Config.yaml file. The Default Config worksheet is used to define global variables. The Mode_Config.yaml file is a YAML format file used to manage multi-mode clock parameters, including mode parameters and process corner parameters for different modes. The Clock Config worksheet of the Chip layer is similar to the Clock Config worksheet of the Tile layer, the Tile Connection worksheet of the Chip layer is similar to the Tile Connection worksheet of the Subsys layer, and the Hierarchy worksheet of the Chip layer is similar to the Hierarchy worksheet of the Subsys layer. The Default Config worksheet includes the attributes and attribute values ​​of the Chip layer.

[0052] Step 120: Based on the multi-level structured configuration file, construct a global clock structured data model; the global clock structured data model is used to represent the cross-level association between clock entities.

[0053] Specifically, after obtaining multi-level structured configuration files, discrete and independent multi-source data are integrated into an internally related global clock structured data model. In this global clock structured data model, the clock topology and related configuration attributes within the entire chip are completely represented in a structured form, that is, the relationship between clock entities at all levels.

[0054] Step 130: Based on the global clock structured data model, integrate the relevant configuration data corresponding to each clock entity to obtain the recombined data corresponding to each clock entity.

[0055] Specifically, after constructing a global clock structured data model, data integration is automatically performed using this model. That is, for any clock entity, along the clock propagation path, the relevant configuration data associated with that clock entity is integrated to obtain the recombined data of each clock entity.

[0056] Step 140: Convert the format of the recombined data corresponding to all clock entities to obtain a standardized clock file.

[0057] Specifically, after integrating and reorganizing all clock entities, all reorganized data is serialized and format-converted into a standardized clock file in XML (Extensible Markup Language) format, which can be directly used by downstream tools.

[0058] The clock configuration integration method provided in this invention constructs a global clock structured data model to represent the cross-level relationships between clock entities through multi-level structured configuration files. Based on this global clock structured data model, the relevant configuration data corresponding to each clock entity is integrated to obtain recombined data for each clock entity. The recombined data is then format-converted to obtain a standardized clock file. In this invention, discrete cross-level structured configuration files are parsed and automatically integrated into a global clock structured data model. This global clock structured data model allows for tracing the complete path of any clock from its source to the user port, significantly improving clock traceability. The entire clock configuration process reduces manual intervention and script writing, avoiding SDC (Synopsys Design Constraint) errors caused by manual data aggregation, ensuring the accuracy and consistency of the global configuration data. Furthermore, during design changes, only targeted modifications to the structured configuration files at each level are needed to automatically update the global configuration based on the existing configuration structure, significantly improving design iteration efficiency.

[0059] In one embodiment, constructing a global clock structured data model based on a multi-level structured configuration file includes:

[0060] Based on a multi-level structured configuration file, multiple clock entities are identified, including ports and clock sources;

[0061] Based on a multi-level structured configuration file, a hierarchical relationship tree and a directed connection graph between ports are constructed; the directed connection graph is used to represent the propagation path of the clock signal between ports; the hierarchical relationship tree is used to represent the hierarchical relationship between levels;

[0062] Based on the port attributes, clock associations, and clock sources in the multi-level structured configuration files, attribute binding is performed on the corresponding clock entities;

[0063] Based on the directed connection graph, the hierarchical relationship tree, and the clock entity with attribute binding, the global clock structured data model is constructed.

[0064] Specifically, after obtaining the multi-level structured configuration files, all levels of structured configuration files are parsed to identify all clock entities, including ports and clock sources. Next, the TileConnection worksheets of the Subsys and Chip layers are parsed to construct a directed connection graph between ports. This graph represents the complete propagation path of the clock signal between ports, with directed edges indicating the propagation direction. Simultaneously, the Hierarchy worksheets of the Subsys and Chip layers are parsed to construct a hierarchical tree describing the affiliation of module instances. Then, the clock entity names in the Tile Interface worksheets of the Tile and Subsys layers are traversed. The attributes corresponding to each clock entity name are queried in the Clock Config worksheets of all layers. These attributes may include port attributes, clock associations, clock source names, etc. These attributes are used as semantic tags and bound to the corresponding clock entities. Finally, based on the Tile layer to which each clock entity belongs, the directed connection graph and the hierarchical tree are connected to obtain the global clock structured data model. The global clock structured data model is a composite data structure, including parameters related to all clock entities, signal propagation paths of each clock entity, and hierarchical relationships across levels. These parameters include frequency, whether frequency division is used, clock creation point, clock grouping, etc.

[0065] For example, Figure 2 This is a schematic diagram of the global clock structured data model provided in an embodiment of the present invention, as shown below. Figure 2As shown, in the hierarchical relationship tree of this global clock structured data model, the Chip layer includes the Sys (short for Subsys) layer, which in turn includes the Tile_A and Tile_B layers. In the directed connection graph, the clock signal sequentially passes through ports Port_1 and Port_2 in the Tile_A layer and Port_3 in the Tile_B layer. The associated clock for these three ports is CLK_A, and the direction corresponding to Port_1 is in, meaning the clock signal propagates from Port_1 to Port_2. Port_2 is of type output, and Port_3 is of type input. After passing through the Tile_A layer and the three ports, the clock signal propagates to the Tile_B layer.

[0066] In this embodiment, configuration attributes, design hierarchy relationships, and connection relationships of different dimensions are automatically deconstructed from multi-source structured configuration files, enabling electronic devices to understand the generation process and propagation path of clock signals across all levels, avoiding information errors caused by manual intervention, and ensuring the consistency and accuracy of subsequent data integration.

[0067] In one embodiment, the step of integrating the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain the recombined data corresponding to each clock entity includes:

[0068] Based on the aforementioned global clock structured data model, the master clock source point is anchored;

[0069] Starting from the master clock source point, retrieve the relevant configuration data corresponding to the master clock source point in the global clock structured data model;

[0070] Based on the multi-level structured configuration file and the directed connection graph, the master clock source and the related configuration data are integrated to obtain the recombined data corresponding to each clock entity.

[0071] Specifically, after constructing the global clock structured data model, the clock configuration data with connectivity is traced back to determine a unique master clock source for each clock signal propagation path. This master clock source is used to generate or input clock signals. Then, starting from the master clock source, the relevant configuration data corresponding to that master clock source is retrieved in the global clock structured data model. This process is then traversed along the signal propagation path corresponding to the directed connection graph to obtain the relevant configuration data of all clock entities along the signal propagation path starting from that master clock source. Finally, combined with the Mode_Config.yaml file, the master clock source and relevant configuration data are integrated to obtain the reconstructed data corresponding to the clock entities.

[0072] In one embodiment, anchoring the master clock source point based on the global clock structured data model includes:

[0073] Based on the global clock structured data model, the source point type of each clock source is determined;

[0074] When the source point type is a physical pin, the source point corresponding to the clock source is determined as the master clock source point;

[0075] When the source point type is a logical port, the clock source at the highest level in the hierarchical relationship tree is determined as the master clock source point.

[0076] Specifically, after determining the global clock structured data model, the source point type (i.e., startpoint_type) in the binding attributes of all clock sources in the global clock structured data model is traversed. This source point type includes physical pins (i.e., pins) or logical ports (i.e., ports). If the source point type of a clock source is pin, then the clock source is the output of a PLL (Phase Locked Logic) or PMA (Physical Media Attachment) or an Internal Pin. In this case, the source point corresponding to this clock source can be determined as the master clock source. If there is no clock source with a source point type of pin among all clock sources, then among all candidate clock sources with a source point type of port, the source point of the clock source at the highest level in the hierarchical relationship tree is determined as the master clock source.

[0077] In one embodiment, the integration of the master clock source and related configuration data based on the multi-level structured configuration file and the directed connection graph to obtain recombined data corresponding to each clock entity includes:

[0078] Based on the multi-level structured configuration file, the clock attributes corresponding to the master clock source are determined, and the clock attributes corresponding to the master clock source are filled into the top-level configuration.

[0079] Traverse each port downstream of the master clock source point in the directed connection graph, determine the attributes corresponding to the port based on the multi-level structured configuration file, and fill the attributes corresponding to the port into the container corresponding to the child element; until all ports have been traversed, a hierarchical container is obtained.

[0080] Based on the mode parameters and process angle parameters of the master clock source point in different modes in the multi-level structured configuration file, a multi-mode scenario structure is generated.

[0081] The uncertainty parameters in the directed connection graph, the top-level configuration, the hierarchical container, and the multi-mode scenario structure are determined as the recombined data corresponding to each clock entity.

[0082] Specifically, after determining the master clock source, based on its clock name, the corresponding clock attribute is retrieved from the Clock Config worksheets at all levels, and this clock attribute is then populated into the top-level configuration. Next, the downstream ports originating from the master clock source are traversed according to the directed connection graph, and the corresponding clock attribute for each port is created sequentially. <level>The container, based on the port name corresponding to each port, determines the attributes corresponding to each port from all levels of the Clock Config worksheet, and then sequentially fills the attributes of each port into the corresponding... <level>Container <tile>Within the child elements, this process continues until all ports have been traversed, resulting in a hierarchical container. Next, the Mode_Config.yaml file is read, extracting the mode parameters and process corner parameters of the master clock source point under different modes. Based on these mode parameters, corresponding parameters for each mode are generated. <mode>The structure is generated based on process corner parameters. <corner>structure, <mode>Structure and <corner>The structure constitutes a multi-modal scenario structure. Then, the uncertainty parameters along the propagation path corresponding to the master clock source are processed. Based on this, combining the uncertainty parameters, top-level configuration, hierarchical containers, and the multi-modal scenario structure, the recombined data corresponding to each clock entity is constructed. For example, Figure 3 This is a schematic diagram of the reconstructed data provided in an embodiment of the present invention. The reconstructed data corresponding to the master clock source point CLK_A is as follows: Figure 3 As shown, the reconstructed data includes the top-level configuration ATTRIBUTES, the hierarchical container Level:SYN, and the multi-mode scene structure. The hierarchical container comprises two... <tile name="‘……’">Child elements. This multi-mode scene structure includes a Mode1 structure and a Mode2 structure, where the details of the Mode1 structure (i.e., Mode1 Details) include...<corner Slow / > Structure and<corner Fast / > Structure; details of the Mode2 structure (i.e., Mode2 Details) also include<corner Slow / > Structure and<corner Fast / > structure.

[0083] It should be noted that the modes corresponding to the master clock source include FUNC (Function) or DFT (Design for Test). FUNC mode is the operating mode when the chip is in normal working condition. In FUNC mode, the master clock source provides stable and efficient timing control for functional modules to achieve the corresponding functions and optimize performance. DFT mode is designed for chip manufacturing testing. In DFT mode, the master clock source controls the chip testing process and isolates the test logic to ensure that physical defects after chip manufacturing can be detected, thereby improving fault coverage. This embodiment of the invention does not limit the mode of the master clock source.

[0084] It should be noted that this process angle represents the analysis scenario of the manufacturing process, voltage, and temperature (PVT) baseline combination. This uncertainty parameter is used in timing analysis to simulate uncertainties such as clock jitter and skew.

[0085] Furthermore, this embodiment is independent of specific design scale and can seamlessly adapt to the increase of levels or the expansion of modules. That is, it can automatically expand based on the original recombined data, providing a reliable configuration data management foundation for the iterative design of chips.

[0086] The clock configuration integration device provided by the present invention is described below. The clock configuration integration device described below and the clock configuration integration method described above can be referred to in correspondence.

[0087] This invention provides a clock configuration integration device. Figure 4 This is a schematic diagram of the clock configuration integration device provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the clock configuration integration device 400 includes: an acquisition module 410, a construction module 420, an integration module 430, and a format conversion module 440.

[0088] Module 410 is used to obtain multi-level structured configuration files;

[0089] Module 420 is used to construct a global clock structured data model based on a multi-level structured configuration file; the global clock structured data model is used to represent the cross-level association relationships between clock entities;

[0090] The integration module 430 is used to integrate the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain the recombined data corresponding to each clock entity.

[0091] The format conversion module 440 is used to convert the format of the recombined data corresponding to all clock entities to obtain a standardized clock file.

[0092] The clock configuration integration device provided in this invention constructs a global clock structured data model to represent the cross-level relationships between clock entities through multi-level structured configuration files. Based on this global clock structured data model, it integrates the relevant configuration data corresponding to each clock entity to obtain recombined data for each clock entity. The recombined data is then format-converted to obtain a standardized clock file. In this invention, discrete cross-level structured configuration files are parsed and automatically integrated into a global clock structured data model. This global clock structured data model allows for tracing the complete path of any clock from its source to the user port, significantly improving clock traceability. The entire clock configuration process reduces manual intervention and script writing, avoiding SDC errors caused by manual data aggregation, and ensuring the accuracy and consistency of the global configuration data. Furthermore, during design changes, only targeted modifications to the structured configuration files at each level are needed to automatically update the global configuration based on the existing configuration structure, significantly improving design iteration efficiency.

[0093] Optionally, this building module 420 is specifically used for:

[0094] Based on a multi-level structured configuration file, multiple clock entities are identified, including ports and clock sources;

[0095] Based on a multi-level structured configuration file, a hierarchical relationship tree and a directed connection graph between ports are constructed; the directed connection graph is used to represent the propagation path of the clock signal between ports; the hierarchical relationship tree is used to represent the hierarchical relationship between levels;

[0096] Based on the port attributes, clock associations, and clock sources in the multi-level structured configuration file, the corresponding ports are bound to attributes.

[0097] Based on the directed connection graph, the hierarchical relationship tree, and the ports after attribute binding, the global clock structured data model is constructed.

[0098] Optionally, the integrated module 430 is specifically used for:

[0099] Based on the aforementioned global clock structured data model, the master clock source point is anchored;

[0100] Starting from the master clock source point, retrieve the relevant configuration data corresponding to the master clock source point in the global clock structured data model;

[0101] Based on the multi-level structured configuration file and the directed connection graph, the master clock source and the related configuration data are integrated to obtain the recombined data corresponding to each clock entity.

[0102] Optionally, the integrated module 430 is specifically used for:

[0103] Based on the global clock structured data model, the source point type of each clock source is determined;

[0104] When the source point type is a physical pin, the source point corresponding to the clock source is determined as the master clock source point;

[0105] When the source point type is a logical port, the clock source at the highest level in the hierarchical relationship tree is determined as the master clock source point.

[0106] Optionally, the integrated module 430 is specifically used for:

[0107] Based on the multi-level structured configuration file, the clock attributes corresponding to the master clock source are determined, and the clock attributes corresponding to the master clock source are filled into the top-level configuration.

[0108] Traverse each port downstream of the master clock source point in the directed connection graph, determine the attributes corresponding to the port based on the multi-level structured configuration file, and fill the attributes corresponding to the port into the container corresponding to the child element; until all ports have been traversed, a hierarchical container is obtained.

[0109] Based on the mode parameters and process angle parameters of the master clock source point in different modes in the multi-level structured configuration file, a multi-mode scenario structure is generated.

[0110] The uncertainty parameters in the directed connection graph, the top-level configuration, the hierarchical container, and the multi-mode scenario structure are determined as the recombined data corresponding to each clock entity.

[0111] Optionally, the multi-level structured configuration files include: chip design layer configuration files, subsystem layer configuration files, and chip top-level design layer configuration files.

[0112] Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiment of the present invention, such as... Figure 5 As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540, wherein the processor 510, communications interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call logical instructions in the memory 530 to execute a clock configuration integration method, which includes: obtaining a multi-level structured configuration file; constructing a global clock structured data model based on the multi-level structured configuration file; the global clock structured data model being used to characterize the cross-level relationships between clock entities; integrating the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain recombined data corresponding to each clock entity; and converting the format of the recombined data corresponding to all clock entities to obtain a standardized clock file.

[0113] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0114] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the clock configuration integration method provided by the above methods. The method includes: obtaining a multi-level structured configuration file; constructing a global clock structured data model based on the multi-level structured configuration file; the global clock structured data model being used to characterize the cross-level association between clock entities; integrating the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain recombined data corresponding to each clock entity; and converting the format of the recombined data corresponding to all clock entities to obtain a standardized clock file.

[0115] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the clock configuration integration method provided by the above methods. This method includes: obtaining a multi-level structured configuration file; constructing a global clock structured data model based on the multi-level structured configuration file; the global clock structured data model being used to characterize the cross-level relationships between clock entities; integrating the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain recombined data corresponding to each clock entity; and converting the format of the recombined data corresponding to all clock entities to obtain a standardized clock file.

[0116] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0117] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.< / tile> < / corner> < / mode> < / corner> < / mode> < / tile> < / level> < / level>

Claims

1. A clock configuration integration method, comprising: include: Obtain multi-level structured configuration files; A global clock structured data model is constructed based on multi-level structured configuration files; The global clock structured data model is used to characterize the cross-level relationships between clock entities; Based on the global clock structured data model, the relevant configuration data corresponding to each clock entity is integrated to obtain the recombined data corresponding to each clock entity; The recombined data corresponding to all clock entities is converted into a standardized clock file. The multi-level structured configuration file is used to construct a global clock structured data model, including: Based on a multi-level structured configuration file, multiple clock entities are identified, including ports and clock sources; Based on a multi-level structured configuration file, a hierarchical relationship tree and a directed connection graph between ports are constructed; the directed connection graph is used to represent the propagation path of the clock signal between ports; the hierarchical relationship tree is used to represent the hierarchical relationship between levels; Based on the port attributes, clock associations, and clock sources in the multi-level structured configuration file, the corresponding ports are bound to attributes. Based on the directed connection graph, the hierarchical relationship tree, and the ports after attribute binding, the global clock structured data model is constructed. The multi-level structured configuration files include: chip design layer configuration files, subsystem layer configuration files, and chip top-level design layer configuration files.

2. The clock configuration integration method according to claim 1, characterized in that, The process of integrating the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain the recombined data corresponding to each clock entity includes: Based on the aforementioned global clock structured data model, the master clock source point is anchored; Starting from the master clock source point, retrieve the relevant configuration data corresponding to the master clock source point in the global clock structured data model; Based on the multi-level structured configuration file and the directed connection graph, the master clock source and the related configuration data are integrated to obtain the recombined data corresponding to each clock entity.

3. The clock configuration integration method according to claim 2, characterized in that, The anchoring of the master clock source point based on the global clock structured data model includes: Based on the global clock structured data model, the source point type of each clock source is determined; When the source point type is a physical pin, the source point corresponding to the clock source is determined as the master clock source point; When the source point type is a logical port, the clock source at the highest level in the hierarchical relationship tree is determined as the master clock source point.

4. The clock configuration integration method according to claim 2, characterized in that, The multi-level structured configuration file and the directed connection graph integrate the master clock source and the related configuration data to obtain the recombined data corresponding to each clock entity, including: Based on the multi-level structured configuration file, the clock attributes corresponding to the master clock source are determined, and the clock attributes corresponding to the master clock source are filled into the top-level configuration. Traverse each port downstream of the master clock source point in the directed connection graph, determine the attributes corresponding to the port based on the multi-level structured configuration file, and fill the attributes corresponding to the port into the container corresponding to the child element; until all ports have been traversed, a hierarchical container is obtained. Based on the mode parameters and process angle parameters of the master clock source point in different modes in the multi-level structured configuration file, a multi-mode scenario structure is generated. The uncertainty parameters in the directed connection graph, the top-level configuration, the hierarchical container, and the multi-mode scenario structure are determined as the recombined data corresponding to each clock entity.

5. A clock configuration integration device, characterized in that, include: The acquisition module is used to acquire multi-level structured configuration files; The building module is used to construct a global clock structured data model based on multi-level structured configuration files; The global clock structured data model is used to characterize the cross-level relationships between clock entities; An integration module is used to integrate the relevant configuration data corresponding to each clock entity based on the global clock structured data model to obtain the recombined data corresponding to each clock entity. The format conversion module is used to convert the format of the recombined data corresponding to all clock entities to obtain a standardized clock file. The construction module is specifically used for: determining multiple clock entities based on a multi-level structured configuration file, wherein the clock entities include ports and clock sources; constructing a hierarchical relationship tree and a directed connection graph between ports based on the multi-level structured configuration file; the directed connection graph is used to represent the propagation path of clock signals between ports; and the hierarchical relationship tree is used to represent the hierarchical relationships between levels. Based on the port attributes, clock associations, and clock sources in the multi-level structured configuration file, the corresponding ports are bound to attributes. Based on the directed connection graph, the hierarchical relationship tree, and the ports after attribute binding, the global clock structured data model is constructed. The multi-level structured configuration files include: chip design layer configuration files, subsystem layer configuration files, and chip top-level design layer configuration files.

6. The clock configuration integration device according to claim 5, characterized in that, The integration module is specifically used for: Based on the aforementioned global clock structured data model, the master clock source point is anchored; Starting from the master clock source point, retrieve the relevant configuration data corresponding to the master clock source point in the global clock structured data model; Based on the multi-level structured configuration file and the directed connection graph, the master clock source and the related configuration data are integrated to obtain the recombined data corresponding to each clock entity.

7. The clock configuration integration device according to claim 5, characterized in that, The integration module is also used for: Based on the global clock structured data model, the source point type of each clock source is determined; When the source point type is a physical pin, the source point corresponding to the clock source is determined as the master clock source point; When the source point type is a logical port, the clock source at the highest level in the hierarchical relationship tree is determined as the master clock source point.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the clock configuration integration method as described in any one of claims 1 to 4.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the clock configuration integration method as described in any one of claims 1 to 4.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the clock configuration integration method as described in any one of claims 1 to 4.

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