Standard cell layout automatic generation method and device, storage medium and electronic equipment

Abstract

The invention discloses a standard cell layout automatic generation method and device, a storage medium and electronic equipment, and the method comprises the steps: obtaining a circuit netlist of a to-be-generated standard cell, and constructing the circuit netlist into a graph structure according to a preset rule; inputting the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; based on node embedding and graph-level embedding, generating layout geometric information of each layout layer through a geometric decoder; carrying out constraint processing on the layout geometric information according to a process design rule; and outputting the layout geometric information subjected to constraint processing as a standard unit layout file format. According to the embodiment of the invention, the generation efficiency of the standard cell layout can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of integrated circuits, and in particular to a standard cell layout automatic generation method and device, a storage medium and an electronic device. BACKGROUND

[0002] In the integrated circuit design process, a standard cell layout is a basic unit for realizing the physical implementation of a logic circuit, and its geometric layout directly affects the area, performance and power consumption of a chip. Traditional standard cell layout design mainly relies on manual placement or heuristic algorithm generation, such as simulated annealing, genetic algorithm or template-based rule placement method.

[0003] However, as the process node continues to shrink, the complexity of the layout layers and design rules increases significantly. Each standard cell often involves the cooperation between active area, polysilicon gate, dielectric layer, multiple metal interconnection layers and contact hole layer and other geometric layers. Manual placement or heuristic algorithm significantly decreases in efficiency when dealing with large-scale design rule constraints and cross-layer connectivity, thereby reducing the generation efficiency of the standard cell layout. SUMMARY

[0004] Embodiments of the present application provide a standard cell layout automatic generation method and device, a storage medium and an electronic device, which can improve the generation efficiency of the standard cell layout.

[0005] In a first aspect, embodiments of the present application provide a standard cell layout automatic generation method, comprising: obtaining a circuit netlist of a standard cell to be generated, and constructing the circuit netlist into a graph structure according to a preset rule; inputting the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; generating layout geometric information of each layout layer through a geometric decoder based on the node embedding and the graph-level embedding; performing constraint processing on the layout geometric information according to process design rules; outputting the layout geometric information after constraint processing into a standard cell layout file format.

[0006] In the standard cell layout automatic generation method provided by embodiments of the present application, the circuit netlist is constructed into a graph structure according to a preset rule, comprising: devices, ports and interconnection networks in the circuit netlist are taken as nodes of the graph structure, respectively; the dependency relationship between the devices and their ports, the electrical connection relationship between the devices through the interconnection networks, and the connection relationship between the ports and the interconnection networks are taken as edges of the graph structure; corresponding attribute features are assigned to the nodes and the edges. construct the graph structure according to the nodes, the edges and the attribute features.

[0007] In the method for automatically generating a standard cell layout provided in the embodiments of the present application, the graph neural network encoder is composed of a graph convolutional neural network or a graph attention network; The inputting of the graph structure into the graph neural network encoder to obtain node embedding and graph-level embedding comprises: The attribute features of each node in the graph structure are updated by the graph convolutional neural network or the graph attention network in multiple layers to obtain node embedding; The node embedding is subjected to a pooling operation to obtain graph-level embedding.

[0008] In the method for automatically generating a standard cell layout provided in the embodiments of the present application, the generation of layout geometry information of each layout layer based on the node embedding and the graph-level embedding by a geometry decoder comprises: The node embedding and the graph-level embedding are fused to generate a comprehensive feature vector; The comprehensive feature vector is input into the geometry decoder to generate the layout geometry information of each layout layer, and the geometry decoder has independent prediction branches set for different layout layers at the output end.

[0009] In the method for automatically generating a standard cell layout provided in the embodiments of the present application, the inputting of the comprehensive feature vector into the geometry decoder to generate the layout geometry information of each layout layer comprises: Based on the comprehensive feature vector, each independent prediction branch of the geometry decoder generates the layout geometry information of each layout layer in a sequence generation or coordinate prediction manner.

[0010] In the method for automatically generating a standard cell layout provided in the embodiments of the present application, the constraint processing of the layout geometry information according to process design rules comprises: The layout geometry information is subjected to process design rule checking to determine whether the layout geometry information meets the constraint condition; The layout geometry information that does not meet the constraint condition is subjected to a correction operation to meet the constraint condition.

[0011] In the method for automatically generating a standard cell layout provided in the embodiments of the present application, the correction operation of the layout geometry information that does not meet the constraint condition to meet the constraint condition comprises: The layout geometry information that does not meet the constraint condition is classified and identified to obtain a violation type; According to the violation type, a corresponding correction operation is performed on the layout geometry information to meet the constraint condition.

[0012] In a second aspect, the embodiments of the present application provide a standard cell layout automatic generation device, comprising: An acquisition unit is configured to acquire a circuit netlist of a standard cell to be generated, and construct the circuit netlist into a graph structure according to a preset rule; An input unit is configured to input the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; A generation unit is configured to generate layout geometry information of each layout layer based on the node embedding and the graph-level embedding through a geometric decoder; A constraint unit is configured to perform constraint processing on the layout geometry information according to a process design rule; An output unit is configured to output the layout geometry information after the constraint processing into a standard cell layout file format.

[0013] In a third aspect, the present application provides a storage medium storing a plurality of instructions, which are adapted to be loaded by a processor to execute the standard cell layout automatic generation method according to any one of the above aspects.

[0014] In a fourth aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the standard cell layout automatic generation method according to any one of the above aspects when executing the computer program.

[0015] To sum up, the standard cell layout automatic generation method provided by the embodiments of the present application comprises acquiring a circuit netlist of a standard cell to be generated, and constructing the circuit netlist into a graph structure according to a preset rule; inputting the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; generating layout geometry information of each layout layer based on the node embedding and the graph-level embedding through a geometric decoder; performing constraint processing on the layout geometry information according to a process design rule; and outputting the layout geometry information after the constraint processing into a standard cell layout file format. The embodiments of the present application can improve the generation efficiency of the standard cell layout. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is an application scenario diagram of the standard cell layout automatic generation method provided by the embodiments of the present application.

[0018] Figure 2 FIG. 1 is a flowchart of a method for automatically generating a standard cell layout according to an example embodiment of the present application.

[0019] Figure 3 FIG. 2 is a block diagram of an apparatus for automatically generating a standard cell layout according to an example embodiment of the present application.

[0020] Figure 4 FIG. 3 is a block diagram of an electronic device according to an example embodiment of the present application. DETAILED DESCRIPTION

[0021] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. In the following description, unless otherwise expressly specified, the same numbers in different drawings represent the same or similar elements. The following example embodiments are not representative of all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application, as detailed in the appended claims.

[0022] It should be noted that, in this document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. Also, a component similar to those identified as a certain name can have the same or different meaning in different embodiments of the present application, and the specific meaning of the component should be determined in light of the description of the certain embodiment or in conjunction with the context of the certain embodiment.

[0023] It should be understood that the specific embodiments described herein are merely exemplary and do not limit the application.

[0024] In the following description, the suffixes "module", "part", or "unit" used for an element are merely intended for facilitating the description of the application, and are not intended to limit the application. Therefore, "module", "part", or "unit" can be mixedly used.

[0025] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0026] As the process node continues to shrink, the number of layout layers and the complexity of design rules increase significantly. Each standard cell often involves the cooperation between active area, polysilicon gate, dielectric layer, multiple metal interconnection layers and contact hole layer and other multiple geometric layers. Artificial layout or heuristic algorithm significantly decreases in efficiency when dealing with large-scale design rule constraints and cross-layer connectivity, thereby reducing the generation efficiency of standard cell layout.

[0027] Based on this, the embodiments of the present application provide a standard cell layout automatic generation method, device, storage medium and electronic equipment. Specifically, the standard cell layout automatic generation device can be integrated in an electronic equipment, which can be a server or a terminal and the like. The terminal can include a mobile phone, a wearable smart device, a tablet computer, a notebook computer, a personal computer (PC) and the like. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0028] For example, as shown in Figure 1 The electronic equipment obtains a circuit netlist of a standard cell to be generated, and constructs the circuit netlist into a graph structure according to a preset rule; inputs the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; generates layout geometry information of each layout layer based on the node embedding and the graph-level embedding through a geometry decoder; performs constraint processing on the layout geometry information according to a process design rule; and outputs the layout geometry information after the constraint processing as a standard cell layout file format.

[0029] The technical solutions shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not limited as the priority order of the embodiments.

[0030] Please refer to Figure 2 , Figure 2 is a flowchart of the standard cell layout automatic generation method provided by the embodiments of the present application. The specific process of the standard cell layout automatic generation method can be as follows: 101. Obtain the circuit netlist of the standard cells to be generated, and construct the circuit netlist into a graph structure according to the preset rules.

[0031] Specifically, the netlist for generating standard cells can be obtained from the standard cell library. The automatic generation of the standard cell layout depends on obtaining the netlist. A netlist is a file that describes the internal connections and attributes of components in an electronic circuit. In IC design, the netlist is the most basic description, typically containing information about devices, ports, and interconnections. It is usually represented in text file format, where each line represents a connection relationship or an attribute of a component. Each component in the netlist (e.g., transistor, diode, resistor, etc.) has a unique identifier. A graph structure is an abstract representation of a circuit netlist, where nodes represent circuit elements (such as transistors, ports, and interconnects). Edges represent electrical or physical connections between these elements, such as the connection between the source and drain of a transistor, or the connection between a port and an interconnect. Graph construction requires mapping various elements in the circuit netlist to the nodes and edges of the graph based on predefined rules.

[0032] Specifically, devices, ports, and interconnections in the circuit netlist can be used as nodes of the graph structure; the dependency relationships between devices and their ports, the electrical connections between devices established through interconnections, and the connections between ports and interconnections can be used as edges of the graph structure; corresponding attribute features can be assigned to nodes and edges; and the graph structure can be constructed based on nodes, edges, and attribute features.

[0033] The attributes of a node can include its electrical parameters, geometric dimensions, and functional type. The attributes of an edge can include its connectivity, signal flow direction, and transmission delay.

[0034] In other words, in this embodiment, each element (device, port, and interconnection network) in the circuit netlist is abstracted as a node in the graph structure, and the electrical and physical relationships connecting these nodes are constructed as edges of the graph structure. The attribute characteristics of the nodes and edges are filled in according to the information in the circuit netlist, thereby constructing the graph structure.

[0035] 102. Input the graph structure into the graph neural network encoder to obtain node embeddings and graph-level embeddings.

[0036] A graph neural network (GNN) is a deep learning method that can effectively process graph-structured data. Since a circuit netlist is essentially a graph structure, using a graph neural network can effectively learn the relationships between nodes and their attributes, thereby providing strong support for subsequent standard cell layout generation. In this embodiment, the graph neural network encoder is composed of a graph convolution neural network (GCNN) or a graph attention network (GAT).

[0037] wherein the GCN can update the features of the nodes by convolution operation, and pass the attribute features of the nodes through the weighted summation of adjacent nodes to achieve the propagation of information and the update of the attribute features of the nodes. Each layer of GCN updates the attributes of the nodes, so that each node can not only focus on its own information, but also obtain the influence of the neighbor nodes.

[0038] The GAT adopts a self-attention mechanism to dynamically adjust the weights according to the relationship between the nodes and the neighbor nodes. This enables the GAT to selectively pass information between different nodes, and better handle the uneven connections between nodes in the graph.

[0039] In the specific implementation process, the initial feature vector of each node can be initialized as the attribute features of the nodes in the graph structure. Then, the attribute features of the nodes in the graph structure are updated by multiple iterations through the graph convolution neural network or the graph attention network, so that the attribute features of each node not only contain its own information, but also combine the information of its adjacent nodes.

[0040] After multiple layers of graph convolution or graph attention update, the attribute features of the nodes will be iteratively updated, and finally each node will obtain an embedding vector containing its electrical characteristics, topological information, etc. This vector can be used as the final representation of the node, capturing the local topological structure of the circuit where the node is located. The embedding vector is the node embedding.

[0041] In some embodiments, in order to consider the global circuit structure information, the graph neural network generally aggregates the attribute features of the nodes through a pooling operation. The pooling operation can be global average pooling or global maximum pooling, which aggregates the attribute features of each node into a global representation, thereby obtaining a graph-level embedding.

[0042] Therefore, step 102 can specifically be to update the attribute features of the nodes in the graph structure through multiple iterations by a graph convolution neural network or a graph attention network to obtain node embeddings; and performing a pooling operation on the node embeddings to obtain a graph-level embedding.

[0043] Through the processing of the graph neural network encoder, the node embedding and the graph-level embedding represent the local features of each element in the circuit and the global features of the entire circuit, respectively. The node embedding and the graph-level embedding can be used as inputs of the subsequent geometric decoder to provide necessary structured information for the standard cell layout generation.

[0044] 103. Based on the node embedding and the graph-level embedding, the geometric information of each layout layer is generated by the geometric decoder.

[0045] In some embodiments, the node embedding and the graph-level embedding can be fused. The node embedding represents the detailed local characteristics of each element in the circuit, while the graph-level embedding captures the global topological features of the entire circuit. By fusing these two features, a comprehensive feature vector with both local and global information of the circuit can be formed.

[0046] The feature fusion can be weighted fusion or splicing fusion.

[0047] The geometric decoder has independent prediction branches at the output end for different layout layers. Each branch is responsible for generating the geometric information of a different layer. For example, for a typical standard cell layout, the layout layers of the metal layer, the contact hole layer, the gate layer, and the source / drain layer may need to be generated.

[0048] Each independent prediction branch of the geometric decoder processes different parts of the comprehensive feature vector and generates corresponding layout geometric information according to the circuit structure, device type, and layout requirements. For example, a branch dedicated to generating the metal layer layout will use information from the node embedding and the graph-level embedding to generate a set of coordinates for each element in the layout layer. That is, the layout geometric information refers to the set of coordinates for each layout layer.

[0049] In some embodiments, step 103 can be a fusion process of the node embedding and the graph-level embedding to generate a comprehensive feature vector; the comprehensive feature vector is input into the geometric decoder to generate the layout geometric information of each layout layer, and the geometric decoder has independent prediction branches at the output end for different layout layers.

[0050] Specifically, each independent prediction branch of the geometric decoder can generate the layout geometric information of each layout layer based on the comprehensive feature vector using sequence generation or coordinate prediction.

[0051] For simple layout layers such as metal lines and contact holes, the decoder can predict their coordinates point by point. For example, when generating a metal line, the decoder can predict the starting point, the ending point, and the intermediate path coordinates of the metal line step by step to ensure that the connection relationship and electrical characteristics are achieved.

[0052] For more complex layout layers (such as active area and gate), the decoder can use a sequence generation method to predict multiple coordinate points. This method usually generates the boundary coordinates of each circuit element step by step, ensuring the correct position of each element in the layout.

[0053] In some embodiments, since the geometric information of each layout layer has different design rules, layout requirements and generation methods. Therefore, in order to meet the different needs of different layout layers, a customized decoding function can be used in each independent prediction branch to process the comprehensive feature vector and generate the corresponding set of geometric coordinates.

[0054] 104、Constrain the layout geometric information according to the process design rule.

[0055] The process design rule (Design Rule Check, DRC) includes but is not limited to the minimum width of the metal line, the minimum size of the contact hole, and the minimum spacing between layers. The process design rule is an indispensable part of the chip manufacturing process, which aims to ensure that the layout can be smoothly implemented in the physical manufacturing process, and there is no manufacturing defect caused by size or spacing error.

[0056] Specifically, the layout geometric information can be subjected to process design rule checking to determine whether the layout geometric information meets the constraint condition; and a correction operation is performed on the layout geometric information that does not meet the constraint condition to make it meet the constraint condition.

[0057] The step of "performing a correction operation on the layout geometric information that does not meet the constraint condition to make it meet the constraint condition" is specifically classifying and identifying the layout geometric information that does not meet the constraint condition to obtain the violation type; and performing a corresponding correction operation on the layout geometric information according to the violation type to make it meet the constraint condition.

[0058] In some embodiments, the DRC tool can be used to identify violations of the layout geometric information and output all elements that violate the rules and their types. For example, when the metal line width does not meet the requirements, the DRC tool will mark the metal line and classify it as a "width insufficient" type.

[0059] For example, for the violation of insufficient metal line width, the width of the metal line can be increased to correct it. For the violation of insufficient metal line spacing, the position of the metal line can be adjusted to increase the spacing to ensure that it meets the process rules. For the violation of incorrect contact hole position, the position of the contact hole can be repositioned to correct it.

[0060] 105、Constrain the layout geometric information according to the process design rule.

[0061] Specifically, all the layout geometry information can be formatted into corresponding data structures according to process design rules and standard file formats (such as GDSII) first. Each layer of layout information (such as a metal layer, a contact hole layer) will be converted into a specific graphical representation.

[0062] Then, the formatted data is written into a GDSII file using a tool (such as gdspy, etc.). The GDSII file contains the coordinates, shapes, and sizes of all the layout layers, and complies with the standard GDSII format specification.

[0063] To sum up, the standard cell layout automatic generation method provided by the embodiments of the present application includes obtaining a circuit netlist of a standard cell to be generated, and constructing the circuit netlist into a graph structure according to a preset rule; inputting the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; generating layout geometry information of each layout layer based on the node embedding and the graph-level embedding through a geometry decoder; performing constraint processing on the layout geometry information according to process design rules; and outputting the layout geometry information after the constraint processing into a standard cell layout file format. The embodiments of the present application can improve the generation efficiency of the standard cell layout. The embodiments of the present application provide a standard cell layout automatic generation method that can automatically generate a standard cell layout that complies with process design rules, greatly improves the generation efficiency of the standard cell layout, and reduces errors that may be caused by manual intervention.

[0064] To better implement the standard cell layout automatic generation method provided by the embodiments of the present application, the embodiments of the present application further provide a standard cell layout automatic generation device. The meanings of the terms are the same as those in the above-described standard cell layout automatic generation method, and specific implementation details can be referred to the description in the method embodiments.

[0065] Please refer to Figure 3 , Figure 3 is a structural schematic diagram of the standard cell layout automatic generation device provided by the embodiments of the present application. The standard cell layout automatic generation device can include an obtaining unit 201, an input unit 202, a generating unit 203, a constraint unit 204, and an output unit 205. Among them, The obtaining unit 201 is configured to obtain a circuit netlist of a standard cell to be generated, and construct the circuit netlist into a graph structure according to a preset rule; The input unit 202 is configured to input the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; The generating unit 203 is configured to generate layout geometry information of each layout layer based on the node embedding and the graph-level embedding through a geometry decoder; The constraint unit 204 is configured to perform constraint processing on the layout geometry information according to process design rules; The output unit 205 is configured to output the layout geometry information after the constraint processing as a standard cell layout file format.

[0066] The specific implementation of each unit can refer to the above-mentioned embodiments of the standard cell layout automatic generation method, which will not be repeated here.

[0067] To sum up, the standard cell layout automatic generation device provided by the embodiments of the present application can obtain the circuit netlist of the standard cell to be generated by the obtaining unit 201, and construct the circuit netlist into a graph structure according to a preset rule; the input unit 202 inputs the graph structure into the graph neural network encoder to obtain node embedding and graph-level embedding; the generation unit 203 generates the layout geometry information of each layout layer based on the node embedding and the graph-level embedding through the geometry decoder; the constraint unit 204 performs constraint processing on the layout geometry information according to the process design rule; and the output unit 205 outputs the layout geometry information after the constraint processing as a standard cell layout file format. The embodiments of the present application can automatically generate a standard cell layout that meets the process design rule, greatly improving the generation efficiency of the standard cell layout and reducing the errors that may be caused by manual intervention.

[0068] The embodiments of the present application also provide an electronic device, which can integrate the standard cell layout automatic generation device of the embodiments of the present application, as shown in Figure 4 The electronic device structure involved in the embodiments of the present application is shown in the figure, which specifically shows the structure of the electronic device involved in the embodiments of the present application, and specifically includes: The electronic device can include a processor 301 with one or more processing cores and a memory 302 with one or more computer readable storage media, and the like. Those skilled in the art can understand that the electronic device structure shown in Figure 4 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and can include more or fewer components than the figure, or combine certain components, or different component arrangements. Among them: The processor 301 is the control center of the electronic device, which connects all parts of the electronic device through various interfaces and lines, and performs various functions and processes data of the electronic device by running or executing software programs and / or the present application stored in the memory 302, and calling data stored in the memory 302. Therefore, the electronic device is overall monitored. Optionally, the processor 301 can include one or more processing cores; preferably, the processor 301 can integrate an application processor and a modem processor, wherein the application processor mainly processes operation storage media, user interfaces and application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 301.

[0069] The memory 302 can be used to store software programs and the present application, and the processor 301 executes various function applications and data processing by running the software programs and the present application stored in the memory 302. The memory 302 can mainly include a program storage area and a data storage area, wherein the program storage area can store application programs required for at least one function of the operation storage medium, and the data storage area can store data created according to the use of the electronic device. In addition, the memory 302 can include a high-speed random access memory, and can also include a non-volatile memory such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory device. Accordingly, the memory 302 can also include a memory controller to provide access for the processor 301 to the memory 302.

[0070] Although not shown, the electronic device can also include a display unit, an input unit, a power supply, and the like, which will not be described here. In particular, in the present embodiment, the processor 301 in the electronic device will load the executable file corresponding to the process of one or more application programs into the memory 302 according to the following instructions, and run the application programs stored in the memory 302 by the processor 301, thereby realizing various functions, as follows: obtaining a circuit netlist of a standard cell to be generated, and constructing the circuit netlist into a graph structure according to a preset rule; inputting the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; generating layout geometry information of each layout layer based on the node embedding and the graph-level embedding through a geometric decoder; constraining the layout geometry information according to a process design rule; outputting the layout geometry information after the constraint processing as a standard cell layout file format.

[0071] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or controlled by instructions related to hardware, which can be stored in a computer readable storage medium and loaded and executed by a processor.

[0072] To this end, the embodiments of the present application provide a storage medium having a plurality of instructions stored therein, which can be loaded by a processor to execute the steps in any of the methods provided by the embodiments of the present application. For example, the instructions can execute the following steps: obtaining a circuit netlist of a standard cell to be generated, and constructing the circuit netlist into a graph structure according to a preset rule; inputting the graph structure into a graph neural network encoder to obtain node embedding and graph-level embedding; generating layout geometry information of each layout layer based on the node embedding and the graph-level embedding through a geometric decoder; The layout geometry information is constrained according to process design rules; The constrained layout geometry information is output as a standard cell layout file format.

[0073] The specific implementation of each operation can refer to the foregoing embodiments, which will not be repeated here.

[0074] The storage medium can include a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, etc.

[0075] Due to the instructions stored in the storage medium, the steps in any method provided by the embodiments of the present application can be executed, thus achieving the beneficial effects of any method provided by the embodiments of the present application. Details are shown in the foregoing embodiments, which will not be repeated here.

[0076] The standard cell layout automatic generation method, device, storage medium and electronic equipment provided by the present application are described in detail above. The principles and implementation manners of the present application are described by applying specific examples in this paper. The foregoing example is only used to help understand the core idea of the present application. Meanwhile, for those skilled in the art, the specific implementation manner and application range can be changed according to the idea of the present application. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method for automatically generating standard cell layouts, characterized in that, include: Obtain the circuit netlist of the standard cells to be generated, and construct the circuit netlist into a graph structure according to preset rules; The graph structure is input into a graph neural network encoder to obtain node embeddings and graph-level embeddings; Based on the node embedding and the graph-level embedding, the layout geometry information of each layout layer is generated by the geometry decoder; The geometric information of the layout is constrained according to the process design rules; The constrained layout geometry information is output as a standard cell layout file format.

2. The method for automatically generating standard cell layouts as described in claim 1, characterized in that, The step of constructing the circuit netlist into a graph structure according to preset rules includes: The devices, ports, and interconnections in the circuit netlist are respectively used as nodes in the graph structure; The dependency relationship between the device and its port, the electrical connection relationship between the devices established through the interconnection network, and the connection relationship between the port and the interconnection network are regarded as the edges of the graph structure; Assign corresponding attribute features to the nodes and the edges; The graph structure is constructed based on the nodes, edges, and attribute features.

3. The method for automatically generating standard cell layouts as described in claim 1, characterized in that, The graph neural network encoder is composed of a graph convolutional neural network or a graph attention network; The step of inputting the graph structure into a graph neural network encoder to obtain node embeddings and graph-level embeddings includes: The attribute features of each node in the graph structure are updated in multiple layers through the graph convolutional neural network or the graph attention network to obtain the node embedding; A pooling operation is performed on the node embeddings to obtain graph-level embeddings.

4. The method for automatically generating standard cell layouts as described in claim 1, characterized in that, The generation of layout geometry information for each layout layer using a geometry decoder, based on the node embedding and the graph-level embedding, includes: The node embedding and graph-level embedding are fused to generate a comprehensive feature vector; The integrated feature vector is input into the geometric decoder to generate the layout geometry information of each layout layer. The geometric decoder has independent prediction branches set for different layout layers at the output end.

5. The method for automatically generating standard cell layouts as described in claim 4, characterized in that, The step of inputting the comprehensive feature vector into the geometric decoder to generate the layout geometric information of each layout layer includes: Based on the comprehensive feature vector, each independent prediction branch of the geometric decoder generates the layout geometry information of each layout layer using sequence generation or coordinate prediction methods.

6. The method for automatically generating standard cell layouts as described in claim 1, characterized in that, The step of constraining the layout geometry information according to process design rules includes: The layout geometry information is validated using process design rules to determine whether the layout geometry information meets the constraints. Perform a correction operation on the layout geometry information that does not meet the constraints to make it conform to the constraints.

7. The method for automatically generating standard cell layouts as described in claim 6, characterized in that, The step of performing a correction operation on the layout geometry information that does not meet the constraints to make it conform to the constraints includes: The layout geometry information that does not meet the constraints is classified and identified to obtain the violation type; According to the violation type, the corresponding correction operation is performed on the layout geometry information to make it conform to the constraint conditions.

8. An automatic standard cell layout generation device, characterized in that, include: The acquisition unit is used to acquire the circuit netlist of the standard cell to be generated, and construct the circuit netlist into a graph structure according to preset rules; The input unit is used to input the graph structure into the graph neural network encoder to obtain node embeddings and graph-level embeddings; The generation unit is used to generate the layout geometry information of each layout layer based on the node embedding and the graph-level embedding through a geometry decoder; The constraint unit is used to constrain the layout geometry information according to the process design rules; The output unit is used to output the constrained layout geometry information as a standard unit layout file format.

9. A storage medium, characterized in that, The storage medium stores multiple instructions, which are adapted for loading by a processor to execute the standard cell layout automatic generation method according to any one of claims 1-7.

10. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the standard cell layout automatic generation method as described in any one of claims 1-7.

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