reader / writer

Abstract

This application discloses a reader / writer, comprising: a demodulation circuit for extracting the envelope signal of a radio frequency signal emitted by an electronic tag; a pulse shaping circuit connected to the demodulation circuit, wherein the pulse shaping circuit outputs an end-modulation pulse signal or a start-modulation pulse signal based on the envelope signal output by the demodulation circuit; a counter connected to the demodulation circuit, wherein the counter counts in response to changes in the amplitude of the envelope signal output by the demodulation circuit; a symbol detection circuit connected to the counter and the pulse shaping circuit, wherein the symbol detection circuit controls the counter to be reset to zero and start counting in response to the start-modulation pulse signal; controls the counter to stop counting in response to the end-modulation pulse signal; and performs symbol detection and demodulation based on the counter's count value to obtain the original data information. Thus, by combining the demodulation circuit, the pulse shaping circuit, and the symbol detection circuit, the reliability of reading information recorded in the electronic tag can be improved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a reader / writer. Background Technology

[0002] With the continuous advancement of the construction of new power systems, the intelligent management of power equipment faces multidimensional challenges. The monitoring data generated by power equipment is characterized by real-time, dynamic, and massive volume. In order to effectively manage power equipment, electronic tags are generally used to record relevant information about the power equipment. Staff can use readers to identify and extract the information recorded in the electronic tags to obtain relevant information about the power equipment.

[0003] However, traditional readers suffer from unstable signal recognition and susceptibility to interference in complex electromagnetic environments, resulting in low reliability of the information recorded in electronic tags read by the readers. Summary of the Invention

[0004] This application provides a reader / writer that can improve the reliability of reading information recorded in electronic tags.

[0005] In a first aspect, embodiments of this application provide a reader / writer, including: A demodulation circuit is used to extract the envelope signal of the radio frequency signal emitted by the electronic tag, the envelope signal including the original data information of the electronic tag; A pulse shaping circuit is connected to the demodulation circuit, and the pulse shaping circuit is used to output an end modulation pulse signal or a start modulation pulse signal based on the envelope signal output by the demodulation circuit. A counter, connected to the demodulation circuit, is used to count in response to changes in the amplitude of the envelope signal output by the demodulation circuit. A symbol detection circuit is connected to the counter and the pulse shaping circuit. The symbol detection circuit is used to control the counter to be reset to zero and start counting in response to the start modulation pulse signal; to control the counter to stop counting in response to the end modulation pulse signal; and to perform symbol detection and demodulation based on the count value of the counter to obtain the original data information.

[0006] In some embodiments, the demodulation circuit includes a low-pass filter circuit, which is connected to the pulse shaping circuit and the counter.

[0007] In some embodiments, the low-pass filter circuit includes: A first resistor, one end of which receives the radio frequency signal; The first transistor, the gate of the first transistor is connected to the other end of the first resistor; The second resistor has one end connected to the source of the first transistor and the other end grounded. The second transistor has its gate connected to the source of the first transistor, its source grounded, and its drain connected to the pulse shaping circuit and the counter. A third resistor, one end of which is connected to the drain of the first transistor and the other end of which is connected to the drain of the second transistor.

[0008] In some embodiments, the demodulation circuit further includes: The third transistor has its gate connected to the low-pass filter circuit and its source grounded. A high-pass filter circuit, wherein the first terminal of the high-pass filter circuit is connected to the drain of the first transistor, the second terminal is connected to the drain of the third transistor, and the third terminal is connected to the pulse shaping circuit and the counter.

[0009] In some embodiments, the high-pass filter circuit includes: A fourth resistor, one end of which is connected to the drain of the first transistor and the other end of which is connected to the drain of the third transistor; A first capacitor, one end of which is connected to the other end of the fourth resistor, and the other end of which is connected to the pulse shaping circuit and the counter; The fifth resistor has one end connected to the other end of the first capacitor and the other end grounded.

[0010] In some embodiments, the demodulation circuit further includes: The fourth transistor has its drain connected to the other end of the first capacitor, and its source and gate are grounded.

[0011] In some embodiments, the pulse shaping circuit includes: A fifth transistor, the gate of which is connected to the demodulation circuit, and the source of which is grounded; A sixth transistor, wherein the drain of the sixth transistor is connected to the drain of the fifth transistor, and the source of the sixth transistor is connected to the source of the fifth transistor; A sixth resistor, one end of which is connected to the drain of the fifth transistor; A power supply circuit is provided to supply power to the fifth transistor and the sixth transistor. The first terminal of the power supply circuit is connected to the other terminal of the sixth resistor, and the second terminal of the power supply circuit is grounded. A time constant circuit is provided, which is used to determine the pulse width generated by the pulse shaping circuit. The first terminal of the time constant circuit is connected to the drain of the fifth transistor, and the second terminal is connected to the third terminal of the power supply circuit. A seventh transistor, the gate of which is connected to the third terminal of the time constant circuit, the source of which is connected to the source of the sixth transistor, and the drain of which is connected to the second terminal of the time constant circuit. A push-pull circuit is provided to buffer the signal output by the seventh transistor. The first terminal of the push-pull circuit is connected to the drain of the seventh transistor, the second terminal of the push-pull circuit is connected to the source of the seventh transistor, the third terminal of the push-pull circuit is connected to the drain of the seventh transistor, the fourth terminal of the push-pull circuit is connected to the gate of the sixth transistor, and the fifth terminal of the push-pull circuit is connected to the symbol detection circuit.

[0012] In some embodiments, the power supply circuit includes: The second capacitor has one end connected to the other end of the sixth resistor, and the other end grounded. The eighth transistor has its source connected to one end of the second capacitor and its drain connected to the second terminal of the time constant circuit.

[0013] In some embodiments, the time constant circuit includes: The third capacitor has one end connected to the drain of the fifth transistor and the other end connected to the gate of the seventh transistor. The seventh resistor has one end connected to the other end of the third capacitor and the other end connected to the drain of the eighth transistor and the drain of the seventh transistor.

[0014] In some embodiments, the push-pull circuit includes: A ninth transistor, wherein the gate of the ninth transistor is connected to the drain of the seventh transistor, the source of the ninth transistor is connected to the source of the seventh transistor, and the drain of the ninth transistor is connected to the drain of the seventh transistor. The tenth transistor has its source connected to the source of the ninth transistor, its gate connected to the drain of the ninth transistor, and its drain connected to the symbol detection circuit. The eleventh transistor has its gate connected to the gate of the sixth transistor, its source connected to the drain of the tenth transistor, and its drain connected to the drain of the ninth transistor.

[0015] Secondly, embodiments of this application provide an electronic device, which includes the reader / writer of the first aspect.

[0016] The reader / writer and electronic device of this application embodiment can extract the envelope signal from the radio frequency signal through a demodulation circuit, effectively filtering out the carrier frequency and its harmonics, retaining only the modulation information of the signal, i.e., the envelope signal. Since the envelope signal contains the actual transmitted data information, and high-frequency noise and interference are usually located near the carrier frequency, extracting the envelope signal can significantly reduce the impact of these noises and interferences on the signal. The pulse shaping circuit generates start and end modulation pulses based on the envelope signal, further optimizing the shape of the signal, enhancing the edge clarity of the signal, reducing misjudgments caused by blurred signal edges, and making it more suitable for subsequent symbol detection; after receiving the start modulation pulse signal, the symbol detection circuit controls the counter to be reset to zero and begins counting the amplitude changes of the envelope signal. When the end modulation pulse signal is received, the counting stops. This counting method based on a precise synchronization signal can ensure the accuracy of the counting, thereby improving the accuracy of symbol detection. In this way, the accuracy of signal processing and anti-interference ability are improved, solving the technical problems of unstable signal recognition and susceptibility to interference in complex electromagnetic environments of traditional readers / writers, while enhancing the data processing capability and reliability of the system. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the reader / writer provided in an embodiment of this application; Figure 2 This is a circuit diagram of the first embodiment of the demodulation circuit provided in this application; Figure 4 This is a circuit diagram of a second embodiment of the demodulation circuit provided in this application. Figure 5 This is a schematic diagram of the pulse shaping circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of the symbol detection circuit provided in an embodiment of this application; Figure 7 This is a circuit diagram of an electronic tag provided in an embodiment of this application; Figure 7 This is a schematic diagram of a square patch antenna provided in an embodiment of this application. Detailed Implementation

[0019] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0020] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0021] To address the related technical problems, embodiments of this application provide a reader / writer. The reader / writer provided in these embodiments is described below.

[0022] This reader can be used to read information from electronic tags.

[0023] Figure 1 A schematic diagram of the reader / writer provided in an embodiment of this application is shown. Figure 1 As shown, the reader includes a demodulation circuit, a pulse shaping circuit, a counter, and a symbol detection circuit.

[0024] The demodulation circuit is used to extract the envelope signal (Env_out signal) of the radio frequency signal emitted by the electronic tag. The envelope signal includes the original data information of the electronic tag.

[0025] The pulse shaping circuit is connected to the demodulation circuit, and the pulse shaping circuit is used to output an end-modulation pulse signal or an start-modulation pulse signal based on the envelope signal output by the demodulation circuit.

[0026] The counter is connected to the demodulation circuit and is used to count in response to changes in the amplitude of the envelope signal output by the demodulation circuit.

[0027] The symbol detection circuit is connected to the counter and the pulse shaping circuit. The symbol detection circuit is used to control the counter to be reset to zero and start counting in response to the start modulation pulse signal; to control the counter to stop counting in response to the end modulation pulse signal; and to perform symbol detection and demodulation based on the counter count value to obtain the original data information.

[0028] Specifically, refer to Figure 2 , Figure 2 A circuit diagram of a first embodiment of the demodulation circuit provided in this application.

[0029] The main function of the demodulation circuit (AM demodulation circuit) is to extract the envelope of the AM modulated signal from the radio frequency (RF) signal, which is the Env_out signal.

[0030] like Figure 2 As shown, the demodulation circuit may include a low-pass filter circuit, which is connected to a pulse shaping circuit and a counter. The low-pass filter circuit is used to attenuate the input radio frequency signal (RF signal) to obtain the Env_out signal, and outputs the Env_out signal to the pulse shaping circuit and the counter, as shown. Figure 2 The green line in the diagram indicates the signal path, and the output signal is Env_out.

[0031] In some embodiments, the low-pass filter circuit may include a first resistor. First transistor Second resistor Second transistor and the third resistor .

[0032] Among them, the first resistor One end receives the radio frequency signal; the first transistor The gate and the first resistor The other end is connected; the second resistor One end is connected to the first transistor The source of the first transistor is connected, and the other end is grounded; the second transistor The gate and the first transistor The source connection, the second transistor The source is grounded, and the second transistor The drain is connected to the pulse shaping circuit and the counter; the third resistor One end is connected to the first transistor The drain is connected, and the other end is connected to the second transistor. The drain connection.

[0033] RF signals are first generated by , and Gate-source capacitance , capacitor A low-pass filter network (low-pass filter circuit) composed of components connected in parallel is used for attenuation. As a voltage follower, it makes the upper half of the RF signal sine wave operate in the saturation region and the lower half enter the cutoff region. of and Together, they determine the discharge time constant required to obtain the AM envelope of the RF signal (i.e., the Env_out signal).

[0034] In some embodiments, such as Figure 3 As shown, Figure 3 This is a circuit diagram of a second embodiment of the demodulation circuit provided in this application. The demodulation circuit may further include a third transistor. and high-pass filter circuit.

[0035] In this circuit, the gate of the third transistor is connected to the low-pass filter circuit, and the source of the third transistor is grounded; the first terminal of the high-pass filter circuit is connected to the first transistor. The drain is connected, and the second terminal is connected to the third transistor. The drain is connected, and the third terminal is connected to the pulse shaping circuit and the counter.

[0036] In some embodiments, the high-pass filter circuit may include a fourth resistor. First capacitor Fifth resistor .

[0037] Among them, the fourth resistor One end is connected to the first transistor The drain is connected, and the other end is connected to the third transistor. Drain connection; first capacitor One end is connected to the fourth resistor One end is connected to the pulse shaping circuit and the counter; the fifth resistor One end is connected to the first capacitor One end is connected, and the other end is grounded.

[0038] like Figure 3 The blue line in the diagram indicates the signal path, and the output signal is Env_out.

[0039] To improve the slew rate of the envelope edge, from The Env_out signal from the drain is sent to the second stage ( The gate of ) and ultimately through the gate of ) and by , and This is achieved by constructing a high-pass RC filter (high-pass filter circuit). This generates a brief positive pulse each time the RF carrier reappears. These pulses are used to generate the Endmod signal, which is crucial for the timing control of the tags.

[0040] In some embodiments, the demodulation circuit may further include a fourth transistor. The fourth transistor The drain (D) is connected to the first capacitor. At the other end, the fourth transistor The source (S) and gate (G) are grounded.

[0041] In some embodiments, the transistor described above may be an NPN transistor or a PNP transistor, etc.

[0042] For example, specifically, such as Figure 3 or Figure 2 As shown, 13.56MHz The signal first passes through a 170 kΩ ( resistors NPN transistor 11fF of Capacitors and 2 megohms ( resistance and NPN transistor of An RC filter network consisting of capacitors connected in parallel. of The capacitor is designed with a high value, and by selecting a high aspect ratio, high instantaneous gain is achieved, thereby effectively filtering out the RF carrier frequency and extracting the required AM envelope signal. Among these, The transistor acts as a voltage follower, causing the upper half of the RF sine wave to operate in the saturation region and the lower half to be in the cutoff region. of Capacitor and The resistance together determines the discharge time constant of the AM envelope signal of the RF signal, ensuring the stable extraction of the envelope signal.

[0043] like Figure 3 As shown, The drain's Env_out signal is first transmitted to the second stage. The gate, then through the... capacitance, resistance and A high-pass RC filter composed of resistors generates short positive pulses each time the RF carrier recovers. These pulses are used to generate the Endmod signal, which is crucial for tag timing control. Figure 3 China and Israel of , For example.

[0044] In some embodiments, refer to Figure 4 , Figure 4 This is a schematic diagram of a pulse shaping circuit provided in an embodiment of this application.

[0045] The pulse shaping circuit (i.e., the EC (Eccles–Jordan) circuit) uses an improved monostable circuit, and its function is to generate the Endmod signal (end modulation pulse signal) and the Startmod signal (start modulation pulse signal).

[0046] like Figure 4 As shown, the pulse shaping circuit may include a fifth transistor. The sixth transistor The sixth resistor R D Power supply circuit, time constant circuit, seventh transistor And a push-pull circuit. The power supply circuit is used to power the fifth transistor. and the sixth transistor The power supply and time constant circuit are used to determine the pulse width generated by the pulse shaping circuit, and the push-pull circuit is used to buffer the signal output by the seventh transistor.

[0047] Among them, the fifth transistor The gate (G) of the fifth transistor is connected to the demodulation circuit. The source (S) of the transistor is grounded; the sixth transistor The drain (D) and the fifth transistor The drain (D) connection of the six transistors The source (S) and the fifth transistor The source (S) is connected; the sixth resistor R D One end is connected to the fifth transistor The drain (D) is connected; the first terminal of the power supply circuit is connected to the sixth resistor R. D The other end is connected, and the second end of the power supply circuit is grounded; the first end of the time constant circuit is connected to the fifth transistor. The drain (D) is connected, and the second terminal of the time constant circuit is connected to the third terminal of the power supply circuit; the seventh transistor The gate (G) of the seventh transistor is connected to the third terminal of the time constant circuit. The source (S) and the sixth transistor The source (S) connection, the seventh transistor The drain (D) of the circuit is connected to the second terminal of the time constant circuit; the first terminal of the push-pull circuit is connected to the seventh transistor. The drain (D) is connected, and the second terminal of the push-pull circuit is connected to the seventh transistor. The source (S) is connected, and the third terminal of the push-pull circuit is connected to the seventh transistor. The drain (D) is connected, and the fourth terminal of the push-pull circuit is connected to the sixth transistor. The gate is connected, and the fifth terminal of the push-pull circuit is connected to the symbol detection circuit.

[0048] In some embodiments, the power supply circuit may include a second capacitor. and the eighth transistor .

[0049] Among them, the second capacitor One end is connected to the sixth resistor R D The other end is connected, and the other end of the second capacitor is grounded; the eighth transistor The source and the second capacitor One end is connected to the eighth transistor. The drain of the circuit is connected to the second terminal of the time constant circuit.

[0050] In some embodiments, the time constant circuit may include a third capacitor. and the seventh resistor .

[0051] Among them, the third capacitor One end is connected to the fifth transistor The drain (D) is connected, and the third capacitor is connected. The other end is connected to the seventh transistor Gate connection; seventh resistor One end is connected to the third capacitor The other end is connected to the seventh resistor. The other end is connected to the eighth transistor The drain of the seventh transistor The drain (D) connection.

[0052] In some embodiments, the push-pull circuit may include a ninth transistor. 10th transistor and the eleventh transistor .

[0053] Among them, the ninth transistor The gate and the seventh transistor The drain connection, the ninth transistor The source and the seventh transistor The source connection, the ninth transistor The drain and the seventh transistor Drain connection; tenth transistor The source and the ninth transistor The source connection, the tenth transistor The gate and the ninth transistor The drain connection, the tenth transistor Drain connection sign detection circuit; eleventh transistor The gate and the sixth transistor Gate connection, eleventh transistor The source and the tenth transistor The drain connection, the eleventh transistor The drain and the ninth transistor The drain connection.

[0054] In some embodiments, the pulse shaping circuit may further include an eighth resistor. The eighth resistor One end is connected to the seventh transistor The drain connection, the eighth resistor The other end is connected to the second end of the time constant circuit, specifically, the eighth resistor. The other end can be the seventh resistor in a time constant circuit. The other end is connected.

[0055] In some embodiments, the pulse shaping circuit may further include a ninth resistor. Ninth resistor One end is connected to the third end of the push-pull circuit; specifically, the ninth resistor... One end can be connected to the ninth transistor in the push-pull circuit. The drain connection, the ninth resistor The other end is connected to the seventh transistor The drain connection.

[0056] In some embodiments, the pulse shaping circuit may further include an eighth resistor. In this case, the other end of the ninth resistor can be connected to the eighth resistor. The other end is connected.

[0057] Among them, the seventh transistor The drain and gate of the system voltage source connect.

[0058] In some embodiments, the pulse shaping circuit further includes a twelfth transistor. Thirteenth transistor and the fourteenth transistor .

[0059] Among them, the twelfth transistor The gate and source of the sixth transistor The source connection, the twelfth transistor The drain and the thirteenth transistor The gate and source are connected, the thirteenth transistor. The drain and the third capacitor The other end is connected to the fourteenth transistor. The source, gate and thirteenth transistor The drain connection, the fourteenth transistor The drain of the circuit is connected to the reference voltage source Vref.

[0060] In some embodiments, the pulse shaping circuit may further include a tenth resistor. The tenth resistor One end is connected to the tenth transistor Drain connection, tenth resistor The other end is connected to the eleventh transistor. The drain connection.

[0061] Specifically, the E-C circuit consists of A positive pulse at the gate of the transistor triggers the signal. The drain resistance of the transistor and the first stage of the E-C circuit (i.e. )Depend on Bypass capacitor and Power is supplied by a transistor (used as a diode). This method enables... and The drain voltage is not affected The effect of fluctuations. Therefore, the pulse width generated by the E-C circuit depends only on... and The time constant is used to ensure that the Endmod pulse signal and the Startmod pulse signal are immune to changes in RF field strength. To ensure... Stable charging conditions, the second stage of the EC circuit (i.e. The maximum gate voltage is limited by a reference voltage source inside the tag ( = 1.1V) and Transistor threshold voltage (Used as a diode for limiting) The sum of the voltages is within the range. To maintain a high switching rate between the Endmod pulse signal and the Startmod pulse signal, the second stage of the E-C circuit uses an RTL inverter (utilizing...) ) and by and A push-pull circuit composed of transistors is used for buffering to maintain the high slew rate characteristics of the Endmod pulse signal and the Startmod pulse signal, ensuring stable and fast signal transmission.

[0062] In some embodiments, refer to Figure 5 , Figure 5 This is a schematic diagram of a symbol detection circuit provided in an embodiment of this application.

[0063] The symbol detection circuit may include a pseudo-CMOS inverter, a counter, and a first D flip-flop. Second D flip-flop And a detection and demodulation circuit. The detection and demodulation circuit is used to perform symbol detection and demodulation based on the counter value to obtain the original data information. The bistable synchronous circuit includes a pair of D flip-flops.

[0064] In this circuit, the first terminal of the pseudo-CMOS inverter is connected to the pulse shaping circuit, the first terminal of the counter is connected to the demodulation circuit, the second terminal of the counter is connected to the second terminal of the pseudo-CMOS inverter, and the first D flip-flop... The first terminal is connected to the third terminal of the pseudo-CMOS inverter, and the first D flip-flop... The second terminal is connected to the third terminal of the counter, forming the second D flip-flop. The first terminal and the first D flip-flop The first terminal is connected to the second D flip-flop. The second terminal is connected to the fourth terminal of the counter, and one terminal of the detection demodulation circuit is connected to the first D flip-flop. Second D flip-flop The third terminal is connected to the other end of the demodulation circuit, which outputs the raw data information.

[0065] Specifically, a pseudo-CMOS inverter can include multiple unipolar transistors, such as Figure 5 As shown, Figure 5 Take a pseudo-CMOS inverter, which includes five unipolar transistors, as an example.

[0066] The i-th unipolar transistor One end is connected to the pulse shaping circuit, and the (i+1)th unipolar transistor One end is connected to the i-th unipolar transistor The other end is connected, where i takes values ​​from 1 to N-1, and N is the number of unipolar transistors contained in the multiple unipolar transistors, with the Nth unipolar transistor being... One end is connected to the (N-1)th unipolar transistor One end, the (N-1)th unipolar transistor The other end is connected to the second end of the counter, the Nth unipolar transistor. The other end is connected to the first D flip-flop The first end is connected.

[0067] A counter can include multiple D flip-flops, such as Figure 5 As shown, Figure 5 Take a counter consisting of four D flip-flops as an example.

[0068] Third D trigger The first terminal is connected to the demodulation circuit and the clock, and the (i+1)th D flip-flop... The first terminal and the i-th D flip-flop The second terminal D, the i-th D flip-flop The third end Connection, i+1th D flip-flop The fourth terminal R and the i-th D flip-flop The fourth terminal R is connected, and the value of i ranges from 3 to 3+M, where M is the number of D flip-flops contained in the multiple D flip-flops, and the 3+MD flip-flop... The fourth terminal R is connected to the (N-1)th unipolar transistor The other end is connected to the 3+MD trigger. The first terminal and the first D flip-flop The second terminal D is connected, and the 3+MD flip-flop is... The third end With the second D flip-flop The second end D is connected.

[0069] The counter can be a 4-bit ripple counter composed of cascaded D flip-flops, instead of a traditional synchronous counter with a shared clock signal, to reduce the fan-out load from the main clock node of the carrier divider. When OOK modulation is initiated, the ripple counter is initialized by the Startmod pulse signal. After completing the interval measurement, the high-order output of the counter is buffered and synchronized by a pair of D flip-flops. This synchronization process is triggered by the Startmod signal, which has been delayed by a four-stage pseudo-CMOS inverter.

[0070] Furthermore, for ease of understanding, the signal flow process of the aforementioned reader / writer is explained below: The AM demodulation circuit first extracts the envelope (Env_out) from the 13.56 MHz RF signal and generates Startmod and Endmod pulses through a pulse shaping circuit to mark the start and end of modulation. These pulses are then optimized by the pulse shaping circuit to ensure their fixed width is unaffected by voltage fluctuations before being passed to the symbol detection circuit. The symbol detection circuit uses the Startmod pulse to trigger a four-bit ripple counter to measure the modulation interval, thereby distinguishing different commands such as the detection request signal SENS_REQ or the read data channel signal RID.

[0071] With the continuous advancement of the construction of new power systems, intelligent management of power equipment faces multidimensional challenges. The monitoring data generated by power equipment is characterized by real-time nature, dynamism, and massive volume. Traditional paper labels are no longer sufficient to meet the needs of modern power systems for power equipment management, specifically manifesting in the following shortcomings: First, traditional power equipment labels rely on paper-based work order systems, resulting in scattered data storage and low retrieval efficiency; second, power equipment inspection operations are easily constrained by extreme environmental and climatic conditions, leading to insufficient monitoring continuity; third, manual recording methods lack multidimensional data analysis capabilities, making it difficult to support intelligent assessment of equipment status.

[0072] While traditional RFID (Radio Frequency Identification) electronic tags have been widely used in some industries, they cannot meet the actual needs of the special environment of smart grid power equipment scenarios. Specifically, this is reflected in the following aspects: 1) Lack of flexibility. Smart grid power equipment comes in various forms (such as transformers and cable connectors), and the size of traditional RFID tags is difficult to fit into confined spaces; 2) Insufficient transmission rate and poor real-time monitoring. Traditional RFID tags cannot meet the transmission rate requirements of smart grid scenarios due to limitations in communication protocol standards; 3) Insufficient security and confidentiality. The security and encryption deficiencies of traditional RFID tags do not meet the security requirements of sensitive data transmission equipment in smart grids. Vulnerabilities in traditional encryption methods pose a significant threat to data integrity, grid reliability, and physical equipment security.

[0073] To address the aforementioned issues, this embodiment provides an electronic tag, referring to... Figure 6 , Figure 6 This embodiment provides a circuit diagram of an electronic tag, such as... Figure 6 As shown, the electronic tag includes an electronic tag chip U1, an antenna, and peripheral circuitry. The peripheral circuitry is connected to preset pins of the electronic tag chip, and the antenna is also connected to preset pins of the electronic tag chip.

[0074] In one implementation, the electronic tag chip can be an integrated circuit chip based on near-field communication (NFC) technology. In a specific implementation, the integrated circuit chip based on NFC technology can be a PN532 chip. Figure 6 Taking the PN532 chip as an example, the U1 electronic tag chip is chosen because it has the following advantages: 1) Performance: Due to the large number of electronic devices in power systems, reading speed is a core indicator for NFC control chips. The PN532 chip used in this embodiment, supporting the ISO1443B protocol, can achieve a maximum communication rate of 424 kbit / s, far exceeding commonly used NFC chips on the market, such as ST ST25R3916, TI RF430FRL152H, and NXP PN65T. This significantly reduces the time required for the reader to read electronic tags on power equipment, saving time and costs. Furthermore, the PN532 chip also possesses superior stability, reliability, and energy efficiency, making it ideal for electronic tags on devices that require stable operation for extended periods and infrequent battery replacements.

[0075] 2) Compatibility: The PN532 chip used in this embodiment supports multiple standards including ISO14443A / B (Type 2 / Type 4), ISO15693, FeliCa, and NFC Forum Type 1 to Type 4 tags, covering more than 90% of scenarios. Furthermore, the PN532 chip has broad frequency adaptability, enabling stable operation across different frequency bands.

[0076] 3) Security and Confidentiality: The PN532 chip incorporates the AES-128 encryption algorithm, which is simple to implement and develop, and can be widely applied in the construction of new power systems. The PN532 chip supports encrypted data transmission and multiple authentication mechanisms, effectively preventing unauthorized access and protecting user privacy and data security. It is highly suitable for power equipment with high confidentiality requirements, ensuring that the electronic tags on them cannot be read by unfamiliar readers, thus preventing losses to the power system.

[0077] 4) Interface flexibility: The PN532 chip supports multiple interfaces such as SPI, I2C, and UART, which can be easily adapted to mainstream master control chips such as Arduino, Raspberry Pi, and STM32. Moreover, the PN532 chip provides a variety of interface options, so it can be easily integrated into the electronic tags required by the power system without being limited by the device.

[0078] A square patch antenna can be used.

[0079] Reference Figure 7 , Figure 7 This is a schematic diagram of a square patch antenna provided in an embodiment of this application. The square patch antenna can be a small-volume square patch antenna, including a radiating patch 1, a dielectric layer 2, and a ground layer 3. Through the application of technologies such as microstrip lines and high-frequency materials, the small-volume square patch antenna can achieve high-efficiency communication performance.

[0080] The above design has the following advantages: the square antenna configuration can provide good gain and directivity within a limited space, which can meet the high-speed data transmission requirements of electronic tags on power equipment that need real-time monitoring and rapid response; secondly, the small-volume patch antenna has strong flexibility, and its small size makes the electronic tag proposed in this embodiment applicable to most power equipment.

[0081] In some embodiments, the peripheral circuit may include a power supply circuit, a reset circuit, a crystal oscillator circuit, and a communication interface circuit.

[0082] The power supply circuit supplies operating voltage to the electronic tag chip through the VCC and GND pins.

[0083] In one specific embodiment, the power supply circuit can supply a 3.3V operating voltage to the chip via the VCC and GND pins, wherein a 110 nanofarad decoupling capacitor is used. It is used to filter out power supply noise, smooth voltage fluctuations, effectively suppress power supply ripple, reduce electromagnetic interference, and ensure the stability of power supply voltage.

[0084] In one embodiment, one end of the reset circuit is connected to a preset pin of the electronic tag chip, and the other end is connected to a preset voltage source. The reset circuit may include a diode D1, a resistor R1, and a capacitor C1, wherein the cathode of the diode D1 is connected to the preset pin of the electronic tag chip, one end of the resistor R1 is connected to the anode of the diode D1, the other end of the resistor R1 is connected to the preset voltage source, one end of the capacitor C1 is connected to one end of the resistor R1, and the other end of the capacitor C1 is connected to the other end of the resistor R1.

[0085] Specifically, such as Figure 6 As shown, the reset circuit uses diodes. 1kΩ resistor (It should be noted here that) Figure 1 The resistors mentioned are all in ohms, and the capacitors are 10 microfarads. This circuit constitutes a power-on reset circuit. During the charging and discharging process of the capacitor, the RC delay circuit generates a reset pulse, which controls the speed of current flow through the capacitor through the resistor, thereby controlling the speed of voltage change. This effectively eliminates power supply noise and transient interference, ensuring that the microcontroller only starts working after the power supply voltage has stabilized, and avoiding abnormal startup caused by voltage fluctuations.

[0086] In one implementation, diode D1 can be a light-emitting diode LED1 to form an LED indicator circuit. The LED is connected to the I / O pin of the microcontroller through a current-limiting resistor and can be controlled by the program to turn on or off. It can intuitively show the system operating status to the user or be used as a debugging tool. The LED indicator circuit intuitively shows the operating status of the device to the user through the design of the light signal.

[0087] In one embodiment, the first and second terminals of the crystal oscillator circuit are connected to preset pins of the electronic tag chip, and the third terminal of the crystal oscillator circuit is grounded. The crystal oscillator circuit may include a crystal oscillator X1, a capacitor C14, and a capacitor C15. The two ends of the crystal oscillator X1 are respectively connected to different preset pins of the electronic tag chip. One end of the capacitor C14 is connected to one end of the crystal oscillator X1, and the other end of the capacitor C14 is grounded. One end of the capacitor C15 is connected to the other end of the crystal oscillator X1, and the other end of the capacitor C15 is connected to the other end of the capacitor C14.

[0088] In a specific implementation, the crystal oscillator circuit can adopt a Pierce oscillator circuit, wherein the input pin of the electronic tag chip is connected to one end of the crystal oscillator X1, and the output pin is connected to the other end of the crystal oscillator X1. The crystal oscillator X1 is connected in parallel with the first capacitor and the second capacitor respectively to form a π-type network structure.

[0089] Specifically, such as Figure 6 As shown, the crystal oscillator circuit used consists of a 27.12MHz crystal oscillator and two 22 picofarad capacitors. constitute, The pin is connected to one end of X1 to receive the signal from the crystal oscillator and form a feedback path for oscillation through the internal inverting amplifier; The pin is connected to the other end of the crystal oscillator, feeding back the output signal of the internal inverting amplifier to the crystal oscillator. Together, they form the Pierce Oscillator circuit, ensuring that the system can obtain a high-precision, low-drift clock signal, and guaranteeing the timing synchronization and stable operation of the microcontroller core, peripheral modules and communication modules.

[0090] In some embodiments, the communication interface circuit described above includes resistors R3, R4, R5, R6, R7, and R9, capacitors C4, C5, C6, C7, C8, C9, C12, and C13, inductors L1 and L2, and a pin connector.

[0091] One end of inductor L1 is connected to a preset pin of the electronic tag chip; one end of capacitor C6 is connected to the other end of inductor L1; the other end of capacitor C6 is grounded; one end of capacitor C4 is connected to one end of capacitor C6; one end of capacitor C5 is connected to the other end of capacitor C4; the other end of capacitor C5 is connected to the other end of capacitor C6; one end of resistor R4 is connected to one end of capacitor C5; the other end of resistor R4 is connected to the other end of capacitor C5; one end of resistor R3 is connected to one end of resistor R4; the first end of the pin connector is connected to the other end of resistor R3; the second end of the pin connector is connected to the other end of resistor R4; one end of capacitor C6 is connected to the third end of the pin connector; one end of resistor R5 is connected to the other end of capacitor C6; the other end of resistor R5 is connected to the second end of the pin connector; the capacitor... One end of capacitor C7 is connected to one end of resistor R5. The other end of capacitor C7 is connected to the second end of the pin connector. One end of capacitor C9 is connected to one end of capacitor C7. One end of capacitor C8 is connected to the other end of capacitor C9. The other end of capacitor C8 is connected to the other end of capacitor C6. One end of inductor L2 is connected to one end of capacitor C8. The other end of inductor L2 is connected to the preset pin of the electronic tag chip. One end of resistor R7 is connected to one end of capacitor C8. One end of capacitor C12 is connected to the other end of resistor R7. One end of resistor R9 is connected to the other end of capacitor C12. The other end of resistor R9 is connected to the preset pin of the electronic tag chip. One end of capacitor C13 is connected to one end of resistor R9, the other end of resistor R9, and the preset pin of the electronic tag chip. The other end of capacitor C13 is grounded.

[0092] Depend on - and , Together with the inductor L, they form a filter circuit to achieve impedance matching, ensure signal integrity, and suppress noise and interference, thereby improving the data accuracy of ADC sampling.

[0093] Figure 6 The part marked ANT is the pin connector used to connect the antenna, which is then connected to the circuit through this pin connector.

[0094] In one specific embodiment, the communication interface circuit consists of a UART (Universal Asynchronous Receiver / Transmitter) interface and two 560 nanohenry inductors. (Send) and The (receive) pin is used for serial data transmission. and As a common-mode choke, it suppresses common-mode noise through high impedance while maintaining the integrity of differential-mode signals, thus reducing the impact of electromagnetic interference on communication.

[0095] in, Figure 6The Header section also refers to the pin connector, which is used for electrical connections to other modules or external devices for debugging and functional expansion.

[0096] In some embodiments, the peripheral circuit may further include a capacitor C3, the two ends of which are respectively connected to different preset pins of the electronic tag chip.

[0097] In some embodiments, the peripheral circuit described above may further include a capacitor C2 and a resistor R2. One end of the resistor R2 is connected to a preset pin of the electronic tag chip, one end of the capacitor C2 is connected to the other end of the resistor R2, and the other end of the capacitor C2 is grounded.

[0098] In some embodiments, the peripheral circuit may further include a patch button KEY1, one end of which is connected to a preset pin of the electronic tag chip and the cathode of diode D1, and the other end is grounded.

[0099] In some embodiments, the peripheral circuitry described above may further include a key input circuit, which is implemented by an 8-bit key matrix and its surrounding circuitry. The 8-bit key matrix is ​​connected to corresponding pins, allowing users to input commands or control functions via keys. Through appropriate software programming, each key can correspond to a different function, greatly enhancing the system's flexibility and user experience.

[0100] exist Figure 6 In China, with , , , , , , , , , , , , , , , , , , , , , , , For example.

[0101] This embodiment provides a near-field communication system, including the aforementioned electronic tag and NFC reader. At the hardware design level, the electronic tag uses the PN532 chip as its core, achieving high-precision timing control through an improved EC monostable circuit. The circuit structure between the antenna and the chip effectively reduces signal reflection and signal loss and distortion during transmission, ensuring signal transmission efficiency and integrity between the antenna and the chip. Furthermore, the impedance matching network acts as a filter, suppressing external noise and interference, and improving the system's anti-interference capability. By designing the reader's tag demodulation circuit, pulse shaping circuit, and symbol detector, accurate decoding and interval measurement of the OOK modulated signal are achieved, ensuring stable communication under RF field strength fluctuations.

[0102] This application also provides an electronic device that includes the aforementioned reader / writer.

[0103] In all the examples shown and described above, any specific value should be interpreted as merely exemplary and not as a limitation; therefore, other examples of exemplary embodiments may have different values.

[0104] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0105] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

[0106] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A reader / writer, characterized in that, include: A demodulation circuit is used to extract the envelope signal of the radio frequency signal emitted by the electronic tag, the envelope signal including the original data information of the electronic tag; A pulse shaping circuit is connected to the demodulation circuit, and the pulse shaping circuit is used to output an end modulation pulse signal or a start modulation pulse signal based on the envelope signal output by the demodulation circuit. A counter, connected to the demodulation circuit, is used to count in response to changes in the amplitude of the envelope signal output by the demodulation circuit. A symbol detection circuit is connected to the counter and the pulse shaping circuit, and the symbol detection circuit is used to control the counter to be reset to zero and start counting in response to the start modulation pulse signal; The counter is stopped counting in response to the end modulation pulse signal; Furthermore, symbol detection and demodulation are performed based on the counter's count value to obtain the original data information; wherein, The pulse shaping circuit includes: A fifth transistor, the gate of which is connected to the demodulation circuit, and the source of which is grounded; A sixth transistor, wherein the drain of the sixth transistor is connected to the drain of the fifth transistor, and the source of the sixth transistor is connected to the source of the fifth transistor; A sixth resistor, one end of which is connected to the drain of the fifth transistor; A power supply circuit is provided to supply power to the fifth transistor and the sixth transistor. The first terminal of the power supply circuit is connected to the other terminal of the sixth resistor, and the second terminal of the power supply circuit is grounded. A time constant circuit is provided, which is used to determine the pulse width generated by the pulse shaping circuit. The first terminal of the time constant circuit is connected to the drain of the fifth transistor, and the second terminal is connected to the third terminal of the power supply circuit. A seventh transistor, the gate of which is connected to the third terminal of the time constant circuit, the source of which is connected to the source of the sixth transistor, and the drain of which is connected to the second terminal of the time constant circuit. A push-pull circuit is provided to buffer the signal output by the seventh transistor. The first terminal of the push-pull circuit is connected to the drain of the seventh transistor, the second terminal of the push-pull circuit is connected to the source of the seventh transistor, the third terminal of the push-pull circuit is connected to the drain of the seventh transistor, the fourth terminal of the push-pull circuit is connected to the gate of the sixth transistor, and the fifth terminal of the push-pull circuit is connected to the symbol detection circuit.

2. The reader / writer according to claim 1, characterized in that, The demodulation circuit includes a low-pass filter circuit, which is connected to the pulse shaping circuit and the counter.

3. The reader / writer according to claim 2, characterized in that, The low-pass filter circuit includes: A first resistor, one end of which receives the radio frequency signal; The first transistor, the gate of the first transistor is connected to the other end of the first resistor; The second resistor has one end connected to the source of the first transistor and the other end grounded. The second transistor has its gate connected to the source of the first transistor, its source grounded, and its drain connected to the pulse shaping circuit and the counter. A third resistor, one end of which is connected to the drain of the first transistor and the other end of which is connected to the drain of the second transistor.

4. The reader / writer according to claim 3, characterized in that, The demodulation circuit further includes: The third transistor has its gate connected to the low-pass filter circuit and its source grounded. A high-pass filter circuit, wherein the first terminal of the high-pass filter circuit is connected to the drain of the first transistor, the second terminal is connected to the drain of the third transistor, and the third terminal is connected to the pulse shaping circuit and the counter.

5. The reader / writer according to claim 4, characterized in that, The high-pass filter circuit includes: A fourth resistor, one end of which is connected to the drain of the first transistor and the other end of which is connected to the drain of the third transistor; A first capacitor, one end of which is connected to the other end of the fourth resistor, and the other end of which is connected to the pulse shaping circuit and the counter; The fifth resistor has one end connected to the other end of the first capacitor and the other end grounded.

6. The reader / writer according to claim 5, characterized in that, The demodulation circuit further includes: The fourth transistor has its drain connected to the other end of the first capacitor, and its source and gate are grounded.

7. The reader / writer according to claim 1, characterized in that, The power supply circuit includes: The second capacitor has one end connected to the other end of the sixth resistor, and the other end grounded. The eighth transistor has its source connected to one end of the second capacitor and its drain connected to the second terminal of the time constant circuit.

8. The reader / writer according to claim 7, characterized in that, The time constant circuit includes: The third capacitor has one end connected to the drain of the fifth transistor and the other end connected to the gate of the seventh transistor. The seventh resistor has one end connected to the other end of the third capacitor and the other end connected to the drain of the eighth transistor and the drain of the seventh transistor.

9. The reader / writer according to claim 8, characterized in that, The push-pull circuit includes: A ninth transistor, wherein the gate of the ninth transistor is connected to the drain of the seventh transistor, the source of the ninth transistor is connected to the source of the seventh transistor, and the drain of the ninth transistor is connected to the drain of the seventh transistor. The tenth transistor has its source connected to the source of the ninth transistor, its gate connected to the drain of the ninth transistor, and its drain connected to the symbol detection circuit. The eleventh transistor has its gate connected to the gate of the sixth transistor, its source connected to the drain of the tenth transistor, and its drain connected to the drain of the ninth transistor.

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