Non-volatile memory rapid erasing method based on channel hot electron induced hot hole injection and application of non-volatile memory rapid erasing method

Abstract

The invention discloses a fast erasing method for a nonvolatile memory based on channel hot electron induced hot hole injection and application of the fast erasing method. In a nonvolatile flash memory with split gates, positive source voltage, positive drain voltage and negative storage gate voltage are applied when a selection gate (MG) and a storage node (MS) are started; high-energy channel hot electrons are generated in the channel; high-density hot holes are generated in a channel region through the collision ionization effect of channel hot electrons; hot holes are injected into the charge trapping layer through the tunneling oxide layer, so that the neutralization of stored electrons is completed, and the erasing operation is realized. According to the invention, the collision ionization effect of hot electrons is utilized to generate high-density hot holes, and the hot holes are injected into the charge trapping layer for rapid erasing, so that the erasing efficiency is remarkably improved, the electric field stress is reduced, and the durability and retention performance of equipment are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and relates to a non-volatile memory fast erasing method based on channel hot electron induced hot hole (CHH) injection and application thereof. BACKGROUND

[0002] As an important component of semiconductor memory devices, non-volatile memories have been widely used in various electronic devices, including embedded systems, mobile terminals and data centers. The performance parameters, especially the erasing speed, reliability and long-term stability, directly affect the overall efficiency and service life of the storage system. Among many non-volatile memory structures, split-gate charge-trapping flash memory is of great concern due to its high programming efficiency and good charge retention characteristics.

[0003] In the erasing operation of split-gate flash memory, the band-gap band-to-band tunneling hot hole injection (BBHH) mechanism is traditionally used. This mechanism forms a strong electric field region by applying a negative bias to the storage gate and a high positive bias to the drain at the same time, inducing band-to-band tunneling effect, thereby generating hot holes near the drain junction. These hot holes then inject charge trapping layer through tunneling oxide layer and neutralize the storage electrons to achieve the erasing function. However, this method has the problem of slow erasing process due to the limited rate and spatial density of BBHH generated holes, resulting in typical erasing time usually in the order of milliseconds, which is difficult to meet the needs of high-speed storage systems. The strong electric field is concentrated near the drain junction, which easily causes local damage to the tunneling oxide layer, aggravates the generation of interface traps, and affects the durability and long-term reliability of the device. The hot holes generated by BBHH are relatively limited in spatial distribution and density, causing storage charge mismatch effect (TCME), which further inhibits the improvement of erasing efficiency. To improve the erasing efficiency, the operating voltage often needs to be increased, which in turn leads to increased power consumption and may cause reliability degradation. Obviously, it has the problems of slow erasing speed, large local electric field stress and difficult to maintain memory window. These problems seriously limit the further application of flash memory, especially in the storage demand of high speed, large capacity and high reliability.

[0004] Therefore, how to significantly improve the erasing speed and uniformity while maintaining low power consumption and electric field stress, and effectively suppress the TCME effect, has become a technical problem to be solved in the field of memory. SUMMARY

[0005] The application provides a non-volatile memory erasing method based on channel hot electron induced hot hole injection and application thereof, aiming at solving the problems in the existing BBHH erasing mechanism, especially the slow erasing speed, large electric field stress and low erasing efficiency caused by the storage charge mismatch effect (TCME). The method utilizes the collision ionization effect of hot electrons to generate high-density hot holes, and injects the hot holes into the charge trapping layer for rapid erasing, thereby significantly improving the erasing efficiency, reducing the electric field stress, and improving the durability and retention performance of the device.

[0006] In a first aspect, the application provides a non-volatile memory fast erasing method based on channel hot electron induced hot hole injection, comprising the following steps: Step S1, in a non-volatile flash memory with split gates, a positive source voltage, a positive drain voltage and a negative storage gate voltage are applied under the condition that the select gate MG and the storage node MS are turned on, so as to generate high-energy channel hot electrons in the channel; Step S2, high-density hot holes are generated in the channel region through the collision ionization effect of the channel hot electrons; Step S3, the hot holes are injected into the charge trapping layer through the tunneling oxide layer, the neutralization of the storage electrons is completed, and the erasing operation is realized.

[0007] Preferably, the condition for turning on the select gate MG and the storage node MS is that the storage node voltage and the select gate voltage are both greater than 0V. More preferably, the storage node voltage V MS = 5V, and the select gate voltage V MG = 1V.

[0008] Preferably, the source voltage Vs = 0-0.2V, the drain voltage V D = 4.4 ~ 4.8V; Preferably, the storage gate voltage V MD = -5.5 ~ -4.5 V, and more preferably -5 V; Preferably, the erasing time TE ≤ 100 μs.

[0009] Preferably, the generation position of the hot holes is distributed in the deep depletion region of the channel, so that the spatial distribution range of the hot holes is greater than the local hole distribution area under the traditional band-to-band tunneling (BBHH) mechanism, thereby improving the hot hole injection efficiency.

[0010] Preferably, the generation rate of the hot holes through collision ionization is in the range of The above, and the peak concentration of holes in the channel reaches to realize fast and uniform erasing.

[0011] Preferably, the hot hole injection process occurs in a region with a tunnel oxide thickness of 2.5-3.5 nm, ensuring that the hot hole can overcome the barrier and achieve efficient injection.

[0012] In a second aspect, the present application provides a non-volatile memory chip, the erase operation of which uses the above method to achieve charge neutralization through channel hot electron induced hot hole injection.

[0013] The present application has at least the following beneficial effects: The present application uses channel hot electron to excite hot holes, generates a large number of hot holes through the collision ionization effect of hot electrons, and then realizes the erase operation. Compared with the traditional BBHH erase mechanism, the CHH erase mechanism has the following significant features: (1) Hot holes excited by hot electrons: When a certain voltage is applied between the source and the drain, the electrons in the channel gain enough energy to collide and ionize, generating a large number of hot holes. The density and distribution range of hot holes in the channel greatly exceed that of hot holes generated by BBHH, forming a uniform distribution, which makes the erase process more efficient.

[0014] (2) Hot hole injection efficiency: By applying a suitable negative storage gate voltage, hot holes can be injected into the charge trapping layer through the tunneling effect. Because the distribution of hot holes is more extensive, it can more effectively neutralize the stored electrons, thereby improving the erase efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0016] Figure 1 is a non-volatile flash memory cell structure with split gate provided by the embodiment of the present application.

[0017] Figure 2 is a voltage bias configuration diagram for different methods of operation of the flash memory cell provided by the embodiment of the present application. Figure 1 The voltage bias configuration diagram for different methods of operation of the flash memory cell provided by the embodiment of the present application, wherein (a) CHE (channel hot electron programming), (b) BBHH (band gap band-to-band tunneling hot hole erase), (c) CHH (channel hot electron induced hot hole erase of the present application).

[0018] Figure 3Figure is a TCAD simulation diagram of the BBHH and CHH erasing operation provided by the embodiment of the present application, wherein (a) is the trapped hole distribution after BBHH erasing, (b) is the trapped hole distribution after CHH erasing, (c) is the electrostatic potential diagram under the BBHH bias, (d) is the electrostatic potential diagram under the CHH bias, (e) is the change of the hole density with the BBHH erasing process, (f) is the change of the hole density with the CHH erasing process, (g) is the change of the hole generation rate with the BBHH erasing process, (h) is the change of the hole generation rate with the CHH erasing process, (i) is the electron current density in the CHH erasing process, and (j) is a schematic diagram of the CHH erasing principle in the device.

[0019] Figure 4 Figure is a diagram of the change of the electrical performance with time under different erasing operations provided by the embodiment of the present application, wherein (a) is the BBHH, and (b) is the CHH.

[0020] In the figure, 1 is a substrate, 2 is a source, 3 is a drain, 4 is a select gate, 5 is a storage node, 6 is a storage gate, 7 is a storage layer, 71 is a blocking oxide layer, 72 is a charge trapping layer, 73 is a tunneling oxide layer, and 8 is an isolation oxide layer. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be described below in detail with reference to the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0022] The terms “comprising” and “having” and any variations thereof mentioned in the embodiments of the present application are intended to cover the inclusions without exclusivity.

[0023] The common BBHH erasing in the existing erasing mechanism is to generate hot holes by band-to-band tunneling (BTBT) effect. A negative storage gate voltage (V MD ) and a larger source-drain voltage (V SD ) form a tunneling window to allow band-to-band tunneling to generate hot holes. The generated hot holes are mainly concentrated near the drain and are injected into the charge trapping layer through the tunneling oxide layer. Since the select gate V MG = 0 V, no additional electric field can be provided, the erasing effect is limited, and the erasing speed is slow. As can be seen from the above defects, there are problems such as slow erasing speed, large electric field stress, and low erasing efficiency caused by the storage charge mismatch effect (TCME) in the prior art.

[0024] Based on this, the embodiment of the present application provides a non-volatile memory fast erasing method based on channel hot electron induced hot hole injection (CHH for short), and the principle is as follows: 1. Hot electron excitation and collision ionization The erasing method of the present application relies on the collision ionization effect of channel hot electrons. When a proper voltage bias is applied in the channel, the strong electric field between the source and the drain will make the electrons in the channel gain enough energy. These hot electrons will transition to high-energy states and undergo collision ionization reactions with atoms in the channel, generating a large number of hot holes.

[0025] 2. Generation and injection of hot holes The generated hot holes have high energy and can overcome the energy barrier of the tunneling oxide layer through the tunneling effect, thereby being injected into the charge trapping layer (such as a silicon nitride layer). The injection of hot holes directly neutralizes the stored electrons, realizing the erasing operation.

[0026] 3. Advantages of CHH mechanism Unlike the traditional BBHH erasing mechanism, the hot holes generated by the collision ionization of hot electrons in CHH have higher density and more extensive spatial distribution. This uniformly distributed hot hole can effectively overlap with the stored electrons, improving the erasing efficiency and avoiding the TCME effect existing in the traditional BBHH mechanism.

[0027] Referring to the accompanying drawings, Figure 1 The non-volatile memory provided by the embodiment includes: a substrate 1; a source electrode 2 (S) and a drain electrode 3 (D) embedded in the two sides of the substrate 1 respectively; wherein there is also a channel region between the source electrode 2 and the drain electrode 3; a selection gate 4 (MG) disposed above the substrate 1; a storage node 5 (MS) and a storage gate 6 (MD) both disposed above the substrate 1 and located on the two sides of the selection gate 4 respectively; The storage node 5 (MS), the storage gate 6 (MD), and the substrate 1 are all provided with a storage layer 7 (ONO), and the storage layer 7 includes a blocking oxide layer 71, a charge trapping layer 72, and a tunneling oxide layer 73 in sequence from the storage node to the substrate 1.

[0028] Among them, the source electrode 2 is the entrance of the current, and the drain electrode 3 is the exit of the current. By applying a proper voltage bias between the source and the drain, the electrons in the channel will be accelerated and enter or leave the storage unit. These two electrodes play a role in controlling the direction and intensity of the current flow in the programming and erasing process.

[0029] The storage node 5 (MS) and the storage gate 6 (MD) are two independent storage nodes that store the charge in the flash memory cell. Due to the split-gate design, each storage node can be programmed or erased independently, thus improving the storage density. The storage node 5 (MS), the storage gate 6 (MD) and the middle select gate 4 (MG) are electrically isolated. They control the stored charge through voltage bias, thus realizing the programming and erasing of data.

[0030] The select gate 4 (MG) is a key component in the split-gate structure, located between the MS and the MD. The function of the select gate 4 is to selectively control the programming and erasing of the storage node 5 (MS) and the storage gate 6 (MD), ensuring that they can be operated independently without interfering with each other. In the erasing operation, the voltage bias of the select gate adjusts the flow of electrons in the channel, affecting the charge state of the storage node.

[0031] The channel region between the source and the drain is the main path of current flow. This region is controlled by the application of the source-drain voltage (V SD ) and the storage gate voltage (V MD ). In the erasing operation, the bias of the source-drain voltage and the storage gate voltage will affect the movement of electrons in the channel and the generation of hot electrons. Through the application of high voltage, hot electrons in the channel are accelerated and generate hot holes in the channel region through the effect of collision ionization. These hot holes will then be injected into the charge trapping layer through the tunneling oxide layer, thus realizing the erasing operation. In this design, the region where the deep depletion region of the channel region is formed is the key region for the generation of hot holes, ensuring the generation of high-density hot holes and efficient erasing.

[0032] The charge trapping layer 72 is composed of silicon nitride (Si3N4) as the core area of charge storage. This layer is the N part of the ONO structure, which plays a role in capturing stored charge.

[0033] The tunneling oxide layer 73 (Tunneling Oxide) is located between the charge trapping layer and the channel region, allowing hot holes to be injected into the charge trapping layer through the tunneling effect, completing the erasing operation. The preferred thickness of the tunneling oxide layer is 2.5-3.5 nm.

[0034] The blocking oxide layer 71 (Blocking Oxide) is located above the charge trapping layer, which can effectively isolate the stored charge and prevent the diffusion of charge, ensuring long-term stable storage of charge.

[0035] The top of the storage node 5 (MS) and the storage gate 6 (MD) of the embodiment also has an isolation oxide layer 8 and a metal silicide layer, and the isolation oxide layer 8 is close to the select gate 4, and there is an isolation medium between them.

[0036] The above-mentioned non-volatile memory fast erasing method based on channel hot electron induced hot hole injection is specifically: Step S1: Operating bias condition and hot hole generation S11. Voltage bias setting The gate voltage setting must be greater than 0V, and the storage node voltage V MS =5V, the gate voltage V MG = 1V is selected to maintain the channel conduction. In order to excite hot electrons in the channel, a specific voltage bias needs to be applied. Specifically, the source voltage Vs=0-0.2V, the drain voltage V D =4.4 ~4.8V, the source-drain voltage (V SD ) between the source and the drain is set to 4.4 ~4.8V, preferably 4.6V, and the storage gate voltage (V MD ) is set to -5.5 ~ -4.5 V, and the preferred value in the embodiment is -5 V. Through this bias, hot electrons obtain sufficient kinetic energy in the channel and start collision ionization to generate hot holes.

[0037] S12. Spatial distribution of hot holes Under the CHH mechanism, the generation of hot holes is not limited to a small area, but is widely distributed in the channel under the MS or MD. Compared with the local generation in the BBHH mechanism, the hot holes generated by the CHH mechanism have a higher spatial distribution density. The generated hot holes not only cover the entire channel area, but also can neutralize the stored electrons in a larger range, improving the erasing effect.

[0038] Step S2: Hot hole injection into charge trapping layer By applying a negative storage gate voltage (V MD =-5.5 ~ -4.5 V, preferably -5 V in the embodiment), hot holes will tunnel through the tunneling oxide and be effectively injected into the charge trapping layer. The hot hole injection process in the embodiment occurs in the region where the tunneling oxide is 2.5-4.0 nm thick. This process ensures that hot holes can directly neutralize stored electrons to complete the erasing operation.

[0039] The above-mentioned CHH mechanism erasing method at least achieves the following effect improvements: Improved erasing efficiency: Due to the high density and wide distribution of hot holes, more stored electrons can be neutralized by hot holes in a short time during the erasing process, greatly improving the erasing efficiency. Compared with the traditional BBHH mechanism, the CHH mechanism completes the erasing in a shorter time, and there is no local electric field stress concentration problem, avoiding excessive damage to the device.

[0040] Reduced electric field stress: Due to the uniform distribution of thermal holes, excessively large electric field stress regions are not formed during the erasure process. This makes the CHH erasure process gentler than the traditional BBHH erasure, reducing damage to the device interface. Reduced electric field stress not only extends the device's lifespan but also improves long-term write / erase performance.

[0041] Suppression of the TCME effect: The charge mismatch effect (TCME) is a problem in conventional BBHH erasure, stemming from the spatial distribution difference between hot holes and stored electrons during erasure. In the CHH mechanism, the widespread distribution of hot holes effectively suppresses the TCME effect, ensuring the efficiency and reliability of the erasure operation.

[0042] Erasing speed and durability: Compared to the traditional BBHH mechanism, the method of this invention can complete the erasure within 0.1 milliseconds, which is about 100 times faster than BBHH. At the same time, the low electric field stress and effective electron neutralization during the erasure process enable the device to maintain a stable memory window (MW) after up to 100k erase-write cycles, and the retention performance can reach more than 10 years at 175°C.

[0043] See appendix Figure 2 From (a), it can be seen that the voltage condition applied by the CHE mechanism programming operation is the source voltage V. S = 0 V, drain voltage V D = 4.4 V, storage gate voltage V MD = 6.4 V, storage node voltage V MS = 5 V, select gate voltage V MG = 1 V, source voltage V S = 0.2 V. Its erase / write time is 10 μs. In CHE programming, a strong electric field is generated in the channel by combining the source / drain voltage and the storage gate voltage, accelerating hot electrons to a high-energy state. These hot electrons are injected into the charge trapping layer through tunneling, thereby completing the storage operation. Storage node voltage (V MS ) and storage gate voltage (V MD The same principle applies to ensure effective electron injection.

[0044] See appendix Figure 2 From (b), it can be seen that the voltage condition applied during the erase operation of the BBHH mechanism is the source voltage V. S = 0 V, drain voltage V D = 5.4 V, storage gate voltage V MD =-5.4 V, storage node voltage V MS = 0V, select gate voltage V MG =0V, source voltage V S= 1.8V. Its erase / write time is 10 ms. BBHH erase utilizes the bandgap band-to-band tunneling (BTBT) effect to generate hot holes. Negative storage gate voltage (V MD ) and a large source-drain voltage (V SD Together, they form a tunneling window, allowing bandgap band-to-band tunneling to generate hot holes. The generated hot holes are mainly concentrated near the drain and are injected into the charge trapping layer through the tunneling oxide layer. Due to the selection of gate V... MG = 0 V, cannot provide an additional electric field, the erasing effect is relatively limited, and the erasing speed is slow.

[0045] See appendix Figure 2 As can be seen from (c), the voltage condition applied during the erase operation of the CHH mechanism of this invention is the source voltage V. S = 0V, drain voltage V D =4.6V, storage gate voltage V MD =-5V, storage node voltage V MS = 5V, select gate voltage V MG =1V, source voltage V S = 0.2V. Its erase / write time is 100 μs. In the CHH erase mechanism, through the source-drain voltage (V SD ) and storage gate voltage (V MD The combination of electrons generates hot electrons in the channel, which ionize through collisions to create hot holes. These hot holes are then injected into the charge trapping layer via tunneling and neutralize the stored electrons. Unlike the BBHH erase mechanism, in CHH erase, both the selected gate (MG) and the storage node (MS) must be enabled (V). MS = 5 V, V MG = 1 V), to ensure effective generation and uniform injection of hot holes. Compared with BBHH, the CHH mechanism can significantly improve the erasure speed (about 0.1ms) and erasure effect.

[0046] The main difference between the three operations mentioned above is: Voltage settings: In CHE and CHH, the memory gate voltage (VMD) is negative, but it is mainly used for programming in CHE and for the erase process in CHH. In BBHH, the memory gate voltage (VMD) is also negative, but VMS is 0V, and the gate MG is selected as 0V, which limits the area where hot holes are generated.

[0047] Hot hole generation: CHE is the programming process, which accelerates the injection of hot electrons into the memory layer. BBHH generates hot holes through band-to-band tunneling, resulting in a limited distribution of hot holes. CHH generates hot holes through collisional ionization of hot electrons in the channel, resulting in a wider and more uniform distribution, and a much faster erase rate than BBHH.

[0048] Erase efficiency and speed: CHE is mainly used for programming, and is not involved in erasing. The BBHH erasing speed is slow (10 ms), and the erase efficiency is low, and there is a large electric field stress. The CHH erasing speed is the fastest (0.1 ms), the erasing effect is more uniform and efficient, and the electric field stress is low, and the device damage is small.

[0049] Referring to the accompanying drawings, the embodiments of the present application are described in detail. Figure 3 In (a)- Figure 3 As can be seen from (j), the rate of generation of CHH hot holes by collision ionization in this embodiment is in the range of 10~11cm-3s-1, which is higher than that of the BBHH. The above, and the peak concentration of holes in the channel reaches 1012cm-3, which is higher than that of the BBHH. During the erasing operation, through the spatial overlap of hot electrons and hot holes in the channel, complete neutralization of electrons and holes is realized, thereby eliminating the storage charge mismatch effect (TCME), improving the erasing uniformity and reliability. The electric field stress during erasing is reduced by more than 30%, thereby reducing the formation of Si / SiO2 interface traps, delaying device migration and interface degradation.

[0050] Referring to the accompanying drawings, the embodiments of the present application are described in detail. Figure 4 In (a)- Figure 4 As can be seen from (b), the electrical performance changes with time under the BBHH and CHH erasing operation. The CHH erasing mechanism can realize about 100 times faster erasing speed than the BBHH mechanism, and the erasing voltage is reduced by 1~2V. After 100k programming / erasing cycles, the memory window attenuation of the device is less than 15%, and the device has a data retention capability of more than 10 years at 175°C.

[0051] The above is the preferred embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles of the present application, can make a number of improvements and refinements, these improvements and refinements are also considered to be within the scope of protection of the present application.

Claims

1. A method for fast erase of non-volatile memory based on channel hot electron induced hot hole injection, comprising: The method comprises: In a split-gate non-volatile flash memory, a positive source voltage, a positive drain voltage and a negative memory gate voltage are applied under the open condition of a select gate MG and a memory node MS to generate high-energy channel hot electrons in the channel; High-density hot holes are generated in the channel region through collision ionization of the channel hot electrons; The hot holes are injected into the charge trapping layer through the tunneling oxide layer to neutralize the stored electrons, thereby realizing the erase operation.

2. The method of claim 1, wherein, The open condition of the select gate MG and the memory node MS is that the memory node voltage and the select gate voltage are both greater than 0V.

3. The method of claim 2, wherein, The storage node voltage V MS = 5V, and the select gate voltage V MG = 1V.

4. The method of claim 1, wherein, Source voltage Vs = 0 - 0.2V, drain voltage V D = 4.4 ~ 4.8V.

5. The method of claim 1, wherein, The storage gate voltage V MD = -5.5 ~ -4.5 V.

6. The method of claim 1, wherein, The erase time TE is less than or equal to 100 μs.

7. The method of claim 1 wherein, The generation position of the hot holes is distributed in the deep depletion region of the channel.

8. The erasing method according to claim 1 or 2, characterized by, The hot holes are generated at a rate by collision ionization that is The above, and a peak concentration of holes in the channel reaches .

9. The erasing method of claim 1, wherein, The injection process of the hot holes occurs in a region with a tunneling oxide layer thickness of 2.5-3.5 nm.

10. A non-volatile memory chip, comprising: The erase operation of the chip is performed by the method of any one of claims 1-9 to induce hot hole injection by channel hot electrons to achieve charge neutralization and complete erasing.

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