Receiver front-end circuit, control chip and electronic equipment

Abstract

The invention provides a receiver front-end circuit, a control chip and electronic equipment, and belongs to the technical field of artificial intelligence chips, and the receiver front-end circuit comprises a first module, a second module, a reference voltage generation module, a common-mode voltage generation module and a state machine; the first module comprises a differential amplifier, a common-mode feedback circuit, a first resistor, a second resistor, a first switch tube, a second switch tube and a current mirror; the positive phase output end of the differential amplifier is connected with the control end of the first switching tube; the negative phase output end of the differential amplifier is connected with the control end of the second switching tube; the normal phase input end of the second comparator is connected with the first end of the second switch tube through the first RC filter; the state machine is connected with the common-mode voltage generation module and used for controlling the register to generate a control code according to the comparison result of the second comparator, and the control code is used for controlling the common-mode voltage generated by the common-mode voltage generation module. According to the receiver front-end circuit provided by the invention, duty ratio correction is fused at the RX front end, and an additional DCC circuit does not need to be introduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence chip, and particularly relates to a receiver front-end circuit, a control chip and electronic equipment. BACKGROUND

[0002] A receiver (RX) front-end circuit is an analog circuit module responsible for processing extremely weak radio frequency signals in a receiver. Its core task is to amplify the signal to a level that can be processed by subsequent digital circuits without introducing excessive noise, and filter out interference. For double-edge sampling circuits, the duty cycle of the clock signal in the data path and the clock path has an important influence on the subsequent processing of the signal. If there is a deviation in the duty cycle, not only will the eye diagram quality be affected, but the safety margin (skew margin) of the maximum timing skew between parallel input / output (Input / Output, IO) may also be affected. SUMMARY

[0003] The present application provides a receiver front-end circuit, a control chip and electronic equipment, which integrates the duty cycle correction function into the RX front-end to solve the duty cycle correction problem in the RX front-end.

[0004] The application provides a receiver front-end circuit, which comprises a first module, a second module, a reference voltage generating module, a common-mode voltage generating module and a state machine; the first module comprises a differential amplifier, a common-mode feedback circuit, a first resistor, a second resistor, a first switch tube, a second switch tube and a current mirror; a non-inverting output end of the differential amplifier is connected with a control end of the first switch tube; an inverting output end of the differential amplifier is connected with a control end of the second switch tube; an input pad is connected with a non-inverting input end of the differential amplifier; a reference voltage generated by the reference voltage generating module is input to an inverting input end of the differential amplifier; the current mirror comprises a first connection end and a second connection end; the second connection end is a signal output end; wherein the first end of the first switch tube is connected with the first connection end, and the first end of the second switch tube is connected with the second connection end; or the first end of the first switch tube is connected with the second connection end, and the first end of the second switch tube is connected with the first connection end; the first resistor and the second resistor are connected in series between the non-inverting output end and the inverting output end of the differential amplifier; the common-mode feedback circuit comprises a first comparator; a voltage dividing point between the first resistor and the second resistor is connected with a negative inverting input end of the first comparator; a common-mode voltage generated by the common-mode voltage generating module is input to a positive inverting input end of the first comparator; an output end of the first comparator is connected with a common-mode reference voltage end of the differential amplifier; the second module comprises a second comparator; a positive inverting input end of the second comparator is connected with the first end of the second switch tube through a first RC filter; an output end of the second comparator is connected with the state machine; the state machine is connected with the common-mode voltage generating module, and is used for generating a control code according to a comparison result of the second comparator, wherein the control code is used for controlling the common-mode voltage generated by the common-mode voltage generating module.

[0005] In some embodiments, the current mirror comprises a third switch tube and a fourth switch tube; the first switch tube and the second switch tube are voltage-controlled switch tubes with a threshold voltage VTH; and the polarities of the first switch tube and the second switch tube are the same; the polarities of the third switch tube and the fourth switch tube are opposite to the polarities of the first switch tube and the second switch tube.

[0006] In some embodiments, the first switch tube is a first NMOS, and the second switch tube is a second NMOS; the current mirror comprises a first PMOS and a second PMOS; a non-inverting output end of the differential amplifier is connected with a gate of the first NMOS; an inverting output end of the differential amplifier is connected with a gate of the second NMOS; a drain of the first NMOS is connected with a drain of the first PMOS, and a source of the first NMOS is grounded; a drain of the second NMOS is connected with the second connection end, and a source of the second NMOS is grounded; a gate of the first PMOS and a gate of the second PMOS are connected to form a bias node; the bias node is connected with the drain of the first PMOS, and the drain of the first PMOS serves as the first connection end; a source of the second PMOS is connected with a power supply; and a drain of the second PMOS serves as the second connection end.

[0007] In some embodiments, the first switch tube is a third PMOS, and the second switch tube is a fourth PMOS; the current mirror comprises a third NMOS and a fourth NMOS; a non-inverting output terminal of the differential amplifier is connected to a gate of the third PMOS; an inverting output terminal of the differential amplifier is connected to a gate of the fourth PMOS; a source of the third PMOS is connected to a power supply, and a drain of the third PMOS is used as the second connection terminal; a source of the fourth PMOS is connected to the power supply; a drain of the fourth PMOS is connected to a drain of the fourth NMOS; a gate of the third NMOS and a gate of the fourth NMOS are connected to form a bias node; the bias node is connected to the drain of the fourth NMOS, and the drain of the fourth NMOS is used as the first connection terminal; a source of the fourth NMOS is connected to ground; a drain of the third NMOS is connected to the drain of the third PMOS; and a source of the third NMOS is connected to ground.

[0008] In some embodiments, the first RC filter comprises a third resistor and a first capacitor; one end of the first capacitor is connected to ground, and the other end of the first capacitor is connected to a non-inverting input terminal of the second comparator; and the third resistor is connected between the non-inverting input terminal of the second comparator and the second connection terminal.

[0009] In some embodiments, the second module further comprises a fourth resistor and a fifth resistor; the fourth resistor and the fifth resistor are connected in series between the power supply and the ground; the fourth resistor and the fifth resistor have equal resistance values; and a voltage division point between the fourth resistor and the fifth resistor is connected to an inverting input terminal of the second comparator.

[0010] In some embodiments, the second module further comprises a second RC filter; the second RC filter comprises a sixth resistor and a second capacitor; one end of the second capacitor is connected to ground, and the other end of the second capacitor is connected to an inverting input terminal of the second comparator; and the sixth resistor is connected between the inverting input terminal of the second comparator and the first connection terminal.

[0011] In some embodiments, the differential amplifier is a variable gain amplifier CTLE or a continuous equalization amplifier VGA.

[0012] Embodiments of the present application also provide a control chip, comprising the receiver front-end circuit according to any one of the above.

[0013] Embodiments of the present application also provide an electronic device, comprising the receiver front-end circuit according to any one of the above; and / or the control chip according to any one of the above.

[0014] The receiver front-end circuit, the control chip and the electronic equipment provided by the application, the positive-phase output and the negative-phase output of the differential amplifier are divided by the first resistor and the second resistor to generate a feedback common-mode voltage, and the feedback common-mode voltage is used to adjust the common-mode voltage of the first comparator output; the differential output of the differential amplifier is loaded by a current mirror to convert the differential output into a single-ended output, and the signal of the single-ended output is a signal for correcting the duty cycle; the signal of the single-ended output is filtered by a first RC filter to convert an alternating voltage into a direct current voltage; a second comparator compares the direct current voltage with a second reference voltage, and the comparison result is returned to a state machine, and a control code is output by the state machine to control the common-mode voltage, thereby indirectly controlling whether the duty cycle needs to be increased or decreased, so that the scheme provided by the embodiment of the application does not need to introduce an additional DCC circuit, adopts a closed-loop feedback, does not need additional control, can monitor the duty cycle in real time, and can adjust the common-mode voltage through the control code of a control register, and the difference between the common-mode voltage and a threshold voltage determines the opening speed of a switch tube, when the common-mode voltage changes, the opening speed of the switch tube also changes, so that the duty cycle can be corrected by changing the common-mode voltage, a closed-loop feedback is formed, and the problem of the signal duty cycle is solved from the front end and the source of the signal input. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0016] Figure 1 is one of the topological schematic diagrams of the receiver front-end circuit provided by the embodiment of the application; Figure 2 is the second topological schematic diagram of the receiver front-end circuit provided by the embodiment of the application; Figure 3 is the third topological schematic diagram of the receiver front-end circuit provided by the embodiment of the application; Figure 4 is the fourth topological schematic diagram of the receiver front-end circuit provided by the embodiment of the application.

[0017] The correspondence between the reference signs and the component names is as follows: 10 first module, 20 second module; current mirror 101; M1 first switch tube, M2 second switch tube, M3 third switch tube, M4 fourth switch tube, M11 first NMOS, M21 second NMOS, M31 first PMOS, M41 second PMOS; M12 third PMOS, M22 fourth PMOS, M32 third NMOS, M42 fourth NMOS; R1 first resistor, R2 second resistor, R3 third resistor, R4 fourth resistor, R5 fifth resistor, R6 sixth resistor; C1 first capacitor, C2 second capacitor; VREF GEN reference voltage generation module, VCM GEN common mode voltage generation module, FSM state machine, DCM_1 first comparator, DCM_2 second comparator, Diff_Amp1 differential amplifier; P1 first connection end, P2 second connection end, OUT output end; PAD input pad, VCM_CTRL common mode voltage, VCM_R voltage dividing point feedback common mode voltage, VCM_CODE control code, Vref_2 second reference voltage, Vref_1 first reference voltage. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described below in connection with the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the protection scope of the present application.

[0019] It should be noted that in the description of the present application, the terms "comprising", "containing" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or apparatus that comprises a list of elements not only includes those elements, but also includes other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element. The terms "upper", "lower" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. Unless otherwise specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0020] The terms "first", "second", and the like used in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / ", generally means that the front and rear associated objects are in a "or" relationship.

[0021] The RX front-end circuit is the core part of the high-speed IP (Intellectual Property) analog circuit, responsible for processing the signal quality on the PAD, which can generally improve the quality of the front-end eye diagram by compensating for channel loss. For double-edge sampling circuits, the duty cycle of the data path and the clock path has an important influence on the subsequent processing of the signal. If the duty cycle cannot reach the expected ideal duty cycle (50%) or deviates greatly from the ideal duty cycle, it will not only affect the eye width, but also affect the skew margin between parallel IOs. Therefore, introducing the duty cycle correction technology in the receiver front-end has important value for signal integrity.

[0022] At present, in the related art, the RX front-end circuit does not have a separate duty cycle correction circuit, but after receiving a signal by the front-end circuit, a path is additionally introduced to a comparator (Duty Cycle Monitor, DCM) and a duty cycle correction (Duty Cycle Correction, DCC) circuit to correct the duty cycle.

[0023] For example, a correction scheme in the related art introduces two modules of circuits of DCC and DCM. One is called DCC, and the other is called DCM. In order to reduce the influence of the introduced DCC and DCM on the performance of the main path (or referred to as the data signal path datapath) as much as possible, the DCC circuit is generally copied to detect the duty cycle on the main path, correct it, and backfill the register configuration after correction to the main path. In this way, a certain device mismatch is introduced, that is, there is a device mismatch between the copied circuit and the circuit on the main path, and this device mismatch makes the register configuration that can achieve accurate correction of the duty cycle on the copied circuit cannot achieve the same correction effect when backfilled to the main path. The copied circuit is equivalent to introducing an additional path to access the DCM for detection, and it is difficult to ensure that it is completely consistent with the main path.

[0024] In addition, the above scheme in the related art needs to additionally design the DCC circuit, and the DCC design is very difficult, which often introduces the problems of linearity and incorrect correction.

[0025] In view of this, the embodiment of the present application provides a receiver front-end circuit, a chip and an electronic device. In the RX front-end, the front-end signal is output as a single-ended signal by a current-mode differential-to-single-ended output circuit, and the duty cycle correction is performed by controlling the common mode voltage (Common Mode Voltage, VCM) of the differential-to-single-ended output and the threshold voltage (Threshold Voltage, VTH) of the switch tube.

[0026] The receiver front-end circuit, the control chip and the electronic device provided by the present application will be described below in conjunction with Figure 1 and Figure 2

[0027] Exemplarily, the receiver front-end circuit (hereinafter referred to as RX front-end) provided by the embodiment of the present application can adopt the circuit structure shown in Figure 1 . As shown in Figure 1 , the RX front-end can include a first module 10, a second module 20, a reference voltage generation module VREF GEN, a common mode voltage generation module VCM GEN and a state machine FSM.

[0028] ​The first module 10 comprises a differential amplifier Diff_Amp1, a common-mode feedback circuit, a first resistor R1, a second resistor R2, a first switch tube M1, a second switch tube M2 and a current mirror 101.

[0029] The differential amplifier Diff_Amp1 is one of the core components of the RX front-end circuit. The positive input of the differential amplifier Diff_Amp1 is the PAD, and the negative input is the reference voltage (the first reference voltage Vref_1), which is generated by the reference voltage generation module VREF GEN. In other words, the positive input terminal of the differential amplifier Diff_Amp1 is connected to the input pad PAD, and the first reference voltage Vref_1 generated by the reference voltage generation module VREF GEN is input to the negative input terminal of the differential amplifier Diff_Amp1. The first reference voltage Vref_1 generated by the reference voltage generation module VREF GEN can be configured to different voltages by a register.

[0030] Exemplarily, the differential amplifier Diff_Amp1 can be a differential amplifier Diff_Amp1 with a full-differential input and a full-differential output structure, for example, a continuous-time linear equalizer (CTLE) or a variable-gain amplifier (VGA).

[0031] The first resistor R1 and the second resistor R2 are connected in series between the positive output terminal and the negative output terminal of the differential amplifier Diff_Amp1. The common-mode feedback circuit comprises a first comparator DCM_1, and the voltage dividing point between the first resistor R1 and the second resistor R2 is connected to the negative input terminal of the first comparator DCM_1. The common-mode voltage generated by the common-mode voltage generation module VCM GEN is input to the positive input terminal of the first comparator DCM_1. The output terminal OUT of the first comparator DCM_1 is connected to the common-mode reference voltage terminal of the differential amplifier Diff_Amp1. In this way, the positive output terminal and the negative output terminal of the differential amplifier Diff_Amp1 are respectively divided by the first resistor R1 and the second resistor R2 for common-mode feedback, and the common-mode voltage VCM_R fed back by the voltage dividing point between the first resistor R1 and the second resistor R2 is input to the negative input terminal of the first comparator DCM_1. The positive input terminal of the first comparator DCM_1 is controlled by the common-mode voltage generation module VCM GEN, for example, different common-mode voltages VCM_CTRL can be generated by configuring the control code VCM_CODE of the register. For example, the control code VCM_CODE can be VCM_CODE<7:0>, indicating that the control code is an 8-bit control code. The number of bits of the control code can also be 16 bits or 4 bits, etc. The number of bits of the control can affect the step size of the duty cycle correction.

[0032] The first resistance R1 and the second resistance R2 have the same resistance value.

[0033] The positive output terminal and the negative output terminal of the differential amplifier Diff_Amp1 are connected to the first switch tube M1 and the second switch tube M2 respectively, and the output signal is output after being converted into a single-ended output signal by the current mirror 101. The output signal is input into the positive input terminal of the second comparator DCM_2 in the second module 20 after being filtered by the first RC filter. Specifically, the positive output terminal of the differential amplifier Diff_Amp1 is connected to the control terminal of the first switch tube M1, and the negative output terminal of the differential amplifier Diff_Amp1 is connected to the control terminal of the second switch tube M2. The current mirror 101 includes a first connection terminal P1 and a second connection terminal P2, and the second connection terminal P2 serves as the signal output terminal OUT. That is, the signal output from the output terminal OUT is the signal after the duty cycle correction. The first terminal of the first switch tube M1 is connected to the first connection terminal P1, and the first terminal of the second switch tube M2 is connected to the second connection terminal P2. Alternatively, the first terminal of the first switch tube M1 is connected to the second connection terminal P2, and the first terminal of the second switch tube M2 is connected to the first connection terminal P1.

[0034] The second module 20 includes the second comparator DCM_2, the positive input terminal of which is connected to the first terminal of the second switch tube M2 through the first RC filter, and the output terminal of which is connected to the state machine FSM. The first RC filter can include the first capacitor C1 and the third resistance R3. The negative input terminal of the second comparator DCM_2 can input the second reference voltage Vref_2, for example, the second reference voltage Vref_2 can be the VDD / 2 voltage.

[0035] The state machine, i.e. the finite state machine FSM, is connected to the common-mode voltage generation module VCM_GEN, and is used to generate a control code for controlling the register according to the comparison result of the second comparator DCM_2. The control code is used to control the common-mode voltage generated by the common-mode voltage generation module VCM_GEN. The output O_DCM of the second comparator DCM_2 is input into the state machine FSM, and the state machine FSM generates different control codes VCM_CODE<7:0> according to O_DCM to trigger the common-mode voltage generation module VCM_GEN to generate different common-mode voltages VCM_CTRL.

[0036] In this way, when the common-mode voltage changes, the turn-on speed of the first switch tube M1 and the second switch tube M2 is determined by the difference between the common-mode voltage VCM_CTRL and the threshold voltage VTH, thereby changing the duty cycle of the output signal.

[0037] The embodiment of the present application fuses the duty cycle correction function into the RX front end, and uses the opening margin of the switch tube to achieve the purpose of indirectly adjusting the duty cycle. In specific analysis, the positive phase output and the negative phase output of the differential amplifier Diff_Amp1 are divided by two resistors (the first resistor R1 and the second resistor R2) to generate a common mode feedback, which is used to adjust the common mode level (i.e. the common mode voltage). The differential output of the differential amplifier Diff_Amp1 is loaded by a current mirror 101, and the differential output is converted into a single-ended output, and the signal of the single-ended output is the signal for correcting the duty cycle, which can be data or a clock signal. The signal of the single-ended output is filtered by a filter (the first RC filter), and the alternating voltage is converted into a direct current voltage. The second comparator DCM_2 compares the direct current voltage with the second reference voltage Vref_2, and the comparison result is returned to the state machine FSM, and the control code is output by the state machine FSM to control the common mode voltage, and then indirectly control whether the duty cycle is up or down.

[0038] The switch tube can be regarded as a switch, which is turned on and off at different threshold voltages, and the response speed of the switch tube is not the same. The embodiment of the present application adjusts the range of the common mode level output in the RX front end, which is equivalent to adjusting the critical state of the switch of the switch tube to be higher or lower, which is specifically embodied as controlling the switch tube to be pulled up faster or turned off faster. For example, the VTH of the first switch tube M1 is 300 millivolts, and it is assumed that the common mode voltage is also 300 millivolts, so that the first switch tube M1 is at the opening threshold of the first switch tube M1, and the first switch tube M1 is turned on very fast, and can be quickly converted from 0 to 1. Similarly, the turning off of the first switch tube M1 can be realized by controlling the common mode voltage, and the signal output from the output terminal OUT will have a similar hysteresis effect, and the falling edge of the signal will come later, that is, the duty cycle will become larger. The scheme proposed in the embodiment of the present application fuses the correction circuit into the RX front end, and realizes the correction of the duty cycle by using the common mode feedback mechanism and the VTH, without introducing an additional DCC circuit, and without causing problems such as linearity.

[0039] In addition, the circuit structure proposed in the embodiment of the present application is a closed-loop feedback circuit, and there is no problem of jumping gears after the state machine FSM is turned on, that is, the common mode voltage can be controlled in a continuously dynamically changing range, and the common mode feedback is performed at the output stage, so as not to affect the process of signal output or receiving on the main path. The state machine FSM does not need to be locked, but can support real-time adjustment.

[0040] In addition, the traditional method of duty cycle correction needs to be inserted into a DCC circuit at a node of decoding or serial code on a path after the RX front end, and the scheme of the embodiment of the application completes the duty cycle correction at the same time as receiving the signal, integrates the correction circuit in the front end, solves the problem of inserting a DCC circuit in the rear circuit, and the rear circuit does not need to consider the error caused by the DCC.

[0041] Figure 1 In the circuit structure example shown, the first switch tube M1 and the second switch tube M2 are both NMOS, the current mirror 101 includes a third switch tube M3 and a fourth switch tube M4, and the third switch tube M3 and the fourth switch tube M4 are both PMOS. Figure 1 The circuit structure shown is only an example and does not limit the receiver front-end circuit.

[0042] In actual application, the first switch tube M1 and the second switch tube M2 can be one of voltage-controlled switch tubes with different threshold voltages VTH. The polarities of the first switch tube M1 and the second switch tube M2 are the same. The polarities of the third switch tube and the fourth switch tube M4 are opposite to the polarities of the first switch tube M1 and the second switch tube M2.

[0043] For example, the same polarity means that the device type and the carrier polarity are the same, for example, the first switch tube M1 and the second switch tube M2 are the same semiconductor type, and the current carriers (carriers) inside move in the same direction. Alternatively, the same polarity means that both are N-channel or both are P-channel.

[0044] The voltage-controlled switch tube with different threshold voltages VTH refers to a switch tube whose conduction and shutdown are controlled by the voltage between the gate / source or the gate / emitter, for example, the voltage-controlled switch tube with a threshold voltage VTH can be one or more of the following switch tubes: Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Insulated-Gate Bipolar Transistor (IGBT), Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor (SiC MOSFET), Gallium Nitride High Electron Mobility Transistor (GaN HEMT).

[0045] For example, in one embodiment, combined with Figure 1 In the circuit structure shown, the first switch M1 is a first NMOS M11, and the second switch M2 is a second NMOS M21. The current mirror 101 includes a first PMOS M31 and a second PMOS M41, meaning the third switch M3 is the first PMOS M31, and the fourth switch M4 is the second PMOS M41. In this embodiment, the positive output terminal of the differential amplifier Diff_Amp1 is connected to the gate of the first NMOS M11; the negative output terminal of the differential amplifier Diff_Amp1 is connected to the gate of the second NMOS M21; the drain of the first NMOS M11 is connected to the drain of the first PMOS M31, and the source of the first NMOS M11 is grounded; the drain of the second NMOS M21 is connected to the second connection terminal P2, and the source of the second NMOS M21 is grounded. The gate of the first PMOS M31 and the gate of the second PMOS M41 are connected to form a bias node; the bias node is connected to the drain of the first PMOS M31, and the drain of the first PMOS M31 serves as the first connection terminal P1; the source of the second PMOS M41 is connected to the power supply; and the drain of the second PMOS M41 serves as the second connection terminal P2.

[0046] In another embodiment, such as Figure 2 As shown, the first switch M1 is the third PMOS M12, and the second switch M2 is the fourth PMOS M22. The current mirror 101 includes the third NMOS M32 and the fourth NMOS M42, that is, the third switch M3 is the third NMOS M32, and the fourth switch M4 is the fourth NMOS M42.

[0047] exist Figure 2 In the circuit structure example shown, the non-inverting output of differential amplifier Diff_Amp1 is connected to the gate of the third PMOS M12, and the negative-inverting output of differential amplifier Diff_Amp1 is connected to the gate of the fourth PMOS M22. The source of the third PMOS M12 is connected to the power supply, and the drain of the third PMOS M12 serves as the second connection terminal. The source of the fourth PMOS M22 is connected to the power supply, and the drain of the fourth PMOS M22 is connected to the drain of the fourth NMOS M42. The gates of the third NMOS M32 and the fourth NMOS M42 are connected to form a bias node, which is connected to the drain of the fourth NMOS M42. The drain of the fourth NMOS M42 serves as the first connection terminal. The source of the fourth NMOS M42 is grounded. The drain of the third NMOS M32 is connected to the drain of the third PMOS M12, and the source of the third NMOS M32 is grounded.

[0048] In some embodiments, the first RC filter includes a third resistor R3 and a first capacitor C1. One end of the first capacitor C1 is grounded, and the other end of the first capacitor C1 is connected to the non-inverting input of the second comparator DCM_2; the third resistor R3 is connected between the non-inverting input of the second comparator DCM_2 and the second connection terminal P2.

[0049] Combination Figure 1 and Figure 2 In one embodiment of the circuit structure example shown, the second module 20 further includes a fourth resistor R4 and a fifth resistor R5, which are connected in series between the power supply and ground. The voltage divider point between the fourth resistor R4 and the fifth resistor R5 is connected to the negative inverting input of the second comparator DCM_2. The fourth resistor R4 and the fifth resistor R5 form a voltage divider structure with two identical resistors, and the connection point (voltage divider point) between the fourth resistor R4 and the fifth resistor R5 generates a voltage of VDD / 2. VDD represents the drain power supply voltage of the switching transistor. The resistance values ​​of the fourth resistor R4 and the fifth resistor R5 are equal.

[0050] like Figure 3 As shown, in another embodiment, the fourth resistor R4 and the fifth resistor R5 can be replaced with a second RC filter. Specifically, the second module 20 further includes a second RC filter, which includes a sixth resistor R6 and a second capacitor C2. One end of the second capacitor C2 is grounded, and the other end of the second capacitor C2 is connected to the negative input terminal of the second comparator DCM_2. The sixth resistor R6 is connected between the negative input terminal of the second comparator DCM_2 and the first connection terminal P1.

[0051] It should be noted that the above figures are exemplary structures and are not intended to limit the receiver front-end circuit structure proposed in the embodiments of the present invention. Those skilled in the art can make appropriate combinations or modifications based on the above examples to obtain other embodiments, such as... Figure 2 Replacing the fourth resistor R4 and the fifth resistor R5 in the exemplary circuit structure shown with the second RC filter can yield the following result: Figure 4 The circuit structure example shown.

[0052] In summary, this embodiment of the invention uses a current-type differential-to-single-ended output circuit at the RX front end to output the front end signal as a single-ended signal. By controlling the common-mode voltage of the differential-to-single-ended output in conjunction with the VTH of the switching transistor, duty cycle correction is performed. The duty cycle correction function is integrated into the RX front end, and the duty cycle is indirectly adjusted by utilizing the turn-on margin of the switching transistor.

[0053] The embodiment of the present application adjusts the range of the common mode level output by the RX front end, which is equivalent to adjusting the critical state of the switch tube switch to be higher or lower, specifically, controlling whether the switch tube is turned on faster or turned off faster, so that the common mode voltage can be controlled, and the speed of turning on or turning off the first switch tube M1 can be controlled, and then the duty cycle of the single-ended output signal can be adjusted. This scheme integrates the correction circuit into the RX front end, and uses the cooperation of the common mode feedback mechanism and VTH to realize the duty cycle correction, without introducing additional DCC circuit, and without causing problems such as linearity.

[0054] In addition, there is no problem of skipping gears after the state machine FSM is turned on, the common mode voltage can be controlled in a continuously dynamically changing range, and the common mode feedback is performed at the output stage, so as not to affect the process of signal output or receiving on the main path.

[0055] In addition, this scheme completes the duty cycle correction while receiving the signal, and integrates the duty cycle correction function into the front end, so that the subsequent circuit on the main path does not need to perform the duty cycle correction again.

[0056] The present application provides a control chip, comprising: the receiver front-end circuit of any one of the above.

[0057] In this embodiment, a control chip is provided, which comprises the receiver front-end circuit of any one of the above embodiments, so as to have all the beneficial effects of the receiver front-end circuit, which will not be repeated here.

[0058] In this embodiment, an electronic device is provided, which comprises the control chip and / or the receiver front-end circuit of any one of the above embodiments, so as to have all the beneficial effects of the receiver front-end circuit, which will not be repeated here.

[0059] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A receiver front-end circuit, characterized in that, It includes a first module, a second module, a reference voltage generation module, a common-mode voltage generation module, and a state machine; The first module includes a differential amplifier, a common-mode feedback circuit, a first resistor, a second resistor, a first switch, a second switch, and a current mirror; The positive output terminal of the differential amplifier is connected to the control terminal of the first switching transistor; the negative output terminal of the differential amplifier is connected to the control terminal of the second switching transistor; the positive input terminal of the differential amplifier is connected to the input pad; the reference voltage generated by the reference voltage generation module is input to the negative input terminal of the differential amplifier; the first resistor and the second resistor are connected in series between the positive output terminal and the negative output terminal of the differential amplifier; The current mirror includes a first connection terminal and a second connection terminal; the second connection terminal is a signal output terminal; wherein, the first end of the first switching transistor is connected to the first connection terminal, and the first end of the second switching transistor is connected to the second connection terminal; or, the first end of the first switching transistor is connected to the second connection terminal, and the first end of the second switching transistor is connected to the first connection terminal. The common-mode feedback circuit includes a first comparator; the voltage divider point between the first resistor and the second resistor is connected to the negative input terminal of the first comparator; the common-mode voltage generated by the common-mode voltage generation module is input to the positive input terminal of the first comparator; the output terminal of the first comparator is connected to the common-mode reference voltage terminal of the differential amplifier. The second module includes a second comparator; the non-inverting input of the second comparator is connected to the first terminal of the second switch via a first RC filter; the output of the second comparator is connected to the state machine; the state machine is connected to the common-mode voltage generation module and is used to control the register to generate a control code based on the comparison result of the second comparator, the control code being used to control the common-mode voltage generated by the common-mode voltage generation module.

2. The receiver front-end circuit according to claim 1, characterized in that, The current mirror includes a third switching transistor and a fourth switching transistor; The first switch and the second switch are voltage-controlled switches with a threshold voltage VTH; and the first switch and the second switch have the same polarity. The polarities of the third and fourth switching transistors are opposite to those of the first and second switching transistors.

3. The receiver front-end circuit according to claim 1 or 2, characterized in that, The first switching transistor is a first NMOS, and the second switching transistor is a second NMOS; the current mirror includes a first PMOS and a second PMOS; The positive output terminal of the differential amplifier is connected to the gate of the first NMOS; the negative output terminal of the differential amplifier is connected to the gate of the second NMOS; the drain of the first NMOS is connected to the drain of the first PMOS, and the source of the first NMOS is grounded; the drain of the second NMOS is connected to the second connection terminal, and the source of the second NMOS is grounded. The gates of the first PMOS and the second PMOS are connected to form a bias node; The bias node is connected to the drain of the first PMOS, and the drain of the first PMOS serves as the first connection terminal; the source of the second PMOS is connected to the power supply; and the drain of the second PMOS serves as the second connection terminal.

4. The receiver front-end circuit according to claim 1 or 2, characterized in that, The first switching transistor is a third PMOS, and the second switching transistor is a fourth PMOS; the current mirror includes a third NMOS and a fourth NMOS; The positive output terminal of the differential amplifier is connected to the gate of the third PMOS; the negative output terminal of the differential amplifier is connected to the gate of the fourth PMOS; the source of the third PMOS is connected to the power supply, and the drain of the third PMOS serves as the second connection terminal; the source of the fourth PMOS is connected to the power supply; and the drain of the fourth PMOS is connected to the drain of the fourth NMOS. The gate of the third NMOS and the gate of the fourth NMOS are connected to form a bias node; the bias node is connected to the drain of the fourth NMOS, and the drain of the fourth NMOS serves as a first connection terminal; the source of the fourth NMOS is grounded; the drain of the third NMOS is connected to the drain of the third PMOS; the source of the third NMOS is grounded.

5. The receiver front-end circuit according to claim 1, characterized in that, The first RC filter includes a third resistor and a first capacitor; One end of the first capacitor is grounded, and the other end of the first capacitor is connected to the non-inverting input of the second comparator; the third resistor is connected between the non-inverting input of the second comparator and the second connection terminal.

6. The receiver front-end circuit according to claim 5, characterized in that, The second module also includes a fourth resistor and a fifth resistor; The fourth resistor and the fifth resistor are connected in series between the power supply and ground; the resistance values ​​of the fourth resistor and the fifth resistor are equal. The voltage divider point between the fourth resistor and the fifth resistor is connected to the negative input terminal of the second comparator.

7. The receiver front-end circuit according to claim 5, characterized in that, The second module also includes a second RC filter, which includes a sixth resistor and a second capacitor; One end of the second capacitor is grounded, and the other end of the second capacitor is connected to the negative input terminal of the second comparator; The sixth resistor is connected between the negative phase input terminal of the second comparator and the first connection terminal.

8. The receiver front-end circuit according to any one of claims 1-2 or 5-7, characterized in that, The differential amplifier is either a variable gain amplifier (CTLE) or a continuous equalizer (VGA).

9. A control chip, characterized in that, include: The receiver front-end circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, include: Receiver front-end circuit as described in any one of claims 1 to 8; And / or, the control chip as described in claim 9.

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