Signal source and test system

Abstract

This invention provides a signal source and a testing system, belonging to the field of signal processing technology. The signal source includes a phase-locked loop (PLL) and a controller connected to the PLL. The controller is used to: acquire a first test parameter, including a target output frequency; determine a target locking voltage corresponding to the target output frequency based on a mapping data table; adjust the output voltage of the resistor divider network in the PLL to the target locking voltage; change the operating state of the PLL from closed-loop to open-loop, so that the resistor divider network outputs voltage to the loop filter in the PLL; and change the operating state of the PLL from open-loop to closed-loop, so that the phase detector in the PLL outputs voltage to the loop filter. By using the resistor divider network to output voltage to the loop filter, the frequency can be quickly adjusted to near the target output frequency. When the PLL is in closed-loop state, the frequency can be quickly locked to the target output frequency, achieving frequency agility.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more particularly to a signal source and a testing system. Background Technology

[0002] With the rapid development of communication technology, especially with the rapid development of digital communication, radar, information warfare, electronic countermeasures and other technologies, higher requirements have been put forward for signal sources. For example, for some test scenarios, the signal source needs to generate high-speed frequency hopping signals, and the hopping speed of high-speed frequency hopping signals can reach 10,000 hops / second.

[0003] The relevant technical solutions employ the following two methods to generate frequency modulation signals:

[0004] The first method uses a standard microwave analog signal source. Specifically, a standard microwave analog signal source first generates a continuous wave signal at the corresponding frequency, then generates a pulse signal and modulates it onto the continuous wave signal. This process is time-consuming, and the frequency switching time of the standard microwave analog signal source is also relatively long, which means that each test frequency point requires a long time, thus affecting the overall test process.

[0005] The second method is to directly generate the frequency hopping signal using a voltage-controlled oscillator (VCO). This method is suitable for situations where the frequency hopping signal is low. However, for situations where the frequency hopping signal is high, the hardware requirements are more demanding, which makes the testing cost higher.

[0006] As can be seen from the above, if a standard microwave analog signal source is used to generate a high-speed frequency hopping signal for testing, the testing time will be relatively long, while using a voltage-controlled oscillator directly will result in high testing costs. Summary of the Invention

[0007] This invention provides a signal source and a testing system to solve the problems in related technologies where using a standard microwave analog signal source to generate a high-speed frequency hopping signal for testing results in a long testing time, while directly using a voltage-controlled oscillator results in high testing costs.

[0008] This invention provides a signal source, the signal source including a phase-locked loop and a controller connected to the phase-locked loop, the controller being used for:

[0009] Obtain the first test parameter, which includes the target output frequency;

[0010] The target lock-in voltage corresponding to the target output frequency is determined based on a mapping data table. The mapping data table includes multiple mapping relationships, and each mapping relationship includes an output frequency and a lock-in voltage corresponding to the output frequency. The output frequency is different in different mapping relationships.

[0011] Adjust the output voltage of the resistor divider network in the phase-locked loop to the target locking voltage;

[0012] The operating state of the phase-locked loop is changed from closed-loop to open-loop, so that the resistor voltage divider network outputs voltage to the loop filter in the phase-locked loop.

[0013] The operating state of the phase-locked loop is changed from the open-loop state to the closed-loop state, so that the phase detector in the phase-locked loop outputs voltage to the loop filter.

[0014] The signal source provided by this invention includes a phase-locked loop comprising:

[0015] A first switch, the first input terminal of the first switch is connected to the output terminal of the resistor divider network, the second input terminal of the first switch is connected to the output terminal of the phase detector, and the output terminal of the first switch is connected to the input terminal of the loop filter;

[0016] A voltage-controlled oscillator (VCO) is provided, wherein the input terminal of the VCO is connected to the output terminal of the loop filter, and the output terminal of the VCO serves as the output terminal of the phase-locked loop (PLL).

[0017] The radio frequency divider has its input terminal connected to the voltage-controlled oscillator and its output terminal connected to the first input terminal of the phase detector.

[0018] The step of changing the operating state of the phase-locked loop from closed-loop to open-loop, so that the resistor divider network outputs voltage to the loop filter in the phase-locked loop, is specifically performed by the controller as follows:

[0019] Control the first switch to perform a first action, so that the first input terminal of the first switch is connected to the output terminal of the first switch;

[0020] The step of changing the operating state of the phase-locked loop from the open-loop state to the closed-loop state, so that the phase detector in the phase-locked loop outputs a voltage to the loop filter, is specifically performed by the controller as follows:

[0021] Control the first switch to perform a second action, so that the second input terminal of the first switch is connected to the output terminal of the first switch.

[0022] The signal source provided by this invention, in the step of determining the target locking voltage corresponding to the target output frequency based on a mapping data table, the controller is specifically used for:

[0023] Determine the first output frequency in the mapping data table that is closest to the target output frequency;

[0024] The locking voltage corresponding to the first output frequency is taken as the target locking voltage.

[0025] The signal source provided by the present invention further includes:

[0026] Multiplexer;

[0027] A frequency multiplier, wherein the input terminal of the frequency multiplier is connected to the output terminal of the voltage-controlled oscillator, the output terminal of the frequency multiplier is connected to the first input terminal of the multiplexer, and the output terminal of the voltage-controlled oscillator is connected to the second input terminal of the multiplexer;

[0028] The first frequency divider has its input terminal connected to the output terminal of the voltage-controlled oscillator, and its output terminal connected to the third input terminal of the multiplexer.

[0029] The signal source provided by the present invention further includes:

[0030] A first voltage-controlled attenuator, wherein the input terminal of the first voltage-controlled attenuator is connected to the output terminal of the phase-locked loop;

[0031] A second voltage-controlled attenuator, wherein the input terminal of the second voltage-controlled attenuator is connected to the output terminal of the first voltage-controlled attenuator;

[0032] A mechanical attenuator, the input of which is connected to the output of the second voltage-controlled attenuator;

[0033] A digital-to-analog converter (DAC) is provided, wherein the output terminal of the DAC is connected to the control terminal of the first voltage-controlled attenuator and the control terminal of the second voltage-controlled attenuator, respectively, and the input terminal of the DAC is connected to the controller.

[0034] The first test parameter also includes the target output power, and the controller is further configured to:

[0035] The target control voltage corresponding to the target output power is determined based on the calibration data table, which includes multiple calibration data relationships, each of which includes the output power and the control voltage corresponding to the output power.

[0036] The digital-to-analog converter is controlled to output the target control voltage to the first voltage-controlled attenuator and the second voltage-controlled attenuator.

[0037] The signal source provided by the present invention has a mechanical attenuator with at least two signal output terminals, and the signals output by different signal output terminals are the same.

[0038] The signal source provided by this invention, wherein the controller is further configured to:

[0039] Obtain a test parameter list, which includes multiple test parameters, including a first test parameter;

[0040] During the operation of the phase-locked loop according to the first test parameters, if a trigger signal is received, the second test parameter is searched based on the test parameter list to control the phase-locked loop to operate according to the second test parameters;

[0041] The first test parameter and the second test parameter are two adjacent test parameters.

[0042] The signal source provided by the present invention further includes:

[0043] Frequency synthesizer;

[0044] The phase-locked loop also includes:

[0045] A reference frequency divider, the input of which is connected to the output of the frequency synthesizer, and the output of which is connected to the second input of the phase detector.

[0046] The signal source provided by this invention has a parallel interface for the control interface of the frequency synthesizer.

[0047] This invention provides a testing system, comprising:

[0048] The signal source as described in any one of the above;

[0049] The device under test;

[0050] The host computer communicates with the signal source and the device under test respectively, and is used to send trigger signals to the signal source and the device under test. The trigger signal includes a first rising edge, a first falling edge and a low-level signal of a first duration.

[0051] Specifically, when the signal source detects the first rising edge, it configures the first test parameter; when it detects the first falling edge, it confirms that the first test parameter is effective; and when it detects that the duration of the low-level signal is greater than or equal to the first duration, it outputs a pulse signal corresponding to the first test parameter.

[0052] The signal source and testing system provided by this invention pre-constructs a mapping data table. Upon receiving the first test parameter, the mapping data table can be used to determine the target locking voltage corresponding to the target output frequency in the first test parameter, and the output voltage of the resistor divider network in the phase-locked loop (PLL) can be adjusted to the target locking voltage. When the PLL is operating in open-loop mode, the voltage output to the loop filter in the PLL via the resistor divider network can quickly adjust the frequency of the PLL output signal to near the target output frequency. By switching the PLL's operating state to closed-loop mode, the frequency of the PLL output signal can be quickly locked to the target output frequency. In this process, the response time of the PLL can be reduced, achieving frequency agility. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0054] Figure 1 This is a flowchart illustrating the working logic of the controller provided by the present invention;

[0055] Figure 2 This is one of the partial topology diagrams of the signal source provided by the present invention;

[0056] Figure 3 This is a second partial topology diagram of the signal source provided by the present invention;

[0057] Figure 4 This is a schematic diagram of the power conversion provided by the present invention;

[0058] Figure 5 This is a schematic block diagram of the signal source provided by the present invention;

[0059] Figure 6 This is a flowchart illustrating the operation of the signal source provided by the present invention;

[0060] Figure 7 This is a schematic diagram illustrating the working principle of the trigger signal provided by the present invention.

[0061] Figure label:

[0062] 200. Phase-locked loop; 201. Resistor voltage divider network; 202. Loop filter; 203. Phase detector; 204. First switch; 205. Voltage-controlled oscillator; 206. RF divider; 207. Multiplexer; 208. Frequency multiplier; 209. First frequency divider; 210. Reference frequency divider; 300. Frequency synthesizer; 401. First voltage-controlled attenuator; 402. Second voltage-controlled attenuator; 403. Mechanical attenuator; 404. Digital-to-analog converter. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0064] It should be noted that in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The terms "upper," "lower," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0065] The terms "first," "second," etc., used in this invention are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0066] The following is combined Figures 1-7 The signal source and test system described in this invention aim to improve upon the limitations of related technologies where using standard microwave analog signal sources to generate high-speed frequency-hopping signals for testing results in long testing times, while directly using voltage-controlled oscillators leads to high testing costs.

[0067] This invention proposes a signal source, Figure 1 This is a flowchart illustrating the working logic of the controller provided by the present invention. Figure 2 This is one of the partial topology diagrams of the signal source provided by the present invention, such as... Figure 1 and Figure 2 As shown, the signal source includes a phase-locked loop 200 and a controller (not shown) connected to the phase-locked loop. The controller performs the following steps:

[0068] Step 101: Obtain the first test parameter, which includes the target output frequency.

[0069] The target output frequency is the frequency of the frequency-hopping signal that the tester wants the signal source to output.

[0070] For example, the target output frequency can be 5GHz, 10GHz or other values, which will not be elaborated here.

[0071] Step 102: Determine the target lock voltage corresponding to the target output frequency based on the mapping data table. The mapping data table includes multiple mapping relationships. Each mapping relationship includes the output frequency and the lock voltage corresponding to the output frequency. The output frequency is different in different mapping relationships.

[0072] In some embodiments, the mapping data table is obtained in the following way:

[0073] The operating state of the phase-locked loop 200 is switched to closed-loop state. All test frequency points are traversed according to a preset step size (the step size is configurable, with a default of 1MHz). After each frequency point stabilizes, the locking voltage of the voltage-controlled oscillator 205 in the phase-locked loop 200 is collected through an analog-to-digital converter. Based on the frequency points and the locking voltage of the voltage-controlled oscillator 205 in the phase-locked loop 200 collected by the analog-to-digital converter, a data table of frequency points and locking voltages is generated. The frequency points are also the output frequencies in this invention, and the data table of frequency points and locking voltages is also the mapping data table in this invention.

[0074] Step 103: Adjust the output voltage of the resistor divider network in the phase-locked loop to the target locking voltage.

[0075] In some embodiments, the maximum value (Vmax) and minimum value (Vmin) of the locking voltage in the mapping data table are obtained. By adjusting the resistance parameters of the resistor voltage divider network 201 in the phase-locked loop 200, the output voltage range of the resistor voltage divider network 201 is made to cover [Vmin, Vmax], for example [Vmin-0.1V, Vmax+0.1V]. The voltage divider is divided into voltage levels according to the frequency range, so that the output voltage of each level approximately matches the average locking voltage of the corresponding range.

[0076] The average lockout voltage is obtained by using an analog-to-digital converter to acquire data and calculate the average value.

[0077] During this process, the output voltage of the resistor voltage divider network 201 is selected by choosing the voltage divider range of the resistor voltage divider network 201, so that the output voltage of the resistor voltage divider network 201 is the target locked voltage.

[0078] For example, if the target lock voltage is 6.5V, and the resistor divider network 201 has three voltage divider levels, namely the first level, the second level, and the third level, where the average lock voltage of the resistor divider network 201 corresponding to the first level is 3V, the average lock voltage of the resistor divider network 201 corresponding to the second level is 6V, and the average lock voltage of the resistor divider network 201 corresponding to the third level is 9V, then 6V is the closest to the target lock voltage. In this case, the voltage divider network 201 selects the second level.

[0079] Step 104: Change the operating state of the phase-locked loop from closed-loop to open-loop so that the resistor divider network outputs voltage to the loop filter in the phase-locked loop.

[0080] Step 105: Change the operating state of the phase-locked loop from open-loop to closed-loop so that the phase detector in the phase-locked loop outputs voltage to the loop filter.

[0081] In this embodiment, a mapping data table is pre-constructed so that after receiving the first test parameter, the target locking voltage corresponding to the target output frequency in the first test parameter can be determined using the mapping data table, and the output voltage of the resistor divider network 201 in the phase-locked loop 200 can be adjusted to the target locking voltage. When the phase-locked loop 200 is operating in open-loop mode, the voltage output from the resistor divider network 201 to the loop filter 202 in the phase-locked loop 200 can quickly adjust the frequency of the output signal of the phase-locked loop 200 to near the target output frequency. By switching the operating state of the phase-locked loop 200 to closed-loop mode, the voltage output from the phase detector 203 to the loop filter 202 can quickly lock the frequency of the output signal of the phase-locked loop 200 to the target output frequency. In this process, the response time of the phase-locked loop 200 can be reduced, achieving frequency agility.

[0082] In this process, there is no need to impose high hardware requirements on the frequency synthesizer 300. Therefore, while maintaining the original cost, the response time of the phase-locked loop 200 can be reduced to achieve frequency agility.

[0083] For example, for the target output frequency ft, the target locking voltage Vt corresponding to the target output frequency is obtained by searching the mapping data table. When the phase-locked loop 200 switches to the open-loop state, the resistor voltage divider network 201 outputs a voltage approximately equal to Vt. At this time, the voltage-controlled oscillator 205 in the phase-locked loop 200 is driven to quickly approach the target output frequency. After a preset delay, the phase-locked loop 200 switches to the closed-loop state, and the phase-locked loop 200 is locked in closed loop, outputting a signal with a precise target output frequency.

[0084] In some embodiments, the phase-locked loop 200 includes:

[0085] The first switch 204 has its first input terminal connected to the output terminal of the resistor divider network 201, its second input terminal connected to the output terminal of the phase detector 203, and its output terminal connected to the input terminal of the loop filter 202.

[0086] A voltage-controlled oscillator 205 is provided, with its input terminal connected to the output terminal of a loop filter 202. The output terminal of the voltage-controlled oscillator 205 serves as the output terminal of a phase-locked loop 200.

[0087] The radio frequency divider 206 has its input terminal connected to the voltage-controlled oscillator 205 and its output terminal connected to the first input terminal of the phase detector 203.

[0088] The controller is specifically used to modify the operating state of the phase-locked loop 200 from closed-loop to open-loop, so that the resistor divider network 201 outputs voltage to the loop filter 202 in the phase-locked loop 200.

[0089] Control the first switch 204 to perform a first action, so that the first input terminal of the first switch 204 is connected to the output terminal of the first switch 204;

[0090] The controller is specifically used to modify the operating state of the phase-locked loop 200 from open-loop to closed-loop, so that the phase detector 203 in the phase-locked loop 200 outputs a voltage to the loop filter 202.

[0091] The first switch 204 is controlled to perform a second action, so that the second input terminal of the first switch 204 is connected to the output terminal of the first switch 204.

[0092] In this embodiment, when the first switch 204 performs a first action to connect the first input terminal of the first switch 204 with the output terminal of the first switch 204, the resistor divider network 201 outputs voltage to the loop filter 202 in the phase-locked loop 200. At this time, the voltage-controlled oscillator 205 can quickly operate near the target output frequency. When the first switch 204 performs a second action to connect the second input terminal of the first switch 204 with the output terminal of the first switch 204, the phase detector 203 outputs voltage to the loop filter 202 to achieve locking of the voltage-controlled oscillator 205 from the nearest frequency to the target output frequency. In this process, the signal locking time during frequency switching is greatly shortened, the response time of the phase-locked loop 200 is shortened, thereby reducing the frequency hopping time and achieving frequency agility.

[0093] In some embodiments, the first action is to connect the first input terminal of the first switch 204 to the output terminal of the first switch 204. Similarly, the second action is to connect the second input terminal of the first switch 204 to the output terminal of the first switch 204.

[0094] In some embodiments, the first switch 204 is a single-pole double-throw switch.

[0095] When the second input terminal of the first switch 204 is connected to the output terminal of the first switch 204, the RF divider 206 feeds back the signal collected from the voltage-controlled oscillator 205 to the first input terminal of the phase detector 203, so that the phase detector 203 can compare the signal collected by the RF divider 206 with the received reference signal, thereby determining the signal to be output to the loop filter 202.

[0096] The signal source provided by this invention determines the target locking voltage corresponding to the target output frequency based on a mapping data table. The controller is specifically used for:

[0097] Determine the first output frequency in the mapping data table that is closest to the target output frequency;

[0098] The locking voltage corresponding to the first output frequency is taken as the target locking voltage.

[0099] In this embodiment, the target locking voltage corresponding to the target output frequency can be quickly located, thereby greatly shortening the signal locking time during frequency switching, shortening the response time of the phase-locked loop 200, reducing the frequency hopping time, and realizing frequency agility.

[0100] In some embodiments, the mapping data table includes three mapping relationships, namely a first mapping relationship, a second mapping relationship, and a third mapping relationship. The output frequency in the first mapping relationship is 3GHz, the output frequency in the second mapping relationship is 4GHz, and the output frequency in the third mapping relationship is 5GHz. If the target output frequency is 3.6GHz, the second mapping relationship is selected, and 4GHz is taken as the closest first output frequency, and the locking voltage corresponding to 4GHz is taken as the target locking voltage.

[0101] In some embodiments, such as Figure 2 As shown, the signal source also includes:

[0102] Multiplexer 207;

[0103] Frequency multiplier 208, the input terminal of frequency multiplier 208 is connected to the output terminal of voltage-controlled oscillator 205, the output terminal of frequency multiplier 208 is connected to the first input terminal of multiplexer 207, and the output terminal of voltage-controlled oscillator 205 is connected to the second input terminal of multiplexer 207;

[0104] The first frequency divider 209 has its input terminal connected to the output terminal of the voltage-controlled oscillator 205, and its output terminal connected to the third input terminal of the multiplexer 207.

[0105] In this embodiment, the core function of the frequency multiplier 208 is to amplify the frequency of the input signal by a fixed integer multiple (2 times, 3 times, 4 times...N times, where N is a positive integer) while maintaining the key characteristics of the signal (such as phase coherence and modulation information) and output a higher frequency signal; the core function of the first frequency divider 209 is to separate the input wideband signal into multiple sub-signals with different frequency ranges according to a preset standard.

[0106] The frequency multiplier 208 amplifies the signal output from the voltage-controlled oscillator 205, while the first frequency divider 209 separates the signal output from the voltage-controlled oscillator 205 to obtain a lower frequency signal. The multiplexer 207 can select the output of the frequency multiplier 208, the signal output from the voltage-controlled oscillator 205, or the output of the first frequency divider 209 to broaden the frequency range of the signal source and meet the testing needs of more scenarios.

[0107] For example, if the signal frequency output by the output terminal of the voltage-controlled oscillator 205 is 1GHz to 4GHz, then after using the frequency multiplier 208, it can be widened to 4GHz to 16GHz, and the use of the first frequency divider 209 can extend it to 0.25GHz to 1GHz. As can be seen from the above, the combined use of the frequency multiplier 208, the first frequency divider 209 and the voltage-controlled oscillator 205 can enable the signal source to output a wider range of signals, thereby meeting the testing needs in more scenarios.

[0108] In some embodiments, such as Figure 3 As shown, the signal source also includes:

[0109] The first voltage-controlled attenuator 401 has its input terminal connected to the output terminal of the phase-locked loop 200.

[0110] The input terminal of the second voltage-controlled attenuator 402 is connected to the output terminal of the first voltage-controlled attenuator 401;

[0111] Mechanical attenuator 403, the input terminal of mechanical attenuator 403 is connected to the output terminal of the second voltage-controlled attenuator 402;

[0112] The digital-to-analog converter 404 has its output terminal connected to the control terminal of the first voltage-controlled attenuator 401 and the control terminal of the second voltage-controlled attenuator 402, respectively, and its input terminal connected to the controller.

[0113] The first test parameter also includes the target output power, and the controller is also used for:

[0114] The target control voltage corresponding to the target output power is determined based on the calibration data table. The calibration data table includes multiple calibration data relationships, and each calibration data relationship includes the output power and the control voltage corresponding to the output power.

[0115] The digital-to-analog converter 404 is controlled to output the target control voltage to the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402.

[0116] The mechanical attenuator 403 has a mechanical internal structure, making it difficult to achieve rapid switching. Therefore, if the mechanical attenuator 403 is used alone to achieve rapid power adjustment, it is very easy to damage the mechanical attenuator 403.

[0117] In the technical solution of the present invention, a first voltage-controlled attenuator 401 and a second voltage-controlled attenuator 402 are set on the basis of the mechanical attenuator 403. The first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 are used to achieve small-step power attenuation. The mechanical attenuator 403, which is the final power adjustment device with large-step attenuation, does not need to be switched quickly. Only the small-step attenuation of the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 is needed to achieve rapid power adjustment. In this process, a wide range of signal power adjustment can be achieved.

[0118] Specifically, the attenuation of the mechanical attenuator 403 is fixed first, and the power agility is completely completed by the voltage-controlled attenuator (i.e., the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402) with small step attenuation, thereby improving the signal switching efficiency and the reliability of the test conditions.

[0119] In the above technical solution, the target control voltage used to control the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 is based on the target output power and is obtained by retrieving from the calibration data table. In this process, the target control voltage of the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 can be quickly located during power adjustment, which shortens the power adjustment time and improves the power adjustment accuracy.

[0120] In some embodiments, the mechanical attenuator 403 has at least two signal output terminals, and the signals output by the different signal output terminals are the same.

[0121] In this embodiment, by defining the mechanical attenuator 403 as having at least two signal output terminals, the signal source can simultaneously output the same signal using at least two signal output terminals to meet the testing needs in different scenarios.

[0122] In this invention, the signals output from different signal output terminals are frequency-hopping signals, which are output in the form of pulses.

[0123] In some embodiments, the mechanical attenuator 403 has two signal output terminals, and the signals output by the two signal output terminals are the same, such as... Figure 5 As shown, the signal output from one of the two signal output terminals (such as channel 1) is used as the horizontal polarization excitation signal, and the signal output from the other of the two signal output terminals (such as channel 2) is used as the vertical polarization excitation signal, thereby performing tests on the device under test in different scenarios.

[0124] In some embodiments, the signal source has a first signal output terminal, a second signal output terminal and a third signal output terminal, wherein the first signal output terminal is the output terminal of the first voltage-controlled attenuator 401, the second signal output terminal is the output terminal of the second voltage-controlled attenuator 402, and the third signal output terminal is the signal output terminal of the mechanical attenuator 403.

[0125] During this process, the target control voltage of the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 can be configured according to the test requirements, and then signals with different power can be output using the first signal output terminal, the second signal output terminal and the third signal output terminal, so as to meet the test requirements under different scenarios.

[0126] For example, such as Figure 4 As shown, power switching from -40dBm to 0dBm can be achieved within 2ms.

[0127] In some embodiments, the controller is further configured to:

[0128] Obtain the test parameter list, which includes multiple test parameters, including the first test parameter;

[0129] During the operation of the phase-locked loop 200 according to the first test parameters, if a trigger signal is received, the second test parameters are searched based on the test parameter list to control the phase-locked loop 200 to operate according to the second test parameters;

[0130] Among them, the first test parameter and the second test parameter are two adjacent test parameters.

[0131] In this embodiment, the test parameters can exist in the form of a test parameter list. By constructing a test parameter list, the second test parameters can be quickly determined after the test is completed according to the first test parameters. In this process, the overall test efficiency can be improved.

[0132] In some embodiments, the test parameter list is a list of multiple preprocessed test parameters.

[0133] Preprocessing is the process of setting test parameters for the signal source. This involves processing the set test parameters in real time and then transmitting the processing results to various functional modules through the control interface, thereby completing the parameter setting.

[0134] In a signal source, it is necessary to test the response to rapid changes in test parameters. Each test parameter requires the above process to be executed once, which takes a long time. By limiting the test parameter list to a list of multiple pre-processed test parameters, it is not necessary to process each test parameter again. Therefore, the overall test efficiency can be improved.

[0135] In some embodiments, the test parameter list is a list stored in memory so that the signal source can quickly recall the test parameters when performing the test.

[0136] If a trigger signal is received, the test parameter list in memory can be used to quickly switch to the next test parameter and directly complete the parameter call and delivery.

[0137] In some embodiments, the operation flow of the signal source includes a parameter initialization and configuration flow and a testing flow, wherein the parameter initialization and configuration flow corresponds to steps 601 to 606, and the testing flow corresponds to steps 607 to 611, as follows. Figure 6 As shown, the operation flow of the signal source includes:

[0138] Step 601: Set the signal frequency and power list.

[0139] The list of signal frequency and power is also the list of test parameters in this invention.

[0140] Step 602: Calculate module parameters based on the signal frequency and power list.

[0141] Step 603: Write the module parameters into memory.

[0142] Step 604: Set test parameters and switch to external trigger mode.

[0143] Step 605: Set the signal pulse width and turn on the internal pulse generation switch.

[0144] Step 606: Set the signal pulse triggering mode to frequency scanning trigger.

[0145] Step 607: Enable signal output.

[0146] Step 608: The signal source receives the trigger signal. If the judgment result is yes, proceed to step 609. If the judgment result is no, proceed to step 610.

[0147] Step 609: The signal source extracts the parameters from the corresponding memory to generate the corresponding pulse signal.

[0148] Step 610: Wait for the trigger signal.

[0149] Step 611: Is this the last list parameter? If the result is yes, end; if the result is no, proceed to step 610.

[0150] In some embodiments, such as Figure 2 As shown, the signal source also includes:

[0151] Frequency synthesizer 300;

[0152] Phase-locked loop 200 also includes:

[0153] The reference frequency divider 210 has its input terminal connected to the output terminal of the frequency synthesizer 300, and its output terminal connected to the second input terminal of the phase detector 203.

[0154] In some embodiments, the control interface of the frequency synthesizer 300 is a parallel interface.

[0155] Among them, the control interface of the frequency synthesizer 300 is the interface for the frequency synthesizer 300 to receive data. Compared with the current serial interface for data transmission, the parallel interface of the control interface can improve the data transmission speed and provide a basis for the rapid response of the signal source.

[0156] In some embodiments, the control interface of the frequency synthesizer 300 is modified from the Serial Peripheral Interface (SPI) to a parallel interface, which can increase the signal transmission rate by 8 times for a single register of the frequency synthesizer 300.

[0157] In some embodiments, a testing system is provided, comprising:

[0158] The signal source as described in any of the above embodiments;

[0159] The device under test;

[0160] The host computer communicates with the signal source and the device under test respectively, and is used to send trigger signals to the signal source and the device under test. The trigger signals include a first rising edge, a first falling edge and a low-level signal of a first duration.

[0161] Specifically, when the signal source detects a first rising edge, it configures a first test parameter; when it detects a first falling edge, it confirms that the first test parameter is effective; and when it detects that the duration of a low-level signal is greater than or equal to a first duration, it outputs a pulse signal corresponding to the first test parameter.

[0162] In this embodiment, such as Figure 7 As shown, the host computer can achieve synchronous control of the device under test and the signal source by outputting a trigger signal. Specifically, when the signal source detects the first rising edge, it configures the first test parameter; when it detects the first falling edge, it confirms that the first test parameter is effective; and when it detects that the duration of the low-level signal is greater than or equal to the first duration, it outputs a pulse signal corresponding to the first test parameter.

[0163] During this process, the signal source can simultaneously output the corresponding parameter signal while the device under test needs to receive the signal.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A signal source, characterized in that, The signal source includes a phase-locked loop (PLL), a controller connected to the PLL, a first voltage-controlled attenuator, a second voltage-controlled attenuator, a mechanical attenuator, and a digital-to-analog converter. The controller is used for: Obtain the first test parameter, which includes the target output frequency; The target lock-in voltage corresponding to the target output frequency is determined based on a mapping data table. The mapping data table includes multiple mapping relationships, and each mapping relationship includes an output frequency and a lock-in voltage corresponding to the output frequency. The output frequency is different in different mapping relationships. Adjust the output voltage of the resistor divider network in the phase-locked loop to the target locking voltage; The operating state of the phase-locked loop is changed from closed-loop to open-loop, so that the resistor voltage divider network outputs voltage to the loop filter in the phase-locked loop. The operating state of the phase-locked loop is changed from the open-loop state to the closed-loop state, so that the phase detector in the phase-locked loop outputs voltage to the loop filter; The input terminal of the first voltage-controlled attenuator is connected to the output terminal of the phase-locked loop; the input terminal of the second voltage-controlled attenuator is connected to the output terminal of the first voltage-controlled attenuator; the input terminal of the mechanical attenuator is connected to the output terminal of the second voltage-controlled attenuator; the output terminal of the digital-to-analog converter is connected to the control terminals of the first voltage-controlled attenuator and the second voltage-controlled attenuator respectively; and the input terminal of the digital-to-analog converter is connected to the controller. The first test parameter also includes the target output power, and the controller is further configured to: The target control voltage corresponding to the target output power is determined based on the calibration data table, which includes multiple calibration data relationships, each of which includes the output power and the control voltage corresponding to the output power. The digital-to-analog converter is controlled to output the target control voltage to the first voltage-controlled attenuator and the second voltage-controlled attenuator; In this process, when adjusting the power, the attenuation of the mechanical attenuator is first fixed, and then the power agility is achieved by the first voltage-controlled attenuator and the second voltage-controlled attenuator.

2. The signal source according to claim 1, characterized in that, The phase-locked loop includes: A first switch, the first input terminal of the first switch is connected to the output terminal of the resistor divider network, the second input terminal of the first switch is connected to the output terminal of the phase detector, and the output terminal of the first switch is connected to the input terminal of the loop filter; A voltage-controlled oscillator (VCO) is provided, wherein the input terminal of the VCO is connected to the output terminal of the loop filter, and the output terminal of the VCO serves as the output terminal of the phase-locked loop (PLL). The radio frequency divider has its input terminal connected to the voltage-controlled oscillator and its output terminal connected to the first input terminal of the phase detector. The step of changing the operating state of the phase-locked loop from closed-loop to open-loop, so that the resistor divider network outputs voltage to the loop filter in the phase-locked loop, is specifically performed by the controller as follows: Control the first switch to perform a first action, so that the first input terminal of the first switch is connected to the output terminal of the first switch; The step of changing the operating state of the phase-locked loop from the open-loop state to the closed-loop state, so that the phase detector in the phase-locked loop outputs a voltage to the loop filter, is specifically performed by the controller as follows: Control the first switch to perform a second action, so that the second input terminal of the first switch is connected to the output terminal of the first switch.

3. The signal source according to claim 2, characterized in that, The step of determining the target locking voltage corresponding to the target output frequency based on the mapping data table, specifically, is performed by the controller as follows: Determine the first output frequency in the mapping data table that is closest to the target output frequency; The locking voltage corresponding to the first output frequency is taken as the target locking voltage.

4. The signal source according to claim 2, characterized in that, The signal source also includes: Multiplexer; A frequency multiplier, wherein the input terminal of the frequency multiplier is connected to the output terminal of the voltage-controlled oscillator, the output terminal of the frequency multiplier is connected to the first input terminal of the multiplexer, and the output terminal of the voltage-controlled oscillator is connected to the second input terminal of the multiplexer; The first frequency divider has its input terminal connected to the output terminal of the voltage-controlled oscillator, and its output terminal connected to the third input terminal of the multiplexer.

5. The signal source according to claim 1, characterized in that, The mechanical attenuator has at least two signal output terminals, and the signals output from different signal output terminals are the same.

6. The signal source according to any one of claims 1 to 5, characterized in that, The controller is also used for: Obtain a test parameter list, which includes multiple test parameters, including a first test parameter; During the operation of the phase-locked loop according to the first test parameters, if a trigger signal is received, the second test parameter is searched based on the test parameter list to control the phase-locked loop to operate according to the second test parameters; The first test parameter and the second test parameter are two adjacent test parameters.

7. The signal source according to any one of claims 2 to 5, characterized in that, The signal source also includes: Frequency synthesizer; The phase-locked loop also includes: A reference frequency divider, the input of which is connected to the output of the frequency synthesizer, and the output of which is connected to the second input of the phase detector.

8. The signal source according to claim 7, characterized in that, The control interface of the frequency synthesizer is a parallel interface.

9. A testing system, characterized in that, include: The signal source as described in any one of claims 1 to 8; The device under test; The host computer communicates with the signal source and the device under test respectively, and is used to send trigger signals to the signal source and the device under test. The trigger signal includes a first rising edge, a first falling edge and a low-level signal of a first duration. Specifically, when the signal source detects the first rising edge, it configures the first test parameter; when it detects the first falling edge, it confirms that the first test parameter is effective; and when it detects that the duration of the low-level signal is greater than or equal to the first duration, it outputs a pulse signal corresponding to the first test parameter.

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