LED display screen monitoring system
The LED display monitoring system, with its gigabit network port connection and modular design, achieves efficient and accurate fault identification, solving the problems of low monitoring efficiency and high cost in existing technologies, and improving the system's reliability and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2026-04-10
AI Technical Summary
Existing LED display monitoring systems are inefficient and lack accuracy, failing to detect potential problems in a timely manner. Furthermore, automated systems are costly, complex, and difficult to maintain.
The host computer, transmitting card, and hub card are connected via gigabit Ethernet ports. Combined with FPGA, MCU, and sensor modules, it achieves high-speed data transmission and accurate monitoring. The FPGA module of the hub card collects data from the light board sensors to identify faults.
It improves monitoring efficiency and accuracy, reduces system response time, enhances the reliability and stability of LED displays, and adapts to application scenarios of different scales and complexities.
Smart Images
Figure CN224109973U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to LED display screen technical field especially relates to a kind of LED display screen monitoring system. BACKGROUND
[0002] Under the background that current large-scale LED display screen is widely applied in advertisement, stage performance, information display and many other fields, its stability and reliability are crucial.
[0003] LED display screen is usually composed of a large number of Hub cards and more numerous lamp panels, these components are prone to various faults in long-term operation process, such as voltage abnormality of lamp panel may lead to uneven display brightness, temperature is too high to shorten the life of components and even cause fire, bad point affects display effect, interface loosening or damage causes data transmission interruption.
[0004] Now in the prior art, the monitoring means of LED display screen is mostly dependent on artificial inspection, and the staff needs to carry professional tools to check Hub cards and lamp panels one by one, which is extremely low in efficiency, and it is difficult to find potential problems in time.
[0005] Part of the system using automatic LED display screen monitoring has the problems of incomplete data collection, high transmission delay, or relying on complex and expensive special monitoring network architecture, which not only increases the system cost, but also makes system integration and maintenance difficult, and cannot meet the modern LED display screen fast, accurate and low-cost monitoring requirements.
[0006] Therefore, it is urgent to design a LED display screen monitoring system to solve the above problems. UTILITY MODEL CONTENT
[0007] The technical problem to be solved by the utility model lies in providing a LED display screen monitoring system, which has the advantages of high monitoring efficiency and precision and speed.
[0008] In order to solve the above technical problems, the utility model provides a kind of LED display screen monitoring system, including host computer, sending card, several Hub cards and several lamp panels, and the host computer is connected with sending card by gigabit network port, and the sending card is connected with several Hub cards by gigabit network port, and each Hub card is connected with several lamp panels;The sending card is used to broadcast monitoring instruction outward;The Hub card includes first FPGA module, MCU module, gigabit phy module and external interface module, the first FPGA module is used to gather the sensor data of connected lamp panel, the MCU module is used to communicate with the first FPGA module, the gigabit phy module is used to communicate with the sending card, and the first FPGA module communicates with the lamp panel by the external interface module;The lamp panel is equipped with sensing module, and the sensing module is used to monitor the sensor data of corresponding lamp panel and send the sensor data to corresponding Hub card.
[0009] As the improvement of the above scheme, the first FPGA module includes first FPGA circuit, second FPGA circuit, test programming circuit and clock generating circuit;The first FPGA circuit is connected with the test programming circuit and clock generating circuit respectively;The first FPGA circuit is connected with MCU module, so that the first FPGA module communicates with the MCU module;The second FPGA circuit is connected with power supply, so as to distribute power supply to the first FPGA circuit, test programming circuit and clock generating circuit;The test programming circuit is used to introduce digital logic;The clock generating circuit is used to synchronize the operation of the first FPGA module digital logic.
[0010] As the improvement of the above scheme, the MCU module includes MCU circuit, Flash circuit, program download interface and MCU reset circuit;The MCU circuit is connected with first FPGA module, gigabit phy module, Flash circuit, program download interface and MCU reset circuit respectively, to process the communication between the first FPGA module, gigabit phy module, Flash circuit, program download interface and MCU reset circuit;The Flash circuit is connected with first FPGA module, MCU circuit and program download interface respectively, to store programs and configuration files for the first FPGA module and MCU circuit;The program download interface is connected with first FPGA module, MCU circuit, Flash circuit and MCU reset circuit respectively, to download programs through the program download interface;The MCU reset circuit is connected with MCU circuit and program download interface respectively, to ensure the normal start and abnormal reset start of the MCU module.
[0011] As an improvement of the above scheme, the gigabit phy module comprises a first gigabit phy module; the first gigabit phy module comprises a first transceiver chip circuit and a first network transformer circuit; the first transceiver chip circuit is connected with the first network transformer circuit and the first FPGA module respectively, and the first network transformer circuit is connected with the external interface module to control the sending and receiving of data of the first FPGA module.
[0012] As an improvement of the above scheme, the gigabit phy module further comprises a second gigabit phy module; the second gigabit phy module comprises a second transceiver chip circuit and a second network transformer circuit; the second transceiver chip circuit is connected with the second network transformer circuit and the first FPGA module respectively, and the second network transformer circuit is connected with the external interface module to control the sending and receiving of data of the first FPGA module.
[0013] As an improvement of the above scheme, the external interface module comprises a first amplifier circuit, a second amplifier circuit and an interface circuit; the first amplifier circuit is connected with the first FPGA module to amplify the signal of the first FPGA module and send it to the lamp panel; the second amplifier circuit is connected with the first FPGA module to amplify the signal of the lamp panel and send it to the first FPGA module; the interface circuit comprises a first connector; the first connector is connected with the first gigabit phy module, the first amplifier circuit, the second amplifier circuit and the first FPGA module respectively to realize signal transmission among the first gigabit phy module, the first amplifier circuit, the second amplifier circuit and the first FPGA module.
[0014] As an improvement of the above scheme, the interface circuit further comprises a second connector; the second connector is connected with the second gigabit phy module, the first amplifier circuit, the second amplifier circuit and the first FPGA module respectively to realize signal transmission among the second gigabit phy module, the first amplifier circuit, the second amplifier circuit and the first FPGA module.
[0015] As the improvement of the above scheme, the Hub card further comprises a power supply control module, which is used for step-down processing of a direct current voltage to supply power to the MCU module and the first FPGA module respectively; the power supply control module comprises a first power supply control chip, which is provided with a power supply control chip first enable pin, a power supply control chip input voltage pin, a power supply control chip second enable pin, a power supply control chip first switch pin and a power supply control chip second switch pin; the power supply control chip first enable pin, the power supply control chip input voltage pin and the power supply control chip second enable pin are connected with a power supply; the power supply control chip first switch pin is connected with the MCU module to supply power to the MCU module; and the power supply control chip second switch pin is connected with the first FPGA module to supply power to the first FPGA module.
[0016] As the improvement of the above scheme, the sending card comprises a CPU module and a second FPGA module; the CPU module is used for generating the monitoring instruction at a time; and the second FPGA module is used for receiving the monitoring instruction generated by the CPU module and broadcasting and forwarding the monitoring instruction to a designated Hub card.
[0017] As the improvement of the above scheme, the sensing module comprises a voltage detector, a temperature detector, a bad point state detector and an interface connection state detector.
[0018] The beneficial effects of the utility model lie in that:
[0019] The utility model discloses LED display screen monitoring system through the host computer between and sending card and between the sending card and Hub card all adopt gigabit network port connection, and high -speed communication mode can obviously promote data transmission efficiency, ensures the quick transmission of monitoring instruction and sensor data, reduces system response time.
[0020] Meanwhile, the first FPGA module of the Hub card can receive the monitoring instruction of the sending card and collect the sensor data of the lamp panel, so that problems can be quickly identified, the reliability and stability of the system are improved, the monitoring efficiency is high, and the precision is fast.
[0021] Further, the modular design of the first FPGA module, the MCU module, the gigabit phy module and the external interface module in the Hub card of the utility model LED display screen monitoring system can improve the management efficiency, improve the performance of the LED display screen monitoring system, make it better adapt to different scale and complexity application scenarios, and meet the high requirements of modern LED display screen monitoring systems. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 It is a structure schematic view of the utility model LED display screen monitoring system.
[0023] Figure 2 It is the first embodiment structure schematic view of Hub card in the LED display screen monitoring system of the utility model;
[0024] Figure 3 It is the circuit diagram of first FPGA circuit in the LED display screen monitoring system of the utility model;
[0025] Figure 4 It is the circuit diagram of second FPGA circuit in the LED display screen monitoring system of the utility model;
[0026] Figure 5 It is the circuit diagram of test programming circuit in the LED display screen monitoring system of the utility model;
[0027] Figure 6 It is the circuit diagram of clock generation circuit in the LED display screen monitoring system of the utility model;
[0028] Figure 7 It is the circuit diagram of MCU circuit in the LED display screen monitoring system of the utility model;
[0029] Figure 8 It is the circuit diagram of Flash circuit in the LED display screen monitoring system of the utility model;
[0030] Figure 9 It is the circuit diagram of program download interface in the LED display screen monitoring system of the utility model;
[0031] Figure 10 It is the circuit diagram of MCU reset circuit in the LED display screen monitoring system of the utility model;
[0032] Figure 11 It is the circuit diagram of first transceiver chip circuit in the LED display screen monitoring system of the utility model;
[0033] Figure 12 It is the circuit diagram of first network transformer circuit in the LED display screen monitoring system of the utility model;
[0034] Figure 13 It is the circuit diagram of second transceiver chip circuit in the LED display screen monitoring system of the utility model;
[0035] Figure 14 It is the circuit diagram of second network transformer circuit in the LED display screen monitoring system of the utility model;
[0036] Figure 15 It is the circuit diagram of fifth bus transceiver and bypass circuit in the LED display screen monitoring system of the utility model;
[0037] Figure 16 The circuit diagram of the seventh bus transceiver and bypass circuit in the LED display screen monitoring system of the utility model;
[0038] Figure 17 The circuit diagram of the eighth bus transceiver and bypass circuit in the LED display screen monitoring system of the utility model;
[0039] Figure 18 The circuit diagram of the ninth bus transceiver and bypass circuit in the LED display screen monitoring system of the utility model;
[0040] Figure 19 The circuit diagram of the first connector in the LED display screen monitoring system of the utility model;
[0041] Figure 20 The circuit diagram of the test connector in the LED display screen monitoring system of the utility model;
[0042] Figure 21 The circuit diagram of the second connector in the LED display screen monitoring system of the utility model;
[0043] Figure 22 The second embodiment structure schematic view of the Hub card in the LED display screen monitoring system of the utility model;
[0044] Figure 23 The circuit diagram of the power supply control module in the LED display screen monitoring system of the utility model. DETAILED DESCRIPTION
[0045] In order to make the purpose, technical scheme and advantage of the utility model more clear, the utility model will be described further in detail below in combination with the drawings. Only this declaration, the direction words of up, down, left, right, front, back, inside and outside etc. appearing or about to appear in the text of the utility model, only take the drawings of the utility model as the base, it is not the specific limitation to the utility model.
[0046] As shown in Figure 1 The LED display screen monitoring system of the utility model includes host computer 1, sending card 2, a plurality of Hub cards 3 and a plurality of lamp panels 4, the host computer 1 is connected through gigabit network port between sending card 2, the sending card 2 is connected through gigabit network port between a plurality of Hub cards 3, every Hub card 3 is connected with a plurality of lamp panels 4;
[0047] The sending card 2 is used to broadcast monitoring instruction outward;
[0048] As shown in Figure 2 Figure 2 The first embodiment of the Hub card in the LED display screen monitoring system is shown, the Hub card 3 comprises a first FPGA module 31, an MCU module 32, a gigabit phy module 33 and an external interface module 34, the first FPGA module 31 is used for collecting sensor data of the connected lamp panel 4, the MCU module 32 is used for communicating with the first FPGA module 31, the gigabit phy module 33 is used for communicating with the sending card 2, and the first FPGA module 31 communicates with the lamp panel 4 through the external interface module 34;
[0049] Specifically, the first FPGA module 31 is used for receiving the monitoring instruction sent by the sending card 2 to collect sensor data of all connected lamp panels 4;
[0050] The lamp panel 4 is provided with a sensing module, and the sensing module is used for monitoring sensor data of the corresponding lamp panel 4 and sending the sensor data to the corresponding Hub card 3.
[0051] Preferably, the sensing module comprises a voltage detector, a temperature detector, a bad point state detector and an interface connection state detector to detect sensor data of the lamp panel 4, i.e. voltage, temperature, bad point state and interface connection state.
[0052] The sending card comprises a CPU module and a second FPGA module;
[0053] The CPU module is used for generating the monitoring instruction at a time;
[0054] The second FPGA module is used for receiving the monitoring instruction generated by the CPU module and broadcasting and forwarding the monitoring instruction to the specified Hub card.
[0055] Specifically, the CPU module is used for performing system management scheduling, including generating the monitoring instruction at a time, receiving and analyzing the configuration parameters issued by the upper computer, uploading the comprehensive analysis data to the upper computer, the comprehensive analysis data comprises sensor data marked with errors by the first FPGA module 31, the second FPGA module is used for receiving the monitoring instruction generated by the CPU module to analyze target monitoring information, and broadcasting and forwarding the target monitoring information, the corresponding Hub card and the number of lamp panels to the specified Hub card, the principle of the CPU module and the second FPGA module of the sending card is prior art, and the specific principle is not described here.
[0056] This utility model LED display monitoring system uses gigabit Ethernet ports for connection between the host computer 1 and the sending card 2, as well as between the sending card 2 and the Hub card 3. This high-speed communication significantly improves data transmission efficiency, ensures rapid transmission of monitoring commands and sensor data, and reduces system response time. Furthermore, the first FPGA module 31 of the Hub card 3 can receive monitoring commands from the sending card 2 and collect sensor data from the lamp board 4, improving the system's reliability and stability, resulting in high monitoring efficiency and accurate and rapid monitoring.
[0057] The following combination Figures 1-23 The first FPGA module 31, MCU module 32, gigabit PHY module 33, and external interface module 34 are described in detail below:
[0058] I. First FPGA Module 31
[0059] The first FPGA module 31 includes a first FPGA circuit, a second FPGA circuit, a test programming circuit, and a clock generation circuit;
[0060] The first FPGA circuit is connected to the test programming circuit and the clock generation circuit, respectively.
[0061] The first FPGA circuit is connected to the MCU module 32 so that the first FPGA module 31 and the MCU module 32 can communicate.
[0062] The second FPGA circuit is connected to a power supply to distribute power to the first FPGA circuit, the test programming circuit, and the clock generation circuit.
[0063] The test programming circuit is used to introduce digital logic;
[0064] The clock generation circuit is used to synchronize the operation of the digital logic of the first FPGA module.
[0065] Specifically:
[0066] 1. First FPGA circuit
[0067] like Figure 3 As shown, the first FPGA circuit includes a first FPGA chip U1A, a twenty-third resistor R23, and a twenty-fifth resistor R25.
[0068] The first FPGA chip U1A is provided with a thirty-fourth general IO pin (IO_B7_3, GCLKIOB_5), a thirty-fifth general IO pin (IO_B1_4, GCLKIOB_2), an eighty-third general IO pin (IO_T_8, M0), an eighty-fourth general IO pin (IO_T_8, M1, ADC_CH_0), a twenty-first general IO pin (IO_L3_2, TDO), a twenty-second general IO pin (IO_L4_2, TMS), a twenty-fifth general IO pin (IO_B2_3, TDI), a twenty-sixth general IO pin (IO_B3_3, TCK), a seventy-ninth general IO pin (IO_T8_7, GCLKIOB_0), a seventy-eighth general IO pin (IO_T2P_7, GCLKIOT_5), a seventy-seventh general IO pin (IO_TE2N_7, GCLKIOT_4), a seventy-sixth general IO pin (IO_T7_7, D5), a seventy-fifth general IO pin (IO_T6_7, GCLKIOT_7), a seventy-fourth general IO pin (IO_T5_7, D6), a seventy-second general IO pin (IO_T4_7, D7), a seventy-first general IO pin (IO_TE1N_7, D4), a seventieth general IO pin (IO_TE1P_7, D3), a sixty-sixth general IO pin IO_R4_6, a sixty-fourth general IO pin IO_R2P_6, a sixty-third general IO pin IO_R2N_6, a sixty-second general IO pin IO_R3_6, a sixty-first general IO pin IO_R1P_6, a sixtieth general IO pin IO_R1N_6, a fifty-seventh general IO pin (IO_R1_6, GCLKIOR_4), a fifty-fifth general IO pin (IO_R3P_5, GCLKIOR_1), a fifty-fourth general IO pin (IO_R3N_5, GCLKIOR_0), a fifty-second general IO pin IO_R3_5, a fifty-first general IO pin IO_R2_5, a fiftieth general IO pin IO_R2N_5, a forty-ninth general IO pin IO_R2P_5, a forty-eighth general IO pin IO_R1N_5, a forty-seventh general IO pin IO_R1P_5, a forty-fifth general IO pin IO_R1_5, an eighth general IO pin (IO_L3_1, DONE), a sixty-seventh general IO pin (IO_T1_7, PROGRAM_B), an eighty-second general IO pin (IO_T_8, CCLK), an eightieth general IO pin (IO_T_8, D0, MISO), and a sixty-ninth general IO pin (IO_T3_7, CSO_B);
[0069] The thirty-fourth general IO pin (IO_B7_3, GCLKIOB_5) and the thirty-fifth general IO pin (IO_B1_4, GCLKIOB_2) are connected with the clock generation circuit;
[0070] The eighty-third general IO pin (IO_T_8, M0) and the eighty-fourth general IO pin (IO_T_8, M1, ADC_CH_0) are connected with the MCU module 32;
[0071] The twenty-first general IO pin (IO_L3_2, TDO), the twenty-second general IO pin (IO_L4_2, TMS), the twenty-fifth general IO pin (IO_B2_3, TDI) and the twenty-sixth general IO pin (IO_B3_3, TCK) are connected with the test programming circuit;
[0072] The seventy-ninth general IO pin (IO_T8_7, GCLKIOB_0), the seventy-eighth general IO pin (IO_T2P_7, GCLKIOT_5), the seventy-seventh general IO pin (IO_TE2N_7, GCLKIOT_4), the seventy-sixth general IO pin (IO_T7_7, D5), the seventy-fifth general IO pin (IO_T6_7, GCLKIOT_7), the seventy-fourth general IO pin (IO_T5_7, D6), the seventy-second general IO pin (IO_T4_7, D7), the seventy-first general IO pin (IO_TE1N_7, D4), the seventieth general IO pin (IO_TE1P_7, D3), the sixty-sixth general IO pin IO_R4_6, the sixty-fourth general IO pin IO_R2P_6, the sixty-third general IO pin IO_R2N_6, the sixty-second general IO pin IO_R3_6, the sixty-first general IO pin IO_R1P_6, the sixtieth general IO pin IO_R1N_6, the fifty-seventh general IO pin (IO_R1_6, GCLKIOR_4), the fifty-fifth general IO pin (IO_R3P_5, GCLKIOR_1), the fifty-fourth general IO pin (IO_R3N_5, GCLKIOR_0), the fifty-second general IO pin IO_R3_5, the fifty-first general IO pin IO_R2_5, the fiftieth general IO pin IO_R2N_5, the forty-ninth general IO pin IO_R2P_5, the forty-eighth general IO pin IO_R1N_5, the forty-seventh general IO pin IO_R1P_5 and the forty-fifth general IO pin IO_R1_5 are connected with the external interface module 34;
[0073] The eighth general IO pin (IO_L3_1, DONE) is connected with one end of the twenty-third resistor R23;
[0074] The sixty-seventh general IO pin (IO_T1_7, PROGRAM_B) is connected with one end of the twenty-fifth resistor R25;
[0075] The other end of the twenty-third resistor R23 is connected with the other end of the twenty-fifth resistor R25 and a 3.3V voltage;
[0076] The eighty-second general IO pin (IO_T_8, CCLK), the eightieth general IO pin (IO_T_8, D0, MISO) and the sixty-ninth general IO pin (IO_T3_7, CSO_B) are connected with the MCU module 32;
[0077] The model of the first FPGA chip U1A is EG4S20NG88, but it is not limited thereto;
[0078] The EG4S20G88 chip provides a highly flexible, high-performance and multi-functional solution for the first FPGA circuit, which is suitable for applications requiring complex digital logic and high-speed data communication.
[0079] 2. Second FPGA circuit
[0080] As shown in Figure 4 The second FPGA circuit comprises a second FPGA chip U1B, which is provided with a second FPGA auxiliary power supply pin VCCAUX, two second FPGA first IO pins VCCIO1, two second FPGA second IO pins VCCIO2, a second FPGA third IO pin VCCIO3, a second FPGA fourth IO pin VCCIO4, two second FPGA fifth IO pins VCCIO5, two second FPGA sixth IO pins VCCIO6, a second FPGA seventh IO pin VCCIO7, a second FPGA eighth IO pin VCCIO8, three second FPGA power supply pins VCC, a second FPGA ground pin GND and a second FPGA heat dissipation ground pin (EP AD);
[0081] The second FPGA auxiliary power supply pin VCCAUX, the two second FPGA first IO pins VCCIO1, the two second FPGA second IO pins VCCIO2, the second FPGA third IO pin VCCIO3, the second FPGA fourth IO pin VCCIO4, the two second FPGA fifth IO pins VCCIO5, the two second FPGA sixth IO pins VCCIO6, the second FPGA seventh IO pin VCCIO7 and the second FPGA eighth IO pin VCCIO8 are connected with a 3.3V voltage;
[0082] 3 second FPGA power supply pins VCC are connected with 1.2V voltage;
[0083] The second FPGA ground pin GND is connected with a second FPGA heat dissipation ground pin (EP AD) and grounded;
[0084] The model of the second FPGA chip U1B is EG4S20NG88, but it is not limited thereto.
[0085] 3. Test programming circuit
[0086] As shown in Figure 5 , the test programming circuit comprises a first logic device CON1, a fourteenth resistor R14, a fifteenth resistor R15 and a sixteenth resistor R16;
[0087] The first logic device CON1 is provided with a logic device first pin 1 to a logic device sixth pin 6;
[0088] The logic device first pin 1 is connected with the first FPGA circuit through one end of the fourteenth resistor R14;
[0089] The logic device second pin 2 is grounded;
[0090] The logic device third pin 3 is connected with the first FPGA circuit;
[0091] The logic device fifth pin 5 is connected with the first FPGA circuit through one end of the fifteenth resistor R15;
[0092] The logic device sixth pin 6 is connected with the first FPGA circuit through one end of the sixteenth resistor R16;
[0093] The other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15 and the other end of the sixteenth resistor R16 are connected and connected with 3.3V voltage;
[0094] The model of the first logic device CON1 is CPLDPRG, but it is not limited thereto.
[0095] 4. Clock generation circuit
[0096] As shown in Figure 6 , the clock generation circuit comprises a second clock generation chip U2, a first capacitor C1, a second capacitor C2, a fourth resistor R4, a fifth resistor R5, a fiftieth resistor R50, a first resistor R1 and a twentieth resistor FB20;
[0097] The second clock generation chip U2 is provided with an external reference clock pin CLKIN, a power off / enable output pin PD# / OE, a frequency selection pin FS, a second clock generation chip ground pin GND, a second clock generation chip power supply pin VDD, a modulation output pin ModOUT, an extended function pin SSEXTR and a mode selection pin MR;
[0098] The external reference clock pin CLKIN is connected with the first FPGA circuit through the fifth resistor R5, the fiftieth resistor R50 and one end of the twentieth resistor FB20 in sequence;
[0099] The other end of the twentieth resistor FB20 is connected with the modulation output pin ModOUT;
[0100] The power off / enable output pin PD# / OE is connected with one end of the second capacitor C2 and one end of the first capacitor C1;
[0101] The other end of the second capacitor C2 is connected with the other end of the first capacitor C1 and grounded;
[0102] The mode selection pin MR is connected with the second clock generation chip power supply pin VDD and the power off / enable output pin PD# / OE and connected with a 3.3V voltage;
[0103] The frequency selection pin FS is connected with the second clock generation chip ground pin GND through the fourth resistor R4 and grounded;
[0104] The extended function pin SSEXTR is grounded through the first resistor R1.
[0105] The model of the second clock generation chip U2 is SSDCP2501, but it is not limited thereto.
[0106] II. MCU module 32
[0107] The MCU module 32 comprises an MCU circuit, a Flash circuit, a program download interface and an MCU reset circuit;
[0108] The MCU circuit is connected with the first FPGA module, the gigabit phy module, the Flash circuit, the program download interface and the MCU reset circuit respectively to process the communication among the first FPGA module, the gigabit phy module, the Flash circuit, the program download interface and the MCU reset circuit;
[0109] The Flash circuit is connected with the first FPGA module, the MCU circuit and the program download interface respectively to store programs and configuration files for the first FPGA module and the MCU circuit;
[0110] The program download interface is connected with the first FPGA module, the MCU circuit, the Flash circuit and the MCU reset circuit respectively to download programs through the program download interface.
[0111] The MCU reset circuit is connected with the MCU circuit and the program download interface respectively to ensure normal start and abnormal reset start of the MCU module.
[0112] Specifically,
[0113] 1. MCU circuit
[0114] As shown in the figure, the MCU circuit includes a nineteenth controller CU19, a ninety-sixth resistor CR96, a sixtieth capacitor CC60, a sixty-first capacitor CC61, a fifty-eighth capacitor CC58 and an eightieth resistor CR80. Figure 7
[0115] The nineteenth controller CU19 is provided with a start mode configuration pin BOOT0, an external crystal oscillator input pin OSC_IN / PF0, an external crystal oscillator output pin OSC_OUT / PF1, an external reset input pin NRST, a controller power supply pin VDDA, a controller main power supply pin VDD, two controller ground pins VSS, a zeroth A-end controller general-purpose pin PA0 to an eighth A-end controller general-purpose pin PA8, a ninth A-end controller general-purpose pin PA9 / UART_TX, a tenth A-end controller general-purpose pin PA10 / UART_RX, a thirteenth A-end controller general-purpose pin PA13 to a fifteenth A-end controller general-purpose pin PA15, a zeroth B-end controller general-purpose pin PB0, a first B-end controller general-purpose pin PB1, a third B-end controller general-purpose pin PB3 to a seventh B-end controller general-purpose pin PB7.
[0116] The mode configuration pin BOOT0 is grounded through the ninety-sixth resistor CR96.
[0117] The external crystal oscillator input pin OSC_IN / PF0 and the external crystal oscillator output pin OSC_OUT / PF1 are connected with the first FPGA module 31.
[0118] The external reset input pin NRST is connected with the MCU reset circuit.
[0119] The controller power supply pin VDDA and the controller main power supply pin VDD are connected and connected with a 3.3V voltage in turn through one end of the fifty-eighth capacitor CC58, one end of the sixty-first capacitor CC61 and one end of the sixtieth capacitor CC60.
[0120] Two said controller ground pins VSS are connected and grounded in turn through the other end of the fifty-eighth capacitor CC58, the other end of the sixty-first capacitor CC61 and the other end of the sixtieth capacitor CC60;
[0121] The fourth A-end controller general pin PA4 to the seventh A-end controller general pin PA7 are connected with the Flash circuit;
[0122] The ninth A-end controller general pin PA9 / UART_TX and the tenth A-end controller general pin PA10 / UART_RX are connected with the first FPGA module 31;
[0123] The thirteenth A-end controller general pin PA13 and the fourteenth A-end controller general pin PA14 are connected with the program download interface
[0124] The fifteenth A-end controller general pin PA15 is connected with the first FPGA module 31;
[0125] The first B-end controller general pin PB1 and the fourth B-end controller general pin PB4 are connected with the gigabit phy module 33;
[0126] The fifth B-end controller general pin PB5 is connected with 3.3V voltage through the eightieth resistor R80;
[0127] The nineteenth controller CU19 is of the type GD32E230 G8, but is not limited thereto;
[0128] The nineteenth controller CU19 provides a reliable control system suitable for various application scenarios, which can meet complex application requirements by integrating various communication interfaces and peripheral control functions, and has good development friendliness and expansibility.
[0129] 2. Flash circuit
[0130] As shown in Figure 8 The Flash circuit includes an eighteenth memory CU18, the eighteenth memory CU18 is provided with a memory chip selection signal pin CS, a memory data output pin SO, a memory write protection pin WP, a memory power supply pin VCC, a memory pause operation pin HOLD, a memory serial clock input pin SCK and a memory data input pin SI.
[0131] The memory chip selection signal pin CS is connected with the MCU circuit;
[0132] The memory data output pin SO is connected with the MCU circuit and the first FPGA module 31;
[0133] The memory power supply pin VCC is connected to the memory pause operation pin HOLD and is connected to a 3.3V voltage.
[0134] The memory serial clock input pin SCK is connected to the MCU circuit, the program download interface, and the first FPGA module 31.
[0135] The memory data input pin SI is connected to the MCU circuit and the program download interface;
[0136] The model of the eighteenth memory CU18 is W25Q32JVSSIQ, but this is not a limitation.
[0137] 3. Program download interface
[0138] like Figure 9 As shown, the program download interface includes a first program interface CJ1, which has a first interface pin 1 to a tenth interface pin 10.
[0139] The first interface pin 1 is grounded;
[0140] The third interface pin 3 is connected to the MCU reset circuit;
[0141] The fourth interface pin 4 is connected to the MCU circuit, the Flash circuit and the first FPGA module 31;
[0142] The fifth interface pin 5 is connected to the MCU circuit.
[0143] The sixth interface pin 6 is connected to the MCU circuit and the Flash circuit.
[0144] The seventh interface pin 7 is connected to the MCU circuit.
[0145] The eighth interface pin 8 is connected to the MCU circuit and the Flash circuit.
[0146] The tenth interface pin 10 is connected to the MCU circuit, the Flash circuit and the first FPGA module 31;
[0147] The model of the first program interface CJ1 is IDC-10 / NP, but this is not a limitation.
[0148] 4. MCU reset circuit
[0149] like Figure 10 As shown, the MCU reset circuit includes the tenth monitoring chip U10, the seventh capacitor C7, the twenty-eighth resistor R28, the ninth capacitor C9, the twenty-ninth resistor R29, and the tenth capacitor C10.
[0150] The tenth monitoring chip U10 is provided with a monitoring chip reset output pin NRST, a monitoring chip ground pin GND, a monitoring chip power input pin VDD and a monitoring chip manual reset pin / MR;
[0151] The monitoring chip reset output pin NRST is connected with a 3.3V voltage through the twenty-eighth resistor R28 and is connected with the MCU circuit;
[0152] The monitoring chip ground pin GND is grounded;
[0153] The monitoring chip power input pin VDD is connected with a 3.3V voltage and is connected with the monitoring chip manual reset pin / MR in sequence through one end of the ninth capacitor C9, the twenty-ninth resistor R29, one end of the tenth capacitor C10;
[0154] The monitoring chip manual reset pin / MR is connected with a program download interface;
[0155] The other end of the ninth capacitor C9 is grounded;
[0156] The other end of the tenth capacitor C10 is grounded.
[0157] The tenth monitoring chip U10 is of VP811SEUS-T / ZLM811SEUS, but is not limited thereto.
[0158] III. Gigabit phy module 33
[0159] The gigabit phy module 33 comprises a first gigabit phy module;
[0160] The first gigabit phy module comprises a first transceiver chip circuit and a first network transformer circuit;
[0161] The first transceiver chip circuit is connected with the first network transformer circuit and the first FPGA module respectively, and the first network transformer circuit is connected with an external interface module to control the sending and receiving of data of the first FPGA module.
[0162] Specifically:
[0163] 1. First transceiver chip circuit
[0164] As shown in Figure 11 The first transceiver chip circuit comprises a third transceiver chip U3, a first coil L1, a fifty-eighth capacitor C58 and a sixty-eighth capacitor C68;
[0165] The third transceiver chip U3 is provided with a pin zeroth differential signal positive end pin MDI[0]+~third differential signal positive end pin MDI[3]+, a zeroth differential signal negative end pin MDI[0]+~third differential signal negative end pin MDI[3]+, a third analog power supply pin AVDD10_3, an eighth analog power supply pin AVDD10_8, a fortyth analog power supply pin AVDD33_40, a transceiver chip reset pin REST, a thirty-eighth analog power supply pin AVDD10_38, a transceiver chip output pin XTAL_OUT / EXT_CLK, a transceiver chip clock input pin XTAL_IN, a transceiver chip clock output pin CLKOUT, a transceiver chip second indication configuration pin LED2 / CFG_LDO1, a transceiver chip first indication configuration pin LED1 / CFG_LDO0, an indication configuration power mode pin LED0 / CFG_EXT, a transceiver chip configuration application pin INTB / PMEB, an eleventh analog power supply pin AVD33_11, a transceiver chip hardware reset pin PHYRSTB, a transceiver chip management data clock pin MDC, a transceiver chip management data input / output pin MDIO, a transceiver chip third transmission data pin TXD3, a transceiver chip second transmission data pin TXD2, a transceiver chip first transmission data pin TXD1, a transceiver chip zeroth transmission data pin TXD0, a transceiver chip transmission control signal pin TXCTL, a transceiver chip transmission reference clock pin TXC, an internal regulator output pin REG_OUT, a digital non-RGMIII / O power supply pin DVDD33_29, a digital RGMIII / OPad power supply pin DVDD_RG, a continuous acceptance reference clock pin RXC / PHYAD1, a reception control signal pin RXCTL / PHYAD2, a zeroth reception data pin RXD0 / RXDLY, a first reception data pin RXD1 / TXDLY, a second reception data pin RXD2 / PLLOFF, a third reception data pin RXD3 / PHYAD0, and a twenty-first analog power supply pin DVDD10_21.
[0166] The zeroth differential signal positive end pin MDI[0]+~third differential signal positive end pin MDI[3]+and the zeroth differential signal negative end pin MDI[0]+~third differential signal negative end pin MDI[3]+are connected with the first network transformer circuit;
[0167] The fortyth analog power supply pin AVDD33_40 is connected with a 3.3V voltage;
[0168] The transceiver chip clock output pin CLKOUT is connected with the first FPGA module 31;
[0169] The eleventh analog power pin AVD33_11 is connected with 3.3V voltage;
[0170] The internal regulator output pin REG_OUT is connected with one end of the fifty-eighth capacitor C58 and one end of the sixtieth capacitor C60 through the first coil L1 in turn;
[0171] The other end of the fifty-eighth capacitor C58 is connected with the other end of the sixtieth capacitor C60 and grounded;
[0172] The digital non-RGMIII / O power pin DVDD33_29 and the digital RGMIII / O Pad power pin DVDD_RG are connected with 3.3V voltage;
[0173] The model of the third transceiver chip U3 is RTL8211F(D)(I), but is not limited thereto.
[0174] 2. The first network transformer circuit
[0175] As shown in Figure 12 , the first network transformer circuit comprises a third network transformer T3, a first one hundred thirty-sixth capacitor C136, a first one hundred thirty-seventh capacitor C137, a first one hundred thirty-eighth capacitor C138, a first one hundred thirty-ninth capacitor C139, four first one hundred thirty-first resistors RP131 and a first one hundred fifty-ninth capacitor C159;
[0176] The third network transformer T3 is provided with a first synchronous transmission data pin TCT1 to a fourth synchronous transmission data pin TCT4, a first synchronous reception data pin MCT1 to a fourth synchronous reception data pin MCT4, a first positive terminal transmission data pin TD1+ to a fourth positive terminal transmission data pin TD4+, a first negative terminal transmission data pin TD1- to a fourth negative terminal transmission data pin TD4-, a first positive terminal reception data pin MX1+ to a fourth positive terminal reception data pin MX4+ and a first negative terminal reception data pin MX1-+ to a fourth negative terminal reception data pin MX4-;
[0177] The first synchronous transmission data pin TCT1 is connected with one end of the one hundred thirty-sixth capacitor C136;
[0178] The second synchronous transmission data pin TCT2 is connected with one end of the one hundred thirty-seventh capacitor C137;
[0179] The third synchronous transmission data pin TCT3 is connected with one end of the one hundred thirty-eighth capacitor C138;
[0180] The fourth synchronous transmission data pin TCT4 is connected with one end of the one hundred thirty-eighth capacitor C138;
[0181] The other end of the one hundred thirty-sixth capacitor C136 is connected with the other end of the one hundred thirty-seventh capacitor C137, the other end of the one hundred thirty-eighth capacitor C138 and the other end of the one hundred thirty-eighth capacitor C138 and grounded;
[0182] The first synchronization receiving data pin MCT1 is connected with one end of the first one hundred thirty-first resistor RP131;
[0183] The second synchronization receiving data pin MCT2 is connected with one end of the second one hundred thirty-first resistor RP131;
[0184] The third synchronization receiving data pin MCT3 is connected with one end of the third one hundred thirty-first resistor RP131;
[0185] The fourth synchronization receiving data pin MCT4 is connected with one end of the fourth one hundred thirty-first resistor RP131;
[0186] The other end of the first one hundred thirty-first resistor RP131, the other end of the second one hundred thirty-first resistor RP131, the other end of the third one hundred thirty-first resistor RP131 and the other end of the fourth one hundred thirty-first resistor RP131 are connected with the first one hundred fifty-ninth capacitor C159;
[0187] The first positive end transmitting data pin TD1+ to the fourth positive end transmitting data pin TD4+ are all connected with the first transceiver chip circuit;
[0188] The first negative end transmitting data pin TD1- to the fourth negative end transmitting data pin TD4- are all connected with the first transceiver chip circuit;
[0189] The first positive end receiving data pin MX1+ to the fourth positive end receiving data pin MX4+ are all connected with the external interface module 34;
[0190] The first negative end receiving data pin MX1-+ to the fourth negative end receiving data pin MX4- are all connected with the external interface module 34.
[0191] The third network transformer T3 is of the model HR682480, but is not limited thereto.
[0192] The gigabit phy module 33 further comprises a second gigabit phy module;
[0193] The second gigabit phy module comprises a second transceiver chip circuit and a second network transformer circuit;
[0194] The second transceiver chip circuit is connected with a second network transformer circuit and a first FPGA module respectively, the second network transformer circuit is connected with an external interface module to control the sending and receiving of data of the first FPGA module.
[0195] Figure 13 and Figure 14 The circuit structures of the second transceiver chip circuit and the second network transformer circuit are shown respectively, the structure of the second transceiver chip circuit is consistent with that of the first transceiver chip circuit, and the structure of the second network transformer circuit is consistent with that of the first network transformer circuit, which is not repeated here.
[0196] Four, the external interface module 34
[0197] The external interface module 34 includes a first amplifier circuit, a second amplifier circuit and an interface circuit;
[0198] The first amplifier circuit is connected with the first FPGA module 31 to amplify the signal of the first FPGA module 31 and send it to the lamp panel 4;
[0199] The second amplifier circuit is connected with the first FPGA module 31 to amplify the signal of the lamp panel 4 and send it to the first FPGA module 31;
[0200] The interface circuit includes a first connector;
[0201] The first connector is connected with the first gigabit phy module, the first amplifier circuit, the second amplifier circuit and the first FPGA module 31 respectively to transmit signals in the first gigabit phy module, the first amplifier circuit, the second amplifier circuit and the first FPGA module 31.
[0202] Specifically:
[0203] 1. The first amplifier circuit
[0204] As Figure 15 and Figure 16As shown, the first amplifier circuit includes the fifth bus transceiver U5, the seventh bus transceiver U7, the forty-second resistor R24, the sixty-second resistor R62, the sixty-third resistor R63, the fifty-fourth resistor R54, the fifty-fifth resistor R55, the fifty-sixth resistor R56, the fifty-seventh resistor R57, the forty-first resistor R41, the seventieth resistor R70, the seventy-first resistor R71, 4 second resistors RP2, the third capacitor CF3, the fourth capacitor CF4, the fifth capacitor CF5, the sixth capacitor CF6, the seventh capacitor CF7, the eighth capacitor CF8, the ninth capacitor CF9, the first capacitor CB1, the second capacitor CB2, the fifty-eighth resistor R58, the fifty-ninth resistor R59, the sixtieth resistor R60, the sixty-first resistor R61, the sixty-eighth resistor R68, the sixty-ninth resistor R69, 4 fifth resistors RP50, 4 ninth resistors RP9, the nineteenth capacitor CF19, the twentieth capacitor CF20, the thirty-sixth capacitor CF36, the thirty-seventh capacitor CF37, the thirty-eighth capacitor CF38, the thirty-ninth capacitor CF39, the twenty-first capacitor CF21, the fifth capacitor CB5, and the sixth capacitor CB6;
[0205] The fifth bus transceiver U5 is provided with the fifth bus transceiver zeroth A-group pin A0 to the fifth bus transceiver seventh A-group pin A7, the fifth bus transceiver zeroth B-group pin B0 to the fifth bus transceiver seventh B-group pin B7, the fifth bus transceiver enable pin E, the fifth bus transceiver direction pin A>>B, the fifth bus transceiver ground pin GND, and the fifth bus transceiver power pin VCC.
[0206] The fifth bus transceiver zeroth A-group pin A0 is connected with the first FPGA module 31 and connected with the 3.3V voltage through the forty-second resistor R42.
[0207] The fifth bus transceiver first A-group pin A1 is connected with the first FPGA module 31.
[0208] The fifth bus transceiver second A-group pin A2 is connected with one end of the fifty-seventh resistor R57 and connected with the first FPGA module 31.
[0209] The fifth bus transceiver third A-group pin A3 is connected with one end of the fifty-sixth resistor R56 and connected with the first FPGA module 31.
[0210] The fifth bus transceiver fourth A-group pin A4 is connected with one end of the fifty-fifth resistor R55 and connected with the first FPGA module 31.
[0211] The fifth bus transceiver fifth A-group pin A5 is connected with one end of the fifty-fourth resistor R54 and connected with the first FPGA module 31.
[0212] The sixth A group pin A6 of the fifth bus transceiver is connected with one end of the sixth resistor R63 and the first FPGA module 31;
[0213] The seventh A group pin A7 of the fifth bus transceiver is connected with one end of the sixth resistor R62 and the first FPGA module 31;
[0214] The other end of the fifty-seventh resistor R57 is connected with the other end of the fifty-sixth resistor R56, the other end of the fifty-fifth resistor R55, the other end of the fifty-fourth resistor R54, the other end of the sixth resistor R63 and the other end of the sixth resistor R62 and is connected with 3.3V voltage;
[0215] The zero B group pin B0 of the fifth bus transceiver is connected with the first FPGA module 31 and is connected with 3.3V voltage through the forty-first resistor R41;
[0216] The first B group pin B1 of the fifth bus transceiver is connected with the first FPGA module 31;
[0217] The second B group pin B2 of the fifth bus transceiver is connected with one end of the third capacitor CF3 through the seventy-first resistor R70;
[0218] The third B group pin B3 of the fifth bus transceiver is connected with one end of the fourth capacitor CF4 through the seventy-first resistor R71;
[0219] The fourth B group pin B4 of the fifth bus transceiver is connected with one end of the fifth capacitor CF5 through one second resistor RP2;
[0220] The fifth B group pin B5 of the fifth bus transceiver is connected with one end of the sixth capacitor CF6 through one second resistor RP2;
[0221] The sixth B group pin B6 of the fifth bus transceiver is connected with one end of the seventh capacitor CF7 through one second resistor RP2;
[0222] The seventh B group pin B7 of the fifth bus transceiver is connected with one end of the eighth capacitor CF8 through one second resistor RP2;
[0223] The other end of the third capacitor CF3 is connected with the other end of the fourth capacitor CF4, the other end of the fifth capacitor CF5, the other end of the sixth capacitor CF6, the other end of the seventh capacitor CF7 and the other end of the eighth capacitor CF8 and is grounded;
[0224] The enable pin E of the fifth bus transceiver is connected with the ground pin GND of the fifth bus transceiver and is grounded;
[0225] The fifth bus transceiver direction pin A>>B is connected with the fifth bus transceiver power pin VCC and is connected with 3.3V voltage through one end of the second capacitor CB2, one end of the first capacitor CB1 and one end of the ninth capacitor CF9 in turn;
[0226] The other end of the second capacitor CB2 is connected with the other end of the first capacitor CB1 and the other end of the ninth capacitor CF9 and is grounded;
[0227] The seventh bus transceiver U7 is provided with the seventh bus transceiver zeroth A group pin A0-seventh bus transceiver seventh A group pin A7, the seventh bus transceiver zeroth B group pin B0-seventh bus transceiver seventh B group pin B7, the seventh bus transceiver enable pin E, the seventh bus transceiver direction pin A>>B, the seventh bus transceiver ground pin GND, the seventh bus transceiver power pin VCC;
[0228] The seventh bus transceiver zeroth A group pin A0 is connected with the seventh bus transceiver first A group pin A1 and is grounded;
[0229] The seventh bus transceiver second A group pin A2 is connected with one end of the sixty-ninth resistor R69 and is connected with the first FPGA module 31;
[0230] The seventh bus transceiver third A group pin A3 is connected with one end of the sixty-eighth resistor R68 and is connected with the first FPGA module 31;
[0231] The seventh bus transceiver fourth A group pin A4 is connected with one end of the fifty-eighth resistor R58 and is connected with the first FPGA module 31;
[0232] The seventh bus transceiver fifth A group pin A5 is connected with one end of the fifty-ninth resistor R59 and is connected with the first FPGA module 31;
[0233] The seventh bus transceiver sixth A group pin A6 is connected with one end of the sixtieth resistor R60 and is connected with the first FPGA module 31;
[0234] The seventh bus transceiver seventh A group pin A7 is connected with one end of the sixty-first resistor R61 and is connected with the first FPGA module 31;
[0235] The other end of the sixty-ninth resistor R69 is connected with the other end of the sixty-eighth resistor R68, the other end of the fifty-eighth resistor R58, the other end of the fifty-ninth resistor R59, the other end of the sixtieth resistor R60 and the other end of the sixty-first resistor R61 and is connected with 3.3V voltage;
[0236] The seventh bus transceiver second group pin B2 is connected with one end of the nineteenth capacitor CF19 through one fifth resistor RP5;
[0237] The seventh bus transceiver third group pin B3 is connected with one end of the twentieth capacitor CF20 through one fifth resistor RP5;
[0238] The seventh bus transceiver fourth group pin B4 is connected with one end of the thirty-sixth capacitor CF36 through one ninth resistor RP9;
[0239] The seventh bus transceiver fifth group pin B5 is connected with one end of the thirty-seventh capacitor CF37 through one ninth resistor RP9;
[0240] The seventh bus transceiver sixth group pin B6 is connected with one end of the thirty-eighth capacitor CF38 through one ninth resistor RP9;
[0241] The seventh bus transceiver seventh group pin B7 is connected with one end of the thirty-ninth capacitor CF39 through one ninth resistor RP9;
[0242] The other end of the nineteenth capacitor CF19 is connected with the other end of the twentieth capacitor CF20, the other end of the thirty-sixth capacitor CF36, the other end of the thirty-seventh capacitor CF37, the other end of the thirty-eighth capacitor CF38 and the other end of the thirty-ninth capacitor CF39 and grounded;
[0243] The seventh bus transceiver enable pin E is connected with the seventh bus transceiver ground pin GND and grounded;
[0244] The seventh bus transceiver direction pin A>B is connected with the seventh bus transceiver power pin VCC and connected with 3.3V voltage through one end of the sixth capacitor CB6, one end of the fifth capacitor CB5 and one end of the twenty-first capacitor CF21 in turn;
[0245] The other end of the sixth capacitor CB6 is connected with the other end of the fifth capacitor CB5 and the other end of the twenty-first capacitor CF21 and grounded;
[0246] The fifth bus transceiver U5 and the seventh bus transceiver U7 are of the type SN74HC245PWR, but are not limited thereto.
[0247] 2. Second amplifier circuit
[0248] As Figure 17 And Figure 18As shown, the second amplifier circuit includes an eighth bus transceiver U8, a ninth bus transceiver U9, a forty-third resistor R43, a forty-fourth resistor R44, four seventh resistors RP7, a twenty-fourth capacitor CF24, a twenty-fifth capacitor CF25, a twenty-sixth capacitor CF26, a twenty-seventh capacitor CF27, a twenty-eighth capacitor CF28, a twenty-ninth capacitor CF29, a thirty-second resistor R32, a thirty-first resistor R31, a thirtieth resistor R30, a twenty-fourth resistor R24, a sixty-fourth resistor R64, a sixty-fifth resistor R65, an eighth capacitor CB8, a seventh capacitor CB7, a thirtieth capacitor CF30,
[0249] four fourteenth resistors RP14, four sixteenth resistors RP16, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a sixty-sixth resistor R66, a sixty-seventh resistor R67, a first capacitor CF1, a second capacitor CF2, a seventeenth capacitor CF17, an eighteenth capacitor CF18, a twenty-second capacitor CF22, a twenty-third capacitor CF23, a tenth capacitor CB10, a ninth capacitor CB9, and a thirty-first capacitor CF31.
[0250] The eighth bus transceiver U8 is provided with eighth bus transceiver zeroth A group pins A0-seventh bus transceiver seventh A group pins A7, eighth bus transceiver zeroth B group pins B0-eighth bus transceiver seventh B group pins B7, eighth bus transceiver enable pin E, eighth bus transceiver direction pin A>>B, eighth bus transceiver ground pin GND, and eighth bus transceiver power supply pin VCC.
[0251] The eighth bus transceiver second A group pin A2-the eighth bus transceiver seventh A group pin A7 are all connected with the first FPGA module 31;
[0252] The eighth bus transceiver zeroth B group pin B0 is connected with the eighth bus transceiver first B group pin B1 and grounded;
[0253] The eighth bus transceiver second B group pin B2 is connected with one end of the twenty-fourth capacitor CF24 through the forty-third resistor R43 and the sixty-fifth resistor R65 in sequence;
[0254] The eighth bus transceiver third B group pin B3 is connected with one end of the twenty-fifth capacitor CF25 through the forty-fourth resistor R44 and the sixty-fourth resistor R64 in sequence;
[0255] The eighth bus transceiver fourth B group pin B4 is connected with one end of the twenty-sixth capacitor CF26 through one of the seventh resistor RP7 and the twenty-fourth resistor R24 in sequence;
[0256] The eighth bus transceiver fifth B group pin B5 is connected with one end of the twenty-seventh capacitor CF27 through one of the seventh resistor RP7 and thirty-one resistor R31 in turn.
[0257] The eighth bus transceiver sixth B group pin B6 is connected with one end of the twenty-eighth capacitor CF28 through one of the seventh resistor RP7 and thirty-one resistor R31 in turn.
[0258] The eighth bus transceiver seventh B group pin B7 is connected with one end of the twenty-ninth capacitor CF29 through one of the seventh resistor RP7 and thirty-two resistor R32 in turn.
[0259] The other end of the twenty-fourth capacitor CF24 is connected with the other end of the twenty-fifth capacitor CF25, the other end of the twenty-sixth capacitor CF26, the other end of the twenty-seventh capacitor CF27, the other end of the twenty-eighth capacitor CF28 and the other end of the twenty-ninth capacitor CF29 and grounded.
[0260] The eighth bus transceiver enable pin E is connected with the eighth bus transceiver ground pin GND and grounded.
[0261] The eighth bus transceiver direction pin A>>B is grounded.
[0262] The eighth bus transceiver power pin VCC is connected with 3.3V voltage through one end of the eighth capacitor CB8, one end of the seventh capacitor CB7 and one end of the thirtieth capacitor CF30 in turn.
[0263] The other end of the eighth capacitor CB8 is connected with the other end of the seventh capacitor CB7 and the other end of the thirtieth capacitor CF30 and grounded.
[0264] The ninth bus transceiver U9 is provided with ninth bus transceiver zero A group pin A0-ninth bus transceiver seventh A group pin A7, ninth bus transceiver zero B group pin B0-ninth bus transceiver seventh B group pin B7, ninth bus transceiver enable pin E, ninth bus transceiver direction pin A>>B, ninth bus transceiver ground pin GND, ninth bus transceiver power pin VCC.
[0265] The ninth bus transceiver second A group pin A2-ninth bus transceiver seventh A group pin A7 are connected with the first FPGA module 31.
[0266] The ninth bus transceiver zero B group pin B0 is grounded through one of the fourteenth resistor RP14.
[0267] The ninth bus transceiver first B group pin B1 is grounded through one of the fourteenth resistors RP14;
[0268] The ninth bus transceiver second B group pin B2 is connected to one end of the first capacitor CF1 through one of the fourteenth resistors RP14 and one end of the thirty-third resistor R33 in turn;
[0269] The ninth bus transceiver third B group pin B3 is connected to one end of the second capacitor CF2 through one of the fourteenth resistors RP14 and one end of the thirty-fourth resistor R34 in turn;
[0270] The ninth bus transceiver fourth B group pin B4 is connected to one end of the seventeenth capacitor CF17 through one of the sixteenth resistors RP16 and one end of the thirty-fifth resistor R35 in turn;
[0271] The ninth bus transceiver fifth B group pin B5 is connected to one end of the eighteenth capacitor CF18 through one of the sixteenth resistors RP16 and one end of the thirty-sixth resistor R36 in turn;
[0272] The ninth bus transceiver sixth B group pin B6 is connected to one end of the twenty-second capacitor CF22 through one of the sixteenth resistors RP16 and one end of the sixty-sixth resistor R66 in turn;
[0273] The ninth bus transceiver seventh B group pin B7 is connected to one end of the twenty-third capacitor CF23 through one of the sixteenth resistors RP16 and one end of the sixty-seventh resistor R67 in turn;
[0274] The other end of the first capacitor CF1 is connected to the other end of the second capacitor CF2, the other end of the seventeenth capacitor CF17, the other end of the eighteenth capacitor CF18, the other end of the twenty-second capacitor CF22 and the other end of the twenty-third capacitor CF23 and grounded;
[0275] The ninth bus transceiver enable pin E is connected to the ninth bus transceiver ground pin GND and grounded;
[0276] The ninth bus transceiver direction pin A>>B is grounded;
[0277] The ninth bus transceiver power supply pin VCC is connected to 3.3V voltage through one end of the tenth capacitor CB10, one end of the ninth capacitor CB9 and one end of the thirty-first capacitor CF31 in turn;
[0278] The other end of the tenth capacitor CB10 is connected to the other end of the ninth capacitor CB9 and the other end of the thirty-first capacitor CF31 and grounded;
[0279] The model of the eighth bus transceiver U8 and the ninth bus transceiver U9 is SN74HC245PWR, but this is not a limitation.
[0280] 3. Interface circuit
[0281] like Figure 19 As shown, the interface circuit includes a first connector JP1;
[0282] The first connector JP1 is provided with first connector first pin 1 to first connector thirtieth pin 30;
[0283] Pin 3 of the first connector to pin 10 of the tenth connector are all connected to the first gigabit PHY module;
[0284] The eleventh pin 11 of the first connector is grounded;
[0285] The twelfth pin 12 of the first connector is connected to the twenty-sixth pin 26 of the first connector and grounded;
[0286] Pins 13 to 18 of the first connector are all connected to the first amplifier circuit.
[0287] Pins 19 to 24 of the first connector are all connected to the second amplifier circuit.
[0288] The twenty-fifth pin 25 of the first connector is connected to the first FPGA module 31;
[0289] The twenty-seventh pin 27 of the first connector is connected to a 3.3V voltage.
[0290] The twenty-eighth pin 28 of the first connector is grounded;
[0291] Pin 29 of the first connector is connected to the power supply;
[0292] The thirtieth pin 30 of the first connector is connected to the power supply.
[0293] like Figure 20 As shown, the interface circuit also includes a test connector J1;
[0294] The test connector J1 is provided with test connector first pin 1 to test connector fourth pin 4;
[0295] The first pin 1 of the test connector is connected to the first amplifier circuit and connected to 3.3V voltage through the tenth resistor CR10;
[0296] The second pin 2 of the test connector is connected to the fourth pin 4 of the test connector and grounded;
[0297] The third pin 3 of the test connector is connected with the first amplification circuit.
[0298] The interface circuit further comprises a second connector JP2;
[0299] The second connector JP2 is connected with the second gigabit phy module, the first amplification circuit, the second amplification circuit and the first FPGA module respectively, so that the second gigabit phy module, the first amplification circuit, the second amplification circuit and the first FPGA module can transmit signals.
[0300] Figure 19 And Figure 21 The circuit diagram of the first connector JP1 and the circuit diagram of the second connector JP2 are shown respectively, and the structure of the second connector JP2 is consistent with that of the first connector JP1, which is not repeated here.
[0301] As Figure 22 shown, Figure 22 The second embodiment of the Hub card in the LED display screen monitoring system of the utility model is shown, and the difference between the second embodiment and the first embodiment of the Hub card in the LED display screen monitoring system of the utility model is that the Hub card 3 further comprises a power control module 35, and the power control module 35 is used for carrying out step-down processing on a direct current voltage to supply power to the MCU module 32 and the first FPGA module 31 respectively;
[0302] The power control module 35 comprises a first power control chip, and the first power control chip is provided with a power control chip first enable pin, a power control chip input voltage pin, a power control chip second enable pin, a power control chip first switch pin and a power control chip second switch pin;
[0303] The power control chip first enable pin, the power control chip input voltage pin and the power control chip second enable pin are connected with a power supply;
[0304] The power control chip first switch pin is connected with the MCU module 32 to supply power to the MCU module 32;
[0305] The power control chip second switch pin is connected with the first FPGA module 31 to supply power to the first FPGA module 31.
[0306] Specifically:
[0307] As Figure 23As shown, the power control module comprises a first power control chip CU1, a tenth capacitor CC10, an eleventh capacitor CC1, a twelfth capacitor CC12, a fourteenth capacitor CC14, a first resistor CR1, a second resistor CR2, a thirteenth capacitor CC13, a seventh resistor CR7, a first light emitting diode LED1, a seventh capacitor CC7, a ninth capacitor CC9, a fifteenth capacitor CC15, a third resistor CR3, a first coil CL1, a fifth resistor CR5, a second coil CL2, a fourth resistor CR4, a sixth resistor RC6, a sixteenth capacitor CC16, an eighth capacitor C8 and a sixth capacitor CC6;
[0308] The first power control chip CU1 is provided with a power control chip first enable pin EN1, a power control chip input voltage pin IN, a power control chip second enable pin EN2, a power control chip first switch pin SW1, a power control chip second switch pin SW2, a power control chip first feedback pin FB1 and a power control chip second feedback pin FB2.
[0309] The power control chip first enable pin EN1 is grounded through one end of the first resistor CR1, one end of the twelfth capacitor CC12, one end of the eleventh capacitor CC11 and one end of the tenth capacitor CC10 in sequence.
[0310] The power control chip second enable pin EN2 is grounded through one end of the second resistor CR2 and the thirteenth capacitor CC13 in sequence.
[0311] The other end of the first resistor CR1 is connected with the other end of the twelfth capacitor CC12, the other end of the eleventh capacitor CC11, the other end of the tenth capacitor CC10, the power control chip input voltage pin IN and the other end of the second resistor CR2 and is connected with a power supply.
[0312] The power control chip first switch pin SW1 is connected with a 3.3V voltage through the first coil CL1, one end of the third resistor CR3, one end of the fifteenth capacitor CC15, one end of the ninth capacitor CC9 and one end of the seventh capacitor CC7 in sequence and is grounded through the seventh resistor CR7 and the first light emitting diode LED1 in sequence.
[0313] The other end of the third resistor CR3 is connected with the power control chip first feedback pin FB1 and is grounded through the fifth resistor CR5.
[0314] The other end of the fifteenth capacitor CC15 is connected with the other end of the ninth capacitor CC9 and the other end of the seventh capacitor CC7 and is grounded.
[0315] The second switch pin SW2 of the power supply control chip is connected with 1.2V voltage through the second coil CL2, one end of the fourth resistor CR4, one end of the sixteenth capacitor CC16, one end of the eighth capacitor CC8 and one end of the sixth capacitor CC6 in sequence;
[0316] The other end of the fourth resistor CR4 is connected with the second feedback pin FB2 of the power supply control chip and grounded through the sixth capacitor RC6;
[0317] The other end of the sixteenth capacitor CC16 is connected with the other end of the eighth capacitor CC8 and the other end of the sixth capacitor CC6 and grounded.
[0318] In summary, the LED display screen monitoring system of the utility model adopts gigabit network port connection between the upper computer 1 and the sending card 2 and between the sending card 2 and the Hub card 3, and the high-speed communication mode can significantly improve the data transmission efficiency, ensure the rapid transmission of monitoring instructions and sensor data, and reduce the system response time; and the first FPGA module 31 of the Hub card 3 can receive the monitoring instructions of the sending card, collect the sensor data of the lamp panel 4, improve the reliability and stability of the system, and the monitoring efficiency is high and accurate and fast. Further, the modular design of the first FPGA module 31, MCU module 32, gigabit phy module 33, external interface module 34 and other modules in the Hub card 3 of the LED display screen monitoring system of the utility model can improve the management efficiency, improve the performance of the LED display screen monitoring system, make it better adapt to different scales and complexity of application scenarios, and meet the high requirements of modern LED display screen monitoring systems. Overall, the operation and maintenance efficiency is enhanced, so that the operation and maintenance personnel do not need to go to the scene for tedious manual inspection, remotely view the status of each component of the display screen in real time through the upper computer 1, discover and handle potential faults in time, greatly reduce the maintenance workload, and change the maintenance cycle from the previous regular manual inspection to real-time online monitoring. Secondly, the display quality can be improved: the accurate fault monitoring and rapid repair mechanism effectively reduces the display abnormalities caused by lamp panel 4 or Hub card 3 failure, such as dead pixels, uneven brightness and other problems, ensures that the LED display screen always presents high-quality pictures, and improves the audience's visual experience. Compared with the traditional way of relying on special monitoring equipment or a large number of manual inspection, the LED display screen monitoring system of the utility model reduces the hardware procurement cost and labor cost, and reduces the economic losses caused by delayed maintenance due to failure.
[0319] The above is the preferred embodiment of the utility model, and it should be noted that, for ordinary skilled persons in the technical field, without departing from the principle of the utility model, some improvements and refinements can be made, and these improvements and refinements are also considered as the protection range of the utility model.
Claims
1. An LED display screen monitoring system, characterized in that, The system comprises a host computer, a sending card, a plurality of Hub cards and a plurality of lamp panels, the host computer is connected with the sending card through a gigabit network port, the sending card is connected with the plurality of Hub cards through a gigabit network port, and each Hub card is connected with a plurality of lamp panels; The sending card is used for broadcasting monitoring instructions outwardly; The Hub card comprises a first FPGA module, an MCU module, a gigabit phy module and an external interface module, the first FPGA module is used for collecting sensor data of the connected lamp panel, the MCU module is used for communicating with the first FPGA module, the gigabit phy module is used for communicating with the sending card, and the first FPGA module communicates with the lamp panel through the external interface module; The lamp panel is provided with a sensing module, the sensing module is used for monitoring sensor data of the corresponding lamp panel and sending the sensor data to the corresponding Hub card.
2. The LED display screen monitoring system of claim 1, wherein, The first FPGA module comprises a first FPGA circuit, a second FPGA circuit, a test programming circuit and a clock generation circuit; The first FPGA circuit is connected with the test programming circuit and the clock generation circuit respectively; The first FPGA circuit is connected with the MCU module, so that the first FPGA module communicates with the MCU module; The second FPGA circuit is connected with a power supply, so as to distribute the power supply to the first FPGA circuit, the test programming circuit and the clock generation circuit; The test programming circuit is used for introducing digital logic; The clock generation circuit is used for synchronizing the operation of the digital logic of the first FPGA module.
3. The LED display screen monitoring system of claim 1, wherein, The MCU module comprises an MCU circuit, a Flash circuit, a program download interface and an MCU reset circuit; The MCU circuit is connected with the first FPGA module, the gigabit phy module, the Flash circuit, the program download interface and the MCU reset circuit respectively, so as to process the communication between the first FPGA module, the gigabit phy module, the Flash circuit, the program download interface and the MCU reset circuit; The Flash circuit is connected with the first FPGA module, the MCU circuit and the program download interface respectively, so as to store programs and configuration files for the first FPGA module and the MCU circuit; The program download interface is connected with the first FPGA module, the MCU circuit, the Flash circuit and the MCU reset circuit respectively, so as to download programs through the program download interface; The MCU reset circuit is connected with the MCU circuit and the program download interface respectively, so as to guarantee the normal start and abnormal reset start of the MCU module.
4. The LED display screen monitoring system of claim 1, wherein, The gigabit phy module comprises a first gigabit phy module; The first gigabit phy module comprises a first transceiver chip circuit and a first network transformer circuit; The first transceiver chip circuit is connected with the first network transformer circuit and the first FPGA module respectively, and the first network transformer circuit is connected with the external interface module, so as to control the sending and receiving of the data of the first FPGA module.
5. The LED display screen monitoring system of claim 4, wherein, The gigabit phy module further comprises a second gigabit phy module; The second gigabit PHY module comprises a second transceiver chip circuit and a second network transformer circuit; The second transceiver chip circuit is connected with the second network transformer circuit and the first FPGA module respectively, and the second network transformer circuit is connected with the external interface module to control the sending and receiving of data of the first FPGA module.
6. The LED display screen monitoring system of claim 5, wherein, The external interface module comprises a first amplifier circuit, a second amplifier circuit and an interface circuit; The first amplifier circuit is connected with the first FPGA module to amplify the signal of the first FPGA module and send it to the lamp panel; The second amplifier circuit is connected with the first FPGA module to amplify the signal of the lamp panel and send it to the first FPGA module; The interface circuit comprises a first connector; The first connector is connected with the first gigabit PHY module, the first amplifier circuit, the second amplifier circuit and the first FPGA module respectively to transmit signals among the first gigabit PHY module, the first amplifier circuit, the second amplifier circuit and the first FPGA module.
7. The LED display screen monitoring system of claim 6, wherein, The interface circuit further comprises a second connector; The second connector is connected with the second gigabit PHY module, the first amplifier circuit, the second amplifier circuit and the first FPGA module respectively to transmit signals among the second gigabit PHY module, the first amplifier circuit, the second amplifier circuit and the first FPGA module.
8. The LED display screen monitoring system of claim 1, wherein, The Hub card further comprises a power supply control module for step-down processing of a direct current voltage to supply power to the MCU module and the first FPGA module respectively; The power supply control module comprises a first power supply control chip provided with a power supply control chip first enable pin, a power supply control chip input voltage pin, a power supply control chip second enable pin, a power supply control chip first switch pin and a power supply control chip second switch pin; The power supply control chip first enable pin, the power supply control chip input voltage pin and the power supply control chip second enable pin are connected with a power supply; The power supply control chip first switch pin is connected with the MCU module to supply power to the MCU module; The power supply control chip second switch pin is connected with the first FPGA module to supply power to the first FPGA module.
9. The LED display screen monitoring system of claim 1, wherein, The sending card comprises a CPU module and a second FPGA module; The CPU module is used to generate the monitoring instruction at a time; The second FPGA module is used to receive the monitoring instruction generated by the CPU module and broadcast and forward it to the designated Hub card.
10. The LED display screen monitoring system of claim 1, wherein, The sensing module comprises a voltage detector, a temperature detector, a bad point state detector and an interface connection state detector.