A method for manufacturing a field effect transistor, a field effect transistor and a layout structure

Abstract

This application provides a method for manufacturing a field-effect transistor (FET), the FET itself, and its layout structure. The FET separates the shielding gate and the gate electrode, ensuring uniform contact between the shielding gate and the source metal for timely response to state transitions and preventing localized breakdown. Furthermore, the oxide layer at the top of the shielding gate is thinned to reduce reverse recovery charge injection during reverse recovery. By adjusting the position of the shielding gate and thinning the oxide layer, this invention effectively improves the device's ease of use (EAS), reduces the reverse recovery time, enhances its reverse recovery capability, and improves reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit application technology, and in particular to a method for manufacturing a field-effect transistor, the field-effect transistor, and its layout structure. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in various power electronic systems due to their excellent switching characteristics (high speed, low loss) and high input impedance (easy to drive, low drive power). In practical applications, power MOSFETs need to simultaneously meet the requirements of low on-resistance (Ron) to reduce conduction losses and low reverse recovery charge (Qrr) to reduce switching losses. However, in freewheeling mode, hole injection into the drift region significantly degrades efficiency and affects Qrr. Summary of the Invention

[0003] This invention provides a method for manufacturing a field-effect transistor, a field-effect transistor, and a layout structure to solve the technical problem of poor reverse recovery capability of traditional field-effect transistors.

[0004] This invention provides a method for manufacturing a field-effect transistor (FET). The method includes: providing a substrate, comprising a front side and a back side disposed opposite to each other; forming a first conductivity type semiconductor drift region on the front side of the substrate; forming a first trench on the side of the first conductivity type semiconductor drift region away from the substrate, and forming a first oxide layer in the first trench; thinning the first oxide layer on the side located at the opening of the first trench by partially etching the first oxide layer, and then depositing polysilicon on the first oxide layer to form a shielding gate polysilicon electrode; forming a second trench on the side of the first conductivity type drift region away from the substrate, and growing a second oxide layer in the second trench; depositing polysilicon on the second oxide layer to form a gate polysilicon electrode; and further thinning the first conductivity type drift region on the side away from the substrate by ion implantation and... A second conductivity type semiconductor region is formed by push-bonding; a first conductivity type semiconductor source region is formed on the side of the second conductivity type semiconductor region away from the drift region of the first conductivity type semiconductor region by ion implantation and push-bonding; an inter-gate-source dielectric layer is formed on the shielding gate polysilicon electrode, the first conductivity type semiconductor source region, and the gate polysilicon electrode; a contact hole is formed in a portion of the inter-gate-source dielectric layer relative to the shielding gate polysilicon electrode, the first conductivity type semiconductor source region, and the gate polysilicon electrode, and ion implantation is performed based on the contact hole on the first conductivity type semiconductor source region to form a second conductivity type semiconductor ohmic contact region; metal is deposited on the inter-gate-source dielectric layer to form a source metal layer, and the source metal layer contacts the corresponding structure through the contact hole; metal is deposited on the back side of the substrate to form a drain metal layer.

[0005] In one embodiment of the present invention, the step of forming a first trench on the side of the first conductivity type semiconductor drift region away from the substrate and forming a first oxide layer in the first trench includes: generating a first mask layer on the side of the first conductivity type semiconductor drift region away from the substrate; coating, exposing, and developing the first mask layer to determine the position of the first trench; etching the first mask layer and the first conductivity type semiconductor drift region to obtain the first trench; and thermally oxidizing the first trench to form the first oxide layer, wherein the first oxide layer covers the first trench.

[0006] In one embodiment of the present invention, the step of forming a second trench on the side of the first conductivity type drift region away from the substrate and growing a second oxide layer in the second trench includes: generating a second mask layer on the side of the first conductivity type semiconductor drift region away from the substrate; coating, exposing, and developing the second mask layer to determine the position of the second trench; etching the second mask layer and the first conductivity type semiconductor drift region to obtain the second trench; and thermally oxidizing the second trench to form the second oxide layer, wherein the second oxide layer covers the second trench.

[0007] In one embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0008] The present invention also provides a field-effect transistor (FET), which is fabricated by the method described above. The FET includes: a drain metal layer and a substrate and a first conductivity type semiconductor drift region sequentially stacked on the drain metal layer; a first trench and a second trench are provided on the side of the first conductivity type semiconductor drift region away from the substrate, wherein a first oxide layer is covered in the first trench, and the first oxide layer is thinned on the side of the opening of the first trench; a second oxide layer is covered in the second trench; a shielding gate polysilicon electrode is deposited on the first oxide layer, and a gate polysilicon electrode is deposited on the second oxide layer; a gate-source dielectric layer is provided on the first conductivity type semiconductor source region, the gate polysilicon electrode, and a portion of the insulating dielectric layer; a first trench and a second trench are provided on the first conductivity type semiconductor source region, the gate polysilicon electrode, and a portion of the insulating dielectric layer; a first trench and a second trench are provided on the side of the first conductivity type semiconductor drift region away from the substrate, wherein ... A second conductivity type semiconductor region is disposed on the side of the electrical type semiconductor drift region away from the substrate; a first conductivity type semiconductor source region and a second conductivity type semiconductor ohmic contact region are disposed on the second conductivity type semiconductor region, wherein the first conductivity type semiconductor source region is located on opposite sides of the second conductivity type semiconductor ohmic contact region; a gate-source dielectric layer is disposed on the gate polysilicon electrode, the shielding gate polysilicon electrode and the first conductivity type semiconductor source region, and the gate-source dielectric layer extends to the second conductivity type ohmic contact region; a contact hole is disposed on the gate-source dielectric layer on the gate polysilicon electrode and the shielding gate polysilicon electrode, and the source metal layer covering the gate-source dielectric layer contacts the corresponding structure through the contact hole, and the source metal layer contacts the second conductivity type ohmic contact region.

[0009] In one embodiment of the present invention, the gate polysilicon electrode and the shielding gate polysilicon electrode are located on different sides of the regions where the first conductivity type semiconductor source region and the second conductivity type semiconductor ohmic contact region are located.

[0010] The present invention also provides a layout structure of a field-effect transistor, wherein the layout structure is obtained by arranging and combining a plurality of the aforementioned field-effect transistors.

[0011] The beneficial effects of this invention are as follows: The method for manufacturing a field-effect transistor, the field-effect transistor, and the layout structure proposed in this invention separate the shielding gate polysilicon electrode from the gate polysilicon electrode, so that the shielding gate can uniformly contact the source metal, so as to respond to state changes in a timely manner and avoid local breakdown of the device. In addition, the first oxide layer on one side of the first trench opening is thinned. On the one hand, during reverse recovery, electrons will be induced near the top of the shielding gate to form a channel current, thereby reducing the injection of reverse recovery charge. On the other hand, the shielding gate is uniformly distributed in the chip, so that the channel current induced during reverse recovery is more uniformly distributed and the reverse recovery charge is smaller. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0013] In the attached diagram: Figure 1 A schematic flowchart illustrating a method for manufacturing a field-effect transistor according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure in which a first trench and a first oxide layer are formed in the drift region according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after the first oxide layer has been thinned in one embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after polycrystalline silicon is deposited on the first oxide layer in one embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after the second trench is formed in one embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the second oxide layer is grown in the second trench in one embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after polycrystalline silicon is deposited on the second oxide layer in one embodiment of the present invention; Figure 8 This is a schematic diagram of the structure forming a semiconductor region of the first conductivity type in one embodiment of the present invention; Figure 9 This is a schematic diagram of the structure forming a source region of the first conductivity type in one embodiment of the present invention; Figure 10 This is a schematic diagram showing the positional relationship between the gate, the source region of the first conductivity type, the ohmic contact region of the second conductivity type, and the shielding gate in one embodiment of the present invention. Figure 11 This is a schematic diagram showing the positional relationship between the gate, the source region of the first conductivity type, the ohmic contact region of the second conductivity type, and the shielding gate in another embodiment of the present invention; Figure 12 This is a schematic diagram showing the positional relationship between the gate, the source region of the first conductivity type, the ohmic contact region of the second conductivity type, and the shielding gate in another embodiment of the present invention; Figure 13 This is a schematic cross-sectional view of a field-effect transistor in one embodiment of the present invention.

[0014] The attached figures are labeled as follows: 1-Drain metal layer, 2-Substrate, 3-First conductivity type semiconductor drift region, 4-First oxide layer, 6-Second oxide layer, 7-Shielding gate polysilicon electrode, 8-Gate polysilicon electrode, 9-Second conductivity type semiconductor region, 10-First conductivity type semiconductor source region, 11-Second conductivity type semiconductor ohmic contact region, 12-Gate-source dielectric layer, 13-Source metal layer. Detailed Implementation

[0015] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0016] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0017] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0018] The inventor discovered through research that: Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in various power electronic systems due to their excellent switching characteristics (high speed, low loss) and high input impedance (easy to drive, low drive power). In practical applications, power MOSFETs need to simultaneously meet the requirements of low on-resistance (Ron) to reduce conduction losses and low reverse recovery charge (Qrr) to reduce switching losses. However, in freewheeling mode, hole injection into the drift region significantly degrades efficiency and affects Qrr. In traditional shielded gate structures, the shielded gate is connected to the electrode near the chip edge, which may cause localized weaknesses and premature breakdown of the device. To improve Qrr, some related technologies use Schottky diodes, but this method leads to increased leakage current.

[0019] Based on the problems existing in related technologies, this invention proposes a method for manufacturing a field-effect transistor, a field-effect transistor and its layout structure. The technical solution of this invention will be described in detail below with reference to specific embodiments.

[0020] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for manufacturing a field-effect transistor according to an embodiment of the present invention, as shown below. Figure 1 As shown, the manufacturing method includes: Step S100: A substrate 2 is provided, including a front side and a back side disposed opposite to each other, and a first conductivity type semiconductor drift region 3 is generated on the front side of the substrate 2.

[0021] In one embodiment, the substrate 2 may be made of semiconductor materials such as silicon, silicon carbide, or silicon germanium. The specific material and thickness of the substrate 2 can be set and adjusted according to actual application requirements, and are not limited here. A first conductivity type semiconductor drift region 3 is formed on the substrate 2 by epitaxial growth. The substrate 2 may also be of the first conductivity type.

[0022] In step S101, a first trench is formed on the side of the first conductivity type semiconductor drift region 3 away from the substrate 2, and a first oxide layer 4 is formed in the first trench.

[0023] In one embodiment, two first trenches are formed on the side of the drift region away from the substrate 2. The openings of the first trenches are located on the side of the drift region away from the substrate 2, and the first trenches extend into the interior of the drift region. The specific steps for forming the first trenches and the first oxide layer 4 include: generating a first mask layer on the side of the first conductivity type semiconductor drift region 3 away from the substrate 2; coating, exposing, and developing the first mask layer to determine the location of the first trenches; etching the first mask layer and the first conductivity type semiconductor drift region 3 to obtain the first trenches; wherein the etching method can be wet etching or dry etching, and the specific etching method and depth can be determined according to actual production needs; thermally oxidizing the first trenches to form the first oxide layer 4, which covers the first trenches. The first oxide layer 4 can be silicon oxide, etc., and serves as an electrical isolation layer. Specifically, as shown... Figure 2 As shown.

[0024] In step S102, the first oxide layer 4 is partially etched to thin it on one side of the first trench opening, and then polysilicon is deposited on the first oxide layer 4 to form a shielding gate polysilicon electrode 7.

[0025] Please see Figure 3 and Figure 4 In one embodiment, by thinning part of the first oxide layer 4, on the one hand, during reverse recovery, electrons will be induced near the top of the subsequently deposited shielding gate to form a channel current, thereby reducing the injection of reverse recovery charge.

[0026] In step S103, a second trench is formed on the side of the first conductivity type drift region away from the substrate 2, and a second oxide layer 6 is grown in the second trench.

[0027] Please see Figure 5 and Figure 6 In one embodiment, the step of forming a second trench on the side of the first conductivity type drift region away from the substrate 2 and growing a second oxide layer 6 in the second trench includes: generating a second mask layer on the side of the first conductivity type semiconductor drift region 3 away from the substrate 2; coating, exposing, and developing the second mask layer to determine the position of the second trench; etching the second mask layer and the first conductivity type semiconductor drift region 3 to obtain the second trench; and thermally oxidizing the second trench to form the second oxide layer 6, the second oxide layer 6 covering the second trench.

[0028] In step S104, polysilicon is deposited on the second oxide layer 6 to form a gate polysilicon electrode 8.

[0029] Please see Figure 7 In one embodiment, the second oxide layer 6 is a gate oxide layer, which can cover the sidewalls and bottom of the second trench. Polysilicon is deposited on the second oxide layer 6 to obtain the gate polysilicon electrode 8. The gate polysilicon electrode 8 is disposed separately from the shielded gate polysilicon electrode 7.

[0030] In step S105, a second conductivity type semiconductor region 9 is formed on the side of the first conductivity type drift region away from the substrate 2 by ion implantation and push junction.

[0031] Please see Figure 8 In one embodiment, the first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type is P-type and the second conductivity type is N-type. The second conductivity type semiconductor region 9 is located between the shielding gate polysilicon electrode 7 and the gate polysilicon electrode 8.

[0032] In step S106, a first conductivity type semiconductor source region 10 is formed on the side of the second conductivity type semiconductor region 9 away from the first conductivity type semiconductor drift region 3 by ion implantation and push junction.

[0033] Please see Figure 9 In one embodiment, the first conductivity type source region formed after step S106 is stacked on the first conductivity type body region and is also located between the shielding gate polysilicon electrode 7 and the gate polysilicon electrode 8.

[0034] In step S107, a gate-source dielectric layer 12 is formed on the shielded gate polysilicon electrode 7, the first conductivity type semiconductor source region 10, and the gate polysilicon electrode 8.

[0035] In one embodiment, the gate-source dielectric layer 12 may also be made of a material such as silicon oxide. The gate-source dielectric layer 12 obtained in step S107 covers the shielded gate polysilicon electrode 7, the first conductivity type semiconductor source region 10, and the gate polysilicon electrode 8.

[0036] In step S108, a contact hole is formed in a portion of the gate-source dielectric layer 12 relative to the shielding gate polysilicon electrode 7, the first conductivity type semiconductor source region 10, and the gate polysilicon electrode 8, and ion implantation is performed based on the contact hole on the first conductivity type semiconductor source region 10 to form a second conductivity type semiconductor ohmic contact region 11.

[0037] In one embodiment, contact holes are formed on the gate-source inter-dielectric layer 12 corresponding to the shielded gate polysilicon electrode 7, the first conductivity type source region, and the gate polysilicon electrode 8. The width of the contact holes is smaller than the width of the corresponding regions. Ion implantation is performed at the contact hole positions corresponding to the first conductivity type source region to obtain a second conductivity type semiconductor ohmic contact region 11. The second conductivity type semiconductor ohmic contact region 11 contacts the first conductivity type semiconductor source region 10 on both sides, thereby forming a... Figure 10 The structure shown forms an NPN structure with a first conductivity type source region and a second conductivity type semiconductor ohmic contact region 11, and the first conductivity type semiconductor source region 10 and the second conductivity type semiconductor ohmic contact region 11 are located between the gate (gate polysilicon electrode 8) and the shielding gate (shielding gate polysilicon electrode 7). Figure 9 for Figure 10 Cross-sectional view at the tangent AA'. From Figure 10 As can be seen, a second oxide layer is disposed as a dielectric layer between the gate and the first conductivity type source region (N+), and a first oxide layer is disposed as a dielectric layer between the shielding gate and the corresponding second conductivity type source region (N+). Both sides of the gate are separated from the shielding gate by an NPN structure composed of the first conductivity type source region (N+) and the second conductivity type ohmic contact region (P+). The shielding gate can make uniform contact with the source metal through its contact holes.

[0038] In another embodiment, before thinning the first oxide layer, a mask is used to etch the first oxide layer to block it, thus preventing the oxide layer adjacent to the gate from being etched away. Subsequent steps are the same as those described above, and a structure can be formed as follows. Figure 11 In the structure shown, the first conductivity type semiconductor source region 10 and the second conductivity type semiconductor ohmic contact region 11 are located between two shielding gates and between two gates, forming a structure that surrounds the regions where the first conductivity type semiconductor source region 10 and the second conductivity type semiconductor ohmic contact region 11 are located. This device layout allows for a larger channel current density induced during reverse recovery and a smaller Qrr. In another embodiment, a structure similar to... Figure 12The structure shown has shielding gates distributed at the four corners of the top view of the device. The shielding gates are separated from the gates by a dielectric layer. The gates divide the shielding gates at the four corners into two groups. Each group includes two shielding gate regions. A first conductivity type semiconductor source region 10 and a second conductivity type semiconductor ohmic contact region 11 are provided between the two shielding gate regions in each group.

[0039] In step S109, metal is deposited on the gate-source dielectric layer 12 to form a source metal layer 13, which is in contact with the corresponding structure through a contact hole.

[0040] In one embodiment, a source metal layer 13 can be formed by depositing metal (such as gold, copper, etc.) on the gate-source dielectric layer 12. The source metal layer 13 contacts the shielded gate polysilicon electrode 7, the gate polysilicon electrode 8, and the second conductivity type semiconductor ohmic contact region 11 through contact holes on the gate-source dielectric layer 12.

[0041] In step S110, metal is deposited on the back side of substrate 2 to form drain metal layer 1.

[0042] Based on the field-effect transistor obtained through the above steps, the shielding gate and the gate are placed separately, allowing the shielding gate to uniformly contact the source metal for timely response to state transitions and preventing localized breakdown of the device. Furthermore, the oxide layer at the top of the shielding gate is thinned. On one hand, during reverse recovery, electrons are induced near the top of the shielding gate, forming a channel current, thereby reducing the injection of reverse recovery charge. On the other hand, unlike traditional shielding gate structures, this design ensures that the shielding gate is uniformly distributed throughout the chip, resulting in a more uniform distribution of the induced channel current during reverse recovery, thus leading to a smaller Qrr. This invention effectively improves the device's Eas capability, reduces the transistor's reverse recovery time, enhances its reverse recovery ability, and improves reliability by adjusting the position of the shielding gate and thinning the thickness of the shielding gate oxide layer.

[0043] Please see Figure 12In one embodiment, the present invention also provides a field-effect transistor (FET), which is prepared by the aforementioned manufacturing method. Specifically, the FET includes: a drain metal layer 1 and a substrate 2 and a first conductivity type semiconductor drift region 3 sequentially stacked on the drain metal layer 1; a first trench and a second trench are provided on the side of the first conductivity type semiconductor drift region 3 away from the substrate 2, wherein a first oxide layer 4 is covered in the first trench, and the first oxide layer 4 is thinned on the side of the opening of the first trench; a second oxide layer 6 is covered in the second trench; a shielding gate polysilicon electrode 7 is deposited on the first oxide layer 4; and a gate polysilicon electrode 8 is deposited on the second oxide layer 6; a gate-source dielectric layer 12 is provided on the first conductivity type semiconductor source region 10, the gate polysilicon electrode 8, and part of the insulating dielectric layer; and a first conductivity type semiconductor source region 10, the gate polysilicon electrode 8, and part of the insulating dielectric layer are provided with a gate-source dielectric layer 12. A second conductivity type semiconductor region 9 is disposed on the side of the volume drift region 3 away from the substrate 2; a first conductivity type semiconductor source region 10 and a second conductivity type semiconductor ohmic contact region 11 are disposed on the second conductivity type semiconductor region 9, wherein the first conductivity type semiconductor source region 10 is located on opposite sides of the second conductivity type semiconductor ohmic contact region 11; a gate-source dielectric layer 12 is disposed on the gate polysilicon electrode 8, the shielding gate polysilicon electrode 7 and the first conductivity type semiconductor source region 10, and the gate-source dielectric layer 12 extends to the second conductivity type ohmic contact region; a contact hole is disposed on the gate-source dielectric layer 12 located on the gate polysilicon electrode 8 and the shielding gate polysilicon electrode 7, and the source metal layer 13 covering the gate-source dielectric layer 12 contacts the corresponding structure through the contact hole, and the source metal layer 13 contacts the second conductivity type ohmic contact region.

[0044] In one embodiment, the present invention also provides a layout structure of a field-effect transistor, which is obtained by arranging a plurality of the aforementioned field-effect transistors in a certain pattern. The specific structure of the field-effect transistor has been described in detail in the foregoing embodiments and will not be repeated here.

[0045] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a field-effect transistor, characterized in that, The method includes: A substrate is provided, the substrate including a front side and a back side disposed opposite to each other, and a first conductivity type semiconductor drift region is formed on the front side of the substrate; A first trench is formed on the side of the first conductivity type semiconductor drift region away from the substrate, and a first oxide layer is formed in the first trench; By partially etching the first oxide layer, the first oxide layer is thinned on the side located at the opening of the first trench, and then polysilicon is deposited on the first oxide layer to form a shielding gate polysilicon electrode. A second trench is formed on the side of the first conductivity type semiconductor drift region away from the substrate, and a second oxide layer is grown in the second trench; Polysilicon is deposited on the second oxide layer to form a gate polysilicon electrode; A second conductivity type semiconductor region is formed on the side of the first conductivity type semiconductor drift region away from the substrate by ion implantation and push junction; A first conductivity type semiconductor source region is formed on the side of the second conductivity type semiconductor region away from the first conductivity type semiconductor drift region by ion implantation and push junction; A gate-source dielectric layer is formed on the shielded gate polysilicon electrode, the first conductivity type semiconductor source region, and the gate polysilicon electrode. A contact hole is formed in a portion of the gate-source dielectric layer relative to the shielding gate polysilicon electrode, the first conductivity type semiconductor source region, and the gate polysilicon electrode, and ion implantation is performed based on the contact hole on the first conductivity type semiconductor source region to form a second conductivity type semiconductor ohmic contact region. Metal is deposited on the gate-source dielectric layer to form a source metal layer, and the source metal layer contacts the corresponding structure through the contact hole; Metal is deposited on the back side of the substrate to form a drain metal layer.

2. The method for manufacturing a field-effect transistor according to claim 1, characterized in that, The step of forming a first trench on the side of the first conductivity type semiconductor drift region away from the substrate and forming a first oxide layer in the first trench includes: A first mask layer is generated on the side of the first conductivity type semiconductor drift region away from the substrate; The first mask layer is coated, exposed, and developed to determine the position of the first trench. The first mask layer and the first conductivity type semiconductor drift region are etched to obtain the first trench; The first trench is subjected to thermal oxidation growth to form the first oxide layer, which covers the first trench.

3. The method for manufacturing a field-effect transistor according to claim 1, characterized in that, The step of forming a second trench on the side of the first conductivity type semiconductor drift region away from the substrate and growing a second oxide layer in the second trench includes: A second mask layer is generated on the side of the first conductivity type semiconductor drift region away from the substrate; The second mask layer is coated, exposed, and developed to determine the position of the second trench; The second mask layer and the first conductivity type semiconductor drift region are etched to obtain the second trench; The second trench is subjected to thermal oxidation growth to form the second oxide layer, which covers the second trench.

4. The method for manufacturing a field-effect transistor according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

5. A field-effect transistor, characterized in that, The field-effect transistor is manufactured by the method of manufacturing a field-effect transistor according to any one of claims 1-4, and the field-effect transistor comprises: Drain metal layer and substrate and first conductivity type semiconductor drift region sequentially stacked on the drain metal layer; The first conductivity type semiconductor drift region has a first trench and a second trench on the side away from the substrate. The first trench is covered with a first oxide layer, and the first oxide layer is thinned on the side of the opening of the first trench. The second trench is covered with a second oxide layer. A shielding gate polysilicon electrode is deposited on the first oxide layer, and a gate polysilicon electrode is deposited on the second oxide layer. A second conductivity type semiconductor region is provided on the side of the first conductivity type semiconductor drift region away from the substrate; A first conductivity type semiconductor source region and a second conductivity type semiconductor ohmic contact region are disposed on the second conductivity type semiconductor region, wherein the first conductivity type semiconductor source region is located on opposite sides of the second conductivity type semiconductor ohmic contact region; A gate-source dielectric layer is disposed on the gate polysilicon electrode, the shielding gate polysilicon electrode, and the first conductivity type semiconductor source region, and the gate-source dielectric layer extends to the second conductivity type semiconductor ohmic contact region. Contact holes are provided on the gate-source dielectric layer located on the gate polysilicon electrode and the shield gate polysilicon electrode. The source metal layer covering the gate-source dielectric layer contacts the corresponding structure through the contact holes, and the source metal layer contacts the ohmic contact region of the second conductivity type semiconductor.

6. The field-effect transistor according to claim 5, characterized in that, The gate polysilicon electrode and the shielding gate polysilicon electrode are located on different sides of the regions where the first conductivity type semiconductor source region and the second conductivity type semiconductor ohmic contact region are located, respectively.

7. A layout structure for a field-effect transistor, characterized in that, The layout structure is obtained by arranging and combining multiple field-effect transistors as described in claim 5.

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