Manufacturing method of super junction structure

Abstract

The invention discloses a method for manufacturing a super junction structure, which comprises the following steps of: providing a first conductive type doped first epitaxial layer, performing graphical etching to form a plurality of super junction grooves, and forming a first conductive type column by the first epitaxial layer among the super junction grooves; and annealing to enable impurities of the first conductive type column to expand outwards along the inner side surface of the super junction trench, so as to form a first doping concentration reduction region at the side surface region of the first conductive type column. And filling a second conductive type doped second epitaxial layer in the super junction groove, taking the second epitaxial layer filled in the super junction groove as a constituent part of a second conductive type column, and reducing PN reverse expansion between the first conductive type column and the second conductive type column by using a first doping concentration reduction region. According to the super junction structure, PN reverse expansion between PN columns can be reduced, so that the overall doping dosage of the super junction structure can be reduced under the condition that on-resistance is guaranteed, and a process window is increased.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a method for manufacturing a super junction (SJ) structure. Background Technology

[0002] Compared to existing VDMOS, superjunction MOSFETs, by inserting lateral P-type pillars 5 in the vertical drift region, utilize the lateral depletion of the PN junction to significantly increase the doping concentration of the drift region 2 without reducing the breakdown voltage, thereby reducing the specific on-resistance. For example... Figure 1 The diagram shown is a schematic of the structure of an existing superjunction MOSFET (SJ-MOSFET); existing superjunction MOSFETs include: For N-type heavily doped substrates, such as silicon substrates, in order to reduce the resistance of substrate 1, it is generally desirable to have a higher doping concentration and a thinner thickness. A thinner substrate can also reduce thermal resistance and is beneficial for heat dissipation of power devices.

[0003] An N-type doped drift region 2 is formed on the substrate 1; the drift region 2 consists of an epitaxial layer. P-type pillars 5 are formed within the drift region 2. By utilizing the lateral depletion of the P-type pillars 5 and the drift region 2, the doping concentration of the drift region 2 can be significantly increased without reducing the breakdown voltage, thereby reducing the resistance of the drift region 2. The sum of the width of the P-type pillars 5 and the distance between them is called the pitch of the SJ-MOSFET; generally, a lower pitch results in a more pronounced lateral depletion effect, allowing for a further increase in the doping concentration of the drift region and a lower specific on-resistance of the device. Reducing the pitch provides a direction for optimizing SJ-MOSFETs.

[0004] The gate structure is a trench gate, including a gate oxide layer 3 formed in the gate trench and a polysilicon gate 4 filled in the gate trench. The gate oxide layer 3 is usually SiO2; the thickness of the gate oxide layer 3 determines the gate breakdown voltage, which is usually between 200 and 12000 Å, with a typical thickness of 1000 Å.

[0005] A p-type doped channel region 6 is formed on the surface region of drift region 2, with the trench gate extending longitudinally through channel region 6. The doping concentration of channel region 6 determines the device threshold voltage. Channel region 6 is typically formed by ion implantation.

[0006] A heavily N-type doped source region 7 is formed on the surface region of channel region 6. Source region 7 is usually formed by ion implantation, typically using Arsenic implantation, with implantation energy between 40 and 100 keV and implantation dose between 1e15 and 1e16 / cm. 2 between.

[0007] The source region 7 is connected to the source metal 10 through a metal via 8. The metal via 8 is usually filled with Tungsten. In order to ensure a good Ohmic contact between the metal via 8 and the channel region 6, a via implantation layer 9 is formed at the bottom of the metal via 8. The via implantation layer 9 is usually implanted with BF2, with an energy of 15-100keV and a dose of 1e14 / cm 2 ~5e15 / cm 2 .

[0008] The P-type pillar 5 can be realized in two ways, one is based on multiple epitaxy plus ion implantation, the other is based on trench etching plus P-type silicon filling. The trench etching process has fewer steps, but it is difficult to implement. The multiple epitaxy process has more steps and high manufacturing cost. However, it can achieve better performance. This is because the epitaxy is usually intrinsic, and the doping of the N-type drift region 2 and the P-type pillar 5 is defined by ion implantation through a mask.

[0009] As shown in Figure 2 , it is a device structure schematic diagram in a manufacturing method of a super-junction structure. Taking a typical 6µm Pitch, 600V breakdown voltage super-junction MOSFET as an example, 13 layers of epitaxy are usually adopted, and the thickness of each epitaxy layer is between 3.3-3.7µm. The doping concentration of the epitaxy is usually low-doped, with a resistivity of 100-300Ω*cm, or even intrinsic. Figure 2 , it is a device structure schematic diagram in a manufacturing method of a super-junction structure. Taking a typical 6µm Pitch, 600V breakdown voltage super-junction MOSFET as an example, 13 layers of epitaxy are usually adopted, and the thickness of each epitaxy layer is between 3.3-3.7µm. The doping concentration of the epitaxy is usually low-doped, with a resistivity of 100-300Ω*cm, or even intrinsic.

[0010] Super junction is a device based on the balance of PN, when P-type impurity dose and N-type impurity dose are equal, BV is the highest. If P is more, or P is less, BV will decrease. And the speed of this BV decline is related to the absolute value of the difference between P-type impurity dose and N-type impurity. There is a certain space between P-type column 5 and N-type column, which is very helpful to improve performance. P-type column 5 and N-type column will diffuse each other because of the difference in doping, forming a depletion region; this depletion region is not helpful for conduction, and the effective doped region (which can participate in conduction) is reduced because of the existence of the depletion region. The more the mutual diffusion of this region, the more the neutralization of electrons and holes, so in order to ensure the same on-resistance, the dose of P-type impurity or N-type needs to be increased to compensate for the decrease of effective doped impurities caused by PN mutual diffusion. The process window allowed by the device can be determined according to the BV decline it can withstand, generally between 5% and 10%, even if the BV decreases by 5% to 10%; and the process window allowed by the device is mainly related to the absolute value of the difference between P-type impurity and N-type impurity dose. The more N or P-type impurity dose, the lower the percentage of fluctuation it can accept during production, which brings great difficulty to process control. For example Figure 2 As shown in FIG. 1, the mask between the injection regions 12 and 13 ensures a certain space, and at the same time, the doping concentration of the epitaxial layer is low, which reduces the decrease of effective doping caused by the mutual diffusion of P-type column 5 and N-type column. Under the condition of the same on-resistance, the overall impurity dose can be reduced, the process window of the device is improved, and the performance of the device is optimized.

[0011] The same as the above-mentioned multi-layer epitaxial growth plus injection to form P-type column, when P-type column 5 is formed by groove etching plus P-type silicon filling, PN mutual diffusion and PN counter diffusion also exist, and there is no good solution at present. SUMMARY

[0012] The technical problem to be solved by the present application is to provide a manufacturing method of super junction structure, which can reduce PN counter diffusion between PN columns, so as to reduce the overall doping dose of the super junction structure under the condition of ensuring the on-resistance, and increase the process window.

[0013] To solve the above technical problem, the manufacturing method of super junction structure provided by the present application comprises the following steps: A first epitaxial layer doped with a first conductive type is provided, and the first epitaxial layer is patterned and etched to form a plurality of super junction grooves, and the first conductive type column is composed of the first epitaxial layer between each super junction groove.

[0014] The annealing is performed to cause the impurities of the first-conductivity-type pillars to spread out along the side surfaces of the super-junction trenches to form first-doping-concentration-reduction regions at the side-surface regions of the first-conductivity-type pillars.

[0015] A second-conductivity-type-doped second epitaxial layer is filled in the super-junction trenches, the second epitaxial layer filled in the super-junction trenches serving as a component of second-conductivity-type pillars, the first-conductivity-type pillars and the second-conductivity-type pillars being alternately arranged to form a super-junction structure, and the first-doping-concentration-reduction regions being used to reduce the PN counter-diffusion between the first-conductivity-type pillars and the second-conductivity-type pillars.

[0016] A further improvement is that the first-conductivity-type pillars are uniformly doped in the width direction of the first-conductivity-type pillars.

[0017] A further improvement is that the annealing is performed at a temperature of 950-1150℃ for a time of 30-120 minutes.

[0018] A further improvement is that, before the annealing is performed, a natural oxide layer is formed on the inner side surfaces of the super-junction trenches, the natural oxide layer being removed or retained before the annealing.

[0019] A further improvement is that the second epitaxial layer is grown from the bottom surface and the side surfaces of the super-junction trenches, the second epitaxial layer including an initial sub-layer and a main layer, the initial sub-layer being intrinsically doped or having a doping concentration lower than that of the main layer, and the initial sub-layer being used to reduce the PN counter-diffusion.

[0020] A further improvement is that the initial sub-layer is grown for a time of 120 seconds or less.

[0021] A further improvement is that, after the annealing and before the second epitaxial layer is filled, the method further comprises: injecting a first barrier impurity into the inner side surfaces of the super-junction trenches, the first barrier impurity being used to reduce the PN counter-diffusion.

[0022] A further improvement is that the first barrier impurity includes F or C.

[0023] A further improvement is that the super-junction trenches have inclined side surfaces and a top opening width greater than a bottom opening width.

[0024] A further improvement is that the side surfaces of the super-junction trenches have an inclination angle of 88.5-89.5 degrees.

[0025] A further improvement is that the first epitaxial layer is formed on a first-conductivity-type heavily-doped semiconductor substrate.

[0026] Further improvement is that the material of the semiconductor substrate comprises silicon or silicon carbide.

[0027] Further improvement is that the resistivity of the first epitaxial layer is 0.6-1.5 ohm·cm, and the thickness is 45-60 microns.

[0028] Further improvement is that the depth of the super-junction trench is 35-45 microns.

[0029] Further improvement is that the first conductivity type is N type, and the second conductivity type is P type.

[0030] Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

[0031] Further improvement is that when the first conductivity type is N type, and the second conductivity type is P type, the doping impurities of the first epitaxial layer comprise phosphorus and / or arsenic, and the doping impurities of the second epitaxial layer comprise boron and / or boron fluoride.

[0032] Alternatively, when the first conductivity type is P type, and the second conductivity type is N type, the doping impurities of the second epitaxial layer comprise phosphorus and / or arsenic, and the doping impurities of the first epitaxial layer comprise boron and / or boron fluoride.

[0033] The present application anneals after forming the super-junction trench and before filling the super-junction trench. Because the annealing makes the side of the first-conductivity-type pillar between the super-junction trenches to be the side of the super-junction trench, that is, the side of the first-conductivity-type pillar is directly exposed, the annealing makes the doping impurities of the first-conductivity-type pillar to be outwardly diffused from the side of the super-junction trench, that is, the impurities of the first-conductivity-type pillar are diffused into the air, so that a region with reduced doping concentration, that is, a first doping-concentration-reduced region, is formed at the side of the first-conductivity-type pillar, which becomes a buffer region between the first-conductivity-type pillar and a second-conductivity-type pillar to be formed later, which can effectively reduce the PN counter-diffusion, that is, the PN mutual diffusion, between the first-conductivity-type pillar and the second-conductivity-type pillar, that is, the amount of P-type impurities diffused into the N-type pillar and the amount of N-type impurities diffused into the P-type pillar are both reduced, and the width of the depletion region formed by the PN counter-diffusion is also reduced, which can effectively improve the performance of the device, and can reduce the overall doping dose of the super-junction structure and thus increase the process window under the condition that the on-resistance is guaranteed, because the process window is related to the absolute value of the difference between the doses of P-type impurities and N-type impurities between the PN pillars, that is, the P-type pillars and the N-type pillars, when the overall doping dose of the super-junction structure is reduced, the absolute value of the maximum difference between the doses of P-type impurities and N-type impurities corresponding to the process window is reached, the fluctuation of the doping concentration of the P-type pillars and the N-type pillars allowed can be increased, and thus the process window is increased. Therefore, the present application can reduce the PN counter-diffusion between the PN pillars, so that the overall doping dose of the super-junction structure can be reduced and the process window can be increased under the condition that the on-resistance is guaranteed.

[0034] The present application also combines injecting first blocking impurities into the inner side surface of the super-junction trench before filling the super-junction trench, or growing an initial sub-layer with intrinsic doping or doping concentration before filling the super-junction trench, which can further reduce the PN counter-diffusion. BRIEF DESCRIPTION OF DRAWINGS

[0035] The present application will be further described in detail below in combination with the drawings and specific embodiments: Figure 1 is a structure schematic diagram of a prior super-junction MOSFET; Figure 2 is a device structure schematic diagram in a manufacturing method of a prior super-junction structure; Figure 3 is a flow chart of the manufacturing method of the super-junction structure of the embodiment of the present application; Figures 4A-4C is a device structure schematic diagram in each step of the manufacturing method of the super-junction structure of the embodiment of the present application. DETAILED DESCRIPTION

[0036] As shown in Figure 3 is a flow chart of the manufacturing method of the super-junction structure of the embodiment of the present application; as Figures 4A-4CAs shown, it is the device structure schematic diagram in each step of the manufacturing method of the super junction structure of the embodiment of the present application; the manufacturing method of the super junction structure of the embodiment of the present application comprises the following steps: Step S101, as shown, a first epitaxial layer 22 of a first conductivity type is provided, the first epitaxial layer 22 is patterned and etched to form a plurality of super junction trenches 24, and the first epitaxial layer 22 between each super junction trench 24 forms a first conductivity type column. Figure 4A As shown, a first epitaxial layer 22 of a first conductivity type is provided, the first epitaxial layer 22 is patterned and etched to form a plurality of super junction trenches 24, and the first epitaxial layer 22 between each super junction trench 24 forms a first conductivity type column.

[0037] In the embodiment of the present application, the patterned etching of the super junction trench 24 comprises a photoetching process and an etching process, and before the photoetching process, a hard mask layer 23 is formed on the top surface of the first epitaxial layer 22, and then the photoetching process defines the forming area of the super junction trench 24; and then the hard mask layer 23 and the first epitaxial layer 22 are etched in sequence to form the super junction trench 24.

[0038] Figure 4A In the embodiment of the present application, the X direction and the Y direction are also marked, the X direction is along the width direction of the super junction trench 204, and the Y direction is along the depth direction of the super junction trench 24.

[0039] In the embodiment of the present application, the first epitaxial layer 22 is formed on the first conductivity type heavily doped semiconductor substrate 21.

[0040] In the embodiment of the present application, in the width direction of the first conductivity type column, the first conductivity type column is uniformly doped.

[0041] In the embodiment of the present application, the material of the semiconductor substrate 21 is silicon. In other embodiments, the material of the semiconductor substrate 21 can also be silicon carbide.

[0042] In the embodiment of the present application, the super junction trench 24 has an inclined side surface and a top opening width greater than a bottom opening width, which is beneficial to the etching and filling of the super junction trench 24.

[0043] In some embodiments, the electrical resistivity of the semiconductor substrate 21 is usually around 1 mΩ*cm.

[0044] The electrical resistivity of the first epitaxial layer 22 is 0.6 ohm*cm to 1.5 ohm*cm, and typically 1 ohm*cm; the thickness is 45 microns to 60 microns, and typically 50 microns.

[0045] The side surface angle of the super junction trench 24 is 88.5 degrees to 89.5 degrees; and typically 89 degrees.

[0046] The depth of the super junction trench 24 is 35 microns to 45 microns, and typically 40 microns.

[0047] Taking a superjunction MOSFET with a pitch of 6µm as an example, the width of the superjunction trench 24 is usually 2.5µm, the angle of the superjunction trench 24 is 89 degrees, and the depth is 41µm.

[0048] Step S102, as follows Figure 4B As shown, annealing causes impurities in the first conductivity type pillar to expand outward along the side of the superjunction trench 24, forming a first doping concentration reduction region in the side region of the first conductivity type pillar. The first doping concentration reduction region is still a component of the first conductivity type pillar, but the doping distribution of the first conductivity type pillar changes after annealing. For ease of understanding, Figure 4B In the diagram, the first doping concentration reduction region is represented by the region 22a enclosed by the dashed line. Impurities also expand outwards at the bottom surface of the superjunction trench 24. In this embodiment of the invention, the width direction of the first conductivity type pillar is... Figure 4B Impurity expansion in the X or -X direction can reduce the effect of subsequent PN back-expansion.

[0049] The size of the first doping concentration reduction region is related to the thermal process of annealing; the higher the annealing temperature and the longer the annealing time, the larger the corresponding first doping concentration reduction region. In some embodiments, the annealing temperature is 950°C to 1150°C, and the time is 30 minutes to 120 minutes.

[0050] In this embodiment of the invention, a native oxide layer is formed on the inner surface of the superjunction trench 24 before annealing. Typically, the native oxide layer is thin, so it is either removed or retained before annealing. In other embodiments, if the native oxide layer is thick, it needs to be removed before annealing to improve the outward diffusion effect of impurities in the first conductivity type pillar.

[0051] In this embodiment of the invention, after annealing and before filling the second epitaxial layer 25, the following steps are also included: A first barrier impurity is implanted on the inner surface of the superjunction trench 24 to reduce PN back diffusion. Preferably, the first barrier impurity includes F or C. In other embodiments, the implantation of the first barrier impurity may be omitted.

[0052] Step S103, as follows Figure 4C As shown, a second epitaxial layer 25 doped with a second conductivity type is filled in the superjunction trench 24. The second epitaxial layer 25 filled in the superjunction trench 24 serves as a component of the second conductivity type pillar. The superjunction structure is formed by alternating arrangement of the first conductivity type pillar and the second conductivity type pillar. The PN back diffusion between the first conductivity type pillar and the second conductivity type pillar is reduced by utilizing the first doping concentration reduction region.

[0053] In this embodiment of the invention, the second epitaxial layer 25 grows from the bottom surface and side surface of the superjunction trench 24. The second epitaxial layer 25 includes an initial sublayer and a main layer. The initial sublayer is intrinsically doped or has a doping concentration lower than that of the main layer. The initial sublayer is used to reduce PN back diffusion. The thickness of the initial sublayer is related to the epitaxial growth time. The thickness of the initial sublayer can be controlled by controlling the epitaxial growth time. For example, the growth time of the initial sublayer is less than or equal to 120 seconds. In other embodiments, the initial sublayer can also be omitted.

[0054] In this embodiment of the invention, the first conductivity type is N-type and the second conductivity type is P-type. The doping impurities of the first epitaxial layer 22 include phosphorus and / or arsenic, and the doping impurities of the second epitaxial layer 25 include boron and / or boron fluoride. In other embodiments, the first conductivity type can also be P-type, the second conductivity type is N-type, the doping impurities of the second epitaxial layer 25 include phosphorus and / or arsenic, and the doping impurities of the first epitaxial layer 22 include boron and / or boron fluoride.

[0055] In this embodiment of the invention, annealing is performed after the superjunction trench 24 is formed and before it is filled. Because of the annealing, the sides of the first conductive type pillars between the superjunction trenches 24 are directly exposed, causing the doped impurities of the first conductive type pillars to expand outward from the sides of the superjunction trench 24. This outward expansion means the impurities of the first conductive type pillars diffuse into the air. Therefore, a region with reduced doping concentration, i.e., a first doping concentration reduction region, is formed on the sides of the first conductive type pillars. This first doping concentration reduction region serves as a buffer zone between the first conductive type pillars and the subsequently formed second conductive type pillars, effectively reducing the doping concentration of the first and second conductive type pillars. The PN back-expansion, also known as PN cross-expansion, reduces both the amount of P-type impurities diffusing into the N-type pillars and the amount of N-type impurities diffusing into the P-type pillars. This reduces the depletion region width formed by PN back-expansion, significantly improving device performance. It allows for a reduction in the overall doping dose of the superjunction structure while maintaining on-resistance, thereby increasing the process window. This is because the process window is related to the absolute value of the difference in doping dose between P-type and N-type impurities between the PN pillars (P-type and N-type pillars). When the overall doping dose of the superjunction structure is reduced, reaching the maximum absolute value of the difference in doping dose between P-type and N-type impurities corresponding to the process window, the allowable fluctuation in doping concentration of the P-type and N-type pillars can increase, thus increasing the process window. Therefore, this embodiment of the invention reduces PN back-expansion between PN pillars, thereby reducing the overall doping dose of the superjunction structure and increasing the process window while maintaining on-resistance.

[0056] The embodiment of the present application also injects first barrier impurities into the inner surface of the super junction trench 24 before filling the super junction trench 24, or grows an initial sub-layer with intrinsic doping or a doping concentration before filling the super junction trench 24, which can further reduce the PN counter-diffusion.

[0057] During epitaxial (Epi) growth, such as forming the first epitaxial layer 22 and the second epitaxial layer 25, the doping concentration in the y direction can be tuned, but the doping concentration in the x direction is uniform. In order to reduce the PN counter-diffusion, it is desirable to have a low doping concentration near the super junction trench 24 in the x direction and a high doping concentration far from the super junction trench 24 in the x direction. In the embodiment of the present application, after etching the super junction trench 24, high-temperature annealing is performed, and the impurities of the first epitaxial layer 22 will out-diffuse through the exposed sidewall of the super junction trench 24, and the impurities will diffuse out. In this way, the impurity concentration near the super junction trench 24 of the first epitaxial layer 22 is reduced. The high-temperature annealing is usually performed at a temperature of 950-1150°C for a time of 30-120 min, and a typical condition can be 1100°C for 30 min. Before high-temperature annealing, there is usually a thin oxide layer on the sidewall of the super junction trench 24, which is naturally formed by oxidation of silicon in air. This oxide layer can be removed or not removed. However, the thickness of this oxide layer cannot be too thick, otherwise it will reduce the out-diffusion speed of the doping atoms. During annealing, the composition of the gas in the environment can also be freely adjusted to increase the out-diffusion speed of the doping atoms.

[0058] Taking the first conductivity type as N-type and the second conductivity type as an example, when the P-type silicon, i.e., the second epitaxial layer 25, is filled into the super junction trench 24, in order to reduce the PN counter-diffusion, the embodiment of the present application can also: A. During the filling of the P-type silicon, a large amount of F or C element is first doped at the PN junction. The F or C element can reduce the diffusion speed of Boron. The F or C element can also be implanted into the bottom and sidewall of the super junction trench before filling the P-type silicon.

[0059] B. During the filling of the P-type silicon, the doping concentration of Boron can be reduced at the beginning (for a period of time before, such as 120s of filling), or even be intrinsic. The above two methods can both reduce the impurity concentration at the PN junction, thereby reducing the decrease of effective doping caused by diffusion, improving the process window, and improving the performance.

[0060] In the embodiments of the present application, the N-type impurities are usually two kinds, one is phosphorus (Phosphorus), and the other is arsenic (Arsenic); the diffusion rate of Arsenic is slower than that of Phosphorus, so that the first epitaxial layer 22 is doped with Arsenic, and the decrease of effective Doping caused by diffusion can also be reduced.

[0061] The above has carried out the detailed explanation to the present application through the specific embodiments, but these do not constitute the limitation to the present application. In the case of not departing from the principle of the present application, the person skilled in the art can also make many deformations and improvements, and these should be regarded as the protection scope of the present application.

Claims

1. A method for manufacturing a superjunction structure, characterized in that, Includes the following steps: A first epitaxial layer doped with a first conductivity type is provided, and a plurality of superjunction trenches are formed by patterning and etching the first epitaxial layer, wherein the first epitaxial layer between each superjunction trench forms a first conductivity type pillar; Annealing is performed to cause the impurities in the first conductivity type pillar to expand outward along the side of the superjunction trench, so as to form a first doping concentration reduction region in the side region of the first conductivity type pillar. A second epitaxial layer doped with a second conductivity type is filled in the superjunction trench. The second epitaxial layer filled in the superjunction trench serves as a component of the second conductivity type pillar. The superjunction structure is formed by alternating arrangement of the first conductivity type pillar and the second conductivity type pillar. The PN back diffusion between the first conductivity type pillar and the second conductivity type pillar is reduced by utilizing the first doping concentration reduction region.

2. The method for manufacturing the superjunction structure as described in claim 1, characterized in that: The first conductive type pillar is uniformly doped along its width.

3. The method for manufacturing the superjunction structure as described in claim 1, characterized in that, The annealing temperature is 950℃~1150℃, and the time is 30 minutes~120 minutes.

4. The method for manufacturing the superjunction structure as described in claim 1, characterized in that: Prior to the annealing, a natural oxide layer is formed on the inner surface of the superjunction trench, which may be removed or retained before the annealing.

5. The method for manufacturing the superjunction structure as described in claim 1, characterized in that: The second epitaxial layer grows from the bottom surface and side surface of the superjunction trench. The second epitaxial layer includes an initial sublayer and a main layer. The initial sublayer is intrinsically doped or has a doping concentration lower than that of the main layer. The initial sublayer is used to reduce the PN back diffusion.

6. The method for manufacturing the superjunction structure as described in claim 5, characterized in that: The growth time of the initial sublayer is less than or equal to 120 seconds.

7. The method for manufacturing the superjunction structure as described in claim 1, characterized in that: After the annealing and before filling the second epitaxial layer, the method further includes: A first barrier impurity is injected into the inner surface of the superjunction trench to reduce the PN back diffusion.

8. The method for manufacturing the superjunction structure as described in claim 7, characterized in that: The first blocking impurity includes F or C.

9. The method for manufacturing the superjunction structure as described in claim 1, characterized in that: The superjunction trench has inclined sides and the top opening width is greater than the bottom opening width.

10. The method for manufacturing the superjunction structure as described in claim 9, characterized in that: The side slope angle of the super-junction trench is 88.5 degrees to 89.5 degrees.

11. The method for manufacturing the superjunction structure as described in claim 1, characterized in that: The first epitaxial layer is formed on a heavily doped semiconductor substrate of a first conductivity type.

12. The method for manufacturing a superjunction structure as described in claim 11, characterized in that: The semiconductor substrate is made of silicon or silicon carbide.

13. The method for manufacturing the superjunction structure as described in claim 1, characterized in that: The resistivity of the first epitaxial layer is 0.6 ohm·cm to 1.5 ohm·cm, and the thickness is 45 micrometers to 60 micrometers.

14. The method for manufacturing the superjunction structure as described in claim 13, characterized in that: The depth of the superjunction trench is 35 micrometers to 45 micrometers.

15. The method for manufacturing a superjunction structure according to any one of claims 1 to 14, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; Alternatively, the first conductivity type is P-type, and the second conductivity type is N-type.

16. The method for manufacturing the superjunction structure as described in claim 15, characterized in that: When the first conductivity type is N-type and the second conductivity type is P-type, the doping impurities of the first epitaxial layer include phosphorus and / or arsenic, and the doping impurities of the second epitaxial layer include boron and / or boron fluoride. Alternatively, when the first conductivity type is P-type and the second conductivity type is N-type, the doping impurities of the second epitaxial layer include phosphorus and / or arsenic, and the doping impurities of the first epitaxial layer include boron and / or boron fluoride.

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