Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, and belongs to the technical field of solar cells. The solar cell comprises a silicon substrate; a first transparent conducting layer arranged on the front face of the substrate comprises a first TCO body layer and a first In-containing layer which are sequentially stacked from inside to outside, and the first In-containing layer comprises a first In elementary substance layer corresponding to a grid line area and a first In2O3 layer corresponding to a non-grid line area; a second transparent conducting layer arranged on the back face of the substrate comprises a second TCO body layer and a second In-containing layer which are sequentially arranged in a stacked mode from inside to outside, and the second In-containing layer comprises a second In elementary substance layer corresponding to a grid line area and a second In2O3 layer corresponding to a non-grid line area. The solar cell has high open-circuit voltage, short-circuit current and fill factor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof. BACKGROUND

[0002] The preparation process of the existing heterojunction-copper interconnection battery includes: (1) performing texturing cleaning treatment on an N-type monocrystalline silicon wafer; (2) depositing intrinsic amorphous silicon and N-type amorphous silicon films on the front surface of the silicon wafer, and depositing intrinsic amorphous silicon and P-type amorphous silicon films on the back surface of the silicon wafer; (3) plating a transparent conductive film on the amorphous silicon; (4) depositing a Cu electroplating seed layer on the TCO; (5) coating and performing photolithography to form a grid line area for electroplating; (5) electroplating Cu grid lines; (7) removing the photosensitive ink and etching off the Cu seed layer; (8) repairing the damage to the film layer through photoinjection; and (9) tin plating to prevent copper oxidation. The structure of the solar cell prepared by the above method is shown in FIG. 1. Figure 1

[0003] In the process of sputtering the Cu seed layer, the above process can cause damage to the passivation of the battery wafer, affecting the open-circuit voltage of the battery; and during the sputtering process, part of the Cu element enters the TCO film layer, affecting the short-circuit current and the fill factor of the battery; in addition, due to the separate sputtering of the Cu seed layer and the TCO film layer, the stress of the Cu seed layer and the TCO film layer is inconsistent, the layer structure surface is dirty, and other reasons can cause poor adhesion of the Cu grid line to the TCO film layer after electroplating, resulting in low process yield.

[0004] In view of this, the present application is proposed. SUMMARY

[0005] The present application aims to provide a solar cell and a preparation method thereof to solve or improve at least one of the above technical problems.

[0006] The present application can be implemented as follows: In a first aspect, the present application provides a solar cell, which includes a silicon substrate; The first transparent conductive layer arranged on the front surface of the silicon substrate includes a first TCO body layer and a first In-containing layer arranged in sequence from inside to outside, the first In-containing layer including a first In elemental layer corresponding to a grid line area and a first In2O3 layer corresponding to a non-grid line area; The second transparent conductive layer arranged on the back surface of the silicon substrate includes a second TCO body layer and a second In-containing layer arranged in sequence from inside to outside, the second In-containing layer including a second In elemental layer corresponding to a grid line area and a second In2O3 layer corresponding to a non-grid line area.

[0007] ​In optional embodiments, the thickness of the first TCO bulk layer is 50% to 99% of the total thickness of the first transparent conductive layer, and / or the thickness of the second TCO bulk layer is 50% to 99% of the total thickness of the second transparent conductive layer.

[0008] In optional embodiments, the thickness of the first In elemental layer and the second In elemental layer is independently 1 nm to 40 nm.

[0009] In optional embodiments, the front side of the silicon substrate is sequentially provided with a first intrinsic amorphous silicon layer, a first doped amorphous / microcrystalline silicon layer, a first transparent conductive layer, and a first metal electrode. The back side of the silicon substrate is sequentially provided with a second intrinsic amorphous silicon layer, a second doped amorphous / microcrystalline silicon layer, a second transparent conductive layer, and a second metal electrode.

[0010] In optional embodiments, the surface of the first metal electrode is further provided with a first metal protective layer; and the surface of the second metal electrode is further provided with a second metal protective layer.

[0011] In optional embodiments, the solar cell does not contain a copper seed layer.

[0012] In a second aspect, the present application provides a method for preparing a solar cell according to any one of the preceding embodiments, comprising the following steps: A first In elemental layer is deposited on the surface of the first TCO bulk layer deposited on the front side of the silicon substrate, followed by coating a negative photosensitive ink, hardening, printing, developing, and edge wrapping, to prepare a first metal electrode in the developed grid line area, followed by film removal, and oxidizing the In elemental layer in the first In elemental layer corresponding to the non-grid line area to form a first In2O3 layer. A second In elemental layer is deposited on the surface of the second TCO bulk layer deposited on the back side of the silicon substrate, followed by coating a negative photosensitive ink, hardening, printing, developing, and edge wrapping, to prepare a second metal electrode in the developed grid line area, followed by film removal, and oxidizing the In elemental layer in the second In elemental layer corresponding to the non-grid line area to form a second In2O3 layer.

[0013] In optional embodiments, the deposition conditions of the first In elemental layer and the second In elemental layer independently comprise: a cavity vacuum degree of 0.1 Pa to 20 Pa, a power density of 50 W / m to 300 W / m, an argon gas flow rate of 500 sccm to 1100 sccm, and a deposition rate of 0.1 nm / s to 2 nm / s.

[0014] In optional embodiments, after the preparation of the first TCO bulk layer is completed, the first In elemental layer is continuously deposited without taking the cavity out.

[0015] In an optional embodiment, after the preparation of the second TCO bulk layer is completed, the second In single-element total layer is continuously deposited without being taken out of the chamber.

[0016] In an optional embodiment, before the first In single-element total layer is deposited, a first intrinsic amorphous silicon layer, a first doped amorphous / microcrystalline silicon layer and a first TCO bulk layer are sequentially prepared on the front surface of the silicon substrate. Before the second In single-element total layer is deposited, a second intrinsic amorphous silicon layer, a second doped amorphous / microcrystalline silicon layer and a second TCO bulk layer are sequentially prepared on the back surface of the silicon substrate.

[0017] In an optional embodiment, a first metal protective layer and a second metal protective layer are respectively arranged on the surfaces of the first metal electrode and the second metal electrode.

[0018] The beneficial effects of the present application include: The solar cell provided by the present application does not contain a copper seed layer, which can avoid sputtering damage to the TCO film layer during the preparation of the copper seed layer, and can avoid the problem of poor adhesion between the copper seed layer and the TCO film layer. In addition, the solar cell provided by the present application has a high open-circuit voltage, short-circuit current and fill factor. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0020] Figure 1 FIG. 1 is a structural schematic diagram of a solar cell in the prior art; Figure 2 FIG. 2 is a structural schematic diagram of a solar cell provided by the present application.

[0021] Icons: 10 - Silicon substrate; 21 - First intrinsic amorphous silicon layer; 22 - Second intrinsic amorphous silicon layer; 31 - First doped amorphous / microcrystalline silicon layer; 32 - Second doped amorphous / microcrystalline silicon layer; 41 - First transparent conductive layer; 42 - Second transparent conductive layer; 51 - First metal electrode; 52 - Second metal electrode; 411 - First TCO bulk layer; 412 - First In-containing layer; 421 - Second TCO bulk layer; 422 - Second In-containing layer; 4121 - First In elemental layer; 4122 - First In₂O₃ layer; 4221 - Second In elemental layer; 4222 - Second In₂O₃ layer. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0023] The following provides a detailed description of the solar cell and its fabrication method provided in this application.

[0024] This invention provides a solar cell that does not contain a copper seed layer. On the one hand, it avoids sputtering damage to the TCO film during the preparation of the copper seed layer. On the other hand, it avoids the problem of some copper atoms embedding into the TCO film during the preparation of the copper seed layer, blocking light penetration and damaging the TCO film lattice. In addition, it also avoids the problem of poor adhesion between the copper seed layer and the TCO film, thereby improving the product yield.

[0025] like Figure 2 As shown, specifically, the solar cell includes a silicon substrate 10; the front side of the silicon substrate 10 is sequentially provided with a first intrinsic amorphous silicon layer 21, a first doped amorphous / microcrystalline silicon layer 31, a first transparent conductive layer 41 and a first metal electrode 51; the back side of the silicon substrate 10 is sequentially provided with a second intrinsic amorphous silicon layer 22, a second doped amorphous / microcrystalline silicon layer 32, a second transparent conductive layer 42 and a second metal electrode 52.

[0026] The first transparent conductive layer 41 disposed on the front side of the silicon substrate 10 includes a first TCO body layer 411 and a first In-containing layer 412 stacked sequentially from the inside to the outside. The first In-containing layer 412 includes a first In elemental layer 4121 corresponding to the gate line region and a first In2O3 layer 4122 corresponding to the non-gate line region.

[0027] The second transparent conductive layer 42 arranged on the back surface of the silicon substrate 10 comprises a second TCO body layer 421 and a second In-containing layer 422 arranged in sequence from inside to outside, the second In-containing layer 422 comprises a second In single layer 4221 corresponding to the gate line area and a second In2O3 layer 4222 corresponding to the non-gate line area, and the thickness of the second TCO body layer 421 is 50% to 99% of the total thickness of the second transparent conductive layer 42.

[0028] In some optional embodiments, the thickness of the first TCO body layer 411 can be 50% to 99% of the total thickness of the first transparent conductive layer 41, such as 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 99%, etc., or other values within the range of 50% to 99%.

[0029] Similarly, the thickness of the second TCO body layer 421 can be 50% to 99% of the total thickness of the second transparent conductive layer 42, such as 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 99%, etc., or other values within the range of 50% to 99%.

[0030] In some optional embodiments, the thickness of the first In single layer 4121 and the second In single layer 4221 can independently be 1 nm to 40 nm, such as 1 nm, 2 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm, etc., or other values within the range of 1 nm to 40 nm.

[0031] If the thickness of the above-mentioned In single layer is too thin, it will cause poor stability and conductivity, because a thinner In single layer is extremely susceptible to external factors, leading to unstable performance, and even a larger resistance during current transmission, affecting the overall performance of the device. If the thickness of the above-mentioned In single layer is too thick, it will cause increased power consumption and reduced device response speed, because a thicker In single layer will increase the capacitance of the device, leading to increased power consumption, and also slowing down the transmission speed of the electrons, thereby reducing the response speed of the device.

[0032] In some optional embodiments, the front surface of the silicon substrate 10 is sequentially provided with a first intrinsic amorphous silicon layer 21, a first doped amorphous / microcrystalline silicon layer 31, a first transparent conductive layer 41, and a first metal electrode 51.

[0033] The back surface of the silicon substrate 10 is sequentially provided with a second intrinsic amorphous silicon layer 22, a second doped amorphous / microcrystalline silicon layer 32, a second transparent conductive layer 42, and a second metal electrode 52.

[0034] Further, the surface of the first metal electrode 51 can be provided with a first metal protective layer (not shown in the figure); and the surface of the second metal electrode 52 can be provided with a second metal protective layer (not shown in the figure).

[0035] Correspondingly, the application further provides a preparation method of the above-mentioned solar cell, and no copper seed layer is prepared in the whole preparation process.

[0036] In some optional embodiments, the preparation method of the solar cell comprises the following steps: The first In elemental total layer is deposited on the surface of the first TCO body layer 411, and then a negative photosensitive ink is coated, hardened, printed, developed, and edge-coated to prepare the first metal electrode 51 layer in the developed grid line area, and then the film is removed, and the In elemental layer corresponding to the non-grid line area in the first In elemental total layer is oxidized to form the first In2O3 layer 4122. The second In elemental total layer is deposited on the surface of the second TCO body layer 421, and then a negative photosensitive ink is coated, hardened, printed, developed, and edge-coated to prepare the second metal electrode 52 layer in the developed grid line area, and then the film is removed, and the In elemental layer corresponding to the non-grid line area in the second In elemental total layer is oxidized to form the second In2O3 layer 4222.

[0037] The above-mentioned method uses a thinning method to prepare a TCO body layer, and then prepares an In elemental total layer on the surface of the TCO body layer, and the sputtering voltage of In is reduced by 30%~50% compared with the sputtering voltage of Cu in the conventional copper seed layer, so that the damage to the TCO film layer in the sputtering process can be effectively reduced, thereby facilitating the improvement of the open-circuit voltage of the cell.

[0038] In other words, taking the thickness of the conventional transparent conductive layer as x as an example, in the present application, the thickness of the transparent conductive layer is also x, the thickness of the TCO body layer is x1, and the thickness of the In elemental total layer is x2, x1+x2=x. Among them, the In elemental total layer is divided into a position corresponding to the grid line area and a position corresponding to the non-grid line area. The In elemental total layer corresponding to the grid line area is not oxidized in the subsequent oxidation process and still exists in the form of In elemental layer; and the In elemental total layer corresponding to the non-grid line area is oxidized in the subsequent oxidation process and finally exists in the form of In2O3 layer.

[0039] In addition, in the process of preparing the copper seed layer, part of the Cu atoms are embedded into the TCO film layer, and the subsequent process cannot remove the embedded Cu atoms, so the embedded Cu atoms in the TCO film layer will block the penetration of light, thereby affecting the short-circuit current of the battery. Moreover, the embedded Cu atoms in the TCO film layer will cause irreparable damage to the lattice of the TCO film layer, thereby damaging the pseudo fill factor of the battery, and further reducing the fill factor of the battery. The scheme provided in the present application does not prepare a copper seed layer, and Cu atoms are not embedded into the TCO film layer. In addition, the In element of the non-grid line is finally oxidized to form In2O3, which does not affect the short-circuit current of the battery. Moreover, the oxidation of the In element to In2O3 can repair the TCO lattice, thereby reducing or avoiding the impact on the fill factor.

[0040] In some optional embodiments, the deposition conditions of the first In element total layer and the second In element total layer independently include: a cavity vacuum degree of 0.1 Pa to 20 Pa, a power density of 50 W / m to 300 W / m, an argon flow rate of 500 sccm to 1100 sccm, and a deposition rate of 0.1 nm / s to 2 nm / s.

[0041] The cavity vacuum degree can be 0.1 Pa, 0.5 Pa, 1 Pa, 2 Pa, 5 Pa, 10 Pa, 15 Pa, or 20 Pa, or other values within the range of 0.1 Pa to 20 Pa.

[0042] The power density can be 50 W / m, 100 W / m, 150 W / m, 200 W / m, 250 W / m, or 300 W / m, or other values within the range of 50 W / m to 300 W / m.

[0043] The argon flow rate can be 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, 1000 sccm, or 1100 sccm, or other values within the range of 500 sccm to 1100 sccm.

[0044] The deposition rate can be 0.1 nm / s, 0.5 nm / s, 1 nm / s, 1.5 nm / s, or 2 nm / s, or other values within the range of 0.1 nm / s to 2 nm / s.

[0045] In the above operation process, after the preparation of the first TCO body layer 411 is completed, the first In element total layer is continuously deposited without leaving the cavity. Similarly, after the preparation of the second TCO body layer 421 is completed, the second In element total layer is continuously deposited without leaving the cavity.

[0046] It should be noted that the adhesion of the copper seed layer and the TCO film layer in the prior art is poor, which may be due to the fact that the TCO film layer is taken out of the chamber after preparation and even undergoes an additional annealing process, which forms dirt on the surface of the TCO film layer, resulting in poor adhesion between the copper seed layer and the TCO film layer. In addition, the stress of the copper seed layer and the TCO film layer is different, which also causes stress release during electroplating, thereby causing peeling between the copper seed layer and the TCO film layer. In the present application, the deposition process of the TCO body layer and the In single element total layer is carried out in the same chamber, and is carried out without taking out of the chamber, so that the main component In2O3 in the TCO film layer can form a symbiotic state with the In single element, thereby improving the adhesion problem.

[0047] In addition, the preparation of the copper seed layer in the prior art requires a separate PVD device for sputtering Cu, which is costly and not conducive to the promotion of heterojunction technology to mass production. The preparation method provided by the present application is simple, and the In target can be directly installed inside the TCO machine, which can greatly save equipment cost.

[0048] In some optional embodiments, the following steps can be used to prepare a solar cell: A first intrinsic amorphous silicon layer 21, a first doped amorphous / microcrystalline silicon layer 31 and a first TCO body layer 411 are prepared in sequence on the front side of the silicon substrate 10. A first In single element total layer is deposited on the surface of the first TCO body layer 411, and then a negative photosensitive ink is applied, hardened, printed, developed and edge-coated. A first metal electrode 51 layer is prepared in the developed grid line area, and then the film is removed. The In single element layer corresponding to the non-grid line area in the first In single element total layer is oxidized to form a first In2O3 layer 4122. A first metal protective layer is provided on the surface of the first metal electrode 51. A second intrinsic amorphous silicon layer 22, a second doped amorphous / microcrystalline silicon layer 32 and a second TCO body layer 421 are prepared in sequence on the back side of the silicon substrate 10. A second In single element total layer is deposited on the surface of the second TCO body layer 421, and then a negative photosensitive ink is applied, hardened, printed, developed and edge-coated. A second metal electrode 52 layer is prepared in the developed grid line area, and then the film is removed. The In single element layer corresponding to the non-grid line area in the second In single element total layer is oxidized to form a second In2O3 layer 4222. A second metal protective layer is provided on the surface of the second metal electrode 52.

[0049] It should be noted that in the prior art, the efficiency and yield of the Cu electroplating route solar cell are poor, one of the main reasons is that in the process of removing the copper seed layer, the copper seed layer will be over-etched by the chemical solution, resulting in low battery fill factor, and even causing grid breakage. The scheme provided by the present application does not have the process of etching back the copper seed layer, which can fundamentally solve the problem of low efficiency and yield.

[0050] In some more specific embodiments, the solar cell can be prepared by the following process: S1: N-type monocrystalline silicon wafer is subjected to gettering, texturing, and cleaning treatment to form a 1-3 μm pyramid textured surface and keep the silicon wafer surface clean.

[0051] S2: The first intrinsic amorphous silicon layer 21 and the first doped amorphous / microcrystalline silicon layer 31 are deposited on the front side of the textured silicon substrate 10, and the second intrinsic amorphous silicon layer 22 and the second doped amorphous / microcrystalline silicon layer 32 are deposited on the back side to obtain a cell wafer.

[0052] Exemplarily, the thickness of the first intrinsic amorphous silicon layer 21 can be 3-10 nm, the thickness of the second intrinsic amorphous silicon layer 22 can be 2-15 nm, the thickness of the front side phosphorus-doped amorphous silicon layer can be 0.5-1.5 nm, the thickness of the front side phosphorus-doped microcrystalline silicon layer can be 10-20 nm, the thickness of the back side boron-doped amorphous silicon layer can be 0.5-2 nm, and the thickness of the back side boron-doped microcrystalline silicon layer can be 25-40 nm.

[0053] S3: The first TCO body layer 411 and the second TCO body layer 421 are deposited on the front side and the back side of the cell wafer by magnetron sputtering, and the thickness of the first TCO body layer 411 and the second TCO body layer 421 is controlled to be 50-99% of the total thickness of the conventional TCO film layer (for example, when the conventional TCO film layer is 70 nm, the thickness of the first TCO body layer 411 and the second TCO body layer 421 can be controlled to be 35-69 nm). The first TCO body layer 411 and the second TCO body layer 421 have basically the same effect as the conventional TCO film layer, mainly ensuring ohmic contact with the microcrystalline layer and excellent light penetration and high mobility.

[0054] S4: After the deposition of the first TCO body layer 411 and the second TCO body layer 421 is completed, the elemental In layer is sputtered without taking out the chamber, serving as a current transmission layer for the subsequent Cu electroplating process. Compared with the copper seed layer in the prior art, the current transmission layer has the advantage of not introducing impurity elements to the TCO film layer, and the sputtering voltage of In is 30-50% lower than that of Cu, which can effectively reduce sputtering damage and recover the open-circuit voltage of the cell affected by Cu sputtering damage. Moreover, the deposition of the elemental In layer is sputtered immediately after the TCO body layer without taking out the chamber, so there is no interface defect caused by taking out the chamber. In addition, In and In2O3 have excellent adhesion, so there is no risk of peeling and grid breakage during the subsequent Cu electroplating.

[0055] For example, if the thickness of each TCO body layer in S3 is 35 nm, the thickness of each In single-element layer is 35 nm; if the thickness of each TCO body layer in S3 is 69 nm, the thickness of each In single-element layer is 1 nm. In addition, when the thickness of the TCO film layer is different, the thickness of each TCO body layer and In single-element layer is adjusted correspondingly. In some typical embodiments, the thickness of the first In single-element layer 4121 and the second In single-element layer 4221 is independently 1 nm to 40 nm.

[0056] The deposition conditions of the first In single-element total layer and the second In single-element total layer can include: a cavity vacuum degree of 0.1 Pa to 20 Pa, a power density of 50 W / m to 300 W / m, an argon flow rate of 500 sccm to 1100 sccm, and a deposition rate of 0.1 nm / s to 2 nm / s.

[0057] S5: Coating, uniformly coating the surface of the battery piece obtained in S4 with a negative photosensitive ink and hardening.

[0058] S6: Printing, cross-linking / hardening the exposed part so that it is insoluble in the subsequent developer, and dissolving the unexposed part in the subsequent developer.

[0059] S7: Developing, dissolving the unexposed part in the developer to expose the area for subsequent electroplating.

[0060] S8: Edge covering, covering the area where the edge is not coated with the photosensitive ink to prevent the edge from being plated with Cu during electroplating and causing the battery to leak electricity.

[0061] S9: Electroplating, plating a 5 μm to 20 μm Cu grid line lead electrode in the developed grid line area to obtain a metal electrode.

[0062] For example, the electroplating can be carried out in a vertical or horizontal electroplating tank, the current density can be 1 A / dm 2 ~10 A / dm 2 , and the copper plating thickness can be 15 μm to 25 μm.

[0063] S10: Film removal, removing the photosensitive adhesive using a NaOH solution (the concentration can be 10 g / L to 100 g / L). Compared with the prior art, the back-etching process is not used, and there is no lateral etching phenomenon between the electroplated Cu grid line and In, so that the grid line has a larger contact area with the battery piece, and the fill factor of the battery piece is increased (about 0.1% to 0.3%).

[0064] S11: In oxidation. Pure oxygen is introduced into a rapid annealing furnace and the temperature is maintained at 130℃~220℃ to oxidize the solar cell obtained in S10. The oxidation time can be 15min~1h. After all the elemental In corresponding to the non-grid area is oxidized to In2O3, the throughput is consistent with that of conventional indium tin vanadium oxide materials, ensuring that the solar cell has excellent current performance. Moreover, the In at the bottom of the electroplated copper (corresponding to the grid area) will not oxidize much due to the protection of Cu. The direct contact between Cu and In has a lower contact resistance than the Cu and TCO contact in the existing technology (the contact resistance is 9×10⁻⁶ between the TCO film layer and the copper seed layer). -2 ~2×10 -3 The ohmic magnitude was reduced to 5 × 10⁻⁶. -5 ~9×10 -5 (On the order of ohms), resulting in a significantly improved battery fill factor. Ultimately, the total thickness of the In₂O₃ layer formed after In oxidation, along with the unoxidized In layer, matches the required thickness of the final transparent conductive layer. It should be noted that the Cu oxidation thickness can reach 15nm~50nm during this process, but the CuO will be removed during the pre-cleaning stage of the subsequent tinning process. x .

[0065] It should be noted that the In oxidation process described above can also be performed using laser-based annealing with precise film thickness control, as well as other annealing methods.

[0066] S12: Tinning prevents Cu oxidation. Before tinning, CuO on the surface of the Cu gate line is removed by conventional acid cleaning solution. x And other residues, under the catalytic action of additives, the Cu atoms on the surface of the Cu gate wire will reduce Sn in the SnSO4 solution. 2+ It transforms into elemental Sn, which has passivating properties in air, thus ensuring that the internal Cu cannot come into contact with oxygen, thereby protecting the Cu gate lines from oxidation.

[0067] It should be noted that the steps in this invention, such as texturing, intrinsic amorphous silicon layer, doped microcrystalline silicon layer, doped amorphous / microcrystalline silicon layer, coating, printing, developing, edge banding, metal electrode, film removal, and Sn treatment, can all refer to conventional methods and conditions in the art, and will not be elaborated or limited here.

[0068] In summary, the solution provided by this invention avoids sputtering damage to the TCO film during the copper seed layer preparation process in existing technologies. It also prevents copper atoms from embedding into the TCO film during the copper seed layer preparation process, thus avoiding light penetration obstruction and damage to the TCO film lattice. Furthermore, it avoids the problem of poor adhesion between the copper seed layer and the TCO film, thereby improving product yield. The solar cell provided by this invention exhibits high open-circuit voltage, short-circuit current, and fill factor.

[0069] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application. The present application can have various changes and modifications for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A solar cell, characterized in that, The solar cell includes a silicon substrate; The first transparent conductive layer disposed on the front side of the silicon substrate includes a first TCO body layer and a first In-containing layer stacked sequentially from the inside to the outside. The first In-containing layer includes a first In elemental layer corresponding to the gate line region and a first In2O3 layer corresponding to the non-gate line region. The second transparent conductive layer disposed on the back side of the silicon substrate includes a second TCO body layer and a second In-containing layer stacked sequentially from the inside to the outside. The second In-containing layer includes a second In elemental layer corresponding to the gate line region and a second In2O3 layer corresponding to the non-gate line region.

2. The solar cell according to claim 1, characterized in that, The thickness of the first TCO body layer is 50% to 99% of the total thickness of the first transparent conductive layer, and / or the thickness of the second TCO body layer is 50% to 99% of the total thickness of the second transparent conductive layer.

3. The solar cell according to claim 1, characterized in that, The thicknesses of the first In elemental layer and the second In elemental layer are independently 1 nm to 40 nm.

4. The solar cell according to any one of claims 1 to 3, characterized in that, The front side of the silicon substrate is provided with a first intrinsic amorphous silicon layer, a first doped amorphous / microcrystalline silicon layer, a first transparent conductive layer, and a first metal electrode in sequence. The back side of the silicon substrate is sequentially provided with a second intrinsic amorphous silicon layer, a second doped amorphous / microcrystalline silicon layer, a second transparent conductive layer, and a second metal electrode.

5. The solar cell according to claim 4, characterized in that, The surface of the first metal electrode is further provided with a first metal protective layer; the surface of the second metal electrode is further provided with a second metal protective layer.

6. The solar cell according to claim 4, characterized in that, The solar cell does not contain a copper seed layer.

7. A method for fabricating a solar cell, characterized in that, Includes the following steps: A first In elemental total layer is deposited on the surface of the first TCO body layer deposited on the front side of the silicon substrate. Then, negative photosensitive ink is coated, hardened, printed, developed, and edge-bound. A first metal electrode is prepared in the gate line region after development. Then, the film is removed, and the In elemental layer in the corresponding non-gate line region of the first In elemental total layer is oxidized to form a first In2O3 layer. A second In elemental total layer is deposited on the surface of the second TCO body layer deposited on the back side of the silicon substrate. Then, negative photosensitive ink is coated, cured, printed, developed, and edge-bound. A second metal electrode is prepared in the gate line region after development. Then, the film is removed, and the In elemental layer in the corresponding non-gate line region of the second In elemental total layer is oxidized to form a second In2O3 layer.

8. The preparation method according to claim 7, characterized in that, The deposition conditions of the first In elemental total layer and the second In elemental total layer independently include: cavity vacuum degree of 0.1 Pa to 20 Pa, power density of 50 W / m to 300 W / m, argon flow rate of 500 sccm to 1100 sccm, and deposition rate of 0.1 nm / s to 2 nm / s; Preferably, after the first TCO body layer is prepared, the first In elemental total layer is deposited without leaving the cavity; Preferably, after the second TCO body layer is prepared, the second In elemental total layer is deposited without leaving the cavity.

9. The preparation method according to claim 7, characterized in that, Before depositing the first In single-element total layer, the first intrinsic amorphous silicon layer, the first doped amorphous / microcrystalline silicon layer, and the first TCO body layer are sequentially prepared on the front side of the silicon substrate. Before depositing the second In single-element total layer, a second intrinsic amorphous silicon layer, a second doped amorphous / microcrystalline silicon layer, and a second TCO body layer are sequentially prepared on the back side of the silicon substrate.

10. The preparation method according to claim 9, characterized in that, A first metal protective layer and a second metal protective layer are respectively provided on the surfaces of the first metal electrode and the second metal electrode.

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