Layout optimization-based high-CTR and high-speed photo-transistor and manufacturing method thereof

Abstract

The invention relates to the field of photo-transistors, in particular to a high-CTR and high-speed photo-transistor based on layout optimization and a manufacturing method thereof.The high-CTR and high-speed photo-transistor comprises a semiconductor substrate, and an N-type epitaxial layer, a P-type base region and an N-type emitter region are sequentially formed on the semiconductor substrate; the P-type base region comprises a photoelectric sensing region and a base electrode main body which are independently arranged, the photoelectric sensing region is used for receiving optical signals and generating current carriers, the base electrode main body and the N-type emission region form a PN junction, and the node depth and the doping concentration of the base electrode main body can be independently adjusted according to beta value design requirements; the photoelectric sensing area and the base electrode main body are independently arranged, the section depth and the doping concentration of the base electrode main body can be flexibly adjusted according to beta value design, the problem that the section depth of a base electrode in a traditional shared structure is limited by photoelectric conversion efficiency is avoided, CTR is obviously improved, parameter stability is higher, and production efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photosensitive transistor, in particular to a high CTR and high-speed photosensitive transistor based on layout optimization and a manufacturing method thereof. BACKGROUND

[0002] As the core component of optocoupler, photosensitive transistor is widely used in electronic circuits by virtue of optical signal transmission to achieve electrical isolation. Current transfer ratio (CTR) is a key parameter to measure the performance of photosensitive transistor, and the higher the value is, the stronger the transmission ability and reliability of optocoupler are. Meanwhile, the transmission speed determines the response efficiency of the circuit and directly affects the applicability of optocoupler in high requirement interface scenarios (such as IEEE485 interface).

[0003] There are two major defects in traditional photosensitive transistor: firstly, the base and the sensing area of photoelectric conversion share the structure, in order to ensure the photoelectric conversion efficiency, the base junction depth is usually designed as 3-5μm, and the emitter junction depth is 1-3μm. The deeper base junction depth will prolong the carrier diffusion time and increase the parameter variation, making it difficult to achieve high CTR. Secondly, the impedance of the sensing area is high, and the speed of the carrier moving from the sensing area to the base and then to the emitter is slow, so the operating frequency is only 10-40KHz, which cannot meet the speed requirement of IEEE485 interface. In addition, when the traditional photosensitive transistor operates at a large current, the junction depth (interface) between the base and the emitter is prone to emitter crowding, which leads to a significant decrease in β value, and then causes a significant decrease in CTR, affecting the stability of the device in high load scenarios.

[0004] In the prior art, although there are attempts to improve the single performance of CTR or transmission speed, the coordination problem of high CTR, high-speed transmission and wide working current range is not solved from the layout design level, and it is difficult to meet the high requirements of electronic devices on the comprehensive performance of photosensitive transistor.

[0005] Therefore, we improve it and propose a high CTR and high-speed photosensitive transistor based on layout optimization and a manufacturing method thereof. SUMMARY

[0006] In order to achieve the above-mentioned application purpose, the present application provides a high CTR and high-speed photosensitive transistor based on layout optimization and a manufacturing method thereof to solve the above-mentioned problems.

[0007] The present application is specifically as follows: A high CTR and high-speed photosensitive transistor based on layout optimization, comprising a semiconductor substrate, an N-type epitaxial layer, a P-type base region and an N-type emitter region are formed on the semiconductor substrate in sequence. The P-type base region comprises an independently arranged photoelectric sensing region and a base body, the photoelectric sensing region is used for receiving light signals and generating carriers, the base body forms a PN junction with the N-type emitter region, and the depth of the base body can be independently adjusted according to the design requirement of the beta value; The upper part of the photoelectric sensing region is covered with a low-impedance conductive layer, the low-impedance conductive layer is a metal layer, an ITO layer or a polysilicon layer, the low-impedance conductive layer is high-temperature resistant, and is used for collecting the carriers generated by the photoelectric sensing region and transmitting the carriers to the base body; The depth of the P-type base region on both sides of the N-type emitter region is greater than the depth of the P-type base region below the N-type emitter region, forming an emitter two-side base deepening structure to increase the path of carrier injection into the N-type emitter region; and the emitter crowding phenomenon is avoided through circuit layout optimization - a plurality of windows are opened at the positions corresponding to the emitter region and are in communication with the photoelectric sensing region, without the need for additional process flow adjustment; The photoelectric sensing region is defined by an independent photoetching process, the base body and the N-type emitter region are defined by one photoetching process, and the depths of the base body and the N-type emitter region are adjusted by two independent ion implantation processes, without the need for additional photoetching times.

[0008] Preferably, the low-impedance conductive layer is electrically connected to the base body through a metal wire.

[0009] Preferably, the depth of the P-type base region on both sides of the N-type emitter region is 0.5-1 μm greater than the depth of the P-type base region below the N-type emitter region.

[0010] Preferably, a high-CTR and high-speed photosensitive transistor manufacturing method based on layout optimization comprises the following steps (combined with the standard process flow of high-speed photoelectric transistors): Step 1: wafer pretreatment and N-type epitaxial layer preparation An N-type silicon substrate (resistivity 1-10 Ω·cm) is provided, wafer number marking is performed (made by an epitaxial wafer factory), and then the Mark area is subjected to Mask and silicon etching (an optional step, selected according to the photoetching machine requirements of a foundry); An N-type epitaxial layer is grown by a chemical vapor deposition process, and the control parameters are as follows: temperature 1000-1300 ℃, silicon source (such as silane) and doping source (such as phosphine) are introduced, and a uniform N-type epitaxial layer structure is formed.

[0011] Step 2: photoelectric sensing region formation First photoetching: glue coating - exposure - development, the photoelectric sensing region pattern is defined by Mas; Oxide layer etching: the field oxide layer of the region corresponding to the photoelectric sensing region is etched, and the surface oxide layer is removed; Photoresist removal and cleaning: the photoresist is removed and the wafer surface is cleaned; Thin oxide layer preparation: grow thin oxide layer on the surface of the photoelectric sensing area; Photoelectric sensing area ion implantation: implant boron ions (B11), implantation energy 80-180keV, form P-type photoelectric sensing area; P+ diffusion and oxidation: diffusion and oxidation treatment is performed on the photoelectric sensing area, and the sensing area structure is stabilized, and after completion, the subsequent process is entered.

[0012] Step 3: Base body and N-type emitter formation (base and emitter share lithography, optimize process synergy) Second lithography: glue coating-exposure-development, use Mask to define base body and N-type emitter pattern, no need to add lithography step for base body; Oxide layer etching: etch the oxide layer corresponding to the base body and N-type emitter area; Photoresist removal and cleaning: remove photoresist and clean the wafer surface; Thin oxide layer preparation: grow thin oxide layer on the surface of the base body and N-type emitter; Base body ion implantation (patent required base implantation): implant boron ions (B11), implantation energy 80-180keV, adjust the base body depth through this parameter, meet the design requirement of β value; Base diffusion and oxidation (Option, decide whether to do according to CTR and BV): diffusion and oxidation treatment is performed on the base body, further optimize the base depth and performance; N-type emitter ion implantation: select doping source according to the requirement of the emitter area-use phosphorus ions (P31) or arsenic ions (As75), implantation energy 30-120keV; form N-type emitter; N+ diffusion and oxidation: common diffusion and oxidation treatment is performed on the base body and N-type emitter, synchronize the structure of the two, realize the process synergy of base and emitter.

[0013] Contact hole preparation: third lithography defines contact hole pattern, then oxide layer etching, punch through the low impedance conductive layer and the electrical connection channel of the base body; Depositing low impedance conductive layer on the upper part of the photoelectric sensing area, such as: preparing ITO layer (In2O3: SnO2=9:1) or other light-transmitting conductive material through magnetron sputtering process, this method must have one more lithography. Or do not do this step, directly in this paper third lithography, fourth lithography use layout in photosensitive area with finger layout to add appropriate metal wire to guide the photosensitive area signal to the base area.

[0014] Metal deposition: Metal layer is deposited by magnetron sputtering process Metal patterning: The fourth photoetching defines the metal wire pattern, and then a dry etching process is used to etch the metal layer to form the metal wire connecting the low-impedance conductive layer and the base body; Alloy treatment: Under the protection of a nitrogen atmosphere, the metal layer and the semiconductor are enhanced in contact stability at a temperature of 350-480℃ for a proper time.

[0015] Performance detection: After the photosensitive transistor is manufactured, the performance detection link is entered to verify the CTR, transmission speed and anti-emitter crowding performance, so as to ensure that the product meets the design requirements.

[0016] Preferably, in step 2, the ion implantation of the photoelectric sensing area is separated from the traditional base implantation process, and an independent photoetching and implantation parameter (80-120keV) is used to realize a depth of 3-5μm, meeting the photoelectric conversion efficiency requirement.

[0017] In step 3, the base body and the N-type emitter region share one photoetching, and the depth of the two is independently adjusted through different ion implantation parameters (base 80-180keV, emitter 30-120keV), taking into account the process efficiency and structural accuracy.

[0018] Compared with the prior art, the beneficial effects of the present application are: 1. Process synergy is improved, the process is simplified, the cost is reduced, and the process limitation of the traditional base and sensing area sharing photoetching / implantation is broken. The base body and the N-type emitter region share one photoetching, reducing 1 photoetching process, and the structure of the two is stabilized through synchronous diffusion oxidation. The process steps are reduced by 15%-20%, which is suitable for high-speed photoelectric triode standard production line, and reduces the equipment adjustment and time cost.

[0019] 3. The emitter crowding solution is more efficient, and the traditional process adjustment is replaced by circuit layout optimization: a plurality of windows are opened in the emitter region corresponding position, which are connected with the photoelectric sensing area, increasing the carrier diffusion channel, without additional ion implantation or diffusion steps, the emitter crowding phenomenon can be avoided, the β value fluctuation range is reduced from the traditional ±200% to ±25%, and the CTR remains stable in a wide current range.

[0020] 4. High CTR and high-speed transmission cooperate to realize independent implantation of the photoelectric sensing area to guarantee a depth of 3-5μm (high photoelectric conversion efficiency), the base body is implanted at 150keV and the photosensitive area respectively to realize a depth of 1-2μm (shorten the carrier diffusion time), and cooperates with the low-impedance conductive layer (sheet resistance ≤10Ω / □), the transmission speed is improved to more than 120KHz, meeting the IEEE485 interface requirement, and the CTR value is more stable than the traditional structure. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1A layout schematic diagram of a photoelectric sensing area and a base body in an embodiment of the present application; Figure 2 A flowchart of a manufacturing method in an embodiment of the present application. DETAILED DESCRIPTION

[0022] For those skilled in the technical field, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0023] The present application aims to overcome the defects of low CTR, slow transmission speed and easy occurrence of emitter crowding under large current of the conventional photosensitive transistor, and to provide a high-CTR and high-speed photosensitive transistor based on layout optimization and a manufacturing method thereof. By splitting the photoelectric sensing area and the base structure, optimizing the carrier collection path and adjusting the base node depth layout, the CTR is improved, the transmission speed is accelerated and the wide working current interval is adapted.

[0024] For those skilled in the technical field, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0025] It should be noted that the embodiments in the present application and the features and technical solutions in the embodiments can be combined with each other without conflict.

[0026] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0027] A high-CTR and high-speed photosensitive transistor based on layout optimization and a manufacturing method thereof, comprising: The semiconductor substrate comprises an N-type epitaxial layer, a P-type base region and an N-type emitter region formed in sequence on the semiconductor substrate; the P-type base region comprises a photoelectric sensing area and a base body arranged independently; the photoelectric sensing area is used for receiving a light signal and generating carriers; the base body and the N-type emitter region form a PN junction; and the node depth and the doping concentration of the base body can be independently adjusted according to the design requirements of the beta value; A part of the photoelectric sensing area is covered with a low-impedance conductive layer, which is a metal layer, an ITO layer or a polysilicon layer, for collecting the carriers generated by the photoelectric sensing area and transmitting them to the base body; The P-type base region on both sides of the N-type emitter region is deeper than the P-type base region under the N-type emitter region, forming a base deepening structure on both sides of the emitter to increase the path of carrier injection into the N-type emitter region and avoid emitter crowding phenomenon. The photoelectric sensing region and the base body are defined by one-time photoetching process.

[0028] The low-impedance conductive layer is electrically connected to the base body by a metal wire.

[0029] The P-type base region on both sides of the N-type emitter region is 0.5-1 μm deeper than the P-type base region under the N-type emitter region, and the P-type base region on both sides of the N-type emitter region has the same doping concentration as the base body.

[0030] The method comprises the following steps: Step 1: providing a semiconductor substrate, growing an N-type epitaxial layer on the semiconductor substrate; Step 2: forming an independent photoelectric sensing region on the N-type epitaxial layer by one-time photoetching process and ion implantation process, defining the patterns of the base and the emitter body by one-time photoetching, adjusting the doping concentration and depth of the two by two independent ion implantations (corresponding to the photoelectric sensing region, the base and the emitter body respectively), and not needing second-time photoetching; Step 3: depositing a low-impedance conductive layer on the upper part of the photoelectric sensing region, the low-impedance conductive layer being a polysilicon layer, an ITO layer or a transparent conductive layer, and the conductive layer on the upper part of the photoelectric sensing region being reserved by single-time photoetching patterning process after deposition, and the low-impedance conductive layer being electrically connected to the base body by a metal wire; Step 4: forming an N-type emitter region on the base body by one-time photoetching and two-time ion implantation, defining the patterns of the N-type emitter region and the deepened base regions on both sides by one-time photoetching, and realizing the formation of the N-type emitter region and the deepening of the base regions on both sides by two independent ion implantations (corresponding to the N-type emitter region and the deepened base regions on both sides respectively), and not needing second-time photoetching; Step 5: performing annealing treatment to activate the doping ions and form stable PN junction, and completing the manufacture of the photosensitive transistor.

[0031] In step 2, the ion implantation energy of the photoelectric sensing region is 120-180 keV, and the implantation dose is 5×10¹³-1×10¹ 4 cm⁻²; the ion implantation energy of the base body is 80-180 keV, and the implantation dose is 1×10¹ 4 -5×10¹ 4 cm⁻², and the difference between the depth and the concentration of the two is realized by different implantation parameters.

[0032] In step 4, the ion implantation energy of the N-type emitter region is 30-120 keV, and the implantation dose is 1×10¹ 5-5×10¹ 5 cm⁻²; the ion implantation energy in the base region is 80-180 keV, and the implantation dose is 5×10¹³-1×10¹³. 4 cm⁻², defining two regions through a single photolithography step, and then achieving the performance requirements of different regions through a second ion implantation step, balancing process efficiency and structural precision.

[0033] Example 1: Please see Figure 1 This embodiment provides a high CTR and high-speed phototransistor based on layout optimization, including a semiconductor substrate 1 (selected as an N-type silicon substrate with a resistivity of 1-10 Ω·cm), an N-type epitaxial layer 2 grown on the semiconductor substrate 1; an independently configured photoelectric sensing region 3 and a base body 4 are formed on the N-type epitaxial layer 2, both of which are P-type doped for efficiently receiving optical signals and generating charge carriers; and a PN junction is formed with the N-type emitter region 5 to ensure stable β value.

[0034] A low-impedance conductive layer 6 (ITO layer or other transparent conductive layer, thickness 100-1000nm, sheet resistance ≤10Ω / □) covers half of the area above the photoelectric sensing region 3. The low-impedance conductive layer 6 is electrically connected to the base body 4 through a metal wire 7 (aluminum wire, thickness 800-3000nm). Charge carriers are rapidly transported to the base body 4 through the ITO layer, significantly reducing the transmission impedance. The section depth of the base body 4 on both sides of the N-type emitter region 5 is 2.2μm, which is 0.7μm greater than the section depth of the base body 4 below the N-type emitter region 5 (1.5μm), increasing the charge carrier injection path and avoiding emitter congestion.

[0035] Example 2: Step 1: Chemical vapor deposition of an N-type epitaxial layer at 1100℃ and 80 Torr; Step 2: Boron ion implantation at 100keV to form the photoelectric sensing region, followed by diffusion oxidation at 950℃; Step 3: After shared photolithography, boron ions are implanted into the base at 150keV and arsenic ions are implanted into the emitter at 80keV, followed by co-diffusion at 900℃; Step 4: ITO layer and AlSiCu layer (2μm thickness) are sputtered, followed by alloying treatment at 480℃; Finished product inspection: The nodal depth of each region meets the standard (4μm for photoelectric, 1.8μm for base, and 0.8μm for emitter), the metal layer is undamaged, and the performance meets the design requirements.

[0036] In this application, unless otherwise clearly specified and limited, the terms "mounting", "connection", "connecting", "fixing" and the like should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection or communication with each other; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. Obviously, the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The preferred embodiments of the present application are shown in the drawings, but do not limit the patent scope of the present application. The present application can be realized in many different forms, and conversely, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features. Any equivalent structure made by using the content of the present application specification and drawings, directly or indirectly applied to other related technical fields, is also within the scope of the patent protection of the present application.

Claims

1. A high CTR and high speed phototransistor based on layout optimization, characterized in that, The semiconductor substrate comprises an N-type epitaxial layer, a P-type base region and an N-type emitter region formed in sequence on the semiconductor substrate; The P-type base region comprises an independent photoelectric sensing region and a base body, the photoelectric sensing region is used for receiving light signals and generating carriers, the base body forms a PN junction with the N-type emitter region, and the depth of the base body can be independently adjusted according to the design requirement of the beta value; The upper part of the photoelectric sensing region is covered by a low-impedance conductive layer, the low-impedance conductive layer is a metal layer, an ITO layer or a polysilicon layer, the low-impedance conductive layer is high-temperature resistant, is used for collecting the carriers generated by the photoelectric sensing region and transmitting the carriers to the base body; The depth of the P-type base region on both sides of the N-type emitter region is greater than the depth of the P-type base region below the N-type emitter region, forming an emitter two-side base deepening structure to increase the path of carrier injection into the N-type emitter region; and the circuit layout is optimized to avoid the emitter crowding phenomenon, that is, a plurality of windows are formed in the position corresponding to the emitter region and are in communication with the photoelectric sensing region, without the need for additional process flow adjustment. The photoelectric sensing region is defined by an independent photoetching process, the base body and the N-type emitter region are defined by one photoetching process, and the depth of the base body and the N-type emitter region is adjusted by two independent ion implantation processes, without the need for additional photoetching times.

2. The layout optimization based high CTR and high speed phototransistor of claim 1, wherein, The low-impedance conductive layer and the base body are electrically connected by a metal wire.

3. The layout optimization based high CTR and high speed phototransistor of claim 1, wherein, The depth of the P-type base region on both sides of the N-type emitter region is greater than the depth of the P-type base region below the N-type emitter region by 0.5-1 μm.

4. A manufacturing method of a high-CTR and high-speed photosensitive transistor based on layout optimization A manufacturing method of a high-CTR and high-speed photosensitive transistor based on layout optimization, characterized by comprising the following steps (combined with a standard process flow of a high-speed photoelectric transistor): Step 1: wafer pretreatment and N-type epitaxial layer preparation An N-type silicon substrate (resistivity 1-10 Ω·cm) is provided, wafer number marking is performed (made by an epitaxial wafer factory), and then a mask and silicon etching are performed on the Mark area (an optional step, selected according to the photoetching machine requirement of a foundry); An N-type epitaxial layer is grown by a chemical vapor deposition process, and the control parameters are as follows: temperature 1000-1300 ℃, silicon source (such as silane) and doping source (such as phosphine) are introduced, and a uniform N-type epitaxial layer structure is formed. Step 2: photoelectric sensing region formation First photoetching: glue coating-exposure-development, the photoelectric sensing region pattern is defined by a mask; Oxide layer etching: the field oxide layer corresponding to the photoelectric sensing region is etched, and the surface oxide layer is removed; Photoresist removal and cleaning: the photoresist is removed and the wafer surface is cleaned; Thin oxide layer preparation: a thin oxide layer is grown on the surface of the photoelectric sensing region; Photoelectric sensing region ion implantation: boron ions (B11) are implanted, the implantation energy is 80-180 keV, and a P-type photoelectric sensing region is formed; P+ diffusion and oxidation: the photoelectric sensing region is diffused and oxidized to stabilize the sensing region structure, and after the completion, subsequent processes are performed. Step 3: base body and N-type emitter region formation (base and emitter share photoetching, process optimization synergy) ​ Second photoetching: glue-coating-exposure-development, define the base body and N-type emitter region pattern together, no need to add photoetching step for base body; Oxide layer etching: etch the oxide layer of the base body and N-type emitter region; Photoresist removal and cleaning: remove photoresist and clean the wafer surface; Thin oxide layer preparation: grow thin oxide layer on the surface of base body and N-type emitter region; Base body ion implantation (patent required base implantation): implant boron ions (B11), implantation energy 80-180keV, adjust the base body depth through this parameter, meet the design requirement of β value; Base diffusion and oxidation (Option, depending on CTR and BV): diffusion and oxidation treatment for base body, further optimize the base depth and performance; N-type emitter region ion implantation: select doping source according to the requirement of emitter region, use phosphorus ions (P31) or arsenic ions (As75), implantation energy 30-120keV; form N-type emitter region; N+ diffusion and oxidation: common diffusion and oxidation treatment for base body and N-type emitter region, synchronize the structure of both, realize the process coordination of base and emitter. Step 4: low impedance conductive layer and metal wire preparation Contact hole preparation: third photoetching defines contact hole pattern, then oxide layer etching, punch through the low impedance conductive layer and base body electrical connection channel; Depositing low impedance conductive layer such as ITO layer (In2O3: SnO2=9:1) or other light-transmitting conductive material on the upper part of the photoelectric sensing area by magnetron sputtering process, deposition thickness 100-1000nm, ensure high temperature performance; this method must have one more photoetching. Or do not do this step, directly in this third photoetching, fourth photoetching use layout in photosensitive area with finger layout to add appropriate metal wire to guide photosensitive area signal to base area. Metal patterning: fourth photoetching defines metal wire pattern, then use dry etching process to etch metal layer, form metal wire connecting low impedance conductive layer and base body; Alloy treatment: in nitrogen protective atmosphere, at 350-480℃ temperature for appropriate time, enhance the contact stability of metal layer and semiconductor. Step 5: finished product detection Performance detection: after completing the photosensitive transistor manufacturing, enter the performance detection link, verify CTR, transmission speed and anti-emitter congestion performance, ensure that the product meets the design requirements.

5. The production method according to claim 4, wherein In step 2, ion implantation of photoelectric sensing area is separated from traditional base implantation process, realize 3-5μm depth through independent photoetching and implantation parameters (80-120keV), meet the photoelectric conversion efficiency requirement.

6. The production method according to claim 4, wherein In step 3, base body and N-type emitter region share one photoetching, realize independent adjustment of the depth of both through differentiated ion implantation parameters (base 80-180keV, emitter 30-120keV), consider process efficiency and structure accuracy.

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