An automatic impedance matcher and control method

Abstract

The application provides an automatic impedance matcher and a control method, and relates to the technical field of impedance matchers. Voltage signals and current signals output by a radio frequency power supply are obtained by a voltage sampling circuit and a current sampling circuit respectively, and are transmitted to a signal conditioning module. The signal conditioning module outputs active power digital signals, reactive power digital signals, current square digital signals and voltage square digital signals according to the signals. A control module calculates complex impedance representing a load by using the digital signals, and adjusts impedance matching according to the complex impedance. The control module can also detect whether the radio frequency power signal exists according to the voltage square digital signals, and the detection result is used as one of the judgment conditions for starting automatic impedance matching. The application can obtain relatively complete complex impedance information, and realize automatic impedance matching, so that a good balance between speed and reliability is achieved.

Description

Technical Field

[0001] This application relates to the field of impedance matching technology, and more specifically, to an automatic impedance matching device and its control method. Background Technology

[0002] Automatic impedance matching (AIM) circuits are key components in radio frequency (RF) power transfer systems, widely used in high-tech fields such as semiconductor processing, plasma cleaning, and RF heating. Their core function is to dynamically adjust the parameters of a matching network (typically composed of variable capacitors or inductors) to achieve conjugate matching between varying load impedance and a fixed source impedance (typically 50Ω), thereby maximizing power transmission, improving system stability, and ensuring the safety of power devices.

[0003] Existing automatic impedance matching technology mainly consists of two parts: detection circuitry and control algorithms. However, both of these current technical solutions have significant shortcomings, which restrict their large-scale application in industrial scenarios.

[0004] In terms of detection circuits, mainstream solutions can be divided into two types. The first is the traditional solution based on reflected power or VSWR detection. This solution uses directional couplers or dual-diode detector circuits to obtain the amplitude information of the forward and reflected power, and calculates the VSWR by their ratio. Although this solution is simple in structure and low in cost, its fundamental drawback is that it can only obtain the amplitude information of the signal and cannot detect its phase change at all. This means the system can only determine the "goodness" of the match (i.e., the magnitude of the reflection coefficient |Γ| or the magnitude of the voltage standing wave ratio (VSWR)), but cannot know the "direction of mismatch" (i.e., the specific location and nature of the load impedance on the Smith chart). Due to the lack of phase information, the system cannot intelligently determine whether the load is inductive or capacitive, nor can it know the magnitude of the resistive component, severely limiting the efficiency of the control algorithm. The second is the high-end solution based on directional couplers and quadrature demodulators. This solution can accurately obtain the amplitude and phase of the reflection coefficient, thereby directly calculating the complex impedance of the load, and is considered the "gold standard" of performance. However, its limitations lie in its high cost and system complexity. It requires high-performance directional couplers and expensive IQ demodulator chips, along with multiple high-precision analog-to-digital converters for synchronous sampling. Furthermore, its circuit design is complex, demanding extremely high precision in RF layout and routing, and typically requires sophisticated calibration algorithms to compensate for errors. This makes its power consumption, size, and cost difficult to meet the requirements of large-scale industrial applications.

[0005] In terms of control algorithms, existing technologies mostly employ local search strategies such as gradient descent. In "blind search" schemes lacking complete impedance information, the algorithm is forced to fix one variable and fine-tune another, gradually approaching the optimal solution by observing the gradual trend of the matching index. This method is not only slow in matching speed but also prone to getting trapped in local optima, leading to matching failures or lingering at near-optimal levels, resulting in poor system reliability and robustness.

[0006] In summary, existing technologies struggle to achieve a good balance between high speed and high reliability. Therefore, there is an urgent need in this field for an innovative technical solution capable of acquiring complete impedance information and employing intelligent and rapid control strategies to overcome the limitations of existing technologies.

[0007] There is currently no effective technical solution to the above problems. Summary of the Invention

[0008] The purpose of this application is to provide an automatic impedance matching device and control method, which aims to solve the key technical problems of existing automatic impedance matching technology in achieving a good balance between high speed and high reliability, and how to obtain complete complex impedance information (including amplitude and phase) in the detection circuit.

[0009] In a first aspect, this application provides an automatic impedance matching device for use in radio frequency power supplies, including: a voltage sampling circuit, a current sampling circuit, a signal conditioning module, and a control module;

[0010] The voltage sampling circuit is connected to the radio frequency power supply and is used to acquire the voltage signal output by the radio frequency power supply.

[0011] The current sampling circuit is connected to the radio frequency power supply and is used to collect the current signal output by the radio frequency power supply.

[0012] The voltage output terminal of the voltage sampling circuit and the current output terminal of the current sampling circuit are both connected to the signal conditioning module. The signal conditioning module is used to receive voltage and current signals and to output active power digital signals, reactive power digital signals, current square digital signals and voltage square digital signals based on the voltage and current signals.

[0013] The control module is connected to the signal conditioning module and is used to calculate the complex impedance representing the load based on the active power digital signal, reactive power digital signal and current square digital signal, and to perform impedance matching adjustment based on the complex impedance. The complex impedance refers to the total impedance including the matching device, transmission line and load device.

[0014] The control module is also used to detect the presence of the RF power signal based on the voltage squared digital signal, and as one of the criteria for determining whether to start automatic impedance matching.

[0015] This technical solution enables the application to obtain complete complex impedance information characterizing the load, including amplitude and phase, thereby overcoming the limitation of existing technologies that can only obtain amplitude information but cannot perceive phase changes. It also solves the problem that traditional solutions cannot determine the mismatch direction and provides a precise data basis for subsequent impedance matching adjustments, significantly improving the efficiency and reliability of matching.

[0016] Optionally, the signal conditioning module includes: a first multiplication circuit, a second multiplication circuit, a third multiplication circuit, a fourth multiplication circuit, and an ADC analog-to-digital conversion circuit;

[0017] The first multiplication circuit has two input terminals, which are connected to the voltage output terminal and the current output terminal respectively. The first multiplication circuit is used to output an active power analog signal.

[0018] The second multiplication circuit has two input terminals, which are connected to the voltage output terminal and the current output terminal respectively. The second multiplication circuit is used to output a reactive power analog signal.

[0019] The input terminal of the third multiplication circuit is connected to the current output terminal. The third multiplication circuit is used to output the analog signal of the squared current.

[0020] The input terminal of the fourth multiplication circuit is connected to the voltage output terminal. The fourth multiplication circuit is used to output an analog signal of the squared voltage.

[0021] The outputs of the first, second, third, and fourth multiplication circuits are all connected to the ADC analog-to-digital converter circuit through a filter circuit.

[0022] The ADC analog-to-digital converter circuit is used to convert analog signals of active power, reactive power, current square, and voltage square into digital signals of active power, reactive power, current square, and voltage square for output.

[0023] Through this technical solution, this application introduces multiple multiplication circuits and ADC analog-to-digital conversion circuits to achieve precise processing of voltage and current signals. It can simultaneously acquire analog signals of active power, reactive power, current square, and voltage square, and convert them into digital signals. This provides comprehensive and accurate raw data for the control module to calculate load impedance, further improving the accuracy and real-time performance of impedance detection.

[0024] Optionally, the first multiplication circuit includes: a first multiplier chip, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first capacitor;

[0025] One end of the first resistor is connected to the voltage output terminal, one end of the second resistor is grounded, and the other ends of both the first and second resistors are connected to the non-inverting input terminal of the X channel of the first multiplier chip.

[0026] One end of the third resistor is connected to the current output terminal, one end of the fourth resistor is grounded, and the other ends of both the third and fourth resistors are connected to the positive input terminal of the Y channel of the first multiplier chip.

[0027] The inverting input terminals of the X and Y channels of the first multiplier chip are both grounded. The positive power supply pin of the first multiplier chip is connected to the first positive power supply, and the negative power supply pin of the first multiplier chip is connected to the second negative power supply. The non-inverting input terminal of the Z channel of the first multiplier chip is grounded through the first capacitor. A voltage input terminal for inputting the first DC bias voltage is provided between the non-inverting input terminal of the Z channel of the first multiplier chip and the first capacitor. The output pin of the first multiplier chip is connected to the ADC analog-to-digital conversion circuit through a filter circuit.

[0028] Through this technical solution, this application achieves accurate multiplication of voltage and current signals by using a multiplier chip in conjunction with a resistor and capacitor network, thereby efficiently generating an active power analog signal. This provides a high-quality analog input for subsequent digital conversion and impedance calculation, ensuring the accuracy of active power measurement.

[0029] Optionally, the second multiplication circuit includes: a second multiplier chip, a first phase-shifting circuit, a second phase-shifting circuit, and a second capacitor;

[0030] The input terminal of the first phase shift circuit is connected to the voltage output terminal, and the output terminal of the first phase shift circuit is connected to the positive input terminal of the X channel of the second multiplier chip.

[0031] The input terminal of the second phase-shifting circuit is connected to the current output terminal, and the output terminal of the second phase-shifting circuit is connected to the positive input terminal of the Y channel of the second multiplier chip.

[0032] The first phase-shifting circuit and the second phase-shifting circuit are used to generate the first phase shift and the second phase shift, respectively, and the sum of the absolute values ​​of the first phase shift and the second phase shift is 90°;

[0033] The inverting input terminals of the X and Y channels of the second multiplier chip are both grounded. The positive power supply pin of the second multiplier chip is connected to the third positive power supply, and the negative power supply pin of the second multiplier chip is connected to the fourth negative power supply. The non-inverting input terminal of the Z channel of the second multiplier chip is grounded through the second capacitor. A voltage input terminal for inputting the second DC bias voltage is provided between the non-inverting input terminal of the Z channel of the second multiplier chip and the second capacitor. The output pin of the second multiplier chip is connected to the ADC analog-to-digital converter circuit through a filter circuit.

[0034] Through this technical solution, this application introduces a phase-shifting circuit and a multiplier chip to achieve precise 90-degree phase shifting and multiplication of voltage and current signals, thereby accurately obtaining the reactive power analog signal, providing key data for calculating the phase information of load impedance, and significantly improving the comprehensiveness and accuracy of impedance matching.

[0035] Optionally, the third multiplication circuit includes: a third multiplier chip and a fifth resistor;

[0036] One end of the fifth resistor is grounded, and the other end of the fifth resistor is connected to the current output terminal and the non-inverting input terminal of the X channel of the third multiplier chip. The non-inverting input terminal of the X channel of the third multiplier chip is connected to the non-inverting input terminal of the Y channel of the third multiplier chip. The inverting input terminals of the X channel and the Y channel of the third multiplier chip are both grounded. The non-inverting input terminal of the Z channel of the third multiplier chip is grounded. The positive power supply pin of the third multiplier chip is connected to the fifth positive power supply, and the negative power supply pin of the third multiplier chip is connected to the sixth negative power supply. The output pin of the third multiplier chip is connected to a filter circuit, which is connected to the ADC analog-to-digital conversion circuit through a first proportional reduction circuit.

[0037] Optionally, the fourth multiplication circuit includes: a fourth multiplier chip and a sixth resistor;

[0038] One end of the sixth resistor is grounded, and the other end is connected to the voltage output terminal and the non-inverting input terminal of the X channel of the fourth multiplier chip. The non-inverting input terminal of the X channel of the fourth multiplier chip is connected to the non-inverting input terminal of the Y channel of the fourth multiplier chip. The inverting input terminals of the X channel and Y channel of the fourth multiplier chip are both grounded. The non-inverting input terminal of the Z channel of the fourth multiplier chip is grounded. The positive power supply pin of the fourth multiplier chip is connected to the seventh positive power supply, and the negative power supply pin of the fourth multiplier chip is connected to the eighth negative power supply. The output pin of the fourth multiplier chip is connected to a filter circuit, which is connected to the ADC analog-to-digital converter circuit through a second scaling circuit.

[0039] Optionally, the current sampling circuit includes: a current transformer, a seventh resistor, an eighth resistor, a first bandpass filter circuit, and a current output terminal;

[0040] The first terminal of the output side of the current transformer is grounded through the seventh resistor. The first terminal of the output side of the current transformer is also connected to one end of the eighth resistor. The other end of the eighth resistor is connected to the current output terminal through the first bandpass filter circuit. The second terminal of the output side of the current transformer is grounded. The seventh and eighth resistors are sampling resistors.

[0041] Optionally, the first bandpass filter circuit includes: a first inductor, a second inductor, a third inductor, a fourth inductor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a seventh capacitor;

[0042] The first inductor, the fifth capacitor, the second inductor, and the current output terminal are connected in series. One end of the third inductor is grounded, and the other end of the third inductor is connected between the first inductor and the fifth capacitor.

[0043] One end of the third capacitor is grounded, and the other end of the third capacitor is connected between the first inductor and the fifth capacitor.

[0044] One end of the fourth capacitor is grounded, and the other end of the fourth capacitor is connected between the first inductor and the fifth capacitor.

[0045] One end of the fourth inductor is grounded, and the other end of the fourth inductor is connected between the second inductor and the current output terminal;

[0046] One end of the sixth capacitor is grounded, and the other end of the sixth capacitor is connected between the second inductor and the current output terminal.

[0047] One end of the seventh capacitor is grounded, and the other end of the seventh capacitor is connected between the second inductor and the current output terminal.

[0048] It also includes coupling capacitors integrated on the PCB board; the voltage sampling circuit includes: a ninth resistor, a tenth resistor, an eighth capacitor, a second bandpass filter circuit, and a voltage output terminal;

[0049] One end of the coupling capacitor integrated on the PCB is connected to one end of the tenth resistor. One end of the eighth capacitor is connected between the coupling capacitor and the tenth resistor, and the other end of the eighth capacitor is grounded. One end of the ninth resistor is connected between the coupling capacitor and the tenth resistor, and the other end of the ninth resistor is grounded. The other end of the tenth resistor is connected to the voltage output terminal through the second bandpass filter circuit.

[0050] Secondly, this application also provides a control method for an automatic impedance matching device, applied to an RF power supply. The control method for the automatic impedance matching device includes the following steps:

[0051] Initialize the system by loading a pre-stored impedance-capacitance mapping database and driving the two variable capacitors of the matching network to their initial positions. The impedance-capacitance mapping database includes the complex impedance characterizing the load and the two variable capacitor values ​​that best match the complex impedance.

[0052] The first target capacitance value is obtained by querying the pre-stored impedance-capacitance mapping database based on the complex impedance characterizing the load detected in real time by the automatic impedance matching device.

[0053] The complex impedance characterizing the load is detected in real time by the automatic impedance matching device, and the current capacitance values ​​of the two variable capacitors are recorded in real time by the control module. A new combination of capacitance values ​​is obtained by using the simulated annealing algorithm. The new combination of capacitance values ​​is then used to query the impedance-capacitance mapping database to obtain the corresponding complex impedance. The reflection coefficient is calculated based on the complex impedance as the target function value. After multiple iterations, the process ends when the preset termination condition is met. The combination of capacitance values ​​corresponding to the minimum target function value is taken as the second target capacitance value.

[0054] Compare the difference between the first target capacitance value and the second target capacitance value, and select the final target capacitance value according to a preset threshold.

[0055] Drive the two variable capacitors of the matching network to the final target capacitance value;

[0056] After a successful match, the current combination of complex impedance and capacitance values ​​is updated in the pre-stored impedance-capacitance mapping database.

[0057] This application achieves fast, accurate, and robust impedance matching control by combining impedance-capacitance mapping database lookup with simulated annealing algorithm optimization. This method not only quickly locates the initial matching point but also avoids local optima through iterative optimization, significantly improving matching speed and success rate. Furthermore, it dynamically updates the database after successful matching, further enhancing the system's adaptability and long-term stability.

[0058] As can be seen from the above, the automatic impedance matching device and control method provided in this application, by introducing a voltage sampling circuit, a current sampling circuit, a signal conditioning module, and a control module, achieves accurate detection and matching adjustment of the RF power supply load impedance. The voltage sampling circuit and the current sampling circuit acquire the load voltage and current signals, respectively, and transmit them to the signal conditioning module. The signal conditioning module outputs active power digital signals, reactive power digital signals, current square digital signals, and voltage square digital signals based on these signals. The control module then uses these digital signals to calculate the load impedance and performs impedance matching adjustment accordingly. Furthermore, the control module can also detect the presence of the RF power signal based on the voltage square digital signal, serving as one of the criteria for initiating automatic impedance matching. This application can obtain relatively complete impedance information at a lower cost and achieve automatic impedance matching, thus achieving a good balance between cost, speed, and reliability, effectively solving the technical deadlock of "high performance equals high cost" in the prior art.

[0059] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0060] Figure 1 The circuit diagram of the automatic impedance matching device provided in the embodiments of this application is shown.

[0061] Figure 2 A circuit diagram of the first multiplication circuit provided in the embodiments of this application.

[0062] Figure 3 A circuit diagram of the second multiplication circuit provided in an embodiment of this application.

[0063] Figure 4 A circuit diagram of the third multiplication circuit provided in the embodiments of this application.

[0064] Figure 5 A circuit diagram of the fourth multiplication circuit provided in an embodiment of this application.

[0065] Figure 6 A circuit diagram of the current sampling circuit provided in an embodiment of this application.

[0066] Figure 7 A circuit diagram of the voltage sampling circuit provided in an embodiment of this application.

[0067] Figure 8 A circuit diagram of the ADC analog-to-digital conversion circuit provided in the embodiments of this application.

[0068] Label Explanation: U6, First Multiplier Chip; R20, First Resistor; R21, Second Resistor; R11, Third Resistor; R12, Fourth Resistor; C50, First Capacitor; U1, Second Multiplier Chip; C49, Second Capacitor; U4, Third Multiplier Chip; R18, Fifth Resistor; U9, Fourth Multiplier Chip; R17, Sixth Resistor; T1, Current Transformer; R4, Seventh Resistor; R3, Eighth Resistor; IS, Current Output Terminal; L3, First Inductor; L6, Second Inductor; L2, Third Inductor; L7, Fourth Inductor; C8, Third Capacitor; C7, Fourth Capacitor; C6, Fifth Capacitor; C17, Sixth Capacitor; C16, Seventh Capacitor; R27, Ninth Resistor; R26, Tenth Resistor; C42, Eighth Capacitor; VS,

[0069] Voltage output terminal; L15, fifteenth inductor; L12, twelfth inductor; L14, fourteenth inductor; L13, thirteenth inductor; C39, thirty-ninth capacitor; C40, fortieth capacitor; C41, forty-first capacitor; C27, twenty-seventh capacitor; C29, twenty-ninth capacitor; 102, RC low-pass filter circuit; 103, ADC analog-to-digital converter circuit; 104, first scaling circuit; 105, second scaling circuit. Detailed Implementation

[0070] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0071] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0072] Please refer to Figure 1-8 , Figure 1 This is a circuit diagram of an automatic impedance matching device in some embodiments of this application. It aims to address the key technical problems of existing automatic impedance matching technologies in achieving a good balance between low cost, high speed, and high reliability, as well as how to obtain complete impedance information (including amplitude and phase) at a low cost in terms of the detection circuit.

[0073] In a first aspect, this application provides an automatic impedance matching device for use in radio frequency power supplies, comprising: a voltage sampling circuit, a current sampling circuit, a signal conditioning module, and a control module;

[0074] The voltage sampling circuit is connected to the radio frequency power supply and is used to acquire the voltage signal output by the radio frequency power supply.

[0075] The current sampling circuit is connected to the radio frequency power supply and is used to collect the current signal output by the radio frequency power supply.

[0076] The voltage output terminal VS of the voltage sampling circuit and the current output terminal IS of the current sampling circuit are both connected to the signal conditioning module. The signal conditioning module is used to receive voltage and current signals and to output active power digital signals, reactive power digital signals, current square digital signals and voltage square digital signals based on the voltage and current signals.

[0077] The control module is connected to the signal conditioning module and is used to calculate the complex impedance representing the load based on the active power digital signal, reactive power digital signal and current square digital signal, and to perform impedance matching adjustment based on the complex impedance. The complex impedance refers to the total impedance including the matching device, transmission line and load device.

[0078] The control module is also used to detect the presence of the RF power signal based on the voltage squared digital signal, and as one of the criteria for determining whether to start automatic impedance matching.

[0079] Radio frequency (RF) power supplies are devices capable of generating RF energy, typically used in applications such as driving plasma and RF heating. A load is a device or medium that receives RF energy; its impedance characteristics may vary with operating conditions. Impedance matching refers to adjusting the parameters of a matching network to achieve a conjugate match between the complex impedance and the source impedance of the RF power supply, maximizing power transfer efficiency. Voltage and current signals are the instantaneous voltage and current waveforms acquired from the output of the RF power supply. Active power digital signals, reactive power digital signals, current square digital signals, and voltage square digital signals are digital quantities obtained after processing by a signal conditioning module; they contain amplitude and phase information of the load impedance. Complex impedances typically consist of resistive and reactive components.

[0080] Specifically, the active power digital signal can be obtained by directly multiplying the voltage signal and the current signal and then averaging them; the reactive power digital signal can be obtained by multiplying the voltage signal and the current signal after a 90-degree phase shift and then averaging them; the current square digital signal can be obtained by multiplying the current signal by itself; and the voltage square digital signal can be obtained by multiplying the voltage signal by itself.

[0081] The control module can be a microcontroller (MCU), a digital signal processor (DSP), or a field-programmable gate array (FPGA). For example, based on the received active power digital signal P, reactive power digital signal Q, and current square digital signal I², the control module can calculate the resistive component R and the reactive component X of the complex impedance using the formulas R = P / I² and X = Q / I², thus obtaining the complex impedance Z = R + jX, where j is the imaginary unit. After obtaining the complex impedance, the control module will adjust the variable capacitor or inductor in the matching network according to the control method of the automatic impedance matching device of this application to achieve impedance matching.

[0082] The control module also detects the presence of an RF power signal based on the voltage squared digital signal, using this as one of the criteria for initiating automatic impedance matching. For example, the control module can set a threshold for the voltage squared digital signal. When the detected voltage squared digital signal is below this threshold, it indicates that the RF power signal may be absent or too low. In this case, the control module will pause or not initiate the automatic impedance matching process to avoid unnecessary matching adjustments when there is no valid signal, thereby improving system stability and reliability.

[0083] The automatic impedance matching device of this application acquires the voltage and current signals of the load through voltage sampling circuits and current sampling circuits, respectively. These analog signals are sent to a signal conditioning module. In the signal conditioning module, the voltage and current signals undergo a series of analog calculations and filtering processes, and are converted into active power analog signals, reactive power analog signals, current squared analog signals, and voltage squared analog signals. Subsequently, these analog signals are converted into corresponding digital signals by an analog-to-digital converter, namely active power digital signals, reactive power digital signals, current squared digital signals, and voltage squared digital signals. These digital signals are transmitted to the control module.

[0084] After receiving these digital signals, the control module first uses the voltage squared digital signal to detect the presence of the RF power signal. If the voltage squared digital signal is higher than a preset threshold, it indicates that the RF power signal is valid, and the control module will initiate an automatic impedance matching process. Next, the control module calculates the current complex impedance using a built-in algorithm based on the received active power, reactive power, and current squared digital signals. For example, the resistance R and reactance X of the complex impedance can be deduced using the relationships P = I²R and Q = I²X, thus obtaining complete complex impedance information. After calculating the complex impedance, the control module determines the matching network parameters (such as the values ​​of variable capacitors or inductors) that need adjustment according to a preset matching strategy, such as by searching a pre-stored impedance-capacitance mapping database or executing a simulated annealing algorithm. Finally, the control module drives the variable components in the matching network to adjust, achieving conjugate matching between the complex impedance and the source impedance of the RF power supply, thereby maximizing power transfer efficiency. The entire process is dynamic and real-time, adapting to changes in load impedance and ensuring the system is always in an optimal matching state.

[0085] The automatic impedance matching device of this application demonstrates significant innovation and advantages in solving existing technical problems. Traditional automatic impedance matching technologies struggle to achieve a good balance between low cost, high speed, and high reliability, especially in the detection circuit. How to obtain complete impedance information at a low cost is a critical technical problem that urgently needs to be solved. Existing solutions are either costly and complex, or they can only obtain signal amplitude information and cannot detect phase changes, resulting in limited control algorithm performance.

[0086] The core innovation of this application lies in directly acquiring the load's voltage and current signals through voltage and current sampling circuits, and then using a signal conditioning module to convert these signals into digital signals for active power, reactive power, current squares, and voltage squares. The control module calculates the load impedance based on these digital signals and performs impedance matching adjustment. Compared to the closest prior art, the advantages of this application are:

[0087] First, this application indirectly but accurately inverts the complete complex impedance characterizing the load by directly measuring voltage and current and calculating active and reactive power, thus obtaining the amplitude and phase information of the complex impedance. This overcomes the limitation of traditional schemes based on reflected power or VSWR detection, which can only obtain amplitude information. It enables the system to intelligently determine whether the load is inductive or capacitive, and the magnitude of the resistive component, thereby providing comprehensive impedance information for the control algorithm and significantly improving the efficiency and accuracy of the matching process.

[0088] Secondly, this application avoids the use of expensive directional couplers and IQ demodulator chips. The voltage / current transformer T1 and analog multiplier used in this solution are general-purpose, mature, and low-cost components. The circuits such as the multiplier are generally more tolerant of environmental temperature and noise factors than precision IQ demodulation circuits, which are extremely sensitive to phase noise, making them more suitable for harsh industrial environments. This significantly reduces the cost and complexity of the system, enabling high-performance impedance matching technology to be more widely applied in cost-sensitive industrial fields.

[0089] Furthermore, by employing digital signal processing, the control module of this application can perform intelligent and rapid control. After obtaining complete impedance information, the control algorithm no longer needs to perform a "blind search," but can adopt more efficient strategies, such as directly calculating the matching network parameters or using a pre-stored database for rapid searching, thereby significantly improving the matching speed and avoiding getting trapped in local optima, thus enhancing the reliability and robustness of the system.

[0090] Finally, the control module also uses the squared voltage digital signal to detect the presence of the RF power signal, and uses this as one of the criteria for initiating automatic impedance matching. This design avoids unnecessary matching adjustments when there is no valid signal, further improving the stability and reliability of the system.

[0091] In summary, the automatic impedance matching device of this application achieves a good balance between low cost, high speed and high reliability through innovative detection and control schemes, providing an efficient, economical and robust impedance matching solution for radio frequency power transmission systems, and has significant technological progress and practical value.

[0092] In some implementations, the signal conditioning module includes: a first multiplication circuit, a second multiplication circuit, a third multiplication circuit, a fourth multiplication circuit, and an ADC analog-to-digital conversion circuit 103;

[0093] The first multiplication circuit has two input terminals, which are connected to the voltage output terminal VS and the current output terminal IS respectively. The first multiplication circuit is used to output an active power analog signal.

[0094] The second multiplication circuit has two input terminals, which are connected to the voltage output terminal VS and the current output terminal IS respectively. The second multiplication circuit is used to output a reactive power analog signal.

[0095] The input terminal of the third multiplication circuit is connected to the current output terminal IS. The third multiplication circuit is used to output the analog signal of the squared current.

[0096] The input terminal of the fourth multiplication circuit is connected to the voltage output terminal VS. The fourth multiplication circuit is used to output an analog signal of the squared voltage.

[0097] The outputs of the first, second, third, and fourth multiplication circuits are all connected to the ADC analog-to-digital converter circuit 103 through a filter circuit.

[0098] The ADC analog-to-digital converter circuit 103 is used to convert active power analog signals, reactive power analog signals, current square analog signals and voltage square analog signals into active power digital signals, reactive power digital signals, current square digital signals and voltage square digital signals for output.

[0099] Among them, the ADC analog-to-digital conversion circuit 103 is existing technology, such as... Figure 8 As shown, without going into specific details here, the ADC analog-to-digital conversion circuit 103 includes an analog-to-digital converter (ADC) chip, the chip model of which includes but is not limited to AD7190, ADS1256 or ADS7841EB / 2K5.

[0100] The solution in this application achieves precise processing of voltage and current signals by refining the signal conditioning module into multiple dedicated multiplication circuits and an ADC analog-to-digital converter circuit 103. Specifically, the first and second multiplication circuits are responsible for calculating the analog values ​​of active and reactive power in real time, respectively, while the third and fourth multiplication circuits calculate the analog values ​​of the square of the current and the square of the voltage, respectively. Before entering the ADC analog-to-digital converter circuit 103, these analog signals are processed by a filtering circuit (e.g., an RC low-pass filter circuit 102 to filter out high-frequency noise), thereby effectively suppressing any noise and harmonic interference and ensuring signal purity. Subsequently, the ADC analog-to-digital converter circuit 103 (e.g., using a 12-bit or 16-bit ADC chip to ensure conversion accuracy) converts these high-quality analog signals into digital signals, providing accurate input data for the control module. As a result, the control module can more accurately calculate the load impedance and perform corresponding impedance matching adjustments based on these precise digital signals, while also more reliably detecting the presence of RF power signals.

[0101] Through the above technical solution, the signal conditioning module can extract the power, current, and voltage information of the load more accurately. Specifically, by setting up a dedicated multiplication circuit to calculate the analog signals of active power, reactive power, current square, and voltage square, and combining this with a filtering circuit to preprocess the signals, the influence of noise and harmonics on the measurement results is effectively reduced, significantly improving the signal quality and accuracy. Subsequently, the ADC analog-to-digital converter circuit 103 converts these high-quality analog signals into digital signals, providing a more reliable data foundation for the control module. This refined signal conditioning method not only improves the accuracy and reliability of automatic impedance matching, but also reduces the stringent requirements on the performance of the ADC analog-to-digital converter circuit 103 by performing preliminary processing in the analog domain, thereby helping to reduce the design complexity and cost of the entire system.

[0102] In some implementations, the first multiplication circuit includes: a first multiplier chip U6, a first resistor R20, a second resistor R21, a third resistor R11, a fourth resistor R12, and a first capacitor C50.

[0103] One end of the first resistor R20 is connected to the voltage output terminal VS, one end of the second resistor R21 is grounded, and the other ends of both the first resistor R20 and the second resistor R21 are connected to the non-inverting input terminal of the X channel of the first multiplier chip U6.

[0104] One end of the third resistor R11 is connected to the current output terminal IS, one end of the fourth resistor R12 is grounded, and the other ends of the third resistor R11 and the fourth resistor R12 are both connected to the positive input terminal of the Y channel of the first multiplier chip U6.

[0105] The inverting input terminals of the X and Y channels of the first multiplier chip U6 are both grounded, and the positive power supply pin of the first multiplier chip U6 is connected to the first positive power supply. Figure 2 In the +VS3 pin, the negative power supply pin of the first multiplier chip U6 is connected to the second negative power supply ( Figure 2 In the first multiplier chip U6 (-VS3), the non-inverting input terminal of the Z channel of the first multiplier chip U6 is grounded through the first capacitor C50. A voltage input terminal for inputting the first DC bias voltage is provided between the non-inverting input terminal of the Z channel of the first multiplier chip U6 and the first capacitor C50. The output pin of the first multiplier chip U6 is connected to the ADC analog-to-digital conversion circuit 103 through a filter circuit.

[0106] Specifically, such as Figure 2As shown, the first multiplier chip U6 is an AD835 chip, which serves as the core multiplication unit to perform the product operation of voltage and current signals. The first resistor R20 and the second resistor R21 form a voltage divider network to divide the voltage signal from the voltage output terminal VS, adjusting its amplitude to match the non-inverting input of the X channel of the first multiplier chip U6. Similarly, the third resistor R11 and the fourth resistor R12 form another voltage divider network to divide the current signal from the current output terminal IS and input it to the non-inverting input of the Y channel of the first multiplier chip U6. This voltage divider design aims to ensure that the amplitude of the input signal is within the effective operating range of the multiplier chip, while also helping to suppress some noise.

[0107] In this design, the inverting input terminals of both the X and Y channels of the first multiplier chip U6 are grounded. This is to provide a stable reference potential, effectively suppress common-mode noise and interference, and improve the purity of signal processing. The positive power supply pin of the first multiplier chip U6 is connected to a first positive power supply, and the negative power supply pin is connected to a second negative power supply to ensure normal power supply to the chip.

[0108] In practical applications, the non-inverting input terminal of the Z channel of the first multiplier chip U6 is grounded through a first capacitor C50. This first capacitor C50 is used to filter out high-frequency noise on the Z channel, improving the signal-to-noise ratio. Between the non-inverting input terminal of the Z channel of the first multiplier chip U6 and the first capacitor C50, a voltage input terminal is provided for inputting a first DC bias voltage. This first DC bias voltage is used to adjust the output range and zero-point drift of the multiplier chip, ensuring that the output active power analog signal has good linearity and accuracy. Finally, the output pin of the first multiplier chip U6 is connected to the ADC analog-to-digital converter circuit 103 through a filter circuit. This filter circuit further smooths the output signal, filters out residual noise, and provides a high-quality analog signal for subsequent analog-to-digital conversion.

[0109] This application's solution effectively solves the problem of traditional multiplication circuits being susceptible to noise, interference, and DC drift when processing radio frequency signals by introducing a resistor divider network, a DC bias voltage, and a multi-stage filtering mechanism. Specifically, the voltage divider network composed of the first resistor R20, the second resistor R21, the third resistor R11, and the fourth resistor R12 can adjust the amplitude of the voltage and current signals to the ideal input range of the first multiplier chip U6, avoiding signal overload or underload, thereby ensuring the accuracy of the multiplication operation. Simultaneously, the inverting input terminals of the X and Y channels of the first multiplier chip U6 are grounded, effectively suppressing common-mode noise and improving the signal's anti-interference capability. Furthermore, filtering the Z channel through the first capacitor C50 and introducing the first DC bias voltage can precisely adjust the output characteristics of the multiplier chip, compensate for DC drift, and ensure the zero-point stability and linearity of the output active power analog signal. Finally, the filtering circuit at the output pin further purifies the signal, providing a clean analog signal to the ADC analog-to-digital conversion circuit 103, thereby ensuring the accuracy of subsequent digital signal processing.

[0110] In some implementations, the second multiplier circuit includes: a second multiplier chip U1, a first phase shifting circuit, a second phase shifting circuit, and a second capacitor C49;

[0111] The input terminal of the first phase shift circuit is connected to the voltage output terminal VS, and the output terminal of the first phase shift circuit is connected to the positive input terminal of the X channel of the second multiplier chip U1.

[0112] The input terminal of the second phase shift circuit is connected to the current output terminal IS, and the output terminal of the second phase shift circuit is connected to the positive input terminal of the Y channel of the second multiplier chip U1.

[0113] The first phase-shifting circuit and the second phase-shifting circuit are used to generate the first phase shift and the second phase shift, respectively, and the sum of the absolute values ​​of the first phase shift and the second phase shift is 90°;

[0114] The inverting input terminals of the X and Y channels of the second multiplier chip U1 are both grounded, and the positive power supply pin of the second multiplier chip U1 is connected to the third positive power supply. Figure 3 In the +VS2 pin, the negative power supply pin of the second multiplier chip U1 is connected to the fourth negative power supply ( Figure 3 In the second multiplier chip U1 (-VS2), the non-inverting input terminal of the Z channel is grounded through the second capacitor C49. A voltage input terminal for inputting the second DC bias voltage is provided between the non-inverting input terminal of the Z channel of the second multiplier chip U1 and the second capacitor C49. The output pin of the second multiplier chip U1 is connected to the ADC analog-to-digital conversion circuit 103 through a filter circuit.

[0115] Specifically, such as Figure 3As shown, the second multiplier chip U1 can be understood as an analog multiplier, such as using an AD835 chip, which can perform multiplication operations on two input signals and output the result. The first and second phase-shifting circuits are used to adjust the phase of the input signals, aiming to precisely control the phase relationship between the voltage and current signals before they enter the second multiplier chip U1. The sum of the absolute values ​​of the first and second phase shifts is set to 90° to ensure a specific phase difference between the voltage and current signals during multiplication, thus accurately reflecting reactive power. The voltage output terminal VS and the current output terminal IS refer to the load voltage and current signals output by the voltage sampling circuit and the current sampling circuit, respectively. The non-inverting input terminals of the X and Y channels of the second multiplier chip U1 are the ports for receiving input signals, while the inverting input terminals of the X and Y channels are grounded to provide a stable reference potential. The third positive power supply and the fourth negative power supply provide the power required for the normal operation of the second multiplier chip U1. The non-inverting input of the Z channel of the second multiplier chip U1 is grounded through the second capacitor C49 to provide a stable AC reference point. Simultaneously, a voltage input terminal for inputting a second DC bias voltage is provided between the non-inverting input of the Z channel and the second capacitor C49. This is to adjust the chip's output bias and dynamic range to optimize measurement accuracy and stability. Finally, the output pin of the second multiplier chip U1 is connected to the ADC analog-to-digital converter circuit 103 through a filter circuit to filter the analog signal and convert it into a digital signal for use by subsequent control modules.

[0116] The solution in this application achieves precise phase adjustment of the voltage and current signals by introducing a first phase-shifting circuit and a second phase-shifting circuit before they are input to the second multiplier chip U1. Specifically, the first phase-shifting circuit shifts the voltage signal to produce a first phase shift; the second phase-shifting circuit shifts the current signal to produce a second phase shift. Since the formula for calculating reactive power typically involves voltage, current, and the sine value of the phase difference between them, by precisely adjusting the phase difference between the voltage and current signals to 90°, the output signal of the second multiplier chip U1 can directly and accurately reflect the reactive power of the load during multiplication. Furthermore, the Z-channel non-inverting input terminal of the second multiplier chip U1 is grounded through a fourth capacitor C7 and a second DC bias voltage is set. This facilitates fine adjustment of the chip's output, ensuring a stable and high-precision reactive power analog signal output under different operating conditions. Therefore, this solution effectively solves the problem of insufficient accuracy when traditional multipliers directly calculate reactive power.

[0117] In some preferred embodiments, a specific example is given below. Assume the RF power supply operates at a frequency of 13.56MHz. The voltage signal output by the voltage sampling circuit is V(t) = Vm * sin(ωt + φv), where Vm is the peak amplitude of the voltage signal, ω is the angular frequency, and φv is the initial phase of the voltage signal. The current signal output by the current sampling circuit is I(t) = Im * sin(ωt + φi), where Im is the peak amplitude of the current signal, and φi is the initial phase of the current signal. To accurately measure reactive power, the phase difference between the voltage and current signals needs to be adjusted to 90°.

[0118] Specifically, the first phase-shifting circuit can be designed as an RC phase-shifting network or an all-pass filter to phase-shift the voltage signal V(t), making its output signal V'(t) = Vm * sin(ωt + φv + θ1). Similarly, the second phase-shifting circuit can be designed as an RC phase-shifting network or an all-pass filter to phase-shift the current signal I(t), making its output signal I'(t) = Im * sin(ωt + φi + θ2). Here, θ1 is the first phase shift, θ2 is the second phase shift, and |θ1| + |θ2| = 90°.

[0119] The phase-shifted V'(t) and I'(t) signals are input to the X and Y channels of the second multiplier chip U1 (e.g., AD835 chip). The second multiplier chip U1 performs a multiplication operation on these two signals, and the DC component of its output signal, after filtering, will be proportional to V'I'sin(Δφ), where Δφ is the phase difference between the current signal and the voltage signal. By adjusting the phase shift so that the signals entering the multiplier are 90° out of phase with the original voltage and current signals, the DC component of the multiplier output will be proportional to the reactive power Q.

[0120] Furthermore, the non-inverting input terminal of the Z channel of the second multiplier chip U1 is grounded through the fourth capacitor C7, and a second DC bias voltage, for example, 1.024V, is set to ensure that the chip operates in the optimal linear operating region and to provide a stable output reference point, thereby further improving the measurement accuracy and stability of the reactive power analog signal. Finally, after passing through the filtering circuit, the analog signal is converted into a digital signal by the ADC analog-to-digital converter circuit 103, which is then used by the control module for subsequent impedance calculation and matching adjustment.

[0121] In some implementations, the third multiplication circuit includes: a third multiplier chip U4 and a fifth resistor R18;

[0122] One end of the fifth resistor R18 is grounded, and the other end of the fifth resistor R18 is connected to the current output terminal IS and the non-inverting input terminal of the X channel of the third multiplier chip U4. The non-inverting input terminal of the X channel of the third multiplier chip U4 is connected to the non-inverting input terminal of the Y channel of the third multiplier chip U4. The inverting input terminals of the X channel and the Y channel of the third multiplier chip U4 are both grounded. The non-inverting input terminal of the Z channel of the third multiplier chip U4 is grounded. The positive power supply pin of the third multiplier chip U4 is connected to the fifth positive power supply (…). Figure 4 In the +VS1 pin, the negative power supply pin of the third multiplier chip U4 is connected to the sixth negative power supply ( Figure 4 In the -VS1), the output pin of the third multiplier chip U4 is connected to a filter circuit, which is connected to the ADC analog-to-digital converter circuit 103 through a first scaling circuit 104.

[0123] Specifically, such as Figure 4 As shown, the third multiplier chip U4 in the third multiplication circuit can be an AD835 chip, which has good high-frequency characteristics and linearity, making it suitable for radio frequency signal processing. The fifth resistor R18 is used to introduce the current signal output from the current output terminal IS into the non-inverting input terminals of the X and Y channels of the third multiplier chip U4, thereby realizing the squaring operation of the current signal. The inverting input terminals of the X and Y channels of the third multiplier chip U4 are both grounded, and the non-inverting input terminal of the Z channel is also grounded to ensure that the multiplier operates in a specific mode. The positive power supply pin of the third multiplier chip U4 is connected to the fifth positive power supply, and the negative power supply pin is connected to the sixth negative power supply, providing the power required for its normal operation.

[0124] The filter circuit can be a low-pass filter, such as an RC filter composed of resistors and capacitors, or an LC filter composed of inductors and capacitors. Its cutoff frequency is designed to effectively filter out the radio frequency carrier and its harmonics, while retaining the current square information of the baseband.

[0125] Furthermore, the output of the filter circuit is connected to the ADC analog-to-digital converter circuit 103 via a first scaling factor circuit 104. The scaling factor circuit attenuates the amplitude of the filtered current squared analog signal, adjusting its amplitude to within the input range of the ADC analog-to-digital converter circuit 103. For example, this scaling factor circuit can be constructed from a precision resistor voltage divider network; by appropriately selecting the resistor values, a precise signal amplitude reduction ratio can be achieved. Its purpose is to avoid signal overload and ensure that the ADC analog-to-digital converter circuit 103 can perform high-precision conversion within its optimal operating range.

[0126] Through the above technical solution, this application can effectively avoid the analog signal of the current squared output by the third multiplication circuit from exceeding the input range of the ADC analog-to-digital conversion circuit 103 due to excessive amplitude, thereby significantly improving the accuracy and reliability of analog-to-digital conversion.

[0127] In some implementations, the fourth multiplication circuit includes: a fourth multiplier chip U9 and a sixth resistor R17;

[0128] One end of the sixth resistor R17 is grounded, and the other end of the sixth resistor R17 is connected to the voltage output terminal VS and the non-inverting input terminal of the X channel of the fourth multiplier chip U9. The non-inverting input terminal of the X channel of the fourth multiplier chip U9 is connected to the non-inverting input terminal of the Y channel of the fourth multiplier chip U9. The inverting input terminals of the X channel and the Y channel of the fourth multiplier chip U9 are both grounded. The non-inverting input terminal of the Z channel of the fourth multiplier chip U9 is grounded. The positive power supply pin of the fourth multiplier chip U9 is connected to the seventh positive power supply. Figure 5 In the +VS4 section, the negative power supply pin of the fourth multiplier chip U9 is connected to the eighth negative power supply ( Figure 5 In the -VS4), the output pin of the fourth multiplier chip U9 is connected to a filter circuit, which is connected to the ADC analog-to-digital converter circuit 103 through a second scaling circuit 105.

[0129] The solution in this application introduces a filter circuit and a scaling circuit at the output of the fourth multiplication circuit, such as... Figure 5 As shown, this effectively solves the problem of distortion or damage to the ADC analog-to-digital converter circuit 103 caused by excessively large amplitude of the voltage squared analog signal. Specifically, after the fourth multiplier chip U9 outputs the voltage squared analog signal, the signal is first sent to the filter circuit. The filter circuit, through its inherent frequency selectivity, suppresses high-frequency noise components in the signal, thereby improving signal quality. Subsequently, the filtered voltage squared analog signal is sent to the scaling circuit. The scaling circuit reduces the signal amplitude to an acceptable input range for the ADC analog-to-digital converter circuit 103 according to a preset attenuation ratio. It is precisely due to the synergistic effect of the filter circuit and the second scaling circuit 105 that the voltage squared analog signal is optimized before entering the ADC analog-to-digital converter circuit 103, thereby ensuring the accuracy and reliability of subsequent digital conversion.

[0130] Through the above technical solution, this application can effectively avoid potential damage or signal distortion to the ADC analog-to-digital converter circuit 103 caused by excessively large voltage square analog signal amplitude. Compared with the solution of directly inputting the voltage square analog signal into the ADC analog-to-digital converter circuit 103, this application significantly improves the signal-to-noise ratio by adding a filtering circuit, making the voltage square digital signal purer; at the same time, by introducing a scaling circuit, the signal amplitude is accurately adjusted to the range of the ADC analog-to-digital converter circuit 103, thereby ensuring the normal operation of the ADC analog-to-digital converter circuit 103 and the accuracy of the output data. As a result, the control module can detect the presence of the RF power signal based on a more accurate voltage square digital signal, thereby improving the judgment accuracy of automatic impedance matching and the overall system reliability, providing a strong guarantee for the stable operation of the RF power supply.

[0131] In some preferred embodiments, the fourth multiplier chip U9 can be the Analog Devices AD835 chip, which has good high-frequency characteristics and linearity and is suitable for radio frequency signal processing.

[0132] In some implementations, the current sampling circuit includes: a current transformer T1, a seventh resistor R4, an eighth resistor R3, a first bandpass filter circuit, and a current output terminal IS;

[0133] The first terminal on the output side of current transformer T1 ( Figure 6 W2) is grounded through the seventh resistor R4. The first terminal of the output side of the current transformer T1 is also connected to one end of the eighth resistor R3. The other end of the eighth resistor R3 is connected to the current output terminal IS through the first bandpass filter circuit. The second terminal of the output side of the current transformer T1 ( Figure 6 W1) is grounded, and the seventh resistor R4 and the eighth resistor R3 are sampling resistors.

[0134] Specifically, such as Figure 6 As shown, current transformer T1 is used to sense the current signal of the radio frequency power supply. Its working principle is to use electromagnetic induction to proportionally convert the large current in the main circuit into a small current in the secondary coil, thereby realizing non-contact sampling of the current and providing electrical isolation to improve the safety of the system.

[0135] Among them, the seventh resistor R4 and the eighth resistor R3 are configured as sampling resistors. One end of the seventh resistor R4 is grounded, providing a venting path for the first terminal of the output side of the current transformer T1, effectively preventing the current transformer T1 from outputting excessively high voltage and protecting subsequent circuits. The eighth resistor R3 is used to convert the current signal output from the secondary coil of the current transformer T1 into a voltage signal for processing by the signal conditioning module. Through the cooperation of these two resistors, accurate sampling and voltage conversion of the current signal can be achieved.

[0136] In practical applications, the first bandpass filter circuit is connected between the eighth resistor R3 and the current output terminal IS. The main function of this filter circuit is to filter out any noise and harmonic components that may exist in the current signal, retaining only the current signal within the target frequency range. This ensures that the current signal output to the signal conditioning module has high purity and accuracy, thereby improving the reliability of subsequent impedance calculations.

[0137] The proposed solution achieves electrical isolation from the main circuit through a current transformer T1, sensing the current signal from the RF power supply. The sensed current signal is converted into a voltage signal through a sampling network composed of a seventh resistor R4 and an eighth resistor R3. Specifically, the seventh resistor R4 is grounded to limit the secondary voltage of the transformer, while the eighth resistor R3 converts the current output by the transformer into a measurable voltage. This voltage signal is then fed into a first bandpass filter circuit, which effectively filters out common broadband noise and harmonic interference in the RF environment, ensuring that only the current signal component at the target frequency is extracted and ultimately provided to the signal conditioning module through the current output terminal IS. This design ensures the accuracy, stability, and safety of the current sampling, providing reliable input data for subsequent impedance calculation and matching adjustment.

[0138] In some implementations, the first bandpass filter circuit includes: a first inductor L3, a second inductor L6, a third inductor L2, a fourth inductor L7, a third capacitor C8, a fourth capacitor C7, a fifth capacitor C6, a sixth capacitor C17, and a seventh capacitor C16.

[0139] The first inductor L3, the fifth capacitor C6, the second inductor L6 and the current output terminal IS are connected in series in sequence. One end of the third inductor L2 is grounded, and the other end of the third inductor L2 is connected between the first inductor L3 and the fifth capacitor C6.

[0140] One end of the third capacitor C8 is grounded, and the other end of the third capacitor C8 is connected between the first inductor L3 and the fifth capacitor C6.

[0141] One end of the fourth capacitor C7 is grounded, and the other end of the fourth capacitor C7 is connected between the first inductor L3 and the fifth capacitor C6.

[0142] One end of the fourth inductor L7 is grounded, and the other end of the fourth inductor L7 is connected between the second inductor L6 and the current output terminal IS.

[0143] One end of the sixth capacitor C17 is grounded, and the other end of the sixth capacitor C17 is connected between the second inductor L6 and the current output terminal IS.

[0144] One end of the seventh capacitor C16 is grounded, and the other end of the seventh capacitor C16 is connected between the second inductor L6 and the current output terminal IS.

[0145] In this circuit, inductors L3, L6, L2, and L7 are all inductors, functioning to provide impedance to signals of specific frequencies, thus achieving filtering. Capacitors C8, C7, C6, C17, and C16 are all capacitors, functioning to provide capacitive reactance to signals of specific frequencies. Together with the inductors, they form a resonant circuit to achieve frequency selection or filtering of the signal. The current output terminal IS refers to the output interface of the filtered current signal, used to transmit the high-quality current signal to the signal conditioning module.

[0146] In some implementations, a coupling capacitor integrated on the PCB board is also included; the voltage sampling circuit includes: a ninth resistor R27, a tenth resistor R26, an eighth capacitor C42, a second bandpass filter circuit, and a voltage output terminal VS;

[0147] One end of the coupling capacitor integrated on the PCB board ( Figure 7 One end of the coupling capacitor C42 is connected to one end of the tenth resistor R26, and the other end of the coupling capacitor C42 is connected between the coupling capacitor and the tenth resistor R26. The other end of the eighth capacitor C42 is grounded. One end of the ninth resistor R27 is connected between the coupling capacitor and the tenth resistor R26, and the other end of the ninth resistor R27 is grounded. The other end of the tenth resistor R26 is connected to the voltage output terminal VS through the second bandpass filter circuit.

[0148] The coupling capacitor integrated on the PCB board, together with the eighth capacitor C42, forms a voltage divider network. This network attenuates the higher voltage signal output from the RF power supply to a level suitable for subsequent circuit processing. Simultaneously, the capacitor's DC blocking and AC passing characteristics effectively isolate the DC component. The placement of the ninth resistor R27 and the tenth resistor R26 ensures a good match between the input impedance of the voltage sampling circuit and the output impedance of the RF power supply, thereby minimizing signal reflection loss during transmission and ensuring the integrity of the voltage signal. Furthermore, the second bandpass filter circuit is configured to accurately filter out various high-frequency noise and spurious signals that may be present in the voltage signal, ensuring that only a clean voltage signal within the target frequency range is sent to the voltage output terminal VS. It is due to these synergistic effects that the voltage sampling circuit of this application can provide a more accurate and stable voltage signal, laying a solid foundation for subsequent impedance matching calculations.

[0149] Through the above technical solution, the automatic impedance matching device of this application can significantly improve the signal-to-noise ratio of voltage sampling and effectively suppress interference generated by other components on the PCB board, thereby ensuring the accuracy of the voltage signal. As a result, the matching accuracy and stability of the automatic impedance matching device are significantly improved, enabling the RF power supply to operate more efficiently and stably. This improvement not only optimizes the performance of impedance matching but also extends the lifespan of RF equipment and reduces the risk of system failure, demonstrating significant practical value and technological advancement.

[0150] In some implementations, the second bandpass filter circuit includes: the fifteenth inductor L15, the twelfth inductor L12, the fourteenth inductor L14, the thirteenth inductor L13, the thirty-ninth capacitor C39, the fortieth capacitor C40, the forty-first capacitor C41, the twenty-seventh capacitor C27, and the twenty-ninth capacitor C29.

[0151] The fifteenth inductor L15, the thirty-ninth capacitor C39, the twelfth inductor L12 and the voltage output terminal VS are connected in series. One end of the fourteenth inductor L14 is grounded, and the other end of the fourteenth inductor L14 is connected between the fifteenth inductor L15 and the thirty-ninth capacitor C39.

[0152] One end of the fortieth capacitor C40 is grounded, and the other end of the fortieth capacitor C40 is connected between the fifteenth inductor L15 and the thirty-ninth capacitor C39.

[0153] One end of the forty-first capacitor C41 is grounded, and the other end of the forty-first capacitor C41 is connected between the fifteenth inductor L15 and the thirty-ninth capacitor C39.

[0154] One end of the thirteenth inductor L13 is grounded, and the other end of the thirteenth inductor L13 is connected between the twelfth inductor L12 and the voltage output terminal VS.

[0155] One end of the twenty-seventh capacitor C27 is grounded, and the other end of the twenty-seventh capacitor C27 is connected between the twelfth inductor L12 and the voltage output terminal VS.

[0156] One end of the 29th capacitor C29 is grounded, and the other end of the 29th capacitor C29 is connected between the 12th inductor L12 and the voltage output terminal VS.

[0157] Among them, the fifteenth inductor L15, the twelfth inductor L12, the fourteenth inductor L14, and the thirteenth inductor L13 are all inductor components, whose function is to generate impedance to signals of specific frequencies, thereby achieving the filtering function. The thirty-ninth capacitor C39, the fortieth capacitor C40, the forty-first capacitor C41, the twenty-seventh capacitor C27, and the twenty-ninth capacitor C29 are all capacitor components, whose function is to generate capacitive reactance to signals of specific frequencies, forming a resonant circuit with the inductors to achieve frequency selection or filtering of the signal. The voltage output terminal VS refers to the output interface of the filtered voltage signal, used to transmit the high-quality voltage signal to the signal conditioning module.

[0158] Secondly, this application also provides a control method for an automatic impedance matching device, applied to an RF power supply. The control method for the automatic impedance matching device includes the following steps:

[0159] Initialize the system by loading a pre-stored impedance-capacitance mapping database and driving the two variable capacitors of the matching network to their initial positions. The impedance-capacitance mapping database includes the complex impedance characterizing the load and the two variable capacitor values ​​that best match the complex impedance.

[0160] The first target capacitance value is obtained by querying the pre-stored impedance-capacitance mapping database based on the complex impedance characterizing the load detected in real time by the automatic impedance matching device.

[0161] The complex impedance characterizing the load is detected in real time by the automatic impedance matching device, and the current capacitance values ​​of the two variable capacitors are recorded in real time by the control module. A new combination of capacitance values ​​is obtained by using the simulated annealing algorithm. The new combination of capacitance values ​​is then used to query the impedance-capacitance mapping database to obtain the corresponding complex impedance. The reflection coefficient is calculated based on the complex impedance as the target function value. After multiple iterations, the process ends when the preset termination condition is met. The combination of capacitance values ​​corresponding to the minimum target function value is taken as the second target capacitance value.

[0162] During the iteration process, the current solution is first randomly perturbed to generate new candidate capacitor combinations. Then, by looking up the impedance-capacitance mapping database in reverse, the theoretical reflection coefficient corresponding to the combination is calculated as the objective function value (e.g., Γ=(ZL-Z0) / (ZL+Z0) is a complex number operation, where Γ is the reflection coefficient, ZL is the impedance, and Z0 is the characteristic impedance of the transmission line (a real number, e.g., 50Ω)) to evaluate the quality of the solution. Its core Metropolis acceptance criterion allows the algorithm to accept a candidate solution that is worse than the current solution with a certain probability. The acceptance probability is determined by the difference in the objective function (ΔE) and the current temperature (T), and the formula is P=exp(-ΔE / T), where P is the acceptance probability and ΔE is the difference in the objective function value between the new candidate solution and the current solution. ΔE=|Γ_new|-|Γ_current|, where Γ_new is the reflection coefficient of the new candidate solution and Γ_current is the reflection coefficient of the current solution. If the difference in the objective function (ΔE) is less than zero, it means that the reflection coefficient of the new solution is smaller and it is a better solution; otherwise, it is a worse solution. After multiple iterations, the algorithm ends when a preset termination condition is met (e.g., when the reflection coefficient is less than 0.05), and the combination of capacitance values ​​corresponding to the minimum objective function value is taken as the second target capacitance value.

[0163] Compare the difference between the first target capacitance value and the second target capacitance value, and select the final target capacitance value according to a preset threshold.

[0164] Drive the two variable capacitors of the matching network to the final target capacitance value;

[0165] After a successful match, the current combination of complex impedance and capacitance values ​​is updated in the pre-stored impedance-capacitance mapping database.

[0166] Specifically, during initialization, a pre-stored impedance-capacitance mapping database is loaded. This database can be understood as a dataset containing historical matching experience, storing various complex impedances characterizing the load, and the two variable capacitor values ​​that best match these complex impedances. The two variable capacitors of the matching network are driven to their preset initial positions, preparing for the subsequent matching process.

[0167] The real-time detection of the complex impedance representing the load via the automatic impedance matching device refers to the current complex impedance representing the load, obtained by the voltage sampling circuit, current sampling circuit, and signal conditioning module, and calculated by the control module. Based on this real-time detected complex impedance, the control module queries a pre-stored impedance-capacitance mapping database to quickly obtain a preliminary, historically based combination of capacitance values, which is referred to as the first target capacitance value.

[0168] Furthermore, to improve the accuracy and robustness of the matching, this application introduces an intelligent search mechanism. The control module utilizes the real-time detected complex impedance and the actual capacitance values ​​of the two variable capacitors to obtain new capacitance value combinations using a simulated annealing algorithm. Simulated annealing is a heuristic search algorithm characterized by its ability to accept "worse" solutions with a certain probability, effectively avoiding getting trapped in local optima and helping to find the global optimum. During the iteration process of the simulated annealing algorithm, new capacitance value combinations are used to query the impedance-capacitance mapping database to obtain the corresponding complex impedance, and the reflection coefficient is calculated based on this complex impedance. The smaller the reflection coefficient, the better the matching effect. After multiple iterations, the simulated annealing algorithm outputs an optimal solution as the second target capacitance value.

[0169] The control module then compares the first and second target capacitance values ​​to assess the difference between them. Based on a preset threshold, the system intelligently selects the final target capacitance value. This threshold can be set according to the capacitance adjustment accuracy requirements in actual applications.

[0170] After determining the final target capacitance value, the two variable capacitors of the matching network are driven to that value. In practical applications, considering model errors and nonlinear factors, even if a perfect match is achieved in one step, it may not be possible. Therefore, the system initiates a fine-tuning process, such as using a fast local search algorithm (e.g., steepest descent), starting from the current capacitance value and performing a small number of iterations (3-5 steps). If a perfect match is still not achieved after 3-5 iterations, the final target capacitance value is selected based on the minimum difference obtained in the last iteration, in order to precisely converge to the optimal matching point.

[0171] As a preferred implementation, upon successful matching, i.e., when the reflection coefficient is less than a preset successful matching threshold (e.g., 0.05), the current combination of complex impedance and capacitance values ​​is acquired and updated in a pre-stored impedance-capacitance mapping database. This update mechanism enables the database to self-learn and optimize, thereby better adapting to slow drifts such as component aging and environmental changes, and improving the long-term matching performance of the system.

[0172] This application's solution effectively addresses the limitations of traditional methods in terms of matching accuracy, speed, and adaptability by combining the fast query capability of a pre-stored impedance-capacitance mapping database with the global optimization capability of the simulated annealing algorithm. Specifically, the database is loaded during the initialization phase, providing a historical experience base for subsequent matching. When the system detects complex impedance in real time, it first quickly obtains a preliminary, experience-based first target capacitance value through a database query, significantly narrowing the search range and ensuring initial matching speed. Based on this, the simulated annealing algorithm is introduced, starting with the current capacitance value and performing a refined search near the database query results. The characteristics of the simulated annealing algorithm allow it to escape local optima and find the global optimum, overcoming the model errors and data sparsity problems that may exist when relying solely on the database, thus improving matching accuracy. By comparing the target capacitance values ​​under two modes and making intelligent decisions based on preset thresholds, the system achieves a balance between fast response and accurate matching. Finally, after a successful match, the current complex impedance and capacitance value combination is updated in the database, giving the system self-learning capabilities. As a result, the database can continuously accumulate new matching experience and adapt to the dynamic changes in complex impedance, thereby ensuring the robustness of the system and the continuous optimization of matching performance during long-term operation.

[0173] Through the above technical solutions, the control method of the automatic impedance matching device in this application can significantly improve the efficiency and accuracy of impedance matching. Specifically, by combining database query and simulated annealing algorithm, it not only ensures the ability to quickly obtain preliminary matching results, but also achieves accurate convergence to the optimal matching point through intelligent search, effectively solving the problem of difficulty in balancing matching speed and accuracy in traditional methods. In addition, the introduced database self-learning update mechanism enables the system to continuously optimize its matching strategy according to actual operating conditions, thereby better adapting to factors such as dynamic changes in complex impedance, component aging, and environmental drift, greatly enhancing the long-term stability and robustness of the system. Thus, this control method ensures matching speed while taking into account matching accuracy and long-term stability, effectively solving the shortcomings of existing technologies.

[0174] In some preferred embodiments, this application is implemented as follows:

[0175] First, the automatic impedance matching network initializes by loading a pre-stored impedance-capacitance mapping database. This database contains multiple key-value pairs, such as resistance RL and reactance XL, with each key-value pair corresponding to the two variable capacitor values ​​(e.g., CT_db, CL_db) that best match that impedance. Simultaneously, the two variable capacitors of the matching network are driven to their preset initial positions.

[0176] For example, suppose the automatic impedance matching device detects the current complex impedance as (R_current, X_current) in real time. The control module will first enter "database query mode" (mode A). In this mode, the control module will search the pre-stored database for the impedance point (RL_db, XL_db) with the closest Euclidean distance to (R_current, X_current). For example, by calculating the distance: distance = sqrt( (R_current - RL_db)² + (X_current - XL_db)² ), the database record that minimizes the distance is found. Then, the capacitance value combination (CT_db, CL_db) corresponding to that record is read as the first target capacitance value.

[0177] Simultaneously, the control module also activates the "Intelligent Search Mode" (Mode B). In this mode, the system does not rely entirely on pre-stored models but autonomously explores the optimal solution through algorithms. The control module detects the current complex impedance (R_current, X_current) and the current capacitance values ​​(CT_now, CL_now) of the two variable capacitors. Starting from (CT_now, CL_now), a simulated annealing algorithm is used to randomly perturb the area around it, generating a new combination of capacitance values ​​(CT_new, CL_new). Subsequently, the system queries the database in reverse to find the complex impedance corresponding to the capacitor with the closest Euclidean distance to (CT_new, CL_new), and then calculates the reflection coefficient |Γ| under that complex impedance. The simulated annealing algorithm iterates several times to find the combination of capacitance values ​​that minimizes |Γ|, and finally outputs the currently obtained optimal solution (CT_sa, CL_sa) as the second target capacitance value.

[0178] Specifically, during the collaborative decision-making phase, the control module compares the difference between the first target capacitance value (CT_db, CL_db) and the second target capacitance value (CT_sa, CL_sa). For example, it calculates ΔCT = |CT_db - CT_sa| and ΔCL = |CL_db - CL_sa|. If ΔCT is less than a preset threshold Threshold_CT and ΔCL is less than a preset threshold Threshold_CL (e.g., the thresholds are set according to the capacitance adjustment accuracy), then the load change is considered to be within expectations, and the database query result is reliable. In this case, the result of mode A (CT_db, CL_db) is used as the final target capacitance value. Otherwise, if the difference is large, it is considered that the load may have changed drastically or the current impedance point is not within the effective range of the database, and the database may be malfunctioning. In this case, the result of mode B (CT_sa, CL_sa) is used as the final target capacitance value to ensure the robustness of the system.

[0179] Subsequently, the control module drives the two variable capacitors of the matching network to the final target capacitance value determined in the decision-making stage via the drive circuit. To further improve the matching accuracy, the system initiates a fast local search process, such as using the steepest descent method, starting from the current point and performing a very small number of iterative fine-tuning steps (e.g., 3-5 steps), eventually converging precisely to the optimal matching point.

[0180] In one specific implementation, after the system successfully matches via the above steps (e.g., the reflection coefficient |Γ| is less than 0.05), the system acquires the key-value pair at that moment. The key is the actual complex impedance at the time of successful matching (RL_success, XL_success) (measured by the detection circuit), and the value is the capacitance value at the time of successful matching (CT_success, CL_success). This new key-value pair is added to the pre-stored impedance-capacitance mapping database. Therefore, when encountering the same or similar load impedance again, the query results for Mode A will be more accurate, and the system can adapt to slow drift due to component aging, environmental changes, etc., achieving a "more accurate with use" effect.

[0181] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0182] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An automatic impedance matcher applied to a radio frequency power source, characterized by, The application relates to a signal processing circuit for a radio frequency (RF) power supply. The signal processing circuit comprises a voltage sampling circuit, a current sampling circuit, a signal processing module and a control module. The voltage sampling circuit is connected with the RF power supply and used for collecting a voltage signal output by the RF power supply. The current sampling circuit is connected with the RF power supply and used for collecting a current signal output by the RF power supply. The voltage output end of the voltage sampling circuit and the current output end of the current sampling circuit are connected with the signal processing module, the signal processing module is used for receiving the voltage signal and the current signal, and is used for outputting active power digital signals, reactive power digital signals, current square digital signals and voltage square digital signals according to the voltage signal and the current signal. The control module is connected with the signal processing module, is used for calculating a complex impedance representing a load according to the active power digital signals, the reactive power digital signals and the current square digital signals, and is used for adjusting impedance matching according to the complex impedance, wherein the complex impedance refers to a total impedance of a matching device, a transmission line and the load device. The control module is also used for detecting whether the RF power signal exists according to the voltage square digital signals, and taking the detection result as one of the judgment conditions for starting automatic impedance matching.

2. The automatic impedance matcher of claim 1, wherein, The signal processing module comprises a first multiplication circuit, a second multiplication circuit, a third multiplication circuit, a fourth multiplication circuit and an ADC analog-digital conversion circuit (103). The first multiplication circuit has two input ends connected with the voltage output end and the current output end respectively, and is used for outputting active power analog signals. The second multiplication circuit has two input ends connected with the voltage output end and the current output end respectively, and is used for outputting reactive power analog signals. The input end of the third multiplication circuit is connected with the current output end, and the third multiplication circuit is used for outputting current square analog signals. The input end of the fourth multiplication circuit is connected with the voltage output end, and the fourth multiplication circuit is used for outputting voltage square analog signals. The output ends of the first multiplication circuit, the second multiplication circuit, the third multiplication circuit and the fourth multiplication circuit are connected with the ADC analog-digital conversion circuit (103) through a filter circuit. The ADC analog-digital conversion circuit (103) is used for converting the active power analog signals, the reactive power analog signals, the current square analog signals and the voltage square analog signals into the active power digital signals, the reactive power digital signals, the current square digital signals and the voltage square digital signals for output.

3. The automatic impedance matcher of claim 2, wherein, The first multiplication circuit comprises a first multiplier chip U6, a first resistor R20, a second resistor R21, a third resistor R11, a fourth resistor R12 and a first capacitor C50. One end of the first resistor R20 is connected with the voltage output end VS, one end of the second resistor R21 is grounded, and the other ends of the first resistor R20 and the second resistor R21 are connected with the positive phase input end of the X channel of the first multiplier chip U6. One end of the third resistor R11 is connected with the current output end IS, one end of the fourth resistor R12 is grounded, and the other ends of the third resistor R11 and the fourth resistor R12 are connected with the positive phase input end of the Y channel of the first multiplier chip U6. One end of the third resistor R11 is connected with the current output end IS, one end of the fourth resistor R12 is grounded, and the other ends of the third resistor R11 and the fourth resistor R12 are connected with the positive phase input end of the Y channel of the first multiplier chip U6. The inverting input end of the X channel and the inverting input end of the Y channel of the first multiplier chip U6 are grounded, the positive power supply pin of the first multiplier chip U6 is connected to the first positive power supply, the negative power supply pin of the first multiplier chip U6 is connected to the second negative power supply, the non-inverting input end of the Z channel of the first multiplier chip U6 is grounded through the first capacitor C50, and a voltage input end for inputting a first direct current bias voltage is arranged between the non-inverting input end of the Z channel of the first multiplier chip U6 and the first capacitor C50; and the output pin of the first multiplier chip U6 is connected to the ADC analog-digital conversion circuit (103) through a filter circuit.

4. The automatic impedance matcher of claim 2, wherein, The second multiplication circuit comprises a second multiplier chip U1, a first phase shift circuit, a second phase shift circuit and a second capacitor C49; The input end of the first phase shift circuit is connected to the voltage output end VS, and the output end of the first phase shift circuit is connected to the non-inverting input end of the X channel of the second multiplier chip U1; The input end of the second phase shift circuit is connected to the current output end IS, and the output end of the second phase shift circuit is connected to the non-inverting input end of the Y channel of the second multiplier chip U1; The first phase shift circuit and the second phase shift circuit are used for generating a first phase shift amount and a second phase shift amount respectively, and the sum of the absolute values of the first phase shift amount and the second phase shift amount is 90°; The inverting input end of the X channel and the inverting input end of the Y channel of the second multiplier chip U1 are grounded, the positive power supply pin of the second multiplier chip U1 is connected to the third positive power supply, the negative power supply pin of the second multiplier chip U1 is connected to the fourth negative power supply, the non-inverting input end of the Z channel of the second multiplier chip U1 is grounded through the second capacitor C49, a voltage input end for inputting a second direct current bias voltage is arranged between the non-inverting input end of the Z channel of the second multiplier chip U1 and the second capacitor C49, and the output pin of the second multiplier chip U1 is connected to the ADC analog-digital conversion circuit (103) through a filter circuit.

5. The automatic impedance matcher of claim 2, wherein, The third multiplication circuit comprises a third multiplier chip U4 and a fifth resistor R18; One end of the fifth resistor R18 is grounded, the other end of the fifth resistor R18 is connected to the current output end IS and the non-inverting input end of the X channel of the third multiplier chip U4 respectively, the non-inverting input end of the X channel of the third multiplier chip U4 is connected to the non-inverting input end of the Y channel of the third multiplier chip U4, the inverting input end of the X channel of the third multiplier chip U4 and the inverting input end of the Y channel of the third multiplier chip U4 are grounded, the non-inverting input end of the Z channel of the third multiplier chip U4 is grounded, the positive power supply pin of the third multiplier chip U4 is connected to the fifth positive power supply, the negative power supply pin of the third multiplier chip U4 is connected to the sixth negative power supply, and the output pin of the third multiplier chip U4 is connected to a filter circuit, and the filter circuit is connected to the ADC analog-digital conversion circuit (103) through a first scale-down circuit (104).

6. The automatic impedance matcher of claim 2, wherein, The fourth multiplication circuit comprises a fourth multiplier chip U9 and a sixth resistor R17; One end of the sixth resistor R17 is grounded, and the other end of the sixth resistor R17 is connected with the voltage output end VS and the positive input end of the X channel of the fourth multiplier chip U9 respectively, the positive input end of the X channel of the fourth multiplier chip U9 is connected with the positive input end of the Y channel of the fourth multiplier chip U9, the negative input end of the X channel of the fourth multiplier chip U9 and the negative input end of the Y channel of the fourth multiplier chip U9 are grounded, the positive input end of the Z channel of the fourth multiplier chip U9 is grounded, the positive power supply pin of the fourth multiplier chip U9 is connected with the seventh positive power supply, the negative power supply pin of the fourth multiplier chip U9 is connected with the eighth negative power supply, and the output pin of the fourth multiplier chip U9 is connected with a filter circuit, and the filter circuit is connected with the ADC analog-digital conversion circuit (103) through a second proportional reduction circuit (105).

7. The automatic impedance matcher of claim 1, wherein, The current sampling circuit comprises a current transformer T1, a seventh resistor R4, an eighth resistor R3, a first band-pass filter circuit and a current output end IS; The first end of the output side of the current transformer T1 is grounded through the seventh resistor R4, and the first end of the output side of the current transformer T1 is also connected with one end of the eighth resistor R3, the other end of the eighth resistor R3 is connected with the current output end IS through the first band-pass filter circuit, and the second end of the output side of the current transformer T1 is grounded, wherein the seventh resistor R4 and the eighth resistor R3 are sampling resistors.

8. The automatic impedance matcher of claim 7, wherein, The first band-pass filter circuit comprises a first inductor L3, a second inductor L6, a third inductor L2, a fourth inductor L7, a third capacitor C8, a fourth capacitor C7, a fifth capacitor C6, a sixth capacitor C17 and a seventh capacitor C16. The first inductor L3, the fifth capacitor C6, the second inductor L6 and the current output end IS are connected in series, one end of the third inductor L2 is grounded, and the other end of the third inductor L2 is connected between the first inductor L3 and the fifth capacitor C6; One end of the third capacitor C8 is grounded, and the other end of the third capacitor C8 is connected between the first inductor L3 and the fifth capacitor C6; One end of the fourth capacitor C7 is grounded, and the other end of the fourth capacitor C7 is connected between the first inductor L3 and the fifth capacitor C6; One end of the fourth inductor L7 is grounded, and the other end of the fourth inductor L7 is connected between the second inductor L6 and the current output end IS; One end of the sixth capacitor C17 is grounded, and the other end of the sixth capacitor C17 is connected between the second inductor L6 and the current output end IS; One end of the seventh capacitor C16 is grounded, and the other end of the seventh capacitor C16 is connected between the second inductor L6 and the current output end IS.

9. The automatic impedance matcher of claim 1, wherein, The voltage sampling circuit comprises a ninth resistor R27, a tenth resistor R26, an eighth capacitor C42, a second band-pass filter circuit and a voltage output end VS; One end of the coupling capacitor integrated in the PCB is connected with one end of the tenth resistor R26, one end of the eighth capacitor C42 is connected between the coupling capacitor and the tenth resistor R26, the other end of the eighth capacitor C42 is grounded, one end of the ninth resistor R27 is connected between the coupling capacitor and the tenth resistor R26, the other end of the ninth resistor R27 is grounded, and the other end of the tenth resistor R26 is connected with the voltage output end VS through the second band-pass filter circuit.

10. A control method of an automatic impedance matcher applied to a radio frequency power supply, characterized by, The control method of the automatic impedance matcher according to any one of claims 1-9, comprising the steps of: initializing, loading a pre-stored impedance-capacitance mapping database, and driving two variable capacitors of the matching network to initial positions, wherein the impedance-capacitance mapping database comprises a complex impedance representing a load and two variable capacitor values most matched with the complex impedance; querying a first target capacitor value from the pre-stored impedance-capacitance mapping database based on the complex impedance representing the load detected by the automatic impedance matcher in real time; obtaining a new capacitor value combination by using the simulated annealing algorithm based on the complex impedance representing the load detected by the automatic impedance matcher in real time and the current capacitor values of the two variable capacitors recorded by the control module in real time, querying the impedance-capacitance mapping database by using the new capacitor value combination to obtain a corresponding complex impedance, calculating a reflection coefficient based on the complex impedance as a target function value, and ending when a preset termination condition is met after multiple iterations, and taking the capacitor value combination corresponding to the minimum target function value as a second target capacitor value; comparing the difference between the first target capacitor value and the second target capacitor value, and selecting a final target capacitor value according to a preset threshold; driving the two variable capacitors of the matching network to the final target capacitor value; updating the current complex impedance and capacitor value combination to the pre-stored impedance-capacitance mapping database after successful matching.

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