Chip analog circuit layout editing method and related device

Abstract

The application belongs to the technical field of semiconductor design automation, and proposes a chip analog circuit wiring editing method and related equipment. The method comprises the following steps: in response to a user selecting a target area in a wiring interface of a chip analog circuit, all and / or part of each metal pattern falling into the target area is classified into a target metal pattern set; based on the geometric feature information of the metal pattern, the metal patterns in the target metal pattern set are clustered to obtain at least one metal pattern subset; the metal patterns in each metal pattern subset are sorted to determine the arrangement serial number of each metal pattern in each metal pattern subset, wherein the arrangement serial numbers of adjacent metal patterns are adjacent; and the metal patterns of any one or more metal pattern subsets in the target metal pattern set are batch edited according to the arrangement serial number of the metal pattern. The technical scheme provided by the application can improve the editing efficiency of the chip analog circuit wiring.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor design automation, and particularly relates to a chip analog circuit wiring editing method and related equipment. BACKGROUND

[0002] In the field of integrated circuit design, as a core functional module, chip analog circuit undertakes key tasks such as signal processing, power management, and signal amplification. Metal patterns (i.e., metal lines) are the core carriers for interconnecting transistors, resistors, capacitors, and other components in analog circuits, and the rationality and accuracy of their wiring design directly affect the performance, stability, and manufacturing yield of chips. With the continuous iteration of semiconductor technology, chip processes continue to evolve towards 7nm, 5nm, and even more advanced nodes, and the integration of analog circuits increases exponentially, resulting in a significant increase in the number and density of metal patterns. In complex analog circuits (such as radio frequency analog circuits and high-precision analog-to-digital conversion circuits), the number of metal patterns in a single chip can reach millions or even tens of millions, and these metal patterns have significant differences in arrangement (horizontal, vertical), shape characteristics, and spacing requirements.

[0003] Currently, the editing of metal patterns during the wiring process of chip analog circuits is still mainly done manually. However, with the rapid increase in the number of metal patterns and the increasing complexity of the design, the limitations of manual editing are becoming increasingly apparent. On the one hand, manual processing of a large number of metal patterns is extremely inefficient, severely affecting chip development progress. On the other hand, manual editing relies on visual judgment of the geometric characteristics and arrangement rules of metal patterns, which is easily affected by factors such as fatigue and subjective judgment bias, leading to editing errors. These errors not only require additional time for verification and correction, but also can result in serious consequences such as lithography deviation and interconnection failure in subsequent manufacturing processes, significantly increasing design costs and risks. Therefore, there is an urgent need for an editing method for chip analog circuit wiring to address the pain points of manual editing. SUMMARY

[0004] Embodiments of the present application provide an editing method, device, computer program product, computer-readable storage medium, and electronic equipment for chip analog circuit wiring, thereby improving the editing efficiency of chip analog circuit wiring to some extent.

[0005] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0006] According to a first aspect of the embodiments of the present application, a chip analog circuit layout editing method is provided. The method comprises: in response to a user selecting a target region in a layout interface of a chip analog circuit, grouping all and / or part of metal patterns falling within the target region into a target metal pattern set; clustering metal patterns in the target metal pattern set based on geometric feature information of the metal patterns, to obtain at least one metal pattern subset; sorting metal patterns in each metal pattern subset to determine an arrangement serial number for each metal pattern in the metal pattern subset, wherein arrangement serial numbers of adjacent metal patterns are adjacent; and performing batch editing on metal patterns of any one or more metal pattern subsets in the target metal pattern set according to the arrangement serial numbers of the metal patterns.

[0007] In some embodiments of the present application, based on the foregoing scheme, the geometric feature information comprises position information, shape information, and extension direction information of the metal patterns. The clustering of the metal patterns in the target metal pattern set based on the geometric feature information of the metal patterns to obtain at least one metal pattern subset comprises: determining a distance between any adjacent metal patterns in the target metal pattern set according to the position information of the metal patterns; and if the distance between the adjacent metal patterns is less than or equal to a set distance, and the shape information and the extension direction information of the adjacent metal patterns are consistent, then clustering the adjacent metal patterns into the same metal pattern subset.

[0008] In some embodiments of the present application, based on the foregoing scheme, the sorting of the metal patterns in each metal pattern subset comprises: determining a direction perpendicular to the extension direction of the metal patterns in the metal pattern subset as a pattern arrangement direction of the metal pattern subset; and sorting the metal patterns in the metal pattern subset according to the pattern arrangement direction.

[0009] In some embodiments of the present application, based on the foregoing scheme, the geometric feature information includes position information and shape information of the metal pattern, the position information includes boundary coordinates of the metal pattern, and in the case that the shape information is a rectangle, the geometric feature information based on the metal pattern is used to cluster the metal patterns in the target metal pattern set to obtain at least one metal pattern subset, including: determining the spacing between any adjacent metal patterns in the target metal pattern set according to the position information of the metal patterns; if the spacing between the any adjacent metal patterns is less than or equal to a set spacing, and the absolute value of the difference between the lower boundary coordinates or the absolute value of the difference between the upper boundary coordinates is less than a set difference, then the any adjacent metal patterns are clustered into a metal pattern subset arranged in a horizontal direction; if the spacing between the any adjacent metal patterns is less than or equal to a set spacing, and the absolute value of the difference between the left boundary coordinates or the absolute value of the difference between the right boundary coordinates is less than a set difference, then the any adjacent metal patterns are clustered into a metal pattern subset arranged in a vertical direction.

[0010] In some embodiments of the present application, based on the foregoing scheme, the sorting of the metal patterns in each metal pattern subset includes: if the each metal pattern subset is a metal pattern subset arranged in a horizontal direction, then the metal patterns in the each metal pattern subset are sorted in order of the left boundary coordinates or the right boundary coordinates from small to large; and if the each metal pattern subset is a metal pattern subset arranged in a vertical direction, then the metal patterns in the each metal pattern subset are sorted in order of the lower boundary coordinates or the upper boundary coordinates from small to large.

[0011] In some embodiments of the present application, based on the foregoing scheme, the batch editing of the metal patterns in any one or more metal pattern subsets in the target metal pattern set according to the arrangement order of the metal patterns includes: in response to a pattern coloring request, determining the pattern production process of each metal pattern subset in the any one or more metal pattern subsets; if the pattern production process of any one metal pattern subset is a single pattern process, then all the metal patterns in the any one metal pattern subset are rendered into a first color; if the pattern production process of any one metal pattern subset is a double pattern process, then the metal pattern with an even arrangement order and the metal pattern with an odd arrangement order in the any one metal pattern subset are rendered into a first color and a second color, respectively; and if the pattern production process of any one metal pattern subset is a four-fold pattern process, then the metal pattern with an arrangement order of 0+4n, the metal pattern with an arrangement order of 1+4n, the metal pattern with an arrangement order of 2+4n, and the metal pattern with an arrangement order of 3+4n in the any one metal pattern subset are rendered into a first color, a second color, a third color, and a fourth color, respectively; wherein n is a non-negative integer.

[0012] In some embodiments of the present application, based on the foregoing scheme, the method further comprises: after color rendering of the metal patterns in the arbitrary one of the metal pattern subsets, locking the coloring information of the metal patterns in the arbitrary one of the metal pattern subsets.

[0013] In some embodiments of the present application, based on the foregoing scheme, the batch editing of the metal patterns in the arbitrary one or more metal pattern subsets in the target metal pattern set according to the arrangement serial numbers of the metal patterns comprises: in response to a pattern selection request, selecting the metal patterns in the arbitrary one or more metal pattern subsets in the target metal pattern set according to the arrangement serial numbers of the metal patterns in a number of pattern intervals, the number of pattern intervals matching the operation instruction of the pattern selection request; and editing the selected metal patterns according to a given editing instruction; the editing instruction comprises any one or more of pattern moving, pattern rotating, pattern stretching, and pattern compressing.

[0014] According to a second aspect of embodiments of the present application, an editing device for chip simulation circuit wiring is provided, the device comprising: a grouping unit configured to group all and / or part of metal patterns falling within a target region into a target metal pattern set in response to a user selecting the target region in a wiring interface of a chip simulation circuit; a clustering unit configured to cluster the metal patterns in the target metal pattern set based on geometric feature information of the metal patterns to obtain at least one metal pattern subset; an ordering unit configured to order the metal patterns in each metal pattern subset to determine arrangement serial numbers for the metal patterns in the each metal pattern subset, wherein the arrangement serial numbers of adjacent metal patterns are adjacent; and an editing unit configured to batch edit the metal patterns in the arbitrary one or more metal pattern subsets in the target metal pattern set according to the arrangement serial numbers of the metal patterns.

[0015] According to a third aspect of embodiments of the present application, a computer program product is provided, the computer program product comprising computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform operations performed to implement the method according to the first aspect described above.

[0016] According to a fourth aspect of embodiments of the present application, a computer readable storage medium is provided, the computer readable storage medium storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by a processor to implement operations performed to implement the method according to the first aspect described above.

[0017] According to a fifth aspect of the embodiments of the present application, an electronic device is provided, which includes one or more processors and one or more memories, the one or more memories storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by the one or more processors to implement the operations performed by the method according to the first aspect described above.

[0018] Based on the technical solutions proposed in the present application, the efficiency of chip analog circuit wiring editing can be significantly improved. Specifically, after the user selects a target area in the wiring interface, all or part of the metal patterns in the area can be automatically classified into a target metal pattern set. This operation directly replaces the inefficient manual point selection mode, accurately locks the editing range, avoids misoperation on irrelevant metal patterns outside the area, completes the collection of target objects at one time, greatly reduces the time cost of pre-screening metal patterns, and lays a solid foundation for subsequent efficient processing. Based on the geometric feature information, the metal patterns in the target set can be clustered, the metal patterns with similar geometric features can be divided into the same subset, the pain points of mixed metal types in the area that cannot be uniformly edited are resolved, the editing operation can be accurately carried out according to the metal pattern characteristics, and invalid actions caused by repeated adaptation of different metal patterns are reduced. The metal patterns in each subset are sorted and assigned with adjacent arrangement serial numbers, which can realize orderly management in line with the logic of signal transmission, pin connection and other wiring, so that engineers can clearly understand the metal pattern arrangement logic, and provide a regular operation sequence for batch editing, thereby avoiding the wiring logic confusion caused by disordered adjustment. Finally, based on the arrangement serial numbers, batch editing can be carried out on any metal pattern subset, which can quickly complete the editing operation, reduce the number of repeated operations and shorten the time consumption of single batch editing, and ensure the editing consistency of the same type of patterns, thereby comprehensively improving the efficiency of chip analog circuit wiring editing.

[0019] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0021] Figure 1 A flowchart of an editing method of a chip analog circuit wiring in an embodiment of the present application is shown;

[0022] Figure 2A schematic diagram of a metal pattern in a target region in an embodiment of the application is shown.

[0023] Figure 3 A schematic diagram of a metal pattern in a target region in an embodiment of the application is shown.

[0024] Figure 4 A schematic diagram of a metal pattern in a target region in an embodiment of the application is shown.

[0025] Figure 5 A block diagram of an editing device for a chip simulation circuit layout in an embodiment of the application is shown.

[0026] Figure 6 A structural schematic diagram of an electronic device in an embodiment of the application is shown. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0028] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a sufficient understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or can employ other methods, components, devices, steps, etc. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring the aspects of the present application.

[0029] The block diagrams shown in the drawings are only functional entities, which do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices. It should be noted that in the drawings, some components in the drawings are omitted to ensure the simplicity and adaptability of the drawings, which do not affect the explanation of the technical solutions of the present application.

[0030] The flowcharts shown in the drawings are only exemplary illustrations, which do not necessarily include all the contents and operations / steps, and are not necessarily executed in the described order. For example, some operations / steps can be further decomposed, and some operations / steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0031] In the description of the present application, it is to be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0032] In order for those skilled in the art to better understand the present application, first, the technical concepts and application background involved in the present application are briefly described.

[0033] Integrated Circuit (IC): Integrated circuit, also known as microchip or chip, refers to a microelectronic device with specific circuit functions, which is formed by concentrating a large number of transistors, diodes, resistors, capacitors, inductors and other electronic components and the interconnection between these components on one or more semiconductor wafers (usually silicon wafers), insulating substrates and other carriers through semiconductor manufacturing processes (such as photolithography, etching, doping, deposition, etc.), and packaging in an outer shell.

[0034] Chip Analog Circuit (CAC): Chip analog circuit is the core functional circuit module of integrated circuit which takes analog signal as the processing object. The so-called analog signal refers to the signal (such as continuously changing voltage, current signal) which continuously changes in time and amplitude. In contrast, digital signal (only represented by 0 and 1 two discrete states).

[0035] Metal pattern: In the field of integrated circuit design, metal pattern (also commonly known as metal line, metal wiring) is the core physical carrier of realizing the electrical interconnection of transistors, resistors, capacitors and other components in chip analog circuit, and is the basic unit of chip interconnection network, and the rationality of its design directly affects the performance, stability and manufacturing yield of chip.

[0036] In the field of integrated circuit design, chip analog circuit as a core functional module, undertakes signal processing, power management, signal amplification and other key tasks, and metal pattern (i.e. metal line) is the core carrier for realizing the interconnection of transistors, resistors, capacitors and other components in analog circuit, and the rationality and accuracy of its wiring design directly affect the performance, stability and manufacturing yield of the chip. With the continuous iteration of semiconductor technology, chip manufacturing continues to evolve to 7nm, 5nm and even more advanced nodes, and the integration of analog circuits is growing exponentially, and the number and density of metal patterns have also increased significantly. In complex analog circuits (such as radio frequency analog circuits, high-precision analog-to-digital conversion circuits), the number of metal patterns in a single chip can reach millions or even tens of millions, and the arrangement mode (horizontal, vertical), shape characteristics, and spacing requirements of these metal patterns differ significantly.

[0037] Currently, the metal pattern editing work in the wiring process of chip analog circuit is still mainly in the form of manual editing. However, with the sharp increase in the number of metal patterns and the increase in design complexity, the limitations of manual editing mode are increasingly evident. On the one hand, manual processing of a large number of metal patterns is extremely inefficient, seriously affecting the progress of chip research and development; on the other hand, manual editing relies on visual judgment of the geometric characteristics and arrangement rules of metal patterns, which is easily affected by factors such as fatigue and subjective judgment bias, and errors are likely to occur, which not only requires additional time for verification and correction, but also may cause serious consequences such as lithography deviation and interconnection failure in subsequent manufacturing processes, significantly increasing design costs and risks.

[0038] In this case, the present application proposes an editing scheme for chip analog circuit wiring to improve the editing efficiency and accuracy of chip analog circuit wiring.

[0039] The implementation details of the technical solutions of the embodiments of the present application are described below:

[0040] Referring to Figure 1 , a flowchart of an editing method for chip analog circuit wiring in the embodiments of the present application is shown, which can be executed by a device with computing processing function. Referring to Figure 1 , the editing method for chip analog circuit wiring includes at least steps 110 to 140, which are described in detail as follows:

[0041] Step 110: In response to the user selecting a target area in the wiring interface of the chip analog circuit, all and / or part of the metal patterns falling into the target area are classified into a target metal pattern set.

[0042] Step 120: Based on the geometric feature information of the metal patterns, the metal patterns in the target metal pattern set are clustered to obtain at least one metal pattern subset.

[0043] Step 130, sorting the metal patterns in each metal pattern subset to determine the arrangement number of each metal pattern in the metal pattern subset, wherein the arrangement numbers of adjacent metal patterns are adjacent.

[0044] Step 140, batch editing the metal patterns in any one or more metal pattern subsets in the target metal pattern set according to the arrangement numbers of the metal patterns.

[0045] In the present application, the user can define a specific area through mouse selection, circle selection and other operations through the interactive interface of the layout design software, such as the layout view of the electronic design automation tool (EDA), which can be a rectangle, a circle or any other shape. Then, the system can automatically identify the metal patterns in the area.

[0046] In the present application, the following definitions are made for the concepts of all and part involved in the collection process of the target metal pattern set: all refers to the outline of a single metal pattern being entirely within the range defined by the target area, and part refers to the outline of a single metal pattern being partially within the range defined by the target area, and the remaining part of the outline being outside the range defined by the target area. For example, the user performs a circle selection operation through the interactive interface of the layout design software in the M2 metal layer EDA layout view of a 7nm radio frequency analog circuit, and selects a rectangular area of 100μm x 80μm. There are 200 metal patterns in the area, of which 130 metal patterns have their outlines entirely within the circular area, and 70 metal patterns have their outlines partially within the circular area.

[0047] In the traditional manual mode, the user needs to manually select the target metal patterns one by one. It takes at least 10-20 minutes to complete the selection when facing hundreds or thousands of metal lines. However, the present application can complete the construction of the target metal pattern set in a short time through automatic identification and selection, greatly shortening the preparation time. At the same time, by defining the target area and determining the target metal pattern set, the range of metal patterns that need to be edited can be accurately locked, avoiding indiscriminate processing of the metal patterns of the entire chip, reducing unnecessary calculation, and also meeting the individual needs of the user for editing the local area, laying a foundation for subsequent batch editing.

[0048] In the present application, the geometric feature information is the key data for distinguishing metal patterns. Different metal patterns are divided into different metal pattern subsets due to the difference in geometric features, and metal patterns with similar features are clustered into the same metal pattern subset, so as to realize the classification and management of the target metal pattern. The clustering operation can classify the disordered target metal patterns according to the geometric features, so that the metal patterns with the same or similar features are concentrated together, avoiding confusion during subsequent editing, and also laying a foundation for differentiated batch editing of metal patterns with different features.

[0049] In the present application, after completing clustering to obtain metal pattern subsets, the metal patterns in each metal pattern subset can be arranged in order and assigned with arrangement serial numbers, and the arrangement serial numbers corresponding to adjacent metal patterns are also consecutive numbers (such as the consecutive sequence of 0, 1, 2, 3…), so as to establish an ordered sequence of metal patterns, facilitating subsequent batch editing operation according to the serial numbers. It should be noted that the arrangement serial numbers of metal patterns in two different metal pattern subsets can be the same. By sorting and determining the arrangement serial numbers, the metal patterns in each metal pattern subset can form an ordered sequence, so that the subsequent batch editing operation can accurately locate the target pattern according to the serial number, avoiding misplacement of the editing operation, and improving the accuracy of editing.

[0050] Further, after completing sorting and determining the arrangement serial numbers, one or more metal pattern subsets can be initiated editing instructions based on these serial numbers. The system will process the metal patterns with specified serial numbers in the corresponding subset in batches according to the instructions, realizing efficient editing operation. The editing types can include coloring, selection, shape adjustment and other forms. Based on the batch editing of arrangement serial numbers, the traditional manual editing mode can be completely changed, greatly improving the editing efficiency of metal patterns. At the same time, relying on the ordered serial numbers, the accuracy of editing operation can be guaranteed, reducing editing errors caused by manual operation mistakes, and reducing the risk and cost of chip design.

[0051] Based on the technical scheme provided in the present application, the editing efficiency of chip analog circuit wiring can be significantly improved. Specifically, after the user selects the target area in the wiring interface, all or part of the metal patterns in the area can be automatically classified into the target metal pattern set. This operation directly replaces the inefficient manual point selection mode, accurately locks the editing range, avoids misoperation on irrelevant patterns outside the area, completes the collection of target objects at one time, greatly reduces the time cost of pre-screening patterns, and lays a solid foundation for subsequent efficient processing. Based on the geometric feature information, the metal patterns in the target set can be clustered, the patterns with similar geometric features can be divided into the same subset, the pain points of mixed pattern types in the area and the inability to edit uniformly can be resolved, the editing operation can be accurately carried out according to the pattern characteristics, and the invalid actions caused by repeated adaptation of different patterns can be reduced. The metal patterns in each subset are sorted and assigned with adjacent arrangement serial numbers, which can realize orderly management in line with the logic of signal transmission, pin connection and other wiring, enable engineers to clearly understand the pattern arrangement logic, provide a neat operation sequence for batch editing, and avoid wiring logic confusion caused by disordered adjustment. Finally, based on the arrangement serial number, batch editing of any metal pattern subset can be carried out, which can quickly complete the editing operation, reduce the number of repeated operations and shorten the time consumption of single batch editing, ensure the editing consistency of the same type of patterns, and finally realize the overall improvement of the editing efficiency of chip analog circuit wiring.

[0052] In order to enable those skilled in the art to better understand the editing method of chip analog circuit wiring provided in the present application, the steps of the present application will be described in detail.

[0053] In an embodiment of the present application, the geometric feature information can include position information, shape information, and extension direction information of the metal pattern.

[0054] In the present application, the position information can include boundary coordinates and center point coordinates of the metal pattern, and the position information of the metal pattern can be represented by coordinate data in the wiring coordinate system. The shape information can include rectangle, trapezoid, irregular pattern, etc. The extension direction information can include horizontal, vertical, and inclined.

[0055] In the present application, the set distance is a threshold value preset according to the chip manufacturing process and the wiring design requirement. For example, the set distance under the advanced process can be set to 0.1 μm.

[0056] Further, in the present embodiment, the metal patterns in the target metal pattern set are clustered based on the geometric feature information of the metal patterns to obtain at least one metal pattern subset, which can be performed according to the following steps 121 to 122:

[0057] Step 121, according to the position information of any adjacent metal pattern in the target metal pattern set, determine the interval between the any adjacent metal patterns.

[0058] Step 122, if the interval between the any adjacent metal patterns is less than or equal to the set interval, and the shape information and the extension direction information of the any adjacent metal patterns are consistent, then cluster the any adjacent metal patterns to the same metal pattern subset.

[0059] In this application, according to the position information of any adjacent metal pattern in the target metal pattern set, the distance between the corresponding boundaries of any two adjacent metal patterns can be calculated, and the interval between the two metal patterns can be obtained. If the interval is less than or equal to the set interval, and the shape information and the extension direction information of the any adjacent metal patterns are consistent, then the any adjacent metal patterns are clustered to the same metal pattern subset. That is, only the adjacent metal patterns that meet the three conditions of interval ≤ set interval, shape information consistent, and extension direction information consistent are clustered to the same metal pattern subset, and the three conditions are indispensable.

[0060] In order to better understand the application by those skilled in the art, the following specific embodiments are described in conjunction with the accompanying drawings. Figure 2 A specific embodiment is described.

[0061] Referring to Figure 2 , a schematic diagram of metal patterns in a target region in an embodiment of the application is shown.

[0062] As Figure 2 shown, metal image A2 and metal pattern B0 have consistent shape information and extension direction, but the interval between them cannot meet the requirement of being less than the set interval, so they cannot be clustered to the same metal pattern subset; metal images B0-B3 and metal pattern C3 have consistent shape information and the interval between them meets the requirement of being less than the set interval, but their extension directions are not consistent, so they cannot be clustered to the same metal pattern subset; metal image B3 and metal pattern D0 have consistent extension direction and the interval between them meets the requirement of being less than the set interval, but their shape information is not consistent, so they cannot be clustered to the same metal pattern subset; metal images C2-C3 and metal pattern D0 have the interval between them meeting the requirement of being less than the set interval, but their shape information and extension direction are not consistent, so they cannot be clustered to the same metal pattern subset.

[0063] As can be seen, based on the scheme in this embodiment, the metal patterns in the target region 200 can be divided into four metal pattern subsets, specifically: metal pattern subset A (A0, A1, A2), metal pattern subset B (B0, B1, B2, B3), metal pattern subset C (C0, C1, C2, C3), and metal pattern subset D (D0, D1, D2, D3).

[0064] Based on the technical scheme of steps 121 to 122 described above, in the clustering link, first, the distance between adjacent metal patterns is accurately calculated, which can provide quantitative judgment basis for subsequent clustering operation, and guarantee the objectivity and uniformity of the clustering standard. At the same time, relying on the multi-dimensional clustering condition limitation, it can ensure that the metal patterns in the same subset have high consistency, so that the subsequent batch editing of the subset is more targeted, avoids the editing effect not meeting the expectation due to too large difference in pattern characteristics, and further improves the accuracy of editing. In the manual mode, it is difficult for engineers to accurately determine whether the distance meets the requirements, and often relies on experience estimation. However, the rule can significantly improve the clustering accuracy by quantifying the distance threshold and jointly determining multiple characteristics, and can avoid the misclustering of metal patterns of different shapes and different directions, providing more accurate grouping basis for subsequent editing and reducing the risk of process adaptation failure caused by clustering errors.

[0065] Further, in this embodiment, the sorting of the metal patterns in each metal pattern subset can be performed according to the following steps 131 to 132:

[0066] Step 131: determining the direction perpendicular to the extension direction of the metal patterns in each metal pattern subset as the pattern arrangement direction of each metal pattern subset.

[0067] Step 132: sorting the metal patterns in each metal pattern subset according to the pattern arrangement direction.

[0068] In this application, the extension direction of the metal pattern can refer to the direction of its length extension, for example, the horizontally extending metal pattern, and its extension direction is the horizontal direction, and then the vertical direction perpendicular to it is the pattern arrangement direction of the subset, such as upward or downward. If the metal pattern is vertically extended, then the horizontal direction is its arrangement direction, such as left or right. After determining the arrangement direction, the patterns in the metal pattern subset can be arranged in order along the direction, so as to assign an arrangement serial number to each metal pattern.

[0069] In this embodiment, the arrangement serial number of the first metal pattern in a metal pattern subset can be assigned as 0. In other embodiments, the arrangement serial number of the first metal pattern can also be assigned as 1 or 2, and specifically, this application does not make too many limitations.

[0070] for example Figure 2 As shown, for the metal pattern subset B, the extension direction of its metal patterns is vertical, so its arrangement direction is horizontal from left to right (or right to left). After assigning arrangement numbers to each metal pattern in the metal pattern subset B, it can be determined that the arrangement number of metal pattern B0 is 0, the arrangement number of metal pattern B1 is 1, the arrangement number of metal pattern B2 is 2, and the arrangement number of metal pattern B3 is 3. For the metal pattern subset C, the extension direction of its metal patterns is horizontal, so its arrangement direction is vertical from bottom to top (or top to bottom). After assigning arrangement numbers to each metal pattern in the metal pattern subset C, it can be determined that the arrangement number of metal pattern C0 is 0, the arrangement number of metal pattern C1 is 1, the arrangement number of metal pattern C2 is 2, and the arrangement number of metal pattern C3 is 3.

[0071] Based on the technical solutions in steps 131 to 132 above, in the metal graphic sorting stage, using the vertical direction of the extension direction as the arrangement direction can ensure that the sequence of sorted metal graphics conforms to its own distribution pattern, which is convenient for subsequent batch editing according to the ordered sequence. At the same time, sorting based on the arrangement direction determined by the extension direction can make the serial number of the metal graphics correspond to its actual distribution position, improve the logic and readability of the serial number, realize the standardization of the sorting direction, and facilitate users to quickly identify the serial number of the target graphic and efficiently initiate editing commands.

[0072] In another embodiment of this application, the geometric feature information may include the position information and shape information of the metal graphic, and the position information may include the boundary coordinates of the metal graphic.

[0073] Furthermore, in this embodiment, when the shape information is rectangular, the clustering of metal graphics in the target metal graphic set based on the geometric feature information of the metal graphics to obtain at least one subset of metal graphics can be performed according to the following steps 123 to 125:

[0074] Step 123: Determine the spacing between any two adjacent metal graphics based on the position information of any two adjacent metal graphics in the target metal graphic set.

[0075] Step 124: If the spacing between any two adjacent metal figures is less than or equal to a set spacing, and the absolute value of the difference between the lower boundary coordinates or the absolute value of the difference between the upper boundary coordinates is less than a set difference, then the two adjacent metal figures are clustered into a subset of metal figures arranged in the horizontal direction.

[0076] If the spacing between the arbitrary adjacent metal patterns is less than or equal to the set spacing, and the absolute value of the difference between the left boundary coordinates or the absolute value of the difference between the right boundary coordinates is less than the set difference value, the arbitrary adjacent metal patterns are clustered into a subset of metal patterns arranged in the vertical direction.

[0077] In this application, for rectangular metal patterns, if the absolute value of the difference between the lower boundary coordinates or the absolute value of the difference between the upper boundary coordinates is less than the set difference value, it indicates that it is arranged in the horizontal direction. Combined with the condition that the spacing between adjacent metal patterns is less than or equal to the set spacing, it can be determined as a horizontally arranged metal pattern, and then clustered into a subset of metal patterns arranged in the horizontal direction. If the absolute value of the difference between the left boundary coordinates or the absolute value of the difference between the right boundary coordinates is less than the set difference value, it indicates that it is arranged in the vertical direction. Combined with the condition that the spacing between adjacent metal patterns is less than or equal to the set spacing, it can be determined as a vertically arranged metal pattern, and then clustered into a subset of metal patterns arranged in the vertical direction.

[0078] Continuing to refer to Figure 2 As shown in FIG. 1, the lower boundary coordinates and the upper boundary coordinates of the metal patterns A0-A2 are the same (i.e., the absolute value of the difference between the lower boundary coordinates and the absolute value of the difference between the upper boundary coordinates are both 0, which is necessarily less than the set difference value), so the metal patterns A0-A2 can be clustered into a subset of metal patterns arranged in the horizontal direction A; the lower boundary coordinates and the upper boundary coordinates of the metal patterns B0-B3 are the same (i.e., the absolute value of the difference between the lower boundary coordinates and the absolute value of the difference between the upper boundary coordinates are both 0, which is necessarily less than the set difference value), so the metal patterns B0-B3 can be clustered into a subset of metal patterns arranged in the horizontal direction B; the left boundary coordinates and the right boundary coordinates of the metal patterns C0-C3 are the same (i.e., the absolute value of the difference between the left boundary coordinates and the absolute value of the difference between the right boundary coordinates are both 0, which is necessarily less than the set difference value), so the metal patterns C0-C3 can be clustered into a subset of metal patterns arranged in the vertical direction C.

[0079] Based on the technical solutions of steps 123-125, the clustering conditions of the horizontal arrangement feature are set for rectangular metal patterns, which can realize accurate classification of horizontally arranged rectangular metal patterns, provide convenience for subsequent batch editing of horizontally arranged rectangular metal patterns, and at the same time, the clustering conditions of the vertical arrangement feature are set for rectangular metal patterns, which can realize accurate classification of vertically arranged rectangular metal patterns, facilitate subsequent targeted batch editing of such patterns, and improve the efficiency and accuracy of editing. Through the quantitative determination of the boundary coordinates, the accurate differentiation of the arrangement direction of the rectangular metal lines can be realized, the clustering specificity and accuracy are greatly improved, and it is especially suitable for the clustering needs of high-density rectangular metal lines in advanced processes, which provides accurate grouping for subsequent process adaptability editing.

[0080] Further, in the embodiment, the sorting of the metal patterns in each metal pattern subset can be performed according to the following steps 133 to 134.

[0081] In step 133, if the metal pattern subset is a horizontal metal pattern subset, the metal patterns in the metal pattern subset are sorted according to the left border coordinate or the right border coordinate in ascending order.

[0082] In step 134, if the metal pattern subset is a vertical metal pattern subset, the metal patterns in the metal pattern subset are sorted according to the lower border coordinate or the upper border coordinate in ascending order.

[0083] In the present application, for a horizontal rectangular metal pattern, the size of the left border coordinate or the right border coordinate directly reflects the position of the metal pattern in the horizontal direction. The sorting of the metal patterns according to the left border coordinate or the right border coordinate in ascending order means that the metal patterns are arranged in order from left to right and are assigned with arrangement numbers. For a vertical rectangular metal pattern, the size of the lower border coordinate or the upper border coordinate directly reflects the position of the metal pattern in the vertical direction. The sorting of the metal patterns according to the lower border coordinate or the upper border coordinate in ascending order means that the metal patterns are arranged in order from bottom to top and are assigned with arrangement numbers.

[0084] In the embodiment, the arrangement number of the first metal pattern in a metal pattern subset can be assigned as 0. In other embodiments, the arrangement number of the first metal pattern can also be assigned as 1 or 2. In particular, the present application does not make too many limitations on this.

[0085] Continuing to refer to Figure 2As shown, since each metal pattern in the metal pattern subset A is arranged in the horizontal direction, the arrangement number of the metal pattern A0 can be assigned as 0, the arrangement number of the metal pattern A1 can be assigned as 1, and the arrangement number of the metal pattern A2 can be assigned as 2 according to the order from small to large of the left boundary coordinates or the right boundary coordinates of each metal pattern in the metal pattern subset A. Since each metal pattern in the metal pattern subset B is arranged in the horizontal direction, the arrangement number of the metal pattern B0 can be assigned as 0, the arrangement number of the metal pattern B1 can be assigned as 1, the arrangement number of the metal pattern B2 can be assigned as 2, and the arrangement number of the metal pattern B3 can be assigned as 3 according to the order from small to large of the left boundary coordinates or the right boundary coordinates of each metal pattern in the metal pattern subset B. Since each metal pattern in the metal pattern subset C is arranged in the vertical direction, the arrangement number of the metal pattern C0 can be assigned as 0, the arrangement number of the metal pattern C1 can be assigned as 1, the arrangement number of the metal pattern C2 can be assigned as 2, and the arrangement number of the metal pattern C3 can be assigned as 3 according to the order from small to large of the lower boundary coordinates or the upper boundary coordinates of each metal pattern in the metal pattern subset C.

[0086] Based on the technical solutions in steps 133-134, in the sorting of the rectangular metal pattern subset, the left boundary coordinates or the right boundary coordinates are used to realize the ordered arrangement of the horizontal metal pattern subset, so that the arrangement number can be matched with the horizontal position of the metal pattern, which facilitates the user to quickly locate the serial number of the target pattern according to the horizontal position, improves the convenience of editing operation, and meanwhile, the lower boundary coordinates or the upper boundary coordinates are used to complete the ordered sorting of the vertical metal pattern subset, so that the arrangement number can be accurately matched with the vertical position of the metal pattern, which facilitates the user to quickly find the serial number of the target pattern according to the vertical position, and then efficiently initiates the batch editing instruction. For the sorting rule of the rectangular metal line, the adaptability problem of the general sorting rule can be avoided, for example, the rectangular metal line arranged horizontally is sorted according to the left boundary, which completely matches the horizontal extension characteristic of the layout, and the sorting result is more consistent with the design logic of the engineer, which provides an index basis for the subsequent batch editing according to the design demand of the rectangular metal line, improves the practicality of the editing operation, and then the editing efficiency of the analog circuit layout can be improved.

[0087] In the present application, in the step 140 as described above, Figure 1 In the step 140 as described above,

[0088] In step 141, in response to a pattern coloring request, the pattern production process of each metal pattern subset in the one or more metal pattern subsets is determined.

[0089] Step 142, if the production process of any one metal pattern subset is single pattern process, then render all metal patterns of the any one metal pattern subset into the first color.

[0090] Step 143, if the production process of any one metal pattern subset is double pattern process, then render the metal pattern with even number sequence and the metal pattern with odd number sequence in the any one metal pattern subset into the first color and the second color respectively.

[0091] Step 144, if the production process of any one metal pattern subset is four-fold pattern process, then render the metal pattern with 0+4n number sequence, the metal pattern with 1+4n number sequence, the metal pattern with 2+4n number sequence, and the metal pattern with 3+4n number sequence in the any one metal pattern subset into the first color, the second color, the third color, and the fourth color respectively. Wherein, n is a non-negative integer.

[0092] In the present application, the production process of pattern is the process type of forming metal line according to the metal pattern in the chip layout layer in the chip manufacturing process, such as single pattern process, double pattern process, four-fold pattern process, etc. Different processes have different coloring requirements for metal patterns, so the production process of each metal pattern subset needs to be determined before coloring. The production process can be called from the process library of chip design.

[0093] Wherein, the metal pattern corresponding to the single pattern process does not need to be distinguished by different levels or batches during manufacturing, so it can be uniformly rendered into the same color (i.e. the first color, such as red), which is convenient for subsequent process identification and detection. The double pattern process needs to divide the metal pattern into two batches for manufacturing, so it needs to be distinguished by different colors. The odd number sequence and even number sequence patterns can be rendered into two different colors (such as odd number is red and even number is blue) respectively, which is convenient for subsequent division of the metal pattern in the chip layout layer into two chip sub-layouts. The four-fold pattern process needs to divide the metal pattern into four batches for manufacturing, so it needs to render the patterns with different interval sequence numbers into four different colors (such as 0+4n is red, 1+4n is blue, 2+4n is green, and 3+4n is yellow) according to the 4n period rule, in order to meet the requirement of batch processing.

[0094] In order for those skilled in the art to better understand the present application, the following will be described in combination with specific embodiments. Figure 3 A specific embodiment is described.

[0095] Referring to Figure 3 , a schematic diagram of metal patterns in a target area in an embodiment of the present application is shown.

[0096] As Figure 3As shown in subgraph (a) of FIG. 1, assuming that the pattern production process of the metal pattern subset E is a single pattern process, the metal patterns E0, E1, E2, and E3 of the metal pattern subset E can all be rendered as the first color;

[0097] As shown in subgraph (a) of FIG. 1, assuming that the pattern production process of the metal pattern subset E is a single pattern process, the metal patterns E0, E1, E2, and E3 of the metal pattern subset E can all be rendered as the first color; Figure 3 As shown in subgraph (b) of FIG. 1, assuming that the pattern production process of the metal pattern subset F is a double pattern process, the metal patterns F0, F2, F4, and F6 of the metal pattern subset F can be rendered as the first color, and the metal patterns F1, F3, F5, and F7 can be rendered as the second color.

[0098] As shown in subgraph (a) of FIG. 1, assuming that the pattern production process of the metal pattern subset E is a single pattern process, the metal patterns E0, E1, E2, and E3 of the metal pattern subset E can all be rendered as the first color; Figure 3 As shown in subgraph (c) of FIG. 1, assuming that the pattern production process of the metal pattern subset G is a four-fold pattern process, the metal patterns G0 and G4 of the metal pattern subset G can be rendered as the first color, the metal patterns G1 and G5 can be rendered as the second color, the metal patterns G2 and G6 can be rendered as the third color, and the metal patterns G3 and G7 can be rendered as the fourth color.

[0099] Based on the technical solutions of steps 141 to 142, by pre-determining the production process, it can be ensured that the subsequent coloring operation meets the process requirements of chip manufacturing, avoiding the influence of coloring errors on subsequent chip production. For single pattern process, unified coloring can quickly complete the color identification of such patterns, facilitating the identification and control of such patterns in subsequent production links, and improving the efficiency of coloring editing. Based on the odd-even number of serial numbers, differential coloring can accurately distinguish different batches of metal patterns under a double pattern process, meet the manufacturing process requirements, and realize batch rapid coloring, improving editing efficiency. According to the 4n periodic law, differential coloring can accurately distinguish four batches of metal patterns under a four-fold pattern process, completely match the manufacturing process requirements, and through batch coloring operation, greatly improve the editing efficiency, reduce the mistakes of manual operation, and reduce the risk of chip manufacturing yield decline caused by coloring errors.

[0100] In the present application, the following step 145 can also be performed:

[0101] Step 145, after rendering the metal patterns in the arbitrary metal pattern subset in color, locking the coloring information of the metal patterns in the arbitrary metal pattern subset.

[0102] In the present application, the coloring information includes the color category corresponding to each metal pattern, the rendering time, the metal pattern subset to which the metal pattern belongs, and other related data. After the coloring of the metal pattern is completed, the coloring information can be uniformly stored to lock the coloring information. Specifically, the coloring information can be stored in a local database or a cloud storage module, facilitating subsequent query and calling. Locking the coloring information can achieve the following two aspects: on the one hand, the coloring state of the metal pattern can be traced back, and if a color-related problem occurs subsequently, the historical coloring data can be quickly queried for troubleshooting to prevent misoperation in the subsequent design process; on the other hand, in the modification or review link of the subsequent wiring design, the locked color cannot be changed by simple coloring operation, which can improve the stability of the design and improve the efficiency of the overall design process.

[0103] In the present application, in step 140, Figure 1 In step 140, the metal patterns in any one or more metal pattern subsets in the target metal pattern set are batch edited according to the arrangement serial numbers of the metal patterns. The batch editing can also be performed according to the following steps 146 and 147:

[0104] In step 146, in response to a pattern selection request, the metal patterns in any one or more metal pattern subsets in the target metal pattern set are selected by jumping according to the arrangement serial numbers of the metal patterns and the number of pattern intervals. The number of pattern intervals matches the operation instruction of the pattern selection request.

[0105] In step 147, the selected metal patterns are edited according to a given editing instruction. The editing instruction includes any one or more of pattern moving, pattern rotating, pattern stretching, and pattern compressing.

[0106] In the present application, the number of pattern intervals is determined by the operation instruction of the user. For example, if the user instructs the number of intervals to be 1, one metal pattern is selected every 1 metal pattern (i.e., the metal patterns with arrangement serial numbers 1, 3, 5, … are selected). If the number of intervals is 2, the metal patterns with arrangement serial numbers 1, 4, 7, … are selected, so as to realize the jump selection of the metal patterns.

[0107] After the metal patterns are selected, the user can initiate one or more editing instructions such as moving, rotating, stretching, and compressing on the selected metal patterns according to actual needs, so as to batch process all the selected metal patterns based on the editing instructions.

[0108] In order for those skilled in the art to better understand the present application, the following will be described in conjunction with Figure 4 a specific embodiment.

[0109] Referring to Figure 4 , a schematic diagram of metal patterns in a target region in an embodiment of the present application is shown.

[0110] As Figure 4 As shown in the subgraph (a), the user can jump to select the metal patterns H1, H3, H5, H7 with arrangement serial numbers 1, 3, 5, 7 in the metal pattern subset H, and then perform the operations of width compression and movement, to obtain the chip layout layer as shown in the subgraph (b). Figure 4 As shown in the subgraph (a), the user can jump to select the metal patterns H1, H3, H5, H7 with arrangement serial numbers 1, 3, 5, 7 in the metal pattern subset H, and then perform the operations of width compression and movement, to obtain the chip layout layer as shown in the subgraph (b).

[0111] Based on the technical solutions of steps 146 to 147, the jump selection is achieved through arrangement serial number intervals, which can meet the editing needs of the user for specific regular patterns, and can greatly improve the efficiency of metal pattern selection compared with the selection mode one by one, thereby saving time for subsequent batch editing. The batch editing of the jump-selected metal patterns can realize the rapid modification of specific regular patterns, avoid the tedious process of manual editing one by one, improve the editing efficiency, and ensure the consistency of all selected pattern editing operations, thereby reducing the error of manual operation. Meanwhile, the combined editing supports one-time execution of multiple operations, avoids the error of repeated operations, and improves the consistency and accuracy of shape adjustment.

[0112] Overall, based on the editing scheme of the chip analog circuit wiring proposed in the present application, through a series of processes such as target metal pattern set determination, clustering, sorting, and batch editing, efficient and accurate editing of metal patterns in the chip analog circuit can be realized. Compared with the traditional manual editing mode, the technical effect is remarkable. Specifically, first, the editing efficiency can be greatly improved. Through clustering and batch editing operations, the tedious process of manually processing metal patterns one by one can be avoided, and hundreds or thousands of metal patterns can be edited at the same time, thereby greatly shortening the wiring editing time and accelerating the development progress of the chip. Second, the editing error rate can be reduced. Relying on quantitative geometric features for clustering and sorting, as well as standardized batch editing processes, the error caused by manual subjective judgment and operation can be reduced, the risk of photolithography deviation and interconnection failure caused by editing errors can be reduced, and the cost of subsequent verification and correction can be reduced. Third, it can adapt to multiple processes and editing needs. It provides clustering and sorting methods for metal patterns with different geometric features, and supports coloring editing based on production processes and jump selection editing based on serial number intervals, which can meet the metal pattern editing needs of different types of analog circuits and different production processes, and has strong universality and flexibility. Fourth, it can realize traceability of editing information. Through the storage of coloring information, the editing state of the metal pattern is locked, which is convenient for subsequent design modification and problem troubleshooting, and can improve the overall management and control ability of chip wiring design. In summary, the present application can effectively solve the pain points of existing chip analog circuit wiring manual editing, and provide an efficient and accurate solution for metal pattern editing in the field of integrated circuit design, which has high popularization and application value.

[0113] The device embodiments of the present application are introduced below, which can be used to execute the editing method of the chip analog circuit layout in the above-mentioned embodiments of the present application. For details not disclosed in the device embodiments of the present application, refer to the above-mentioned embodiments of the editing method of the chip analog circuit layout.

[0114] Referring to Figure 5 , a block diagram of the editing device of the chip analog circuit layout in the embodiments of the present application is shown.

[0115] As Figure 5 shown, the editing device 500 of the chip analog circuit layout according to the embodiments of the present application comprises a grouping unit 501, a clustering unit 502, a sorting unit 503 and an editing unit 504.

[0116] The grouping unit 501 is configured to group all and / or part of the metal patterns falling into a target region into a target metal pattern set in response to a user selecting the target region in a layout interface of a chip analog circuit; the clustering unit 502 is configured to cluster the metal patterns in the target metal pattern set based on geometric feature information of the metal patterns to obtain at least one metal pattern subset; the sorting unit 503 is configured to sort the metal patterns in each metal pattern subset to determine an arrangement serial number for each metal pattern in the each metal pattern subset, wherein the arrangement serial numbers of adjacent metal patterns are adjacent; and the editing unit 504 is configured to batch edit the metal patterns of any one or more metal pattern subsets in the target metal pattern set according to the arrangement serial numbers of the metal patterns.

[0117] In some embodiments of the present application, based on the foregoing scheme, the geometric feature information comprises position information, shape information and extension direction information of the metal patterns, and the clustering unit 502 is configured to determine the spacing between any adjacent metal patterns in the target metal pattern set according to the position information of the any adjacent metal patterns, and if the spacing between the any adjacent metal patterns is less than or equal to a set spacing and the shape information and the extension direction information of the any adjacent metal patterns are consistent, then the any adjacent metal patterns are clustered into the same metal pattern subset.

[0118] In some embodiments of the present application, based on the foregoing scheme, the sorting unit 503 is configured to determine a pattern arrangement direction of each metal pattern subset as a direction perpendicular to the extension direction of the metal patterns in the each metal pattern subset, and sort the metal patterns in the each metal pattern subset according to the pattern arrangement direction.

[0119] In some embodiments of the present application, based on the foregoing scheme, the geometry feature information includes position information and shape information of the metal pattern, the position information includes boundary coordinates of the metal pattern, and in the case that the shape information is a rectangle, the clustering unit 502 is configured to: determine the spacing between any adjacent metal patterns in the target metal pattern set according to the position information of the any adjacent metal patterns; if the spacing between the any adjacent metal patterns is less than or equal to a set spacing, and the lower boundary coordinates or the upper boundary coordinates are the same, then the any adjacent metal patterns are clustered into a metal pattern subset arranged in a horizontal direction; if the spacing between the any adjacent metal patterns is less than or equal to a set spacing, and the left boundary coordinates or the right boundary coordinates are the same, then the any adjacent metal patterns are clustered into a metal pattern subset arranged in a vertical direction.

[0120] In some embodiments of the present application, based on the foregoing scheme, the sorting unit 503 is configured to: if the each metal pattern subset is a metal pattern subset arranged in a horizontal direction, then sort the metal patterns in the each metal pattern subset in order from small to large according to the left boundary coordinates or the right boundary coordinates; and if the each metal pattern subset is a metal pattern subset arranged in a vertical direction, then sort the metal patterns in the each metal pattern subset in order from small to large according to the lower boundary coordinates or the upper boundary coordinates.

[0121] In some embodiments of the present application, based on the foregoing scheme, the editing unit 504 is configured to: in response to a pattern coloring request, determine the pattern production process of each metal pattern subset in the any one or more metal pattern subsets; if the pattern production process of any one metal pattern subset is a single pattern process, then render all metal patterns in the any one metal pattern subset to a first color; if the pattern production process of any one metal pattern subset is a double pattern process, then render the metal pattern with an even arrangement serial number and the metal pattern with an odd arrangement serial number in the any one metal pattern subset to a first color and a second color, respectively; and if the pattern production process of any one metal pattern subset is a four-fold pattern process, then render the metal pattern with an arrangement serial number of 0+4n, the metal pattern with an arrangement serial number of 1+4n, the metal pattern with an arrangement serial number of 2+4n, and the metal pattern with an arrangement serial number of 3+4n in the any one metal pattern subset to a first color, a second color, a third color, and a fourth color, respectively; wherein n is a non-negative integer.

[0122] In some embodiments of the present application, based on the foregoing scheme, the device further includes a locking unit configured to lock the coloring information of each metal pattern in the any one metal pattern subset after rendering the metal patterns in the any one metal pattern subset in color.

[0123] In some embodiments of the present application, based on the foregoing scheme, the editing unit 504 is configured to: in response to a figure selection request, jump select the metal figures in any one or more metal figure subsets in the target metal figure set according to the arrangement serial number of the metal figure, according to the number of figure intervals matching the operation instruction of the figure selection request; and edit the selected metal figures according to a given editing instruction; the editing instruction includes any one or more of figure moving, figure rotating, figure stretching, and figure compressing.

[0124] Based on the same inventive concept, the embodiments of the present application provide a computer program product, which comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device having the processor to perform the operations performed by the editing method of the chip simulation circuit layout as described above.

[0125] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium, which stores at least one computer program instruction, and the at least one computer program instruction is loaded and executed by a processor to enable the processor to perform the operations performed by the editing method of the chip simulation circuit layout as described above.

[0126] Based on the same inventive concept, the embodiments of the present application further provide an electronic device, which refers to Figure 6 , shows a structural schematic diagram of the electronic device in the embodiments of the present application, and the electronic device comprises one or more memories 604, one or more processors 602, and at least one computer program (computer program instructions) stored in the memory 604 and executable on the processor 602, and the processor 602 implements the editing method of the chip simulation circuit layout as described above when executing the computer program.

[0127] In the above embodiments of the present application, Figure 6In particular embodiments, a bus architecture, represented generally by the bus 600, can include any number of interconnected buses and bridges, the bus 600 linking together various circuits including the processor 602, represented by one or more processors, and the memory 604, represented by the memory. The bus 600 can also link various other circuits together, such as peripheral devices, voltage stabilizers and power management circuits, which are well known in the art, and thus, not further described herein. The bus interface 605 provides an interface between the bus 600 and the receiver 601 and the transmitter 603. The receiver 601 and the transmitter 603 can be the same element, i.e., a transceiver, providing a means for communicating with various other apparatuses over a transmission medium. The processor 602 is responsible for managing the bus 600 and general processing, while the memory 604 can be used for storing data used by the processor 602 in executing operational processes.

[0128] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as technology evolves, the "functionalities" described herein can be implemented by various combinations of digital and / or analog hardware, and / or software.

[0129] In several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. Among them, the above-mentioned device embodiments are only schematic, for example, the division of the units can be a logical function division, and actual implementation can have another division mode, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between units or modules, which can be electrical or other forms.

[0130] The units described as separate components can or can not be physically separated, and the components of the control device can or can not be physical units, that is, they can be located in one place, or they can be distributed on multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0131] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole and / or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server or a network device, etc.) execute all and / or part of the steps of the method described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer program instructions.

[0132] The above only describes the embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. An editing method of a chip analog circuit wiring, characterized by, The method comprises: in response to a user selecting a target region in a wiring interface of a chip simulation circuit, classifying all and / or part of metal patterns falling within the target region into a target metal pattern set; based on geometric feature information of the metal patterns, clustering the metal patterns in the target metal pattern set to obtain at least one metal pattern subset, the geometric feature information comprising position information, shape information and extension direction information of the metal patterns; sorting the metal patterns in each metal pattern subset to determine an arrangement serial number for each metal pattern in the metal pattern subset, wherein the arrangement serial numbers of adjacent metal patterns are adjacent; based on the arrangement serial numbers of the metal patterns, performing batch editing on the metal patterns in any one or more metal pattern subsets in the target metal pattern set; the clustering of the metal patterns in the target metal pattern set based on the geometric feature information of the metal patterns comprises: determining the spacing between any adjacent metal patterns in the target metal pattern set according to the position information of the metal patterns; and if the spacing between the adjacent metal patterns is less than or equal to a set spacing and the shape information and extension direction information of the adjacent metal patterns are consistent, clustering the adjacent metal patterns into the same metal pattern subset.

2. The method of claim 1, wherein, the sorting of the metal patterns in each metal pattern subset comprises: determining a direction perpendicular to the extension direction of the metal patterns in the metal pattern subset as the pattern arrangement direction of the metal pattern subset; sorting the metal patterns in the metal pattern subset according to the pattern arrangement direction.

3. The method of claim 1, wherein, the geometric feature information comprises position information and shape information of the metal patterns, the position information comprising boundary coordinates of the metal patterns, and in the case that the shape information is rectangular, the clustering of the metal patterns in the target metal pattern set based on the geometric feature information of the metal patterns comprises: determining the spacing between any adjacent metal patterns in the target metal pattern set according to the position information of the metal patterns; if the spacing between the adjacent metal patterns is less than or equal to a set spacing and the absolute value of the difference between lower boundary coordinates or the absolute value of the difference between upper boundary coordinates is less than a set difference value, clustering the adjacent metal patterns into a metal pattern subset arranged in a horizontal direction; if the spacing between the adjacent metal patterns is less than or equal to a set spacing and the absolute value of the difference between left boundary coordinates or the absolute value of the difference between right boundary coordinates is less than a set difference value, clustering the adjacent metal patterns into a metal pattern subset arranged in a vertical direction.

4. The method of claim 3, wherein, the sorting of the metal patterns in each metal pattern subset comprises: if the metal pattern subset is a metal pattern subset arranged in a horizontal direction, sorting the metal patterns in the metal pattern subset in ascending order of left boundary coordinates or right boundary coordinates; If each of the metal pattern subsets is a vertically arranged metal pattern subset, the metal patterns in each of the metal pattern subsets are sorted in ascending order of the lower boundary coordinates or the upper boundary coordinates.

5. The method according to any one of claims 1 to 4, characterized in that, The batch editing of the metal patterns in the one or more metal pattern subsets in the target metal pattern set according to the arrangement numbers of the metal patterns includes: In response to a pattern coloring request, determining the pattern production process of each metal pattern subset in the one or more metal pattern subsets; If the pattern production process of any metal pattern subset is a single pattern process, rendering all the metal patterns in the metal pattern subset into a first color; If the pattern production process of any metal pattern subset is a double pattern process, rendering the metal patterns with even arrangement numbers and the metal patterns with odd arrangement numbers in the metal pattern subset into a first color and a second color, respectively; If the pattern production process of any metal pattern subset is a four-fold pattern process, rendering the metal patterns with arrangement numbers of 0+4n, 1+4n, 2+4n and 3+4n in the metal pattern subset into a first color, a second color, a third color and a fourth color, respectively; wherein n is a non-negative integer.

6. The method of claim 5, wherein, The method further includes: After the color rendering of the metal patterns in the metal pattern subset, locking the coloring information of the metal patterns in the metal pattern subset.

7. The method according to any one of claims 1 to 4, characterized in that, The batch editing of the metal patterns in the one or more metal pattern subsets in the target metal pattern set according to the arrangement numbers of the metal patterns includes: In response to a pattern selection request, selecting the metal patterns in the one or more metal pattern subsets in the target metal pattern set according to the arrangement numbers of the metal patterns and a number of pattern intervals, the number of pattern intervals matching the operation instruction of the pattern selection request; According to a given editing instruction, editing the selected metal patterns; the editing instruction includes any one or more of pattern moving, pattern rotating, pattern stretching and pattern compressing.

8. An editing device for chip analog circuit wiring, characterized in that, The device includes: A grouping unit configured to, in response to a user selecting a target region in a layout interface of a chip simulation circuit, group all and / or part of the metal patterns falling into the target region into a target metal pattern set; A clustering unit configured to, based on geometric feature information of the metal patterns, cluster the metal patterns in the target metal pattern set to obtain at least one metal pattern subset, the geometric feature information including position information, shape information and extension direction information of the metal patterns; A sorting unit configured to sort the metal patterns in each metal pattern subset to determine arrangement numbers of the metal patterns in each metal pattern subset, wherein the arrangement numbers of adjacent metal patterns are adjacent. An editing unit is configured to perform batch editing on the metal patterns in any one or more metal pattern subsets in the target metal pattern set according to the arrangement serial numbers of the metal patterns; The metal patterns in the target metal pattern set are clustered based on the geometric feature information of the metal patterns, to obtain at least one metal pattern subset, including: determining the interval between any adjacent metal patterns in the target metal pattern set according to the position information of the any adjacent metal patterns; if the interval between the any adjacent metal patterns is less than or equal to a set interval, and the shape information and the extension direction information of the any adjacent metal patterns are consistent, then the any adjacent metal patterns are clustered into the same metal pattern subset.

9. A computer program product, characterised in that, The computer program product includes computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor, so that a computer device having the processor performs the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program code, and the at least one program code is loaded and executed by the processor to realize the operations performed by the method of any one of claims 1 to 7.

11. An electronic device, comprising: The electronic device includes one or more processors and one or more memories, and the one or more memories store at least one program code, and the at least one program code is loaded and executed by the one or more processors to realize the method of any one of claims 1 to 7.

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