Clock signal calibration circuit, method, and chip

Abstract

Embodiments of the present application provide a clock signal calibration circuit, method and chip, comprising: the output end of a first clock delay module is connected with the input end of a second clock delay module through an inverter, the output end of the first clock delay module is connected with the input end of a clock information detection module through a first AND gate, the output end of the second clock delay module is connected with the input end of the clock information detection module through the first AND gate, the first clock delay module is used for receiving and adjusting an original clock signal, and outputs a first clock signal to the inverter and the first AND gate; the second clock delay module is used for receiving and adjusting the first clock signal performing logical NOT through the inverter, and outputs a second clock signal to the first AND gate; the clock information detection module is used for receiving a target clock signal, and determining a first parameter used for calibrating the target clock signal. The problem of low precision and large energy consumption of clock calibration technology is solved, and the effect of improving clock signal calibration precision and reducing energy consumption is achieved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of communication, in particular to a clock signal calibration circuit, method and chip. BACKGROUND

[0002] Clock distribution and calibration circuits are widely used in high-speed digital-analog hybrid circuits. With the continuous rise of data transmission speed, the detection and correction accuracy of clock error is increasingly demanded. However, the limitations of traditional clock calibration techniques, especially in terms of precision improvement and power consumption control, gradually emerge, especially in high-speed environments such as Serdes (Serial / Parallel Converter), traditional methods often fail to meet the clock requirements and may cause significant energy waste. SUMMARY

[0003] Embodiments of the present application provide a clock signal calibration circuit, method and chip to at least solve the problems of low precision and high energy consumption of clock calibration techniques in related technologies.

[0004] According to an embodiment of the present application, a clock signal calibration circuit is provided, comprising a first clock delay module, a second clock delay module, and a clock information detection module, wherein the output end of the first clock delay module is connected to the input end of the second clock delay module through an inverter, the output end of the first clock delay module is connected to the input end of the clock information detection module through a first AND gate, and the output end of the second clock delay module is connected to the input end of the clock information detection module through the first AND gate, the first clock delay module is configured to receive and adjust an original clock signal, and output a first clock signal to the inverter and the first AND gate; the second clock delay module is configured to receive and adjust the first clock signal performing logical negation through the inverter, and output a second clock signal to the first AND gate; and the clock information detection module is configured to receive a target clock signal, and determine a first parameter for calibrating the target clock signal, wherein the target clock signal is a clock signal obtained by the first AND gate performing logical AND operation on the first clock signal and the second clock signal.

[0005] According to another embodiment of the present application, a clock signal calibration method is provided, applied to the above-mentioned clock signal calibration circuit, comprising: receiving and adjusting an original clock signal to obtain a first clock signal; adjusting the first clock signal to obtain a second clock signal; combining the first clock signal and the second clock signal to obtain a target clock signal; and determining a first parameter for calibrating the target clock signal according to the target clock signal.

[0006] According to still another embodiment of the present application, a chip is also provided, comprising the above-mentioned clock signal calibration circuit.

[0007] Through the above embodiment of the present application, the clock signal calibration circuit is provided, the original clock signal is first adjusted by the first clock delay module, the generated first clock signal is further inverted and adjusted by the second clock delay module, and then the two adjusted signals are subjected to logical AND operation by the first AND gate to generate the target clock signal. The clock information detection module subsequently analyzes the first parameter of the target clock signal for subsequent calibration. Therefore, the problems of low precision and large energy consumption of the clock calibration technology in the related art can be solved, and the effects of improving the clock signal calibration precision and reducing the energy consumption are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a structural schematic diagram of the clock signal calibration circuit of the embodiment of the present application (one);

[0009] Figure 2 is a structural schematic diagram of the clock signal calibration circuit of the embodiment of the present application (two);

[0010] Figure 3 is a circuit structural schematic diagram of the clock delay module of the embodiment of the present application;

[0011] Figure 4 is a circuit structural schematic diagram of the clock information detection module of the embodiment of the present application;

[0012] Figure 5 is a detection waveform schematic diagram of the embodiment of the present application;

[0013] Figure 6 is a flowchart of the clock signal calibration method of the embodiment of the present application. DETAILED DESCRIPTION

[0014] Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0015] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0016] Figure 1 is a structural schematic diagram of the clock signal calibration circuit of the embodiment of the present application (one), as Figure 1 shown, the circuit 10 comprises a first clock delay module 12, a second clock delay module 14, and a clock information detection module 16, wherein the output end of the first clock delay module 12 is connected with the input end of the second clock delay module 14 through an inverter 18, the output end of the first clock delay module 12 is connected with the input end of the clock information detection module 16 through a first AND gate 20, the output end of the second clock delay module 14 is connected with the input end of the clock information detection module 16 through the first AND gate 20,

[0017] The first clock delay module 12 is configured to receive and adjust the original clock signal, and output the first clock signal to the inverter and the first AND gate;

[0018] The second clock delay module 14 is configured to receive and adjust the first clock signal performing logical NOT through the inverter, and output the second clock signal to the first AND gate;

[0019] The clock information detection module 16 is configured to receive the target clock signal, and determine the first parameter for calibrating the target clock signal, wherein the target clock signal is the clock signal performing logical AND on the first clock signal and the second clock signal by the first AND gate.

[0020] For example, the first clock delay module is responsible for receiving the original clock signal, and adjusting the original clock signal to output an adjusted signal, which is defined as the first clock signal. The first clock signal is sent to two downstream components, the inverter and the first AND gate. The first clock signal is first inverted by the inverter, and the level state of the first clock signal is reversed (for example, high level is changed to low level, and vice versa), to generate an inverted first clock signal. Then the inverted first clock signal enters the second clock delay module for secondary delay adjustment, and the generated adjusted signal is defined as the second clock signal. The first clock signal and the second clock signal are sent to the first AND gate respectively. The AND gate performs logical AND operation, that is, the output is high level only when the two input signals are high level at the same time, otherwise the output is low level. In this way, the first AND gate synthesizes the first clock signal and the second clock signal to output a target clock signal. The target clock signal is finally transmitted to the clock information detection module, and the task of the clock information detection module is to analyze the first parameter of the target clock signal, that is, the ratio of the high level duration to the whole cycle time in each cycle. Based on the detection of the first parameter, the clock information detection module can determine the calibration requirement, and then adjust the signal to optimize its performance.

[0021] In an example embodiment, the clock information detection module 16 is further configured to determine the first parameter according to the reference clock signal and the target clock signal, convert the first parameter into a first control signal code and a second control signal code for calibrating the target clock signal, output the first control signal code to the first clock delay module, and output the second control signal code to the second clock delay module;

[0022] The first clock delay module 12 is further configured to receive the first control signal code, and adjust the original clock signal according to the first control signal code;

[0023] The second clock delay module 14 is further configured to receive the second control signal code, and adjust the first clock signal performing logical NOT through the inverter according to the second control signal code.

[0024] For example,Figure 2 is a structural schematic diagram of a clock signal calibration circuit according to an embodiment of the present application (II), as shown in Figure 2 The original clock signal CLK A is passed through the first clock delay chain to generate an adjusted clock signal CLK A H1. Subsequently, the CLK A H1 signal is inverted and passed through the delay chain again to form another adjusted signal CLK A L1. Finally, the logic AND gate combines the CLK A H1 and CLK A L1 signals to obtain the target clock signal CLK A F, completing the signal synthesis process. The clock information detection module inside determines the first parameter using the reference clock signal CLK A R and CLK A F, converts the first parameter into the first control signal code CODE LH and the second control signal code CODE HL used to calibrate the target clock signal, and outputs CODE LH and CODE HL to the two CLK_DELAYLANEs, respectively.

[0025] In an example embodiment, the clock information detection module 16 is further configured to determine the first parameter according to a second parameter between the reference clock signal and the target clock signal, wherein the first parameter comprises at least one of the following: duty cycle, phase, and the second parameter comprises at least one of the following: frequency offset, phase difference.

[0026] For example, the clock information detection module can be combined with Figure 2 For example, taking the duty cycle as the first parameter and the frequency offset as the second parameter, the clock information detection module uses the frequency information of CLK A R and CLK A F to obtain the high level time and low level time of CLK A F. By adjusting CODE HL and CODE LH, the high level time and low level time of CLK A F are made to reach a predetermined ratio, and the duty cycle of CLK A F is adjusted to the desired value.

[0027] In an example embodiment, the first control signal code is used to adjust the delay time of the rising edge of the original clock signal, and the second control signal code is used to adjust the delay time of the falling edge of the first clock signal subjected to logical NOT by the inverter,

[0028] The first control signal code or the second control signal code is composed of X sub-control signal codes, and X is a positive integer.

[0029] For example, the clock information detection module can be combined with Figure 2 The delay chain controlled by CODE LH is used to adjust the rising edge, and the delay chain controlled by CODE HL is used to adjust the falling edge.

[0030] In one example embodiment, the first clock delay module or the second clock delay module comprises a first P-type metal oxide semiconductor field effect transistor (MP), a first N-type metal oxide semiconductor field effect transistor (MN), a second MN, and X MN groups, wherein the MN group comprises a first sub-MN and a second sub-MN, the first sub-MN and the second sub-MN are connected in series, X is a positive integer,

[0031] a gate of the first MP is connected to a clock input, a source of the first MP is connected to a power supply, and a drain of the first MP is connected to a clock output,

[0032] a gate of the first MN is connected to the clock input, a source of the first MN is connected to the clock output, and a drain of the first MN is connected to a ground,

[0033] a gate of the second MN is connected to a first sub-control signal code, a source and a drain of the second MN are connected to the clock output,

[0034] a gate of the first sub-MN in the Xth MN group is connected to an (X+1)th sub-control signal code, a source of the first sub-MN is connected to a drain of the second sub-MN, a drain of the first sub-MN is connected to the clock output, and a gate and a source of the second sub-MN are connected to the ground.

[0035] An example, Figure 3 is a circuit structure schematic diagram of a clock delay module of an embodiment of the present application, such as Figure 3As shown, the substrates of all N-type metal-oxide-semiconductor field-effect transistors (NMOS) are connected to ground, and the wells of all P-type metal-oxide-semiconductor field-effect transistors (PMOS) are connected to the power supply. The gate of the P-type MOS transistor MP1 (first MP) is connected to the clock input CLKIN, the source is connected to the power supply, and the drain is connected to the output CLKOUT; the gate of the N-type MOS transistor MN1 (first MN) is connected to the clock input CLKIN, the drain is grounded, and the source is connected to the output CLKOUT; the gate of MN2 (second MN) is connected to the control signal CODE. <1> The source and drain are connected to the output signal CLKOUT, and the gate of MN1_1 (the first sub-MN in the first MN group) is connected to the control signal CODE. <2> The drain is connected to the output signal CLKOUT, and the source is connected to the drain of MN1_2 (the second sub-MN in the first MN group); the gate and source of MN1_2 are connected to ground; the gate of the subsequent MN X_1 (the first sub-MN in the Xth MN group) is connected to the control signal CODE.<X+1> (X+1th sub-control signal code), the drain is connected to the output signal CLKOUT, and the source is connected to the drain of MN X_2 (the second sub-MN in the Xth MN group); the gate and source of MN X_2 are connected to ground; the delay time is adjusted by adjusting the control signal.

[0036] For example, it can be combined Figure 3 The first control signal code or the second control signal code can be generated by CODE. <1> CODE <2> ...CODE <x>The composition, wherein X is a positive integer.

[0037] In one example embodiment, the clock information detection module comprises a D flip-flop, a first sub-AND gate and a counter, wherein the D terminal of the D flip-flop is connected to the target clock signal, the R terminal of the D flip-flop is connected to the reset signal, the CLK terminal is connected to the reference clock signal, the Q terminal of the D flip-flop is connected to the input terminal of the second AND gate, the output terminal of the second AND gate is connected to the input terminal of the counter,

[0038] The D flip-flop is used to output a third clock signal to the second AND gate according to the signal state of the sampled target clock signal,

[0039] The second AND gate is used to receive the third clock signal, perform logical AND operation between the third clock signal and the reference clock, and output a pulse clock signal to the counter, wherein the pulse clock signal stores the first parameter,

[0040] The counter is used to receive the pulse clock signal and determine the first parameter according to the pulse clock signal.

[0041] An example, Figure 4 is a circuit structure schematic diagram of the clock information detection module of the embodiment of the present application, as Figure 4 shown, the sampling circuit can use a D flip-flop, the D terminal of the D flip-flop is connected to the target clock signal CLKA_F, the R terminal is connected to the reset signal CLKA_RST, the CLK terminal is connected to the reference clock signal CLKA_R, and the Q terminal outputs a third clock signal. Taking the first parameter as the duty cycle and the second parameter as the frequency offset as an example, the second AND gate performs logical AND operation between the third clock signal and the reference clock, and outputs a pulse clock signal CLKA_D to the counter, which stores the duty cycle information. The counter determines the duty cycle information according to the pulse clock signal, and the clock information detection module adjusts the code value (control signal code) to control the duty cycle of CLKA_F according to the duty cycle information until the duty cycle is adjusted to the expected value. It is worth noting that the frequency of the reference clock CLKA_R should be slightly deviated from the frequency of the target clock CLKA_F, but the deviation amount should be kept within a very small range. This is because the detection accuracy is directly affected by the difference between the two signals, and a smaller frequency deviation can provide higher detection accuracy.

[0042] Figure 5 is a detection waveform schematic diagram of the embodiment of the present application, as Figure 5 shown, taking the first parameter as the duty cycle and the second parameter as the frequency offset as an example, the sampling results generated by capturing the frequency deviation between CLKA_R and CLKA_F are combined in the AND gate to generate a pulse signal with a specific duration. Subsequently, the number of pulse signals is counted by the counter, and finally a control code value closely related to the duty cycle of CLKA_F is formed. The whole detection and adjustment process is a closed loop feedback, which ensures the high precision and stability of the clock signal.

[0043] Through the embodiments of the present application, a clock signal calibration circuit is provided, which combines layout and routing strategies, realizes the optimization target of low power consumption and high precision, has the ability to adjust any clock signal parameter, and shows applicability and flexibility. Secondly, the circuit can measure the duty cycle and other key information of the clock signal with high accuracy, and can meet the requirements of the clock in high-speed interface chips. Finally, the circuit effectively reduces the dependence on the quality of the reference clock signal, relaxes the quality requirements, and ensures the accuracy and efficiency of the calibration process.

[0044] In the present embodiment, a clock signal calibration method is provided, which can be applied to the clock signal calibration circuit in the above embodiments, Figure 6 is a flowchart of the clock signal calibration method of the embodiments of the present application, as Figure 6 shown, the flow includes the following steps:

[0045] Step S602, receiving and adjusting the original clock signal to obtain a first clock signal.

[0046] Exemplarily, a series of processing and adjustment can be performed on the initially received original clock signal to improve its performance or make it meet the technical requirements to obtain the first clock signal.

[0047] Step S604, adjusting the first clock signal to obtain a second clock signal.

[0048] Exemplarily, after the adjustment of the first clock signal, the first clock signal that has been preliminarily optimized can be processed and fine-tuned again according to further performance requirements or system requirements, so as to obtain the second clock signal.

[0049] Step S606, combining the first clock signal and the second clock signal to obtain a target clock signal.

[0050] Exemplarily, the first clock signal and the second clock signal can be combined by an AND gate to obtain the target clock signal.

[0051] Step S608, determining a first parameter for calibrating the target clock signal according to the target clock signal.

[0052] Exemplarily, by determining the first parameter for calibrating the target clock signal according to the target clock signal, the target clock signal is calibrated by using the first parameter, so as to ensure that its timing accuracy, frequency stability and signal integrity meet the performance requirements of the circuit or system.

[0053] In an exemplary embodiment, step S608 includes:

[0054] determining a first parameter according to the reference clock signal and the target clock signal;

[0055] converting the first parameter into a first control signal code and a second control signal code used for calibrating the target clock signal.

[0056] For example, the first parameter is determined by measuring and analyzing the reference clock signal and the target clock signal, and then the parameter is converted into a control signal code which can be recognized and executed by a clock calibration circuit to realize accurate fine tuning of the target clock signal.

[0057] In an example embodiment, determining the first parameter according to the reference clock signal and the target clock signal comprises:

[0058] determining the first parameter according to a second parameter between the reference clock signal and the target clock signal, wherein the first parameter comprises at least one of a duty cycle and a phase, and the second parameter comprises at least one of a frequency offset and a phase difference.

[0059] For example, the duty cycle of the target clock signal is determined by using the frequency offset between the reference clock signal and the target clock signal, taking the duty cycle as the first parameter and the frequency offset as the second parameter.

[0060] In an example embodiment, adjusting the original clock signal comprises:

[0061] adjusting the original clock signal according to the first control signal code.

[0062] For example, the original clock signal can be adjusted according to the first control signal code to obtain the first clock signal.

[0063] In an example embodiment, adjusting the first clock signal comprises:

[0064] adjusting the first clock signal according to the second control signal code.

[0065] For example, the first clock signal can be adjusted according to the second control signal code to obtain the second clock signal.

[0066] According to the embodiments of the present application, a clock signal calibration method is provided, which receives and adjusts an original clock signal to obtain a first clock signal, adjusts the first clock signal to obtain a second clock signal, combines the first clock signal and the second clock signal to obtain a target clock signal, and determines a first parameter used for calibrating the target clock signal according to the target clock signal, so as to solve the problems of low precision and high energy consumption of clock calibration technology, and achieve the effects of improving the calibration precision of the clock signal and reducing energy consumption.

[0067] Those skilled in the art can clearly understand that the method according to the above-mentioned embodiments can be realized by means of software and necessary general hardware platforms, and of course, can also be realized by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk) and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device) to execute the method of each embodiment of the present application.

[0068] In the present embodiment, a chip is also provided, which is used to realize the above-mentioned embodiments and preferred embodiments, and has been described above and will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that realizes a predetermined function. Although the chip described in the following embodiments is preferably realized in software, realization by hardware or a combination of software and hardware is also possible and is contemplated.

[0069] For example, the chip can be various high-speed data transmission circuit chips, such as 112 / 224G Serdes, 50GPON, etc.

[0070] In the embodiments of the present application, the above-mentioned chip can also include different modules, and the naming and function division of the modules can also be selected in different ways according to actual conditions, which are not specifically limited here.

[0071] It should be noted that the above-mentioned modules can be realized by software or hardware, and for the latter, the following implementation methods can be used, but are not limited thereto: the above-mentioned modules are located in the same processor; or the above-mentioned modules are located in different processors in any combination.

[0072] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above-mentioned method embodiments when running.

[0073] In an exemplary embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0074] The embodiment of the present application further provides an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the above method embodiments.

[0075] In an example embodiment, the electronic device further comprises a transmission device connected to the processor and an input / output device connected to the processor.

[0076] The embodiment of the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps in any of the above method embodiments.

[0077] In an example embodiment, the computer program product comprises a non-volatile computer readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the steps in the method of the embodiments of the present application.

[0078] The specific examples in the embodiments can refer to the examples described in the above embodiments and example embodiments, and the embodiments will not be described here again.

[0079] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, and they can be realized by program codes executable by computing devices, so that they can be stored in storage devices and executed by computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

[0080] The above is only the preferred embodiment of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the present application shall be included in the protection scope of the present application.< / x>

Claims

1. A clock signal calibration circuit, characterized by, The clock information detection module is used for receiving a target clock signal, and determining a first parameter used for calibrating the target clock signal, wherein the target clock signal is a clock signal obtained by performing logical AND on the first clock signal and the second clock signal by the first AND gate. The first clock delay module is used for receiving and adjusting an original clock signal, and outputting a first clock signal to the inverter and the first AND gate. The second clock delay module is used for receiving and adjusting the first clock signal performing logical NOT by the inverter, and outputting a second clock signal to the first AND gate. The clock information detection module is used for receiving a target clock signal, and determining a first parameter used for calibrating the target clock signal, wherein the target clock signal is a clock signal obtained by performing logical AND on the first clock signal and the second clock signal by the first AND gate. The D flip-flop is used for outputting a third clock signal to the second AND gate according to a signal state of the sampled target clock signal. The second AND gate is used for receiving the third clock signal, performing logical AND on the third clock signal and the reference clock, and outputting a pulse clock signal to the counter, wherein the pulse clock signal stores the first parameter. The counter is used for receiving the pulse clock signal, and determining the first parameter according to the pulse clock signal.

2. The circuit of claim 1, wherein The clock information detection module is further used for determining the first parameter according to a reference clock signal and the target clock signal, converting the first parameter into a first control signal code and a second control signal code used for calibrating the target clock signal, outputting the first control signal code to the first clock delay module, and outputting the second control signal code to the second clock delay module. The first clock delay module is further used for receiving the first control signal code, and adjusting the original clock signal according to the first control signal code. The second clock delay module is further used for receiving the second control signal code, and adjusting the first clock signal performing logical NOT by the inverter according to the second control signal code.

3. The circuit of claim 2, wherein The clock information detection module is further used for determining the first parameter according to a second parameter between the reference clock signal and the target clock signal, wherein the first parameter comprises at least one of a duty cycle and a phase, and the second parameter comprises at least one of a frequency offset and a phase difference. ​ 4. The circuit of claim 2, wherein ​ The first control signal code is used to adjust the delay time of the rising edge of the original clock signal, and the second control signal code is used to adjust the delay time of the falling edge of the first clock signal performing logical NOT through the inverter, The first control signal code or the second control signal code is composed of X sub-control signal codes, and X is a positive integer.

5. The circuit of claim 1, wherein, The first clock delay module or the second clock delay module comprises a first P-type metal oxide semiconductor field effect transistor, a first N-type metal oxide semiconductor field effect transistor, a second N-type metal oxide semiconductor field effect transistor and an X N-type metal oxide semiconductor field effect transistor group, wherein the N-type metal oxide semiconductor field effect transistor group comprises a first sub-N-type metal oxide semiconductor field effect transistor and a second sub-N-type metal oxide semiconductor field effect transistor, and the first sub-N-type metal oxide semiconductor field effect transistor and the second sub-N-type metal oxide semiconductor field effect transistor are connected in series, and X is a positive integer, The gate of the first P-type metal oxide semiconductor field effect transistor is connected to a clock input, the source of the first P-type metal oxide semiconductor field effect transistor is connected to a power supply, and the drain of the first P-type metal oxide semiconductor field effect transistor is connected to a clock output. The gate of the first N-type metal oxide semiconductor field effect transistor is connected to the clock input, the source of the first N-type metal oxide semiconductor field effect transistor is connected to the clock output, and the drain of the first N-type metal oxide semiconductor field effect transistor is connected to ground. The gate of the second N-type metal oxide semiconductor field effect transistor is connected to a first sub-control signal code, and the source and drain of the second N-type metal oxide semiconductor field effect transistor are connected to the clock output. The gate of the first sub-N-type metal oxide semiconductor field effect transistor in the X N-type metal oxide semiconductor field effect transistor group is connected to an X+1 sub-control signal code, the source of the first sub-N-type metal oxide semiconductor field effect transistor is connected to the drain of the second sub-N-type metal oxide semiconductor field effect transistor, the drain of the first sub-N-type metal oxide semiconductor field effect transistor is connected to the clock output, and the gate and source of the second sub-N-type metal oxide semiconductor field effect transistor are connected to ground.

6. A clock signal calibration method, characterized by, The clock signal calibration circuit of claim 1 comprises: receiving and adjusting an original clock signal to obtain a first clock signal; adjusting the first clock signal to obtain a second clock signal; combining the first clock signal and the second clock signal to obtain a target clock signal; determining a first parameter for calibrating the target clock signal according to the target clock signal.

7. The method of claim 6, wherein, Determining a first parameter for calibrating the target clock signal according to the target clock signal comprises: determining the first parameter according to a reference clock signal and the target clock signal; converting the first parameter into a first control signal code and a second control signal code for calibrating the target clock signal.

8. The method of claim 7, wherein, Determining a first parameter for calibrating the target clock signal according to the target clock signal comprises: The first parameter is determined according to a second parameter between the reference clock signal and the target clock signal, wherein the first parameter comprises at least one of a duty cycle, a phase, and the second parameter comprises at least one of a frequency offset, a phase difference.

9. The method of claim 7, wherein, Adjusting the original clock signal comprises: Adjusting the original clock signal according to the first control signal code.

10. The method of claim 7, wherein, Adjusting the first clock signal comprises: Adjusting the first clock signal according to the second control signal code.

11. A chip, characterized by A clock signal calibration circuit comprising any one of claims 1-5.

Images