Electronic device

Abstract

An electronic device includes a display panel and an electronic module. The display panel includes a first region and a second region, and the first region includes a first sub-region and a second sub-region having a lower light transmittance than a light transmittance of the first sub-region. The electronic module is under the display panel and corresponds to the first area. The display panel includes: a first light emitting element in a first sub-region; a first pixel circuit connected to the first light emitting element and located in the second sub-region; a second light emitting element in the second sub-region; a second pixel circuit connected to the second light emitting element and located in the second sub-region; and a connection line connecting the first light emitting element and the first pixel circuit.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to electronic devices that improve productivity. Background Technology

[0002] The electronic device can be a device comprising various electronic components such as a display panel and an electronic module. The electronic module may include a camera, an infrared detection sensor, and / or a proximity sensor. The electronic module may be disposed below the display panel. The transmittance of a portion of the display panel may be higher than that of another portion of the display panel. The electronic module can receive external input through this portion of the display panel, or can provide output through this portion of the display panel. Summary of the Invention

[0003] The embodiments of this disclosure described herein provide an electronic device that improves productivity and the performance of electronic modules.

[0004] According to one or more embodiments of the present disclosure, an electronic device includes: a display panel including a first region and a second region adjacent to the first region, wherein the first region includes a first sub-region and a second sub-region having a lower light transmittance than the first sub-region; and an electronic module located below the display panel and corresponding to the first region.

[0005] The display panel includes: a first light-emitting element in a first sub-region; a first pixel circuit connected to the first light-emitting element and in a second sub-region; a second light-emitting element in the second sub-region; a second pixel circuit connected to the second light-emitting element and in the second sub-region; and a connecting line connecting the first light-emitting element and the first pixel circuit.

[0006] The connecting line includes: a first connecting line on a first layer; and a second connecting line on a second layer covering the first connecting line. The first connecting line has a different length than the second connecting line.

[0007] According to one or more embodiments of the present disclosure, an electronic device includes: a display panel including a first region and a second region adjacent to the first region, wherein the first region includes a first sub-region and a second sub-region having a lower light transmittance than the first sub-region; and an electronic module located below the display panel and corresponding to the first region.

[0008] The display panel includes: a first light-emitting element in a first sub-region; a first pixel circuit connected to the first light-emitting element and located in a second sub-region; a second light-emitting element in the second sub-region; a second pixel circuit connected to the second light-emitting element and located in the second sub-region; and a connecting line connecting the first light-emitting element and the first pixel circuit.

[0009] The connection line includes: a first connection line extending from the second sub-region to the first sub-region; and a second connection line extending from the second sub-region through the second region to the first sub-region. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0012] Figure 2 This is an exploded perspective view illustrating some components of an electronic device according to one or more embodiments of the present disclosure.

[0013] Figure 3 This is a cross-sectional view illustrating a display module according to one or more embodiments of the present disclosure.

[0014] Figure 4 This is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0015] Figure 5 This is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0016] Figure 6A This is a plan view illustrating a display panel according to one or more embodiments of the present disclosure.

[0017] Figure 6B By magnification Figure 6A The image shown is an enlarged view of a portion of the display panel.

[0018] Figure 7 This is a view illustrating the arrangement of connecting lines according to one or more embodiments of the present disclosure.

[0019] Figure 8 This is a block diagram illustrating the arrangement of the first to third connecting lines according to one or more embodiments of the present disclosure.

[0020] Figure 9A and Figure 9B This is a view illustrating the cross-sectional structure of a first sub-area, a second sub-area, and a second area of ​​a display panel according to one or more embodiments of the present disclosure.

[0021] Figure 10 This is a block diagram illustrating the arrangement of the first to third connecting lines according to one or more embodiments of the present disclosure.

[0022] Figure 11A and Figure 11BThis is a view illustrating the cross-sectional structure of the first and second regions of a display panel according to one or more embodiments of the present disclosure.

[0023] Figure 12 This is a block diagram illustrating the lengths of the first to third connecting lines according to one or more embodiments of the present disclosure.

[0024] Figure 13A and Figure 13B This is a cross-sectional view illustrating a first connecting line and a second connecting line according to one or more embodiments of the present disclosure.

[0025] Figure 14 This is a view illustrating the shape of a first region according to one or more embodiments of the present disclosure and the arrangement of connecting lines caused by that shape.

[0026] Figure 15 This is a view illustrating the shape of a first region according to one or more embodiments of the present disclosure and the arrangement of connecting lines caused by that shape.

[0027] Figure 16 This is a view illustrating the shape of a first region according to one or more embodiments of the present disclosure and the arrangement of connecting lines caused by that shape. Detailed Implementation

[0028] In this specification, the statements that a first component (or area, layer, or portion) is "on" a second component, "connected to" or "attached to" a second component mean that the first component is directly on, directly connected to, or attached to the second component, or that a third component is inserted between them.

[0029] The same reference numerals will be assigned to the same parts. Additionally, in the figures, the thickness, scale, and dimensions of parts may be exaggerated to effectively describe technical features. The term "and / or" includes any and all combinations of one or more related parts.

[0030] Although the terms “first” or “second” may be used to describe various components, these components should not be construed as being limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0031] Furthermore, the terms "below," "at the bottom," "above," and "upper" are used to describe the relationships between the components illustrated in the accompanying drawings. These terms are relative and will be described with reference to the directions indicated in the drawings.

[0032] It will be further understood that the terms “comprising,” “including,” or “having,” and variations thereof, specify the presence of the described features, quantities, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof.

[0033] Unless otherwise specified, all terms (including technical and scientific terms) used in this specification shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in a common dictionary) shall be understood to have the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0034] Furthermore, in this specification, the terms "in a plane" or "in a plan view" mean the target portion viewed from the top, and the term "in a cross section" means the cross section formed by vertically cutting the target portion viewed from the side.

[0035] For the purposes of this disclosure, expressions such as “at least one of…”, “one of…”, and “selected from…” modify the entire list of elements when placed after or before the list of elements, and do not modify any individual element in the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, XZ, and YZ) or any variations thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. Furthermore, the use of “may” in describing embodiments of this disclosure means “one or more embodiments of this disclosure”.

[0036] Those skilled in the art will appreciate that, in view of the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0037] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings.

[0038] Figure 1 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0039] refer to Figure 1 The electronic device 1000 can be activated in response to an electrical signal. For example, the electronic device 1000 can be a cellular phone, tablet computer, monitor, television, car navigation system, game console, and / or wearable device. Although Figure 1 The illustration shows electronic device 1000 as a cellular phone, but this disclosure is not limited thereto.

[0040] Electronic device 1000 can display image IM via effective area 10DA. Effective area 10DA may include a plane defined in a first direction DR1 and a second direction DR2. Effective area 10DA may further include curved surfaces bending from at least two sides of the plane. However, the shape of effective area 10DA is not limited thereto. For example, effective area 10DA may consist only of a plane. Alternatively, effective area 10DA may further include four curved surfaces bending from at least two sides of the plane (e.g., four sides of the plane).

[0041] The effective area 10DA can include a first area 10SA (or referred to as the "sensing area") and a second area 10NSA (or referred to as the "non-sensing area"). Although Figure 1 The figure illustrates a first region 10SA, but the number of first regions 10SA is not limited thereto. The first region 10SA may be part of an effective region 10DA. Accordingly, the electronic device 1000 can display an image through the first region 10SA. A second region 10NSA is configured to be adjacent to the first region 10SA. According to one or more embodiments of this disclosure, the first region 10SA may be surrounded by the second region 10NSA. The first region 10SA may have a higher transmittance than the second region 10NSA. The electronic device 1000 can receive or transmit optical signals through the first region 10SA.

[0042] The electronic device 1000 may include an electronic module disposed in a region overlapping with the first region 10SA. The electronic module may receive or output optical signals provided from the outside via the first region 10SA. For example, the electronic module may refer to a sensor for measuring the distance between an object and a smartphone (e.g., a camera module or proximity sensor), a sensor for identifying a part of the user's body (e.g., fingerprint, iris, or face), or a small light that outputs light, but this disclosure is not limited thereto.

[0043] The thickness direction of the electronic device 1000 can be a third direction DR3, which is the normal direction of the effective area 10DA. The front surface (or top surface) and rear surface (or bottom surface) of each component constituting the electronic device 1000 can be defined based on the third direction DR3.

[0044] Figure 2This is an exploded perspective view illustrating some components of an electronic device according to one or more embodiments of the present disclosure.

[0045] refer to Figure 2 The electronic device 1000 may include a display device (or display module) DM and an electronic module CM. The display module DM can generate images and sense input applied from the outside. The electronic module CM is disposed below the display module DM.

[0046] The display module DM may include a display area DD_DA and a peripheral area DD_NA. The display area DD_DA may correspond to... Figure 1 The effective area 10DA is shown in the figure. The display area DD-DA may include a first area DD_SA and a second area DD_NSA. The first area DD_SA of the display area DD_DA may be defined as a sensing area, and the sensing area DD_SA may have a higher transmittance than the second area DD_NSA of the display area DD_DA (hereinafter referred to as the "non-sensing area" (or "normal area")). Accordingly, the sensing area DD_SA can provide external natural light to the electronic module CM. Because the sensing area DD_SA is part of the display area DD_DA, the sensing area DD_SA can display an image.

[0047] Pixel PX is arranged in the display area DD_DA. In other words, pixel PX is set in each of the first area DD_SA and the second area DD_NSA. However, pixel PX can have different configurations in the first area DD_SA and the second area DD_NSA. Details will be omitted below.

[0048] Figure 3 This is a cross-sectional view illustrating a display module according to one or more embodiments of the present disclosure.

[0049] refer to Figure 3 The display module DM may include a display panel DP, an input sensor layer ISP, an anti-reflective layer 300, and a window 400. The anti-reflective layer 300 and the window 400 may be connected to each other via an adhesive layer AD.

[0050] Display panel DP can be the component used to actually generate the image. Display panel DP can be an emissive display panel. For example, display panel DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, a micron-LED display panel, or a nano-LED display panel. Display panel DP can be referred to as a display layer.

[0051] The display panel DP may include a substrate layer BL, a circuit layer DP_CL, a light-emitting element layer DP_ED, and a packaging layer TFE.

[0052] The substrate layer BL can be a component that provides a substrate surface for setting the circuit layer DP_CL. The substrate layer BL can be a rigid substrate or a flexible substrate that allows bending, folding, and / or rolling. The substrate layer BL can be a glass substrate, a metal substrate, and / or a polymer substrate. However, this disclosure is not limited thereto, and the substrate layer BL can be an inorganic layer, an organic layer, or a composite material layer.

[0053] The substrate layer BL can have a multilayer structure. For example, the substrate layer BL may include a first synthetic resin layer, a multilayer or single-layer inorganic layer, and a second synthetic resin layer disposed on the inorganic layer. Each of the first and second synthetic resin layers may include a polyimide resin, but this disclosure is not limited thereto.

[0054] The circuit layer DP_CL can be set on the base layer BL. The circuit layer DP_CL may include insulating layers, semiconductor patterns, conductive patterns, and / or signal lines.

[0055] The light-emitting element layer DP_ED can be disposed on the circuit layer DP_CL. The light-emitting element layer DP_ED can include light-emitting elements. For example, light-emitting elements can include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, micron LEDs and / or nano LEDs.

[0056] A TFE encapsulation layer can be disposed on the DP_ED light-emitting element layer. The TFE encapsulation layer protects the DP_ED light-emitting element layer from moisture, oxygen, and / or foreign matter such as dust particles. The TFE encapsulation layer may include at least one inorganic layer. The TFE encapsulation layer may include a stacked structure of inorganic / organic / inorganic layers.

[0057] The input sensor layer (ISP) can be located on the display panel (DP). The ISP can sense external input applied from the outside. External input can be user input. User input can include various types of external input such as a part of the user's body, light, heat, pen, and / or pressure.

[0058] The input sensor layer (ISP) can be fabricated on the display panel (DP) through a continuous process. In this case, the input sensor layer (ISP) can be directly fabricated on the display panel (DP) (specifically, the encapsulation layer TFE). The term "directly fabricated" in this context indicates that no third component (e.g., adhesive component) is inserted between the input sensor layer (ISP) and the display panel (DP). In other words, a separate adhesive component is not required between the input sensor layer (ISP) and the display panel (DP).

[0059] The anti-reflective layer 300 can be directly disposed on the input sensor layer ISP. The anti-reflective layer 300 reduces the reflectivity of external light incident from outside the display module DM. The anti-reflective layer 300 can be formed on the input sensor layer ISP through a continuous process. The anti-reflective layer 300 may include color filters. The color filters can have a specific arrangement. For example, the color filters can be arranged considering the color of light emitted from pixels included in the display panel DP. Furthermore, the anti-reflective layer 300 may further include a black matrix adjacent to the color filters. Details of the anti-reflective layer 300 will be described in detail later.

[0060] According to one or more embodiments of this disclosure, the positions of the input sensor layer ISP and the anti-reflection layer 300 may be interchanged.

[0061] According to one or more embodiments of this disclosure, the display module DM may further include an optical layer disposed on the antireflective layer 300. For example, the optical layer may be formed on the antireflective layer 300 by a continuous process. The optical layer can improve the front brightness of the display module DM by controlling the direction of light incident from the display panel DP. For example, the optical layer may include an organic insulating layer having openings defined corresponding to the light-emitting areas of pixels included in the display panel DP, and a high-refractive-index layer filling these openings while covering the organic insulating layer. The high-refractive-index layer may have a refractive index higher than that of the organic insulating layer.

[0062] Window 400 can provide electronic device 1000 (see Figure 1 The front surface of the window 400. The window 400 may include a glass film and / or a synthetic resin film as a base film. The window 400 may further include an anti-reflective film and / or an anti-fingerprint film. The window 400 may include a glass film and / or a synthetic resin film. The window 400 may further include a peripheral area DD_NA (see [link to peripheral area]) of the display module DM. Figure 2 Overlapping border patterns.

[0063] Figure 4 This is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0064] refer to Figure 4 The display panel DP may include a display area DP_DA defined within the display panel DP and a non-display area DP_NDA adjacent to the display area DP_DA. The display area DP_DA and the non-display area DP_NDA may be distinguished depending on the presence of a pixel PX. Pixel PX is disposed within the display area DP_DA. The non-display area DP_NDA may include a scan driver SDV, a data driver, and a light-emitting driver EDV. The data driver may be a portion of the circuitry included in the driver chip DIC.

[0065] The display area DP_DA can include a first area DP_SA and a second area DP_NSA. The first area DP_SA can correspond to... Figure 1 The first region 10SA is shown in the figure, and the second region DP_NSA can correspond to Figure 1 The figure shows the second region 10NSA. The first region DP_SA can have a higher transmittance than the second region DP_NSA. Details of the first region DP_SA and the second region DP_NSA will be described later.

[0066] The display panel (DP) includes pixels (PX), initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, light emission control lines ECL1 to ECLm, data lines DL1 to DLn, first control line CSL1 and second control line CSL2, drive voltage line PL, and multiple pads (PD). In this case, "m" and "n" are natural numbers equal to or greater than "2".

[0067] Pixel PX is connected to the initialization scan lines GIL1 to GILm, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, the black scan lines GBL1 to GBLm, the light emission control lines ECL1 to ECLm, and the data lines DL1 to DLn.

[0068] Initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, and black scan lines GBL1 to GBLm can extend along the first direction DR1 and can be electrically connected to the scan driver SDV. Data lines DL1 to DLn can extend along the second direction DR2 and can be electrically connected to the driver chip DIC. Light emission control lines ECL1 to ECLm can extend along the first direction DR1 and can be electrically connected to the light emission driver EDV.

[0069] The driving voltage line PL may include a portion extending in a first direction DR1 and a portion extending in a second direction DR2. The portions extending in the first direction DR1 and the portions extending in the second direction DR2 may be disposed on different layers. The driving voltage line PL can supply driving voltage to the pixel PX.

[0070] The first control line CSL1 can be connected to the scan driver SDV, and the second control line CLS2 can be connected to the light-emitting driver EDV.

[0071] When viewed in a plan view, the pad PD can be positioned adjacent to the lower end of the non-display area DP_NDA. The driver chip DIC, drive voltage line PL, first control line CSL1, and second control line CSL2 can be electrically connected to the pad PD. The flexible circuit board FCB can be electrically connected to the pad PD through an anisotropic conductive adhesive layer.

[0072] although Figure 4 The illustration shows the driver chip DIC mounted on the non-display area DP_NDA of the display panel DP, but this disclosure is not limited thereto. For example, the driver chip DIC can be mounted on a flexible circuit board FCB.

[0073] Figure 5 This is a circuit diagram of pixel PXij according to one or more embodiments of the present disclosure.

[0074] Figure 5 The diagram illustrates multiple pixels PX (see...). Figure 4 The equivalent circuit diagram of pixel PXij is shown below. Since each of the multiple pixels PX has the same equivalent circuit structure, the circuit structure of pixel PXij will be described representatively, and the details of the remaining pixels PX will be omitted.

[0075] refer to Figure 4 and Figure 5 Pixel PXij can be connected to the i-th data line DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th light emission control line ECLj among the light emission control lines ECL1 to ECLm, the first driving voltage line VL1 and the second driving voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4. In this case, "i" can be an integer ranging from "1" to "n", and "j" can be an integer ranging from "1" to "m".

[0076] Pixel PXij includes a light-emitting element ED and a pixel circuit PDC. The light-emitting element ED can be a light-emitting diode (i.e., an LED). According to one or more embodiments of this disclosure, the light-emitting element ED can be an organic light-emitting diode (OLED) including an organic light-emitting layer, but this disclosure is not limited thereto. The pixel circuit PDC can control the amount of current flowing through the light-emitting element ED in accordance with a data signal Di. The light-emitting element ED can emit light with a specific brightness in accordance with the amount of current supplied from the pixel circuit PDC.

[0077] The pixel circuit PDC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as at least one capacitor Cst. The configuration of the pixel circuit PDC according to this disclosure is not limited to... Figure 5 The embodiment shown in the figure. Figure 5 The pixel circuit PDC shown in the figure is only an example, and the configuration of the pixel circuit PDC can be modified and implemented.

[0078] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 can be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be low-temperature polycrystalline silicon (LTPS) transistors.

[0079] In detail, the first transistor T1, which directly affects the brightness of the light-emitting element ED, can be configured to include a semiconductor layer formed of polycrystalline silicon with higher reliability, and thus, a high-resolution electronic device can be realized. At least one of the third transistor T3 and the fourth transistor T4, which is connected to the gate electrode of the first transistor T1, can include an oxide semiconductor to prevent leakage current from flowing into the gate electrode of the first transistor T1.

[0080] Some of the transistors from the first transistor T1 to the seventh transistor T7 may be P-type transistors, and the remaining transistors may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors. However, this disclosure is not limited thereto. For example, all of the first transistors T1 to the seventh transistor T7 may be either P-type or N-type transistors. Alternatively, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-type transistors.

[0081] The j-th initialization scan line GILj, the j-th compensation scan line GCLj, the j-th write scan line GWLj, the j-th black scan line GBLj, and the j-th light emission control line ECLj can respectively transmit the j-th initialization scan signal GIj, the j-th compensation scan signal GCj, the j-th write scan signal GWj, the j-th black scan signal GBj, and the j-th light emission control signal EMj to pixel PXij. The i-th data line DL transmits the i-th data signal Di to pixel PXij. The data signal Di can have the same characteristics as when it is input to electronic device 1000 (see...). Figure 1 The voltage level corresponding to the image signal in the image.

[0082] The first driving voltage line VL1 and the second driving voltage line VL2 can respectively transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij. Furthermore, the first initialization voltage line VL3 and the second initialization voltage line VL4 can respectively transmit the first initialization voltage VINT and the second initialization voltage VAINT to the pixel PXij. The first driving voltage line VL1, the second driving voltage line VL2, the first initialization voltage line VL3, and the second initialization voltage line VL4 can include... Figure 4 The driving voltage line PL is shown in the figure.

[0083] A first transistor T1 is connected between the light-emitting element ED and a first driving voltage line VL1 that receives the first driving voltage ELVDD. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to the pixel electrode (or anode electrode) of the light-emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the first terminal (e.g., the first node N1) of the capacitor Cst. The first transistor T1 may receive the i-th data signal Di via the i-th data line DLi, depending on the switching operation of the second transistor T2, and subsequently supply driving current to the light-emitting element ED.

[0084] A second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 can be turned on in response to a write scan signal GWj received via the j-th write scan line GWLj, to transmit the i-th data signal Di received from the i-th data line DLi to the first electrode of the first transistor T1.

[0085] A third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 can be turned on in response to a j-th compensation scan signal GCj received via the j-th compensation scan line GCLj, thereby connecting the third electrode and the second electrode of the first transistor T1, such that the first transistor T1 is diode-connected.

[0086] A fourth transistor T4 is connected between a first initialization voltage line VL3 for transmitting the first initialization voltage VINT and a first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 for transmitting the first initialization voltage VINT, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on in response to a j-th initialization scan signal GIj received via the j-th initialization scan line GILj. The fourth transistor T4 is turned on to transmit the first initialization voltage VINT to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0087] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode (e.g., a second node N2) connected to the pixel electrode of the light emission element ED, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj.

[0088] The fifth transistor T5 and the sixth transistor T6 are simultaneously (e.g., synchronously) turned on in response to the j-th light emission control signal EMj received via the j-th light emission control line ECLj. The first drive voltage ELVDD applied through the turned-on fifth transistor T5 can be transmitted to the light-emitting element ED via the sixth transistor T6 after being compensated by the first transistor T1 connected by the diode.

[0089] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 for transmitting the second initialization voltage VAINT, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level different from the voltage level of the first initialization voltage VINT. For example, the second initialization voltage VAINT may have a voltage level lower than the voltage level of the first initialization voltage VINT.

[0090] The first terminal of capacitor Cst is connected to the third electrode of the first transistor T1, and the second terminal of capacitor Cst is connected to the first drive voltage line VL1. The cathode of the light-emitting element ED can be connected to the second drive voltage line VL2 for transmitting the second drive voltage ELVSS. The voltage level of the second drive voltage ELVSS can be lower than the voltage level of the first drive voltage ELVDD.

[0091] Figure 6A This is a plan view of a display panel according to one or more embodiments of the present disclosure, and Figure 6B By magnification Figure 6A The image shown is an enlarged view of a portion of the display panel.

[0092] refer to Figure 6A and Figure 6B The display panel DP can include the display area DP_DA and the non-display area DP_NDA.

[0093] The display area DP_DA may include a first area DP_SA and a second area DP_NSA. The first area DP_SA may have an elliptical shape, but this disclosure is not limited thereto. For example, the first area DP_SA may have various shapes such as a polygonal shape, a circular shape, a graphic with at least one curved edge, or an irregular shape. According to one or more embodiments of this disclosure, although the first area DP_SA may be positioned adjacent to the upper corner of the display area DP_DA, the position of the first area DP_SA is not limited thereto. For example, the first area DP_SA may be positioned at the center of the upper part of the display area DP_DA.

[0094] The second region DP_NSA may be adjacent to the first region DP_SA. Although the first region DP_SA is illustrated as being surrounded by the second region DP_NSA, this disclosure is not limited thereto. For example, the first region DP_SA may be partially surrounded by the second region DP_NSA, and one side of the first region DP_SA may be in contact with the non-display region DP_NDA.

[0095] The first region DP_SA may include a first sub-region SA1 and a second sub-region SA2. According to one or more embodiments of this disclosure, the first sub-region SA1 may have a circular shape. The second sub-region SA2 may be adjacent to the first sub-region SA1. The second sub-region SA2 may include a second-1 sub-region configured to be adjacent to a first side of the first sub-region SA1 and a second-2 sub-region configured to be adjacent to a second side of the first sub-region SA1. The first region DP_SA may have an elliptical shape through the first sub-region SA1 and the second sub-region SA2. Each of the first sub-region SA1 and the second sub-region SA2 is not limited to the shapes described above, but may have various shapes.

[0096] The transmittance of the first sub-region SA1 can be higher than that of the second sub-region SA2, and the transmittance of the second sub-region SA2 can be higher than that of the second sub-region DP_NSA.

[0097] A pixel PX can include multiple pixels. These multiple pixels PX can include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 and the second pixel PX2 can be set in the first region DP_SA. The third pixel PX3 can be set in the second region DP_NSA.

[0098] Each first pixel PX1 includes a first light-emitting element ED1 and a first pixel circuit PC1 connected to the first light-emitting element ED1. Each second pixel PX2 includes a second light-emitting element ED2 and a second pixel circuit PC2 connected to the second light-emitting element ED2. The first light-emitting element ED1 is disposed in a first sub-region SA1, and the first pixel circuit PC1 is disposed in a second sub-region SA2. Accordingly, when viewed in a plan view, the first light-emitting element ED1 can be in a state where it does not overlap with the first pixel circuit PC1. The first light-emitting element ED1 can be electrically connected to the first pixel circuit PC1 via a connecting line TCL. The second light-emitting element ED2 and the second pixel circuit PC2 are disposed in the second sub-region SA2 and overlap each other when viewed in a plan view.

[0099] Each third pixel PX3 includes a third light-emitting element ED3 and a third pixel circuit PC3 connected to the third light-emitting element ED3. The third light-emitting element ED3 and the third pixel circuit PC3 are located in the second region DP_NSA and overlap each other when viewed in a plan view.

[0100] According to one or more embodiments of this disclosure, although the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may have equal dimensions, this disclosure is not limited thereto. For example, the dimensions of the first light-emitting element ED1 and the second light-emitting element ED2 may be larger than the dimensions of the third light-emitting element ED3. According to one or more embodiments of this disclosure, although the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may have the same shape, this disclosure is not limited thereto. For example, the first light-emitting element ED1 and the second light-emitting element ED2 may have the same shape, and the third light-emitting element ED3 may have a shape different from that of the first light-emitting element ED1 and the second light-emitting element ED2.

[0101] Each of the first sub-region SA1 and the second sub-region SA2 may have a lower resolution than the second sub-region DP_NSA. For example, the number of first light-emitting elements ED1 disposed in the reference area of ​​the first sub-region SA1 may be equal to the number of second light-emitting elements ED2 disposed in the reference area of ​​the second sub-region SA2, and may be less than the number of third light-emitting elements ED3 disposed in the reference area of ​​the second sub-region DP_NSA. Alternatively, each of the first sub-region SA1 and the second sub-region SA2 may have a resolution equal to the resolution of the second sub-region DP_NSA. For example, the number of first light-emitting elements ED1 disposed in the reference area of ​​the first sub-region SA1 may be equal to the number of second light-emitting elements ED2 disposed in the reference area of ​​the second sub-region SA2 and the number of third light-emitting elements ED3 disposed in the reference area of ​​the second sub-region DP_NSA.

[0102] Figure 7 This is a view illustrating the arrangement of connecting lines according to one or more embodiments of the present disclosure.

[0103] refer to Figure 6B and Figure 7 The first region DP_SA may include a first sub-region SA1 and a second sub-region SA2. According to one or more embodiments of this disclosure, the first sub-region SA1 may have a circular shape. The first sub-region SA1 may be divided into two regions (i.e., sub-region 1-1 SA1a and sub-region 1-2 SA1b) about a reference axis RX that is parallel to the second direction DR2 and passes through the center point CP. In other words, sub-region 1-1 SA1a is located on a first side (e.g., the right side) about the reference axis RX, and sub-region 1-2 SA1b is located on a second side (e.g., the left side) about the reference axis RX. Sub-regions 1-1 SA1a and 1-2 SA1b may have shapes that are symmetrical to each other about the reference axis RX. According to one or more embodiments of this disclosure, each of sub-regions 1-1 SA1a and 1-2 SA1b may have a semi-circular shape.

[0104] Each of sub-regions 1-1 SA1a and 1-2 SA1b may include multiple first connection regions. Although Figure 7 The diagram illustrates a structure including a first sub-region SA1a and a first sub-region SA1b, each of which has three first connecting regions, but this disclosure is not limited thereto. These three first connecting regions may be referred to as first connecting region SA11, first connecting region SA12, and first connecting region SA13. First connecting region SA11 is adjacent to the center, and first connecting region SA12 is disposed outside first connecting region SA11. First connecting region SA12 may be configured to surround first connecting region SA11. First connecting region SA13 may be configured to be adjacent to the boundary between the first sub-region SA1 and the second sub-region SA2. According to one or more embodiments of this disclosure, first connecting region SA12 may be interposed between first connecting region SA11 and first connecting region SA13.

[0105] The first light-emitting element ED1 disposed in the first-1 connection area SA11 is referred to as the first-1 light-emitting element ED11. The first light-emitting element ED1 disposed in the first-2 connection area SA12 is referred to as the first-2 light-emitting element ED12. The first light-emitting element ED1 disposed in the first-3 connection area SA13 is referred to as the first-3 light-emitting element ED13. The pixel circuit PC1 connected to the first-1 light-emitting element ED11 is referred to as the first-1 pixel circuit PC11. The pixel circuit PC1 connected to the first-2 light-emitting element ED12 is referred to as the first-2 pixel circuit PC12. The pixel circuit PC1 connected to the first-3 light-emitting element ED13 is referred to as the first-3 pixel circuit PC13.

[0106] The second sub-region SA2 includes a second-first sub-region SA2a adjacent to the first-first sub-region SA1a and a second-second sub-region SA2b adjacent to the first-second sub-region SA1b. In other words, the second-first sub-region SA2a is interposed between the first-first sub-region SA1a and the second sub-region DP_NSA, and the second-second sub-region SA2b is interposed between the first-second sub-region SA1b and the second sub-region DP_NSA.

[0107] Each of sub-regions 2-1 SA2a and 2-2 SA2b may include multiple second connection regions. Although Figure 7The diagram illustrates a structure including sub-regions 2-1 SA2a and 2-2 SA2b, each of which has three second connection regions, but this disclosure is not limited thereto. These three second connection regions may be referred to as connection region 2-1 SA21, connection region 2-2 SA22, and connection region 2-3 SA23, respectively. A first-1 pixel circuit PC11 connected to the first-1 light-emitting element ED11 is disposed in connection region 2-1 SA21. A first-2 pixel circuit PC12 connected to the first-2 light-emitting element ED12 is disposed in connection region 2-2 SA22. A first-3 pixel circuit PC13 connected to the first-3 light-emitting element ED13 is disposed in connection region 2-3 SA23.

[0108] According to one or more embodiments of this disclosure, the second-2nd connection region SA22 is configured to be closer to the first sub-region SA1 than the second-1st connection region SA21, and the second-3rd connection region SA23 is configured to be closer to the first sub-region SA1 than the second-2nd connection region SA22. Accordingly, the distance between the first-3rd connection region SA13 and the second-3rd connection region SA23 is shorter than the distance between the first-2nd connection region SA12 and the second-2nd connection region SA22. The distance between the first-2nd connection region SA12 and the second-2nd connection region SA22 may be shorter than the distance between the first-1st connection region SA11 and the second-1st connection region SA21.

[0109] The second light-emitting element ED2 and the second pixel circuit PC2 can be disposed in the second-1 connection area SA21, the second-2 connection area SA22 and the second-3 connection area SA23.

[0110] The connecting lines TCL may include multiple connecting lines. These multiple connecting lines may include a first connecting line TCL1, a second connecting line TCL2, and a third connecting line TCL3. Each of the first connecting lines TCL1 connects the first-1 light-emitting element ED11 to the first-1 pixel circuit PC11, and each of the second connecting lines TCL2 connects the first-2 light-emitting element ED12 to the first-2 pixel circuit PC12. Each of the third connecting lines TCL3 connects the first-3 light-emitting element ED13 to the first-3 pixel circuit PC13.

[0111] The length of the first connecting wire TCL1 is longer than the length of the second connecting wire TCL2, and the length of the second connecting wire TCL2 is longer than the length of the third connecting wire TCL3. The line resistance of the first connecting wire TCL1 may be equal to or different from the line resistance of the second connecting wire TCL2. According to one or more embodiments of this disclosure, the thickness and width of the first connecting wire TCL1 are adjusted such that the line resistance of the first connecting wire TCL1 is equal to (or substantially equal to) its line resistance.

[0112] The line resistance of the second connecting line TCL2.

[0113] According to one or more embodiments of this disclosure, the first connecting lines TCL1 have equal lengths, and the second connecting lines TCL2 have equal lengths. According to one or more embodiments of this disclosure, the first connecting lines TCL1 have equal line resistances, and the second connecting lines TCL2 have equal line resistances. Furthermore, since the third connecting line TCL3 has equal lengths, the third connecting line TCL3 can also have equal line resistances.

[0114] The first connecting line TCL1 can extend from the first-1 connecting area SA11 to the second-1 connecting area SA21. The first connecting line TCL1 can be arranged to bypass the second area DP_NSA. Accordingly, some of the first connecting lines TCL1 can partially overlap with the second area DP_NSA. The second connecting line TCL2 can extend from the first-2 connecting area SA12 to the second-2 connecting area SA22. The second connecting line TCL2 can partially overlap with the first-3 connecting area SA13 and the second-3 connecting area SA23. The third connecting line TCL3 can extend from the first-3 connecting area SA13 to the second-3 connecting area SA23.

[0115] According to one or more embodiments of this disclosure, a first connecting line TCL1 is disposed on a first layer, a second connecting line TCL2 is disposed on a second layer, and a third connecting line TCL3 is disposed on either the first or the second layer. In other words, the first connecting line TCL1 and the second connecting line TCL2 may be disposed on different layers from each other, and the third connecting line TCL3 may be disposed on the same layer as the first connecting line TCL1, or on the same layer as the second connecting line TCL2.

[0116] Since some of the connecting lines TCL1 to TCL3 in the first zone DP_SA are routed to the second zone DP_NSA, the connecting lines TCL1 to TCL3 in the first zone DP_SA can be placed on two layers (i.e., the first layer and the second layer). Accordingly, the connecting lines TCL1 to TCL3 are effectively arranged in a confined area to reduce the density of the connecting lines, thus preventing the addition of layers, thereby preventing an increase in the thickness of the display panel DP, or preventing the addition of process masks during the manufacturing of the display panel DP.

[0117] Figure 8 This is a block diagram illustrating the arrangement of the first to third connecting lines according to one or more embodiments of the present disclosure.

[0118] refer to Figure 7 and Figure 8The first-1 light-emitting element ED11 disposed in the first-1 connection area SA11 may include a first red light-emitting element R_ED11, a first-1 green light-emitting element G1_ED11, a first blue light-emitting element B_ED11, and a first-2 green light-emitting element G2_ED11. The first-1 pixel circuit PC11 disposed in the second-1 connection area SA21 may include a first red pixel circuit R_PC11, a first-1 green pixel circuit G1_PC11, a first blue pixel circuit B_PC11, and a first-2 green pixel circuit G2_PC11.

[0119] The first connection line TCL1 may include connection line 1-1 TCL11, connection line 1-2 TCL12, connection line 1-3 TCL13, and connection line 1-4 TCL14. Connection line 1-1 TCL11 electrically connects the first red light-emitting element R_ED11 to the first red pixel circuit R_PC11. Connection line 1-2 TCL12 electrically connects the first green light-emitting element G1_ED11 to the first green pixel circuit G1_PC11. Connection line 1-3 TCL13 electrically connects the first blue light-emitting element B_ED11 to the first blue pixel circuit B_PC11. Connection line 1-4 TCL14 electrically connects the first green light-emitting element G2_ED11 to the first green pixel circuit G2_PC11. The first connecting line TCL11 (1-1), the first connecting line TCL12 (1-2), the first connecting line TCL13 (1-3), and the first connecting line TCL14 (1-4) are connected to the first red pixel circuit R_PC11, the first green pixel circuit G1_PC11 (1-1), the first blue pixel circuit B_PC11, and the first green pixel circuit G2_PC11 (1-2) respectively through the first contact hole CNT1.

[0120] Connecting lines TCL11 (1-1), TCL12 (1-2), TCL13 (1-3), and TCL14 (1-4) can be routed through the second zone DP_NSA and can extend from connecting zone SA21 (2-1) to connecting zone SA11 (1-1). Connecting lines TCL11 (1-1), TCL12 (1-2), TCL13 (1-3), and TCL14 (1-4) can have different shapes from each other.

[0121] The first red pixel circuit R_PC11, the first-1 green pixel circuit G1_PC11, the first blue pixel circuit B_PC11, and the first-2 green pixel circuit G2_PC11 are not disposed in the first-1 connection area SA11. Accordingly, the area provided in the first-1 connection area SA11 between the first red light-emitting element R_ED11, the first-1 green light-emitting element G1_ED11, the first blue light-emitting element B_ED11, and the first-2 green light-emitting element G2_ED11 can be defined as a transmission area LTA for transmitting optical signals.

[0122] The first-second light-emitting element ED12 disposed in the first-second connection area SA12 may include a second red light-emitting element R_ED12, a second-first green light-emitting element G1_ED12, a second blue light-emitting element B_ED12, and a second-second green light-emitting element G2_ED12. The first-second pixel circuit PC12 disposed in the second-second connection area SA22 may include a second red pixel circuit R_PC12, a second-first green pixel circuit G1_PC12, a second blue pixel circuit B_PC12, and a second-second green pixel circuit G2_PC12.

[0123] The second connecting line TCL2 may include connecting line 2-1 TCL21, connecting line 2-2 TCL22, connecting line 2-3 TCL23, and connecting line 2-4 TCL24. Connecting line 2-1 TCL21 electrically connects the second red light-emitting element R_ED12 to the second red pixel circuit R_PC12. Connecting line 2-2 TCL22 electrically connects the second green light-emitting element G1_ED12 to the second green pixel circuit G1_PC12. Connecting line 2-3 TCL23 electrically connects the second blue light-emitting element B_ED12 to the second blue pixel circuit B_PC12. Connecting line 2-4 TCL24 electrically connects the second green light-emitting element G2_ED12 to the second green pixel circuit G2_PC12. The second-1 connecting line TCL21, the second-2 connecting line TCL22, the second-3 connecting line TCL23, and the second-4 connecting line TCL24 are connected to the second red pixel circuit R_PC12, the second-1 green pixel circuit G1_PC12, the second blue pixel circuit B_PC12, and the second-2 green pixel circuit G2_PC12 respectively through the second contact hole CNT2.

[0124] Connecting lines TCL21 (2-1), TCL22 (2-2), TCL23 (2-3), and TCL24 (2-4) extend from connecting area SA22 (2-2), through connecting area SA23 (2-3), and connecting area SA13 (1-3) to connecting area SA12 (1-2). According to one or more embodiments, connecting lines TCL21 (2-1) and TCL23 (2-3) may have the same shape, and connecting lines TCL22 (2-2) and TCL24 (2-4) may have the same shape. Connecting lines TCL21 (2-1), TCL22 (2-2), TCL23 (2-3), and TCL24 (2-4) may have equal lengths.

[0125] The second red pixel circuit R_PC12, the second-first green pixel circuit G1_PC12, the second blue pixel circuit B_PC12, and the second-second green pixel circuit G2_PC12 are not disposed in the first-second connection area SA12. Accordingly, the area provided in the first-second connection area SA12 between the second red light-emitting element R_ED12, the second-first green light-emitting element G1_ED12, the second blue light-emitting element B_ED12, and the second-second green light-emitting element G2_ED12 can be defined as a transmission area LTA for transmitting optical signals.

[0126] The first-third light-emitting element ED13 disposed in the first-third connection area SA13 may include a third red light-emitting element R_ED13, a third-first green light-emitting element G1_ED13, a third blue light-emitting element B_ED13, and a third-second green light-emitting element G2_ED13. The first-third pixel circuit PC13 disposed in the second-third connection area SA23 may include a third red pixel circuit R_PC13, a third-first green pixel circuit G1_PC13, a third blue pixel circuit B_PC13, and a third-second green pixel circuit G2_PC13.

[0127] The third connecting line TCL3 may include connecting line 3-1 (TCL31), connecting line 3-2 (TCL32), connecting line 3-3 (TCL33), and connecting line 3-4 (TCL34). Connecting line 3-1 (TCL31) electrically connects the third red light-emitting element R_ED13 to the third red pixel circuit R_PC13. Connecting line 3-2 (TCL32) electrically connects the third green light-emitting element G1_ED13 to the third green pixel circuit G1_PC13. Connecting line 3-3 (TCL33) electrically connects the third blue light-emitting element B_ED13 to the third blue pixel circuit B_PC13. Connecting line 3-4 (TCL34) electrically connects the third green light-emitting element G2_ED13 to the third green pixel circuit G2_PC13. Connection lines TCL31 (3-1), TCL32 (3-2), TCL33 (3-3), and TCL34 (3-4) are connected to the third red pixel circuit R_PC13, the third green pixel circuit G1_PC13, the third blue pixel circuit B_PC13, and the third green pixel circuit G2_PC13 respectively via the third contact hole CNT3.

[0128] Connecting lines TCL31 (3-1), TCL32 (3-2), TCL33 (3-3), and TCL34 (3-4) can extend from connecting area SA23 (2-3) to connecting area SA13 (1-3). According to one or more embodiments of this disclosure, connecting lines TCL31 (3-1) and TCL33 (3-3) can have the same shape, and connecting lines TCL32 (3-2) and TCL34 (3-4) can have the same shape. Connecting lines TCL31 (3-1), TCL32 (3-2), TCL33 (3-3), and TCL34 (3-4) can have equal lengths.

[0129] The third red pixel circuit R_PC13, the third-first green pixel circuit G1_PC13, the third blue pixel circuit B_PC13, and the third-second green pixel circuit G2_PC13 are not located in the first-third connection area SA13. Accordingly, the area provided in the first-third connection area SA13 between the third red light-emitting element R_ED13, the third-first green light-emitting element G1_ED13, the third blue light-emitting element B_ED13, and the third-second green light-emitting element G2_ED13 can be defined as a transmission area LTA for transmitting optical signals.

[0130] The second light-emitting element ED2 and the second pixel circuit PC2 can be disposed in the 2-1 connection area SA21, the 2-2 connection area SA22, and the 2-3 connection area SA23. The second light-emitting element ED2 includes a fourth red light-emitting element R_ED2, a 4-1 green light-emitting element G1_ED2, a fourth blue light-emitting element B_ED2, and a 4-2 green light-emitting element G2_ED2. The second pixel circuit PC2 includes a fourth red pixel circuit R_PC2, a 4-1 green pixel circuit G1_PC2, a fourth blue pixel circuit B_PC2, and a 4-2 green pixel circuit G2_PC2.

[0131] The fourth red light-emitting element R_ED2 and the fourth red pixel circuit R_PC2 are electrically connected to each other and overlap when viewed in a plan view. The fourth green light-emitting element G1_ED2 and the fourth green pixel circuit G1_PC2 are electrically connected to each other and overlap when viewed in a plan view. The fourth blue light-emitting element B_ED2 and the fourth blue pixel circuit B_PC2 are electrically connected to each other and overlap when viewed in a plan view. The fourth green light-emitting element G2_ED2 and the fourth green pixel circuit G2_PC2 are electrically connected to each other and overlap when viewed in a plan view.

[0132] Figure 9A and Figure 9B This is a view illustrating the cross-sectional structure of a first sub-area, a second sub-area, and a second area of ​​a display panel according to one or more embodiments of the present disclosure. Figure 9A It is a cross-sectional view showing the arrangement of the first connecting line, and Figure 9B This is a cross-sectional view showing the arrangement of the second connecting line.

[0133] refer to Figure 8 , Figure 9A and Figure 9B The display panel DP can include a substrate layer BL, a circuit layer DP_CL, and a light-emitting element layer DP_ED.

[0134] The substrate layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin material. Specifically, the synthetic resin layer may be a polyimide resin layer, and the material of the synthetic resin layer is not particularly limited. The synthetic resin layer may include acrylate resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and / or perylene resins. Additionally, the substrate layer BL may include a glass substrate, a metal substrate, and / or an organic / inorganic composite material substrate.

[0135] A circuit layer DP_CL is disposed on a substrate layer BL. The circuit layer DP_CL may include at least one inorganic layer disposed on the top surface of the substrate layer BL. This inorganic layer may include alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and / or hafnium oxide. This inorganic layer may be formed as multiple layers. Multiple inorganic layers may constitute a barrier layer and / or a buffer layer. The barrier layer and buffer layer may be selectively disposed.

[0136] A barrier layer is disposed on the substrate layer BL to prevent foreign matter from being introduced from the outside. The barrier layer may include a silicon oxide layer and / or a silicon nitride layer. The silicon oxide layer may include multiple silicon oxide layers, and the silicon nitride layer may include multiple silicon nitride layers, and the silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0137] A buffer layer may be disposed on the barrier layer. The buffer layer improves the adhesion between the substrate layer (BL) and the semiconductor pattern and / or conductive pattern. The buffer layer may include a silicon oxide layer and / or a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately. The barrier layer and the buffer layer may be omitted.

[0138] The circuit layer DP_CL includes a first semiconductor pattern disposed on the substrate layer BL. The first semiconductor pattern may include silicon semiconductor. The first semiconductor pattern may include low-temperature polycrystalline silicon. However, this disclosure is not limited thereto. For example, the first semiconductor pattern may include amorphous silicon or oxide semiconductor.

[0139] The first semiconductor pattern may have electrical properties that vary depending on the doping state. Each first semiconductor pattern may include doped and undoped regions. The doped regions may be doped with N-type or P-type dopant. A P-type transistor includes a doped region doped with P-type dopant, and an N-type transistor includes a doped region doped with N-type dopant.

[0140] The doped region is more conductive than the undoped region and is actually used as an electrode or signal line. The undoped region can actually correspond to the channel portion of the transistor. In other words, a first portion of the first semiconductor pattern can be the channel portion of the transistor, and a second portion of the first semiconductor pattern can be the source (or first electrode) or drain (or second electrode) of the transistor.

[0141] like Figure 9A The sixth transistor T6 shown in the diagram (corresponding to...) Figure 5 The first electrode S6, the channel portion CH6, and the second electrode D6 of the sixth transistor T6 shown in the figure are formed by a first semiconductor pattern. The first electrode S6 and the second electrode D6 of the sixth transistor T6 can extend from the channel portion CH6 in opposite directions to each other.

[0142] A first insulating layer (or gate insulating layer) 10 is disposed on the substrate layer BL. The first insulating layer 10 covers a first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The first insulating layer 10 may include aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and / or hafnium oxide. According to one or more embodiments, the first insulating layer 10 may be a single silicon oxide layer. In addition to the first insulating layer 10, other insulating layers of the circuit layer DP_CL, which will be described below, may be inorganic layers and / or organic layers, and may have a single-layer structure or a multilayer structure. Inorganic layers may include at least one of the materials described above.

[0143] The gate electrode G6 of the sixth transistor T6 is disposed on the first insulating layer 10. The gate electrode G6 of the sixth transistor T6 may overlap with the channel portion CH6 of the sixth transistor T6. The gate electrode G6 may include titanium, silver, silver-containing alloys, molybdenum, molybdenum-containing alloys, aluminum, aluminum-containing alloys, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide and / or indium zinc oxide, but this disclosure is not limited thereto.

[0144] A second insulating layer 20 is disposed on the first insulating layer 10 to cover the gate electrode G6 of the sixth transistor T6. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. According to one or more embodiments, the second insulating layer 20 may be a single silicon oxide layer.

[0145] The first gate electrode G3_1 of the third transistor T3 may be disposed on the second insulating layer 20. The third insulating layer 30 is disposed on the second insulating layer 20 to cover the first gate electrode G3_1 of the third transistor T3. According to one or more embodiments, the third insulating layer 30 may be a single silicon oxide layer.

[0146] A second semiconductor pattern may be disposed on the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include multiple regions distinguished by whether the metal oxide is reduced. Regions where the metal oxide is reduced (hereinafter referred to as "reduced regions") have higher conductivity than regions where the metal oxide is not reduced (hereinafter referred to as "non-reduced regions"). The reduced regions are actually used as the source / drain of a transistor or signal lines. The non-reduced regions actually correspond to the active regions (or semiconductor regions or channel regions) of a transistor. In other words, a first portion of the second semiconductor pattern may be the channel portion of a transistor, a second portion of the second semiconductor pattern may be the source (or first electrode) or drain (or second electrode) of a transistor, and a third portion of the second semiconductor pattern may be a signal transmission unit (e.g., a bridging line).

[0147] The third transistor T3 (corresponding to) Figure 5The first electrode D3, the channel portion CH3, and the second electrode S3 of the third transistor T3 shown in the figure can be formed by a second semiconductor pattern. The first gate electrode G3_1 of the third transistor T3 overlaps with the channel portion CH3 of the third transistor T3.

[0148] A fourth insulating layer 40 is disposed on the third insulating layer 30. The fourth insulating layer 40 covers the second semiconductor pattern. The second gate electrode G3_2 of the third transistor T3 may be disposed on the fourth insulating layer 40. The second gate electrode G3_2 of the third transistor T3 overlaps with the channel portion CH3 of the third transistor T3 and the first gate electrode G3_1 of the third transistor T3. According to one or more embodiments of the present disclosure, the second gate electrode G3_2 of the third transistor T3 may be electrically connected to the first gate electrode G3_1 of the third transistor T3.

[0149] A fifth insulating layer 50 is disposed on the fourth insulating layer 40 to cover the second gate electrode G3_2 of the third transistor T3. The fourth insulating layer 40 and the fifth insulating layer 50 can be inorganic layers and / or organic layers, and can have a single-layer structure or a multi-layer structure. According to one or more embodiments, the fourth insulating layer 40 and the fifth insulating layer 50 can be a single silicon oxide layer.

[0150] The first connecting electrode CNE1 and the second connecting electrode CNE2 are disposed on the fifth insulating layer 50. The first connecting electrode CNE1 electrically connects the second electrode D6 of the sixth transistor T6 to the anode AE3 of the third light-emitting element ED3 in the second region DP_NSA, and electrically connects the second electrode D6 of the sixth transistor T6 to the anode AE11 of the first-1 light-emitting element ED11 or the anode AE12 of the first-2 light-emitting element ED12 in the first region DP_SA. The second connecting electrode CNE2 electrically connects the first electrode S6 of the sixth transistor T6 to the second electrode S3 of the third transistor T3.

[0151] A sixth insulating layer 60 is disposed on the fifth insulating layer 50 to cover the first connecting electrode CNE1 and the second connecting electrode CNE2. A third connecting electrode CNE3 may be disposed on the sixth insulating layer 60. The third connecting electrode CNE3 is connected to the first connecting electrode CNE1 through a contact hole formed through the sixth insulating layer 60. The first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 may include, for example, metals, alloys, conductive metal oxides, or transparent conductive materials.

[0152] A seventh insulating layer 70 is disposed on the sixth insulating layer 60 to cover the third connecting electrode CNE3, and a first connecting line TCL1 (or the first-1 connecting line TCL11) and a second intermediate connecting electrode TCNE2 are disposed on the seventh insulating layer (or referred to as the "first layer") 70. According to one or more embodiments, each of the sixth insulating layer 60 and the seventh insulating layer 70 may include a silicon oxide layer or a silicon nitride layer. In the second-1 connecting region SA21, one end (or referred to as the "first end") of the first connecting line TCL1 is connected to the third connecting electrode CNE3 through a contact hole CNT1 formed through the seventh insulating layer 70. The first connecting line TCL1 may extend from the second-1 connecting region SA21 to the first-1 connecting region SA11. The first connecting line TCL1 and the second intermediate connecting electrode TCNE2 may include a transparent conductive material. The transparent conductive material may include a light-transmitting material. The first connecting line TCL1 and the second intermediate connecting electrode TCNE2 can be formed in the form of a film comprising a transparent conductive oxide (TCO) (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO) and / or indium oxide (In2O3)).

[0153] An eighth insulating layer (or "second layer") 80 is disposed on the seventh insulating layer 70 to cover the first connecting line TCL1 and the second intermediate connecting electrode TCNE2, and the second connecting line TCL2 (or the second-first connecting line TCL21) and the first intermediate connecting electrode TCNE1 are disposed on the eighth insulating layer 80. In the second-second connection region SA22, one end (or "first end") of the second connecting line TCL2 is connected to the second intermediate connecting electrode TCNE2 through a contact hole CNT2 formed through the eighth insulating layer 80. The second connecting line TCL2 can extend from the second-second connection region SA22 to the first-second connection region SA12.

[0154] The first intermediate connection electrode TCNE1 is disposed in the first-1 connection region SA11 and is connected to the opposite end (or referred to as the "second end") of the first connection line TCL1 through a contact hole formed through the eighth insulating layer 80 in the first-1 connection region SA11. The second connection line TCL2 and the first intermediate connection electrode TCNE1 may comprise a transparent conductive material. The transparent conductive material may comprise a light-transmitting material. The second connection line TCL2 and the first intermediate connection electrode TCNE1 may be formed in the form of a film comprising a transparent conductive oxide (TCO) (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), and / or indium oxide (In2O3)).

[0155] As described above, since the first connecting line TCL1, the second connecting line TCL2, the first intermediate connecting electrode TCNE1, and the second intermediate connecting electrode TCNE2 are made of transparent conductive material, even if the first connecting line TCL1, the second connecting line TCL2, the first intermediate connecting electrode TCNE1, and the second intermediate connecting electrode TCNE2 are disposed in the first region DP_SA, the light transmittance of the first region DP_SA can be prevented from being reduced due to the first connecting line TCL1, the second connecting line TCL2, the first intermediate connecting electrode TCNE1, and the second intermediate connecting electrode TCNE2 disposed in the first region DP_SA.

[0156] The second connecting line TCL2 and the first intermediate connecting electrode TCNE1 may contain the same material as the first connecting line TCL1 and the second intermediate connecting electrode TCNE2. The first connecting line TCL1, the second connecting line TCL2, and the first intermediate connecting electrode TCNE1 and the second intermediate connecting electrode TCNE2 may contain materials different from the materials of the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3, but this disclosure is not limited thereto.

[0157] although Figure 9B The diagram illustrates a structure in which the second connecting line TCL2 and the third connecting electrode CNE3 are connected to each other via a second intermediate connecting electrode TCNE2, but this disclosure is not limited thereto. For example, the first end of the second connecting line TCL2 can be directly connected to the third connecting electrode CNE3. In this case, the second intermediate connecting electrode TCNE2 can be omitted.

[0158] A ninth insulating layer 90 is disposed on the eighth insulating layer 80 to cover the second connecting line TCL2 and the first intermediate connecting electrode TCNE1.

[0159] The light-emitting element layer DP_ED is disposed on the circuit layer DP_CL. The light-emitting element layer DP_ED may include a first-first light-emitting element ED11 (or a first red light-emitting element R_ED11), a first-second light-emitting element ED12 (or a second red light-emitting element R_ED12), a third light-emitting element ED3, and a pixel defining layer PDL. The first-first light-emitting element ED11 includes a first-first anode AE11, a first-first light-emitting layer EL11, and a common cathode CE. The first-second light-emitting element ED12 includes a first-second anode AE12, a first-second light-emitting layer EL12, and a common cathode CE. The third light-emitting element ED3 includes a third anode AE3, a third light-emitting layer EL3, and a common cathode CE.

[0160] Anodes AE11 (1-1), AE12 (1-2), and AE3 (3-3) are disposed on the ninth insulating layer 90. Anode AE3 is connected to the third connecting electrode CNE3 in the second region DP_NSA via a contact hole formed through the seventh insulating layer 70, the eighth insulating layer 80, and the ninth insulating layer 90. Anode AE11 (1-1) is connected to the first intermediate connecting electrode TCNE1 in the first connecting region SA11 via a contact hole formed through the ninth insulating layer 90. Anode AE12 (1-2) is connected to the opposite end (or "second end") of the second connecting line TCL2 via a contact hole formed through the ninth insulating layer 90 in the first connecting region SA12.

[0161] although Figure 9A The diagram illustrates a structure in which the first connecting line TCL1 and the first-1 anode AE11 are connected to each other via the first intermediate connecting electrode TCNE1, but this disclosure is not limited thereto. For example, the first-1 anode AE11 can be directly connected to the second end of the first connecting line TCL1. In this case, the first intermediate connecting electrode TCNE1 can be omitted.

[0162] The first-first anode AE11, the first-second anode AE12, and the third anode AE3 may include a reflective layer comprising silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, or compounds thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide, and aluminum-doped zinc oxide. For example, the first-first anode AE11, the first-second anode AE12, and the third anode AE3 may include a multilayer structure in which indium tin oxide, silver, and indium tin oxide are sequentially stacked on top of each other.

[0163] A pixel-defining layer (PDL) may be disposed on a ninth insulating layer 90 and may include a first opening OP1, a second opening OP2, and a third opening OP3, which are defined to correspond to a first-first light-emitting element ED11, a first-second light-emitting element ED12, and a third light-emitting element ED3, respectively. The first opening OP1 exposes at least a portion of the first-first anode AE11 of the first-first light-emitting element ED11, and the second opening OP2 exposes at least a portion of the first-second anode AE12 of the first-second light-emitting element ED12. The third opening OP3 exposes at least a portion of the third anode AE3 of the third light-emitting element ED3. The first opening OP1, the second opening OP2, and the third opening OP3 of the pixel-defining layer (PDL) may define a light-emitting area.

[0164] The first-1 light-emitting layer EL11 is configured to correspond to the first opening OP1, the first-2 light-emitting layer EL12 is configured to correspond to the second opening OP2, and the third light-emitting layer EL3 is configured to correspond to the third opening OP3. Although patterned light-emitting layers EL11, EL12, and EL3 are illustrated according to one or more embodiments, this disclosure is not limited thereto. Patterned light-emitting layers EL11, EL12, and EL3 can be used from the first pixel PX1 to the third pixel PX3 (see...). Figure 6A A common light-emitting layer is set together in the two structures. In this case, the common light-emitting layer can produce white light or blue light.

[0165] A common cathode CE is disposed on light-emitting layers EL11, EL12, and EL3. The common cathode CE is shared across multiple pixels PX1 to PX3. Alternatively, the common cathode CE may include a first cathode shared in first pixel PX1 and second pixel PX2 within the first region DP_SA, and a second cathode shared in third pixel PX3 within the second region DP_NSA. The first and second cathodes may receive different second driving voltages ELVSS (see [link to relevant documentation]). Figure 5 ).

[0166] The display panel DP may further include a TFE encapsulation layer (see...). Figure 3 The TFE encapsulation layer can be used to encapsulate the light-emitting element layer DP_ED. The TFE encapsulation layer may include at least one organic layer and at least one inorganic layer. The inorganic layer may include inorganic materials and can protect the DP_ED from moisture and / or oxygen. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon dioxide layer, a titanium oxide layer, and / or an aluminum oxide layer, but this disclosure is not particularly limited thereto. The organic layer may include organic materials and can protect the DP_ED from foreign matter such as dust particles.

[0167] Figure 10 This is a block diagram illustrating the arrangement of the first to third connecting lines according to one or more embodiments of the present disclosure.

[0168] refer to Figure 7 , Figure 8 and Figure 10 The first-1 light-emitting element ED11 and the first-1 sub-light-emitting element ED11S can be disposed in the first-1 connection area SA11. The first-1 light-emitting element ED11 is electrically connected to the first-1 sub-light-emitting element ED11S through the first bridge connection BCL1.

[0169] The first-1 light-emitting element ED11 may include a first red light-emitting element R_ED11, a first-1 green light-emitting element G1_ED11, a first blue light-emitting element B_ED11, and a first-2 green light-emitting element G2_ED11. The first-1 sub-light-emitting element ED11S may include a first sub-red light-emitting element R_ED11S, a first-1 sub-green light-emitting element G1_ED11S, a first sub-blue light-emitting element B_ED11S, and a first-2 sub-green light-emitting element G2_ED11S.

[0170] The first bridge connection BCL1 may include bridge connection 1-1 BCL11, bridge connection 1-2 BCL12, bridge connection 1-3 BCL13, and bridge connection 1-4 BCL14. Bridge connection 1-1 BCL11 electrically connects the first red light-emitting element R_ED11 to the first sub-red light-emitting element R_ED11S, and bridge connection 1-2 BCL12 electrically connects the first green light-emitting element G1_ED11 to the first sub-green light-emitting element G1_ED11S. Bridge connection 1-3 BCL13 electrically connects the first blue light-emitting element B_ED11 to the first sub-blue light-emitting element B_ED11S, and bridge connection 1-4 BCL14 electrically connects the first green light-emitting element G2_ED11 to the first sub-green light-emitting element G2_ED11S.

[0171] The first-1 pixel circuit PC11 disposed in the second-1 connection area SA21 may include a first red pixel circuit R_PC11, a first-1 green pixel circuit G1_PC11, a first blue pixel circuit B_PC11, and a first-2 green pixel circuit G2_PC11 (see, for example, see...). Figure 8 ).

[0172] The first connecting line TCL1 may include connecting line 1-1 TCL11, connecting line 1-2 TCL12, connecting line 1-3 TCL13, and connecting line 1-4 TCL14 (see, for example, see...). Figure 8 and Figure 10Connection line 1-1 (TCL11) electrically connects the first red light-emitting element R_ED11 to the first red pixel circuit R_PC11. Connection line 1-2 (TCL12) electrically connects the first green light-emitting element G1_ED11 to the first green pixel circuit G1_PC11. Connection line 1-3 (TCL13) electrically connects the first blue light-emitting element B_ED11 to the first blue pixel circuit B_PC11. Connection line 1-4 (TCL14) electrically connects the first green light-emitting element G2_ED11 to the first green pixel circuit G2_PC11. The first connecting line TCL11 (1-1), the first connecting line TCL12 (1-2), the first connecting line TCL13 (1-3), and the first connecting line TCL14 (1-4) are connected to the first red pixel circuit R_PC11, the first green pixel circuit G1_PC11 (1-1), the first blue pixel circuit B_PC11, and the first green pixel circuit G2_PC11 (1-2) respectively through the first contact hole CNT1.

[0173] The first red light-emitting element R_ED11 and the first sub-red light-emitting element R_ED11S emit light simultaneously (e.g., synchronously) through the first red pixel circuit R_PC11. The first-1 green light-emitting element G1_ED11 and the first-1 sub-green light-emitting element G1_ED11S emit light simultaneously (e.g., synchronously) through the first-1 green pixel circuit G1_PC11. The first blue light-emitting element B_ED11 and the first sub-blue light-emitting element B_ED11S emit light simultaneously (e.g., synchronously) through the first blue pixel circuit B_PC11. The first-2 green light-emitting element G2_ED11 and the first-2 sub-green light-emitting element G2_ED11S emit light simultaneously (e.g., synchronously) through the first-2 green pixel circuit G2_PC11.

[0174] The first and second light-emitting elements ED12 and the first and second sub-light-emitting elements ED12S can be disposed in the first and second connection area SA12. The first and second light-emitting elements ED12 are electrically connected to the first and second sub-light-emitting elements ED12S via the second bridge wire BCL2. The first and second light-emitting elements ED12 are connected via the second connection line TCL2 (see, for example, see...). Figure 7 It is electrically connected to the first and second pixel circuits PC12 located in the second-second connection area SA22 (see, for example, see...). Figure 7 Accordingly, the first-second light-emitting element ED12 and the first-second sub-light-emitting element ED12S emit light simultaneously (e.g., synchronously) through the first-second pixel circuit PC12.

[0175] The first-third light-emitting element ED13 and the first-third sub-light-emitting element ED13S can be disposed in the first-third connection area SA13. The first-third light-emitting element ED13 is electrically connected to the first-third sub-light-emitting element ED13S via the third bridge wire BCL3. The first-third light-emitting element ED13 is connected via the third connection line TCL3 (see, for example, see...). Figure 7 It is electrically connected to the first-third pixel circuit PC13 located in the second-third connection area SA23 (see, for example, see...). Figure 7 Accordingly, the first-third light-emitting element ED13 and the first-third sub-light-emitting element ED13S emit light simultaneously (e.g., synchronously) through the first-third pixel circuit PC13.

[0176] The fourth red light-emitting element R_ED2, the fourth sub-red light-emitting element R_ED2S, the 4-1 green light-emitting element G1_ED2, the 4-1 sub-green light-emitting element G1_ED2S, the fourth blue light-emitting element B_ED2, the fourth sub-blue light-emitting element B_ED2S, the 4-2 green light-emitting element G2_ED2, and the 4-2 sub-green light-emitting element G2_ED2S are disposed in the 2-1 connection area SA21. The fourth bridge wire BCL4 electrically connects the fourth red light-emitting element R_ED2 to the fourth sub-red light-emitting element R_ED2S, the 4-1 green light-emitting element G1_ED2 to the 4-1 sub-green light-emitting element G1_ED2S, the fourth blue light-emitting element B_ED2 to the fourth sub-blue light-emitting element B_ED2S, and the 4-2 green light-emitting element G2_ED2 to the 4-2 sub-green light-emitting element G2_ED2S.

[0177] Figure 11A and Figure 11B This is a view illustrating the cross-sectional structure of the first and second regions of a display panel according to one or more embodiments of the present disclosure. Figure 11A It is a cross-sectional view showing the arrangement of the first connecting line, and Figure 11B This is a cross-sectional view showing the arrangement of the second connecting line. Figure 11A and Figure 11B The components shown in the figure are... Figure 9A and Figure 9B Components that are identical to those shown in the figures will be assigned the same reference numerals, and their details will be omitted to avoid redundancy.

[0178] refer to Figure 11A and Figure 11B The first semiconductor pattern can be disposed on the substrate layer BL. The sixth transistor T6 (corresponding to...) Figure 5The first electrode S6, the channel portion CH6, and the second electrode D6 of the sixth transistor T6 shown in the figure are formed by a first semiconductor pattern. The gate electrode G6 of the sixth transistor T6 overlaps with the channel portion CH6 of the sixth transistor T6.

[0179] Figure 10 The first to third bridge lines BCL1 to BCL3 shown in the figure can be formed by a second semiconductor pattern. For example, the first to third bridge lines BCL1 to BCL3 can be the reduction regions of the second semiconductor pattern. Although the first to third bridge lines BCL1 to BCL3 can include indium gallium zinc oxide (IGZO), the materials constituting the first to third bridge lines BCL1 to BCL3 are not particularly limited to this.

[0180] The first to third bridge wirings BCL1 to BCL3 are covered by the fourth insulation layer 40.

[0181] The first connecting electrode CNE1 and the second connecting electrode CNE2, as well as the first bridging electrode BCNE1 and the second bridging electrode BCNE2, are disposed on the fifth insulating layer 50. The first bridging electrode BCNE1 is connected to one end (e.g., the first end) of each of the first to third bridging wires BCL1 to BCL3 through a contact hole formed through the fourth insulating layer 40 and the fifth insulating layer 50. The second bridging electrode BCNE2 is connected to the opposite end (e.g., the second end) of each of the first to third bridging wires BCL1 to BCL3 through a contact hole formed through the fourth insulating layer 40 and the fifth insulating layer 50.

[0182] A sixth insulating layer 60 is configured to cover the first connecting electrode CNE1 and the second connecting electrode CNE2, as well as the first bridging electrode BCNE1 and the second bridging electrode BCNE2. A third connecting electrode CNE3, a third bridging electrode BCNE3, and a fourth bridging electrode BCNE4 may be disposed on the sixth insulating layer 60. The third bridging electrode BCNE3 is connected to the first bridging electrode BCNE1 through a contact hole formed through the sixth insulating layer 60, and the fourth bridging electrode BCNE4 is connected to the second bridging electrode BCNE2 through a contact hole formed through the sixth insulating layer 60. The first to fourth bridging electrodes BCNE1 to BCNE4 may include, for example, metals, alloys, conductive metal oxides, and transparent conductive materials.

[0183] A seventh insulating layer 70 is disposed on the sixth insulating layer 60 to cover the third connecting electrode CNE3, the third bridging electrode BCNE3, and the fourth bridging electrode BCNE4. A first connecting line TCL1, a second intermediate connecting electrode TCNE2, a third intermediate connecting electrode TCNE3, and a fourth intermediate connecting electrode TCNE4 are disposed on the seventh insulating layer 70 (or referred to as the "first layer"). The first connecting line TCL1 and the second to fourth intermediate connecting electrodes TCNE2 and TCNE4 may comprise a transparent conductive material. The second intermediate connecting electrode TCNE2 is connected to the third connecting electrode CNE3 through a contact hole formed through the seventh insulating layer 70. The third intermediate connecting electrode TCNE3 is connected to the third bridging electrode BCNE3 through a contact hole formed through the seventh insulating layer 70, and the fourth intermediate connecting electrode TCNE4 is connected to the fourth bridging electrode BCNE4 through a contact hole formed through the seventh insulating layer 70.

[0184] An eighth insulating layer 80 (or "second layer") is disposed on the seventh insulating layer 70 to cover the first connecting line TCL1 and the second intermediate connecting electrode TCNE2, the third intermediate connecting electrode TCNE3, and the fourth intermediate connecting electrode TCNE4. The second connecting line TCL2, the first intermediate connecting electrode TCNE1, and the fifth intermediate connecting electrode TCNE5 are disposed on the eighth insulating layer 80. In the 2-2 connection area SA22, one end (or "first end") of the second connecting line TCL2 is connected to the second intermediate connecting electrode TCNE2 through a contact hole CNT2 formed through the eighth insulating layer 80.

[0185] The first intermediate connecting electrode TCNE1 is disposed in the first-1 connecting region SA11 and is connected to the opposite end (or referred to as the "second end") of the first connecting line TCL1 through a contact hole formed through the eighth insulating layer 80 in the first-1 connecting region SA11. The fifth intermediate connecting electrode TCNE5 is connected to the fourth intermediate connecting electrode TCNE4 through a contact hole formed through the eighth insulating layer 80. Alternatively, the fifth intermediate connecting electrode TCNE5 can be directly connected to the fourth bridging electrode BCNE4 through contact holes formed through the seventh insulating layer 70 and the eighth insulating layer 80.

[0186] although Figure 11B The figure illustrates a structure in which the fifth intermediate connecting electrode TCNE5 is connected to the fourth intermediate connecting electrode TCNE4, but this disclosure is not limited thereto. For example, the fifth intermediate connecting electrode TCNE5 can be directly connected to the fourth bridging electrode BCNE4, and the fourth intermediate connecting electrode TCNE4 can be omitted.

[0187] The ninth insulating layer 90 is disposed on the eighth insulating layer 80 to cover the second connecting line TCL2, the first intermediate connecting electrode TCNE1 and the fifth intermediate connecting electrode TCNE5.

[0188] The first connecting line TCL1 and the second connecting line TCL2 may include a transparent conductive material. Even if the first connecting line TCL1 and the second connecting line TCL2 are disposed in the first region DP_SA, the light transmittance of the first region DP_SA can be prevented from decreasing due to the first connecting line TCL1 and the second connecting line TCL2. Alternatively, when the first bridging line BCL1 to the third bridging line BCL3 also include a transparent conductive oxide, the light transmittance of the first region DP_SA can be further improved.

[0189] The light-emitting element layer DP_ED is disposed on the circuit layer DP_CL. The light-emitting element layer DP_ED may include a first-first light-emitting element ED11, a first-first sub-light-emitting element ED11S, a first-second light-emitting element ED12, a first-second sub-light-emitting element ED12S, a third light-emitting element ED3, and a pixel defining layer PDL. The first-first light-emitting element ED11 includes a first-first anode AE11, a first-first light-emitting layer EL11, and a common cathode CE. The first-first sub-light-emitting element ED11S includes a first-first sub-anode AE11S, a first-first sub-light-emitting layer EL11S, and a common cathode CE. The first-second light-emitting element ED12 includes a first-second anode AE12, a first-second light-emitting layer EL12, and a common cathode CE. The first-second sub-light-emitting element ED12S includes a first-second sub-anode AE12S, a first-second sub-light-emitting layer EL12S, and a common cathode CE.

[0190] Anodes AE11 (1-1) and AE12 (1-2), and sub-anodes AE11S (1-1) and AE12S (1-2) are disposed on the ninth insulating layer 90. Anode AE11 (1-1) is connected to the first intermediate connecting electrode TCNE1 through a contact hole formed in the first connecting region SA11 through the ninth insulating layer 90. Anode AE12 (1-2) is connected to the opposite end (or "second end") of the second connecting line TCL2 through a contact hole formed in the first connecting region SA12 through the ninth insulating layer 90. Sub-anodes AE11S (1-1) and AE12S (1-2) are connected to the fifth intermediate connecting electrode TCNE5 through contact holes formed in the ninth insulating layer 90.

[0191] although Figure 11A and Figure 11BThe figure illustrates a structure in which the first-1 sub-anode AE11S and the first-2 sub-anode AE12S are connected to the fourth intermediate connecting electrode TCNE4 via the fifth intermediate connecting electrode TCNE5, but this disclosure is not limited thereto. For example, the first-1 sub-anode AE11S and the first-2 sub-anode AE12S can be directly connected to the fourth intermediate connecting electrode TCNE4 or the fourth bridging electrode BCNE4. In this case, the fourth intermediate connecting electrode TCNE4 or the fifth intermediate connecting electrode TCNE5 can be omitted.

[0192] A pixel-defining layer (PDL) may be disposed on a ninth insulating layer 90 and may include a first opening OP1, a second opening OP2, and a third opening OP3 defined to correspond to the first-first light-emitting element ED11, the first-second light-emitting element ED12, and the third light-emitting element ED3, respectively, and a first sub-opening S_OP1 and a second sub-opening S_OP2 defined to correspond to the first-first sub-light-emitting element ED11S and the first-second sub-light-emitting element ED12S, respectively. The first opening OP1 exposes at least a portion of the first-first anode AE11 of the first-first light-emitting element ED11, and the second opening OP2 exposes at least a portion of the first-second anode AE12 of the first-second light-emitting element ED12. The third opening OP3 exposes at least a portion of the third anode AE3 of the third light-emitting element ED3 (see, for example, [link to relevant documentation]). Figure 9A and Figure 9B The first sub-opening S_OP1 exposes at least a portion of the first-1 sub-anode AE11S of the first-1 sub-light-emitting element ED11S, and the second sub-opening S_OP2 exposes at least a portion of the first-2 sub-anode AE12S of the first-2 sub-light-emitting element ED12S. The first opening OP1, the second opening OP2, and the third opening OP3 of the pixel-defining layer PDL can define the light-emitting area.

[0193] The first-1 sub-emitting layer EL11S is configured to correspond to the first sub-opening S_OP1, and the first-2 sub-emitting layer EL12S is configured to correspond to the second sub-opening S_OP2.

[0194] A common cathode (CE) is disposed on the light-emitting layers EL11, EL12, and EL3, and the sub-light-emitting layers EL11S and EL12S. The common cathode (CE) is also disposed on multiple pixels PX1 to PX3 (see [link to documentation]). Figure 6A Alternatively, the common cathode CE may include a first common cathode jointly disposed in a first pixel PX1 and a second pixel PX2 in the first region DP_SA, and a second common cathode jointly disposed in a third pixel PX3 in the second region DP_NSA. The first common cathode and the second common cathode may receive different second driving voltages ELVSS (see [link to relevant documentation]). Figure 5 ).

[0195] Figure 12 This is a block diagram illustrating the lengths of the first to third connecting lines according to one or more embodiments of the present disclosure. Figure 12 The components shown in the figure are... Figure 7 Components that are identical to those shown in the figures will be assigned the same reference numerals, and their details will be omitted to avoid redundancy.

[0196] refer to Figure 12 The first region DP_SA may include a first sub-region SA1 and a second sub-region SA2. According to one or more embodiments of this disclosure, the first sub-region SA1 may have an angular circular shape. The first sub-region SA1 may be divided into two regions (i.e., sub-region 1-1 SA1c and sub-region 1-2 SA1d) about a reference axis RX parallel to the second direction DR2 and passing through the center point CP. In other words, sub-region 1-1 SA1c is located on a first side (e.g., the right side) about the reference axis RX, and sub-region 1-2 SA1d is located on a second side (e.g., the left side) about the reference axis RX. Sub-regions 1-1 SA1c and 1-2 SA1d may have shapes symmetrical to each other about the reference axis RX. According to one or more embodiments of this disclosure, each of sub-regions 1-1 SA1c and 1-2 SA1d may have an angular semi-circular shape.

[0197] Each of sub-regions 1-1 (SA1c) and 1-2 (SA1d) may include multiple first connection regions. Although Figure 12 The diagram illustrates a structure including sub-region 1-1 SA1c and sub-region 1-2 SA1d, each of which has three first connecting regions, but this disclosure is not limited thereto. These three first connecting regions may be referred to as connecting region 1-1 SA11, connecting region 1-2 SA12, and connecting region 1-3 SA13, respectively. Connecting region 1-1 SA11 is adjacent to the center, and connecting region 1-2 SA12 is located outside connecting region 1-1 SA11. Connecting region 1-2 SA12 may be configured to surround (e.g., encircle) connecting region 1-1 SA11. Connecting region 1-3 SA13 may be configured to be adjacent to the boundary between sub-region 1 and sub-region 2 SA2. According to one or more embodiments of this disclosure, stepped boundary lines may be formed between connecting region 1-1 SA11 and connecting region 1-2 SA12, and between connecting region 1-2 SA12 and connecting region 1-3 SA13.

[0198] The second sub-region SA2 includes the second-first sub-region SA2c, which is adjacent to the first-first sub-region SA1c, and the second-second sub-region SA2d, which is adjacent to the first-second sub-region SA1d. In other words, the second-first sub-region SA2c is interposed between the first-first sub-region SA1c and the second sub-region DP_NSA, and the second-second sub-region SA2d is interposed between the first-second sub-region SA1d and the second sub-region DP_NSA.

[0199] Each of sub-regions 2-1 (SA2c) and 2-2 (SA2d) may include multiple second connection regions. Although Figure 12 The diagram illustrates a structure including sub-region 2-1 SA2c and sub-region 2-2 SA2d, each of which has three second connection regions, but this disclosure is not limited thereto. These three second connection regions may be referred to as connection region 2-1 SA21, connection region 2-2 SA22, and connection region 2-3 SA23, respectively. According to one or more embodiments of this disclosure, stepped boundary lines may be formed between connection region 2-1 SA21 and connection region 2-2 SA22, and between connection region 2-2 SA22 and connection region 2-3 SA23.

[0200] Accordingly, the distance between the first-third connection area SA13 and the second-third connection area SA23 is shorter than the distance between the first-second connection area SA12 and the second-second connection area SA22. The distance between the first-second connection area SA12 and the second-second connection area SA22 can be shorter than the distance between the first-first connection area SA11 and the second-first connection area SA21.

[0201] The connecting cable TCL may include multiple connecting cables. These multiple connecting cables may include a first connecting cable TCL1, a second connecting cable TCL2, and a third connecting cable TCL3. The length of the first connecting cable TCL1 is longer than the length of the second connecting cable TCL2, and the length of the second connecting cable TCL2 is longer than the length of the third connecting cable TCL3.

[0202] According to one or more embodiments of this disclosure, a first connecting line TCL1 may include a first-1 connecting line TCL11, a first-2 connecting line TCL12, and a first-3 connecting line TCL13. The first-1 connecting line TCL11, the first-2 connecting line TCL12, and the first-3 connecting line TCL13 have equal (or substantially equal) lengths. The first-1 connecting line TCL11, the first-2 connecting line TCL12, and the first-3 connecting line TCL13 may have equal line resistances. A second connecting line TCL2 may include a second-1 connecting line TCL21, a second-2 connecting line TCL22, and a second-3 connecting line TCL23. The second-1 connecting line TCL21, the second-2 connecting line TCL22, and the second-3 connecting line TCL23 have equal (or substantially equal) lengths. Connecting wires TCL21 (2-1), TCL22 (2-2), and TCL23 (2-3) may have equal line resistance. The third connecting wire TCL3 may include connecting wires TCL31 (3-1), TCL32 (3-2), and TCL33 (3-3). Connecting wires TCL31 (3-1), TCL32 (3-2), and TCL33 (3-3) have equal (or substantially equal) lengths. Connecting wires TCL31 (3-1), TCL32 (3-2), and TCL33 (3-3) may have equal line resistance.

[0203] Even though the first connecting line TCL1, the second connecting line TCL2, and the third connecting line TCL3 have unequal lengths, they can still have equal line resistance.

[0204] Figure 13A and Figure 13B This is a cross-sectional view illustrating a first connecting line and a second connecting line according to one or more embodiments of the present disclosure. Figure 13A In this context, the first connecting line TCL1a can have a width wider than the second connecting line TCL2. Figure 13B In this process, the first connecting line TCL1b may have a thickness greater than that of the second connecting line TCL2.

[0205] refer to Figure 13AThe first connecting line TCL1a can be disposed on the seventh insulating layer 70, and the second connecting line TCL2 can be disposed on the eighth insulating layer 80. Because the first connecting line TCL1a can have a longer length than the second connecting line TCL2, the line resistance of the first connecting line TCL1a can be greater than the line resistance of the second connecting line TCL2. However, the width of the first connecting line TCL1a can be adjusted to compensate for the difference in line resistance between the first connecting line TCL1a and the second connecting line TCL2. In other words, when the width of the first connecting line TCL1a is wider than the width of the second connecting line TCL2, the difference in line resistance caused by the difference in length between the first connecting line TCL1a and the second connecting line TCL2 can be compensated. In other words, even if the first connecting line TCL1a and the second connecting line TCL2 have different lengths, the first connecting line TCL1a and the second connecting line TCL2 can have equal line resistance.

[0206] refer to Figure 13B The thickness of the first connecting line TCL1b can be adjusted to compensate for the difference in line resistance between the first connecting line TCL1b and the second connecting line TCL2. In other words, when the thickness of the first connecting line TCL1b is greater than the thickness of the second connecting line TCL2, the difference in line resistance caused by the difference in length between the first connecting line TCL1b and the second connecting line TCL2 can be compensated. In other words, even if the first connecting line TCL1b and the second connecting line TCL2 have different lengths, they can still have equal line resistance.

[0207] The first connecting line TCL1b may have a multi-layer stacked structure (e.g., a two-layer stacked structure or a three-layer stacked structure). According to one or more embodiments of this disclosure, when the first connecting line TCL1b has a two-layer stacked structure, the first connecting line TCL1b may include a first layer line L1 and a second layer line L2 disposed on the first layer line L1. In one or more embodiments, the second connecting line TCL2 may have a single-layer structure.

[0208] Figure 14 This is a view illustrating the shape of a first region according to one or more embodiments of the present disclosure and the arrangement of connecting lines caused by that shape.

[0209] refer to Figure 14The first region DP_SA may include a first sub-region SA3 and a second sub-region SA4. According to one or more embodiments of this disclosure, the first sub-region SA3 may have a circular shape. The first sub-region SA3 may be divided into four regions (i.e., sub-region 1-1 SA3a, sub-region 1-2 SA3b, sub-region 1-3 SA3c, and sub-region 1-4 SA3d) about the horizontal reference axis RX_H and the vertical reference axis RX_V, which is parallel to the second direction DR2 and passes through the center point CP. In other words, sub-regions 1-1 SA3a and 1-2 SA3b are located on a first side (e.g., the right side) about the vertical reference axis RX_V, and sub-regions 1-3 SA3c and 1-4 SA3d are located on a second side (e.g., the left side) about the vertical reference axis RX_V. When viewed on the horizontal reference axis RX_H, sub-region 1-1 SA3a is positioned above sub-region 1-2 SA3b, and when viewed on the horizontal reference axis RX_H, sub-region 1-3 SA3c is positioned above sub-region 1-4 SA3d.

[0210] Sub-regions 1-1 (SA3a) and 1-2 (SA3b) are symmetrical about the horizontal reference axis RX_H. Sub-regions 1-1 (SA3a) and 1-3 (SA3c) may be symmetrical about the vertical reference axis RX_V. Sub-regions 1-3 (SA3c) and 1-4 (SA3d) are symmetrical about the horizontal reference axis RX_H. Sub-regions 1-2 (SA3b) and 1-4 (SA3d) may be symmetrical about the vertical reference axis RX_V.

[0211] Each of sub-regions 1-1 SA3a to 1-4 SA3d may include multiple first connection regions. Although Figure 14 The diagram illustrates a structure including sub-regions 1-1 SA3a to 1-4 SA3d, each of which has six first connection regions, but this disclosure is not limited thereto. These six first connection regions may be referred to as connection region 1-1 SA31, connection region 1-2 SA32, connection region 1-3 SA33, connection region 1-4 SA34, connection region 1-5 SA35, and connection region 1-6 SA36.

[0212] The first-1 connecting region SA31, adjacent to the center point CP, can have a rectangular shape. The first-2 connecting region SA32, adjacent to the first side (e.g., the upper side) of the first-1 connecting region SA31, can have a rectangular shape. The first-3 connecting region SA33, adjacent to the second side (e.g., the right side) of the first-1 connecting region SA31, can have a rectangular shape. The first-4 connecting region SA34 is interposed between the boundary between the first sub-region SA3 and the second region DP_NSA and the first side (e.g., the upper side) of the first-2 connecting region SA32. The first-5 connecting region SA35 is interposed between the boundary between the first sub-region SA3 and the second region DP_NSA and the first side (e.g., the upper side) of the first-3 connecting region SA33. The first-6 connecting region SA36 is interposed between the boundary between the first sub-region SA3 and the second region DP_NSA and the second side (e.g., the right side) of the first-3 connecting region SA33.

[0213] The second sub-region SA4 includes sub-regions SA4a (2-1), SA4b (2-2), SA4c (2-3), and SA4d (2-4). Sub-regions SA4a (2-1) and SA4b (2-2) are positioned adjacent to sub-regions SA3a (1-1) and SA3b (1-2). Sub-regions SA4a (2-1) and SA4b (2-2) have shapes that are symmetrical about a first reference axis RX1 parallel to the vertical reference axis RX_V, respectively, to the shapes of sub-regions SA3a (1-1) and SA3b (1-2). Sub-regions SA4c (2-3) and SA4d (2-4) are positioned adjacent to sub-regions SA3c (1-3) and SA3d (1-4). Subregions 2-3 (SA4c) and 2-4 (SA4d) have shapes that are symmetrical about the shapes of subregions 1-3 (SA3c) and 1-4 (SA3d) about a second reference axis RX2 that is parallel to the vertical reference axis RX_V.

[0214] Each of sub-regions 2-1 SA4a to 2-4 SA4d may include multiple second connection regions. Although Figure 14 The diagram illustrates a structure including sub-regions 2-1 SA4a to 2-4 SA4d, each of which has six second connection regions, but this disclosure is not limited thereto. These six second connection regions may be referred to as connection region 2-1 SA41, connection region 2-2 SA42, connection region 2-3 SA43, connection region 2-4 SA44, connection region 2-5 SA45, and connection region 2-6 SA46.

[0215] The first connecting line TCL1 may include a first-1 connecting line TCL1a, a first-2 connecting line TCL1b, and a first-3 connecting line TCL1c, and the second connecting line TCL2 includes a second-1 connecting line TCL2a, a second-2 connecting line TCL2b, and a second-3 connecting line TCL2c. The first-1 connecting line TCL1a connects the first-1 light-emitting element disposed in the first-1 connecting area SA31 to the first-1 pixel circuit disposed in the second-1 connecting area SA41. The first-2 connecting line TCL1b connects the first-4 light-emitting element disposed in the first-4 connecting area SA34 to the first-4 pixel circuit disposed in the second-4 connecting area SA44. The first-3 connecting line TCL1c connects the first-5 light-emitting element disposed in the first-5 connecting area SA35 to the first-5 pixel circuit disposed in the second-5 connecting area SA45. Connection line TCL2a (2-1) will connect the first and second light-emitting elements in connection area SA32 (1-2) to the first and second pixel circuits in connection area SA42 (2-2). Connection line TCL2b (2-2) will connect the first and third light-emitting elements in connection area SA33 (1-3) to the first and third pixel circuits in connection area SA43 (2-3). Connection line TCL2c (2-3) will connect the first and sixth light-emitting elements in connection area SA36 (1-6) to the first and sixth pixel circuits in connection area SA46 (2-6).

[0216] Connector TCL1a (1-1) can extend from Connector SA31 (1-1) to Connector SA41 (2-1) while passing through Connector SA33 (1-3), Connector SA36 (1-6), Connector SA46 (2-6), and Connector SA43 (2-3). Connector TCL1b (1-2) can be arranged to bypass Connector SA41 (2-4). Connector TCL1b (1-2) can extend from Connector SA34 (1-4) to Connector SA44 (2-4) to pass through Connector SA41 (2-4). Connector TCL1c (1-3) can extend from Connector SA35 (1-5) to Connector SA45 (2-5) to pass through Connector SA41 (2-5).

[0217] Connector TCL2a (2-1) can be arranged to bypass the second zone DP_NSA. Specifically, connector TCL2a can extend from the first-second connection zone SA32 to the second-second connection zone SA42, passing through the first-fourth connection zone SA34, the second zone DP_NSA, and the second-fourth connection zone SA44. Connector TCL2b (2-2) can be arranged to bypass the second zone DP_NSA. Specifically, connector TCL2b can extend from the first-third connection zone SA33 to the second-third connection zone SA43, passing through the first-fifth connection zone SA35, the second zone DP_NSA, and the second-fifth connection zone SA45. Connector TCL2c (2-3) can extend from the first-sixth connection zone SA36 to the second-sixth connection zone SA46, passing through the second zone DP_NSA.

[0218] Connecting lines TCL1a, TCL1b, and TCL1c (first-1, second-2, and third-3) are located on the first layer, while connecting lines TCL2a, TCL2b, and TCL2c (second-1, second-2, and third-3) are located on the second layer. In other words, the first connecting line TCL1 and the second connecting line TCL2 are located on different layers.

[0219] Since some of the connecting lines TCL1a to TCL1c and TCL2a to TCL2c in the first zone DP_SA are configured to bypass to the second zone DP_NSA, the connecting lines TCL1a to TCL1c and TCL2a to TCL2c in the first zone DP_SA can be placed on two layers (i.e., the first layer and the second layer). Accordingly, the connecting lines TCL1a to TCL1c and TCL2a to TCL2c are effectively arranged in a confined area to reduce the density of the connecting lines, thus preventing the addition of layers, thereby preventing an increase in the thickness of the display panel DP, or preventing the addition of process masks during the manufacturing of the display panel DP.

[0220] Figure 15 This is a view illustrating the shape of a first region according to one or more embodiments of the present disclosure and the arrangement of connecting lines caused by that shape.

[0221] refer to Figure 15The first region DP_SA may include a first sub-region SA5 and a second sub-region SA6. According to one or more embodiments of this disclosure, the first sub-region SA5 may have a rectangular shape (e.g., a square shape). The first sub-region SA5 may be divided into two regions (i.e., sub-region 1-1 SA5a and sub-region 1-2 SA5b) about a reference axis RX that is parallel to the second direction DR2 and passes through the center point CP. In other words, sub-region 1-1 SA5a is located on a first side (e.g., the right side) about the reference axis RX, and sub-region 1-2 SA5b is located on a second side (e.g., the left side) about the reference axis RX. Each of sub-region 1-1 SA5a (or referred to as "sub-1 rectangular region") and sub-region 1-2 SA5b (or referred to as "sub-2 rectangular region") may have a rectangular shape. Sub-region 1-1 SA5a and sub-region 1-2 SA5b may have shapes that are symmetrical to each other about the reference axis RX.

[0222] Each of sub-regions 1-1 SA5a and 1-2 SA5b may include multiple first connection regions. Although Figure 15 The diagram illustrates a structure including a first sub-region SA5a and a first sub-region SA5b, each of which has three first connecting regions, but this disclosure is not limited thereto. These three first connecting regions may be referred to as first connecting region SA51, first connecting region SA52, and first connecting region SA53, respectively. First connecting region SA51 is adjacent to the center, and first connecting region SA52 is located outside first connecting region SA51. First connecting region SA53 may be positioned adjacent to the boundary between the first sub-region SA5a and the second sub-region SA6. According to one or more embodiments of this disclosure, first connecting region SA52 may be interposed between first connecting region SA51 and first connecting region SA53.

[0223] The second sub-region SA6 includes a second-first sub-region SA6a (or referred to as the "second-first rectangular region") adjacent to the first-first sub-region SA5a, and a second-second sub-region SA6b (or referred to as the "second-second rectangular region") adjacent to the first-second sub-region SA5b. In other words, the second-first sub-region SA6a is interposed between the first-first sub-region SA5a and the second region DP_NSA, and the second-second sub-region SA6b is interposed between the first-second sub-region SA5b and the second region DP_NSA. The second-first sub-region SA6a may have a shape symmetrical to the shape of the first-first sub-region SA5a about a first reference axis RX1 parallel to the reference axis RX. The second-second sub-region SA6b may have a shape symmetrical to the shape of the first-second sub-region SA5b about a second reference axis RX2 parallel to the reference axis RX.

[0224] Each of sub-regions 2-1 SA6a and 2-2 SA6b may include multiple second connection regions. Although Figure 15 The diagram illustrates a structure including a second-1 sub-region SA6a and a second-2 sub-region SA6b, each of which has three second connection regions, but this disclosure is not limited thereto. These three second connection regions may be referred to as second-1 connection region SA61, second-2 connection region SA62, and second-3 connection region SA63, respectively. According to one or more embodiments of this disclosure, second-2 connection region SA62 is configured to be more adjacent to the first sub-region SA5 than second-1 connection region SA61, and second-3 connection region SA63 is configured to be more adjacent to the first sub-region SA5 than second-2 connection region SA62.

[0225] The connecting line TCL may include multiple connecting lines. The connecting lines may include a first connecting line TCL1, a second connecting line TCL2, and a third connecting line TCL3. The first connecting line TCL1 connects the first-1 light-emitting element located in the first-1 connection area SA51 to the first-1 pixel circuit located in the second-1 connection area SA61. The second connecting line TCL2 connects the first-2 light-emitting elements located in the first-2 connection area SA52 to the first-2 pixel circuit located in the second-2 connection area SA62. The third connecting line TCL3 connects the first-3 light-emitting elements located in the first-3 connection area SA53 to the first-3 pixel circuit located in the second-3 connection area SA63.

[0226] The length of the first connecting wire TCL1 is longer than the length of the second connecting wire TCL2, and the length of the second connecting wire TCL2 is longer than the length of the third connecting wire TCL3. The line resistance of the first connecting wire TCL1 can be equal to or different from the line resistance of the second connecting wire TCL2. The thickness and width of the first connecting wire TCL1 are adjusted so that the line resistance of the first connecting wire TCL1 is equal to the line resistance of the second connecting wire TCL2.

[0227] According to one or more embodiments of this disclosure, the first connecting lines TCL1 have equal lengths, and the second connecting lines TCL2 have equal lengths. Accordingly, the first connecting lines TCL1 have equal line resistances, and the second connecting lines TCL2 have equal line resistances. Furthermore, since the third connecting line TCL3 has equal lengths, the third connecting line TCL3 can also have equal line resistances.

[0228] The first connecting line TCL1 can extend from the first-1 connecting area SA51 to the second-1 connecting area SA61. The first connecting line TCL1 can be arranged to bypass the second area DP_NSA. Some of the first connecting lines TCL1 can partially overlap with the second area DP_NSA. The second connecting line TCL2 can extend from the first-2 connecting area SA52 to the second-2 connecting area SA62. The second connecting line TCL2 can partially overlap with the first-3 connecting area SA53 and the second-3 connecting area SA63. The third connecting line TCL3 can extend from the first-3 connecting area SA53 to the second-3 connecting area SA63.

[0229] According to one or more embodiments of this disclosure, a first connecting line TCL1 is disposed on a first layer, a second connecting line TCL2 is disposed on a second layer, and a third connecting line TCL3 is disposed on either the first or the second layer. In other words, the first connecting line TCL1 and the second connecting line TCL2 may be disposed on different layers from each other, and the third connecting line TCL3 may be disposed on the same layer as the first connecting line TCL1, or on the same layer as the second connecting line TCL2.

[0230] Figure 16 This is a view illustrating the shape of a first region according to one or more embodiments of the present disclosure and the arrangement of connecting lines caused by that shape.

[0231] refer to Figure 16 The first region DP_SA may include a first sub-region SA7 and a second sub-region SA8. According to one or more embodiments of this disclosure, the first sub-region SA7 may have a circular shape. The first sub-region SA7 may be divided into two regions (i.e., sub-region 1-1 SA7a and sub-region 1-2 SA7b) about a reference axis RX that is parallel to the second direction DR2 and passes through the center point CP. In other words, sub-region 1-1 SA7a is located on a first side (e.g., the right side) about the reference axis RX, and sub-region 1-2 SA7b is located on a second side (e.g., the left side) about the reference axis RX. Each of sub-region 1-1 SA7a (or referred to as the 1-1 semicircular region) and sub-region 1-2 SA7b (or referred to as the 1-2 semicircular region) may have a semicircular shape. Sub-region 1-1 SA7a and sub-region 1-2 SA7b may have shapes that are symmetrical to each other about the reference axis RX.

[0232] Each of sub-regions 1-1 SA7a and 1-2 SA7b may include multiple first connection regions. Although Figure 16The diagram illustrates a structure including a first sub-region SA7a and a first sub-region SA7b, each of which has three first connection regions, but this disclosure is not limited thereto. These three first connection regions may be referred to as first-first connection region SA71, first-second connection region SA72, and first-third connection region SA73, respectively. First-first connection region SA71 is adjacent to the center, and first-second connection region SA72 is configured to surround (e.g., encircle) first-first connection region SA71. First-third connection region SA73 is configured to surround (e.g., encircle) first-second connection region SA72. According to one or more embodiments of this disclosure, first-second connection region SA72 may be interposed between first-first connection region SA71 and first-third connection region SA73.

[0233] The second sub-region SA8 includes a second-first sub-region SA8a (or referred to as the "second-first semicircular region") adjacent to the first-first sub-region SA7a, and a second-second sub-region SA8b (or referred to as the "second-second semicircular region") adjacent to the first-second sub-region SA7b. In other words, the second-first sub-region SA8a may have a shape symmetrical to the shape of the first-first sub-region SA7a about a first reference axis RX1 parallel to the reference axis RX. The second-second sub-region SA8b may have a shape symmetrical to the shape of the first-second sub-region SA7b about a second reference axis RX2 parallel to the reference axis RX.

[0234] Although the diagram illustrates a structure including sub-regions 2-1 SA8a and 2-2 SA8b, each of which has three second connection regions, this disclosure is not limited thereto. These three second connection regions may be referred to as connection region 2-1 SA81, connection region 2-2 SA82, and connection region 2-3 SA83, respectively.

[0235] The connecting line TCL may include multiple connecting lines. The connecting lines may include a first connecting line TCL1, a second connecting line TCL2, and a third connecting line TCL3. The first connecting line TCL1 connects the first-1 light-emitting element located in the first-1 connecting area SA71 to the first-1 pixel circuit located in the second-1 connecting area SA81. The second connecting line TCL2 connects the first-2 light-emitting element located in the first-2 connecting area SA72 to the first-2 pixel circuit located in the second-2 connecting area SA82. The third connecting line TCL3 connects the first-3 light-emitting element located in the first-3 connecting area SA73 to the first-3 pixel circuit located in the second-3 connecting area SA83.

[0236] According to one or more embodiments of this disclosure, a first connecting line TCL1 is disposed on a first layer, a second connecting line TCL2 is disposed on a second layer, and a third connecting line TCL3 is disposed on either the first or the second layer. In other words, the first connecting line TCL1 and the second connecting line TCL2 may be disposed on different layers from each other, and the third connecting line TCL3 may be disposed on the same layer as the first connecting line TCL1, or on the same layer as the second connecting line TCL2.

[0237] As described above, some of the connecting lines in the first zone are arranged to bypass the second zone, so that the connecting lines in the first zone can be provided on two layers (i.e., the first layer and the second layer). Accordingly, the connecting lines are effectively arranged in a confined area to reduce the density of the connecting lines, thus preventing the addition of layers, thereby preventing an increase in the thickness of the display panel, or preventing the addition of process masks during the manufacturing of the display panel. Consequently, the manufacturing process of the display panel can be simplified, thereby improving productivity.

[0238] Furthermore, the density of connecting lines in the first region can be reduced. Consequently, the transmittance of the first region can be increased, thereby improving the performance of the electronic module in optical communication through the first region.

[0239] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of this disclosure as set forth in the appended claims and their equivalents.

Claims

1.An electronic device comprising: a display panel including a first area and a second area adjacent to the first area, wherein the first area includes a first sub-area and a second sub-area having a transmittance lower than that of the first sub-area; and an electronic module corresponding to the first area, below the display panel, wherein the display panel includes: a first light emitting element in the first sub-area; a first pixel circuit connected to the first light emitting element and located in the second sub-area; a second light emitting element in the second sub-area; a second pixel circuit connected to the second light emitting element and located in the second sub-area; and a connection line connecting the first light emitting element to the first pixel circuit, wherein the connection line includes: a first connection line on a first layer; and a second connection line on a second layer covering the first connection line, and wherein the first connection line has a length different from a length of the second connection line. 2.The electronic device of claim 1, wherein, the first sub-area includes: a 1-1 connection area adjacent to a center of the first sub-area, a 1-1 light emitting element located in the 1-1 connection area; and a 1-2 connection area outside the 1-1 connection area, a 1-2 light emitting element located in the 1-2 connection area, wherein the second sub-area includes: a 2-1 connection area, a 1-1 pixel circuit connected to the 1-1 light emitting element located in the 2-1 connection area; and a 2-2 connection area, a 1-2 pixel circuit connected to the 1-2 light emitting element located in the 2-2 connection area, and wherein the 2-2 connection area is more adjacent to the first sub-area than the 2-1 connection area. 3.The electronic device of claim 2, wherein, the first connection line connects the 1-1 light emitting element to the 1-1 pixel circuit; wherein the second connection line connects the 1-2 light emitting element to the 1-2 pixel circuit; and wherein the length of the first connection line is greater than the length of the second connection line. 4.The electronic device of claim 3, wherein, the first connection line has the length equal to each other, and wherein the second connection line has the length equal to each other. 5.The electronic device of claim 3, wherein a line resistance of the first connection line is equal to a line resistance of the second connection line. 6.The electronic device of claim 5, wherein, a width of the first connection line is different from a width of the second connection line. 7.The electronic device of claim 5, wherein a thickness of the first connection line is different from a thickness of the second connection line. 8.The electronic device of claim 2, wherein the first connection line partially overlaps the second area. 9.The electronic device of claim 2, wherein the first sub-area further includes: a 1-3 connection area adjacent to a boundary between the first sub-area and the second sub-area, a 1-3 light emitting element located in the 1-3 connection area, wherein the second sub-area further includes: a 2-3 connection area, a 1-3 pixel circuit connected to the 1-3 light emitting element located in the 2-3 connection area, and wherein the 2-3 connection area is interposed between the 1-3 connection area and the 2-2 connection area. 10.The electronic device of claim 9, wherein the first connection line connects the 1-1 light emitting element to the 1-1 pixel circuit, wherein the second connection line connects the 1-2 light emitting element to the 1-2 pixel circuit, wherein the connection line further includes: a third connection line connecting the 1-3 light emitting element to the 1-3 pixel circuit, and wherein the third connection line is on the first layer or the second layer. 11.The electronic device of claim 10, wherein the first connection line has the length longer than the length of the second connection line, and wherein the third connection line has the length shorter than the length of the second connection line. 12.The electronic device of claim 10, wherein, the second connection line overlaps the 1-2 connection area, the 1-3 connection area, the 2-3 connection area, and the 2-2 connection area. 13.The electronic device of claim 10, wherein the first connection line has the length equal to each other, wherein the second connection line has the length equal to each other, and wherein the third connection line has the length equal to each other. 14.The electronic device of claim 10, wherein a line resistance of the first connection line is equal to a line resistance of the second connection line and a line resistance of the third connection line. 15.The electronic device of claim 1, wherein, the first sub-area includes: a 1-1 sub-area at a first side with respect to a reference axis; and a 1-2 sub-area at a second side with respect to the reference axis, and wherein the second sub-area includes: a 2-1 sub-area adjacent to the 1-1 sub-area and symmetrical to the 1-1 sub-area with respect to a first reference axis; and a 2-2 sub-area adjacent to the 1-2 sub-area and symmetrical to the 1-2 sub-area with respect to a second reference axis. 16.The electronic device of claim 15, wherein, the 1-1 sub-area includes: a 1-1 connection area adjacent to a center of the first sub-area, a 1-1 light emitting element being located in the 1-1 connection area; and a 1-2 connection area outside the 1-1 connection area, a 1-2 light emitting element being located in the 1-2 connection area, and wherein the 2-1 sub-area includes: a 2-1 connection area symmetrical to the 1-1 connection area with respect to the first reference axis and including a 1-1 pixel circuit connected to the 1-1 light emitting element; and a 2-2 connection area symmetrical to the 1-2 connection area with respect to the first reference axis and including a 1-2 pixel circuit connected to the 1-2 light emitting element. 17.The electronic device of any one of claims 1-14, wherein, the first sub-area has a circular shape based on a center point, and wherein the second sub-area corresponds to a remaining area of an area based on the center point defined to include the first sub-area except for the first sub-area. 18.The electronic device of any one of claims 1-14, wherein, the first sub-area has a circular shape based on a center point and includes a 1-1 semi-circular area and a 1-2 semi-circular area defined based on the center point, and wherein the second sub-area includes: a 2-1 semi-circular area adjacent to the 1-1 semi-circular area; and a 2-2 semi-circular area adjacent to the 1-2 semi-circular area. 19.The electronic device of any one of claims 1-14, wherein, the first sub-area has a rectangular shape based on a center point and includes a 1-1 rectangular area and a 1-2 rectangular area defined based on the center point, and wherein the second sub-area includes: a 2-1 rectangular area adjacent to the 1-1 rectangular area; and a 2-2 rectangular area adjacent to the 1-2 rectangular area. 20.An electronic device comprising: A display panel including a first area and a second area adjacent to the first area, wherein the first area includes a first sub-area and a second sub-area having a transmittance lower than that of the first sub-area; and An electronic module corresponding to the first area below the display panel, wherein the display panel includes: a first light emitting element in the first sub-area; a first pixel circuit connected to the first light emitting element and located in the second sub-area; a second light emitting element in the second sub-area; a second pixel circuit connected to the second light emitting element and located in the second sub-area; and a connection line connecting the first light emitting element to the first pixel circuit, and wherein the connection line includes: a first connection line extending from the second sub-area to the first sub-area; and a second connection line extending from the second sub-area to the first sub-area through the second area.

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