Semiconductor substrate and power conversion device

Abstract

The first conductor layer has a pair of first switch part connection portions disposed along one surface of the insulating substrate in an orthogonal direction, which is a direction orthogonal to the reference axis, so as to sandwich the third conductor layer therebetween, and the third conductor layer has a pair of second switch part connection portions and a pad formation portion. And a pair of second switch portion connection portions disposed in the orthogonal direction so as to sandwich the second conductor layer therebetween, and a pad formation portion sandwiched by the pair of first switch portion connection portions in the orthogonal direction and provided with an output terminal pad. The plurality of first switch parts are arranged symmetrically with respect to the reference axis at a position closer to the output terminal pad side than the center position of the output terminal pad and the negative terminal pad in the reference axis direction, which is a direction along the reference axis, and the first switch part connection part and the pad formation part are connected. The plurality of second switch parts are symmetrically arranged with respect to the reference axis at a position closer to the negative terminal pad side than the center position in the reference axis direction, and the second switch part connection portion is connected to the second conductor layer.

Description

Technical Field

[0001] This invention relates to semiconductor substrates and power conversion devices. Background Technology

[0002] For example, Patent Document 1 discloses a semiconductor module incorporating semiconductor elements. The semiconductor module disclosed in Patent Document 1 includes a first semiconductor element and a second semiconductor element connected in parallel to form an upper arm. Furthermore, the semiconductor module disclosed in Patent Document 1 includes a third semiconductor element and a fourth semiconductor element connected in parallel to form a lower arm.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141221 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] Patent Document 1 discloses a semiconductor module that is generally rectangular, having an output terminal at one end and a negative terminal at the other end. These output terminals and the negative terminal are positioned at the center of the semiconductor module's width. A first semiconductor element and a second semiconductor element are arranged such that they sandwich the center of the width direction. Furthermore, a third semiconductor element and a fourth semiconductor element are also arranged such that they sandwich the center of the width direction. In this Patent Document 1, current flows through the first and second semiconductor elements toward the center of the width direction, while current flows through the third and fourth semiconductor elements outward from the center of the width direction. Therefore, the path from which the current through the third semiconductor element and the current through the fourth semiconductor element merge is longer than the path from which the current through the first semiconductor element and the current through the second semiconductor element merge, resulting in a larger parasitic inductance in the lower arm than in the upper arm. Consequently, the semiconductor module of Patent Document 1 has a structure that easily induces oscillation.

[0008] The present invention was made in view of the above-mentioned problems, and its object is to suppress oscillations in a semiconductor substrate having an upper arm and a lower arm formed thereon.

[0009] Technical solutions for solving technical problems

[0010] As a technical solution to solve the above-mentioned technical problems, the present invention adopts the following structure.

[0011] The first embodiment of the present invention is a semiconductor substrate having an upper arm and a lower arm forming a bridge arm. The substrate includes an insulating substrate, a conductor layer formed on one side of the insulating substrate, and a semiconductor element mounted on the conductor layer. The semiconductor substrate includes: a first conductor layer having a positive terminal pad for connecting a positive terminal; a second conductor layer having a negative terminal pad for connecting a negative terminal; a third conductor layer having an output terminal pad for connecting an output terminal; a plurality of first switching portions connecting the first conductor layer and the third conductor layer, and having the semiconductor element; a plurality of second switching portions connecting the second conductor layer and the third conductor layer, and having the semiconductor element. The output terminal pad and the negative terminal pad are arranged on a reference axis. The first conductor layer has a pair of first switching portion connection portions, which are connected to the semiconductor element on a surface along one side of the insulating substrate. The third conductor layer is configured to sandwich each other in the orthogonal direction of the reference axis. The third conductor layer has a pair of second switch connection portions and a pad forming portion. The pair of second switch connection portions are configured in the orthogonal direction to sandwich the second conductor layer between each other. The pad forming portion is sandwiched by a pair of first switch connection portions in the orthogonal direction and is provided with the output terminal pad. A plurality of first switches are symmetrically arranged relative to the reference axis at a position closer to the output terminal pad than the center position of the output terminal pad and the negative terminal pad along the reference axis. The first switch connection portions are connected to the pad forming portion. A plurality of second switches are symmetrically arranged relative to the reference axis at a position closer to the negative terminal pad than the center position of the second switch portion. The second switch connection portions are connected to the second conductor layer.

[0012] The second aspect of the present invention adopts the following structure: a power conversion device having a power conversion circuit formed by semiconductor elements, wherein the power conversion device includes a semiconductor substrate of the first aspect of the present invention, the semiconductor substrate having the semiconductor elements.

[0013] Invention Effects

[0014] The present invention can suppress oscillations in a semiconductor substrate having an upper arm and a lower arm. Attached Figure Description

[0015] Figure 1 This is an exploded perspective view schematically illustrating the general structure of a power conversion device according to an embodiment of the present invention.

[0016] Figure 2This is a circuit diagram illustrating the electrical schematic structure of a power conversion device according to an embodiment of the present invention.

[0017] Figure 3 This is a schematic exploded perspective view of the power module of the intelligent power module included in a power conversion device according to an embodiment of the present invention.

[0018] Figure 4 This is a schematic top view of the power module of the intelligent power module included in the power conversion device according to an embodiment of the present invention.

[0019] Figure 5 This is a schematic enlarged view of a power module that includes a power device according to this embodiment.

[0020] Figure 6 This is a top view showing the schematic structure of the power device in this embodiment.

[0021] Figure 7 This is a schematic diagram showing the insulating substrate and conductor layer of the power device in this embodiment.

[0022] Figure 8 This is a schematic diagram illustrating the current flow of the power device in this embodiment when the drive current is supplied from the battery to the motor. Detailed Implementation

[0023] Hereinafter, an embodiment of the semiconductor substrate and power conversion device of the present invention will be described with reference to the accompanying drawings.

[0024] Figure 1 This is an exploded perspective view schematically showing the general structure of a power conversion device 1 according to an embodiment of the present invention. The power conversion device 1 of this embodiment is mounted on a vehicle such as an electric vehicle and is installed in the motor M (see reference 1). Figure 3 ) and battery B (refer to Figure 3 Between ( ). The power conversion device 1 of this embodiment performs power conversion between the motor M and the battery B. For example Figure 1 As shown, the power conversion device 1 of this embodiment includes an inverter housing 2, a smart power module 3, and a capacitor module 4. Furthermore, the power conversion device 1 may also include other components such as a DC-DC converter (not shown), a reactor, etc.

[0025] The inverter housing 2 is a housing that houses the intelligent power module 3 and capacitor module 4, etc., and includes a central housing 2a and a housing cover 2b. These central housing 2a and housing cover 2b are formed in a detachable manner. Figure 1The diagram shows the housing cover 2b separated upwards from the central housing 2a. However, the mounting position of the power conversion device 1 is not particularly limited. That is, the power conversion device 1 can also be mounted on the vehicle with the housing cover 2b located to the side of the central housing 2a.

[0026] The central housing 2a has a bottom wall portion that secures the intelligent power module 3 and the capacitor module 4, and a side wall portion that surrounds the intelligent power module 3 and the capacitor module 4. That is, the central housing 2a is formed as a container with an opening on the housing cover 2b side. Such a central housing 2a may be provided with water channels as needed, forming a structure capable of guiding coolant to cool the intelligent power module 3 and the capacitor module 4.

[0027] The housing cover 2b is fixed to the central housing 2a, covering the intelligent power module 3 and the capacitor module 4. That is, the intelligent power module 3 and the capacitor module 4 are exposed by detaching the housing cover 2b from the central housing 2a.

[0028] Such an inverter housing 2 is fixed, for example, to a housing (not shown) that covers the motor M and to a gearbox that houses the gears that transmit the power generated by the motor M to the outside. In such a case, for example, the central housing 2a is fastened to the motor housing and the gearbox using bolts (not shown).

[0029] Additionally, inverter housing 2 holds a connector (not shown) for connecting battery B. This connector is electrically connected to smart power module 3. Furthermore, inverter housing 2 holds a busbar (not shown) connecting the connector to smart power module 3, and a busbar (not shown) connecting smart power module 3 to motor M.

[0030] The intelligent power module 3 comprises a power module 3a and a substrate unit 3b. The power module 3a is a module equipped with multiple power devices D, which will be described later. The structure of the power module 3a will be explained later.

[0031] The substrate unit 3b is stacked on the power module 3a. This substrate unit 3b includes, for example, a gate driver substrate and an ECU (Electronic Control Unit) substrate. The gate driver substrate is a substrate equipped with a gate driver that generates drive signals for the inverter formed by the power module. The ECU substrate is a substrate equipped with an ECU that controls the gate driver substrate.

[0032] Figure 2This is a circuit diagram showing the general electrical structure of the power conversion device 1 according to this embodiment. The power conversion device 1 of this embodiment includes an inverter circuit E. Furthermore, the power conversion device 1 of this embodiment includes the inverter circuit E and a battery B, and a busbar BU connecting the inverter circuit E and a motor M. Additionally, the power conversion device 1 includes a smoothing capacitor C connected in parallel with the inverter circuit E relative to the busbar BU. The inverter circuit E is formed by a power module 3a. Furthermore, the smoothing capacitor C is formed by a capacitor module 4.

[0033] In this embodiment, the power conversion device 1 converts the power supplied by the battery B into three-phase AC power and supplies it to the motor M. Additionally, the power conversion device 1 supplies regenerated power from the motor M to the battery B.

[0034] like Figure 2 As shown, the inverter circuit E has three bridge arms R corresponding to each motor M. Each bridge arm R has an upper arm HA and a lower arm LA. The upper arm HA is connected to the positive terminal of the battery B via a busbar BU. The lower arm LA is connected to the negative terminal of the battery B via a busbar BU. These upper arms HA and lower arms LA are connected in series. An output terminal connecting the bridge arm R to the motor M is connected between the upper arms HA and the lower arms LA.

[0035] In addition, such as Figure 2 As shown, the power conversion device 1 of this embodiment includes power devices D (semiconductor substrates) corresponding to each bridge arm R. That is, in this embodiment, the power conversion device 1 includes three power devices D (semiconductor substrates). Each power device D has a power transistor corresponding to the upper arm HA and a power transistor corresponding to the lower arm. These power transistors are formed using multiple semiconductor elements.

[0036] Figure 3 This is a schematic exploded perspective view of the power module 3a included in the intelligent power module 3. As shown in the figure, the power module 3a includes a module housing 3a1, the aforementioned power devices D, and a heat sink 3a2. The module housing 3a1 is a resin housing for housing the power devices D, etc. The module housing 3a1 has an opening for housing each power device D. Such a module housing 3a1 is fixed to the heat sink 3a2, for example, by adhesive.

[0037] Each power device D is housed in the opening of the module housing 3a1, mounted on a heat sink 3a2. The heat sink 3a2 supports the module housing 3a1 and the power devices D. Furthermore, the heat sink 3a2 absorbs heat from the power devices D, thus cooling them. The heat sink 3a2 is fixed to the central housing 2a such that its lower surface is exposed to the flow path of the central housing 2a. Additionally, the heat sink 3a2 may also have multiple fins formed on its lower surface.

[0038] Figure 4 This is a schematic top view of power module 3a. (See attached image.) Figure 4 As shown, the power module 3a includes a positive side busbar 3a3, a negative side busbar 3a4, an output side busbar 3a5, a lead frame 3a6, a control terminal 3a7, and a control terminal wire 3a8.

[0039] The positive-side busbar 3a3 is connected to the positive terminal of battery B. It is also connected to one end of capacitor module 4. The negative-side busbar 3a4 is connected to the negative terminal of battery B. It is also connected to the other end of capacitor module 4.

[0040] Output-side busbars 3a5 are provided for each power device D. That is, in this embodiment, the same number of output-side busbars 3a5 as power devices D (3) are provided. Each output-side busbar 3a5 is connected to the motor M, guiding current between the power device D and the motor M.

[0041] These positive-side busbars 3a3, negative-side busbars 3a4, and output-side busbars 3a5 are held in the module housing 3a1. The lead frame 3a6 connects the power device D to the busbars (positive-side busbar 3a3, negative-side busbar 3a4, or output-side busbar 3a5) via solder or other solder.

[0042] Control terminals 3a7 are terminals used to connect power module 3a and substrate unit 3b. Multiple control terminals 3a7 are provided. One end of each control terminal 3a7 protrudes towards substrate unit 3b, and the other end is connected to power device D via control terminal wire 3a8. That is, by connecting control terminals 3a7 to substrate unit 3b, each power device D is electrically connected to substrate unit 3b. Control terminal wire 3a8 is a linear wiring connecting control terminals 3a7 and power devices D, and multiple wires are connected to each power device D.

[0043] Figure 5 This is a schematic enlarged view of a power module 3a containing a power device D. (See diagram below.) Figure 5 As shown, the power module 3a has multiple lead frames 3a6 connected to a power device D.

[0044] In this embodiment, the power module 3a has four lead frames 3a6 connected to a power device D. These four lead frames 3a6 include two positive-side lead frames 10 (positive terminals), one negative-side lead frame 11 (negative terminal), and one output-side lead frame 12.

[0045] The positive terminal frame 10 is the positive terminal connecting the power device D to the positive terminal busbar 3a. The power device D is connected to the positive terminal of the battery B via the positive terminal frame 10. Alternatively, the two positive terminal frames 10 can be integrated on the outside of the power device D. The negative terminal frame 11 is the negative terminal connecting the power device D to the negative terminal busbar 3a. The power device D is connected to the negative terminal of the battery B via the negative terminal frame 11.

[0046] In addition, such as Figure 5 As shown, the power module 3a has multiple control terminal wires 3a8 connected to a power device D. The multiple control terminal wires 3a8 connected to the power device D include a first conductor layer connection wire 20, a second conductor layer connection wire 21, a third conductor layer connection wire 22, a first gate wiring connection conductor layer wire 23, and a second gate wiring connection conductor layer wire 24.

[0047] The first conductor layer connecting wire 20 is a control terminal wire 3a8 connected to the first conductor layer 40 of the power device D (described later). In this embodiment, there are two first conductor layer connecting wires 20 connected to one power device D. The second conductor layer connecting wire 21 is a control terminal wire 3a8 connected to the second conductor layer 50 of the power device D (described later). The third conductor layer connecting wire 22 is a control terminal wire 3a8 connected to the third conductor layer 60 of the power device D (described later).

[0048] The first gate wiring connection conductor layer wire 23 is a control terminal wire 3a8 connected to the first gate wiring connection conductor layer 70 (described later) of the power device D. The second gate wiring connection conductor layer wire 24 is a control terminal wire 3a8 connected to the second gate wiring connection conductor layer 80 (described later) of the power device D. Alternatively, if the power device D includes a sensor such as a temperature sensor, the power module 3a may also include a control terminal wire 3a8 connecting the sensor and the control terminal 3a7.

[0049] Next, the power device D will be explained. Figure 6 This is a top view showing the schematic structure of power device D. Additionally, to illustrate the shape of power device D, [the following is used] Figure 6 The reference axis L is shown. Reference axis L is an imaginary straight line. The direction parallel to reference axis L is called the reference axis direction. The direction orthogonal to reference axis L is called the orthogonal direction.

[0050] like Figure 6As shown, each power device D is formed as a generally rectangular shape. Each power device D is formed as a rectangle with its width direction being orthogonal and the reference axis L located at the center of the width direction. That is, in this embodiment, the reference axis L is formed as a plate-like rectangle located at the center of the width direction of the power device D. Figure 6 As shown, each power device D includes an insulating substrate 30, a conductor layer 31, a first switching section 32, a second switching section 33, a first gate wiring 34, and a second gate wiring 35.

[0051] The insulating substrate 30 is a substrate formed using an insulating material (e.g., silicon nitride) and supports the conductor layer 31, the first switch portion 32, and the second switch portion 33. The conductor layer 31 is formed on one side of the insulating substrate 30.

[0052] The conductor layer 31 is formed of copper, for example. The conductor layer 31 is a wiring layer for the flow of current between the battery B and the motor M, and for the transmission and reception of signals between the power module 3a and the substrate unit 3b. Alternatively, the conductor layer may be provided on the other side of the insulating substrate 30. In this embodiment, multiple conductor layers 31 are provided with gaps separating them from each other.

[0053] The first switch section 32 and the second switch section 33 are provided in such a way that the separately arranged conductor layers 31 are connected to each other. Multiple first switch sections 32 are semiconductor switches that connect a first conductor layer 40 (described later, one of the conductor layers 31) to a third conductor layer 60 (described later, one of the conductor layers 31). Multiple second switch sections 33 are semiconductor switches that connect a second conductor layer 50 (one of the conductor layers 31) to the aforementioned third conductor layer 60.

[0054] Each first switch section 32 includes a first semiconductor element 32a (semiconductor element) and a first conductive strip 32b (first connection wiring). The first semiconductor element 32a is, for example, a SiC-MOSFET type semiconductor chip formed of SiC (silicon carbide). Alternatively, the first semiconductor element 32a may also be a semiconductor chip formed of other materials such as Si (silicon) or GaN (gallium nitride). A gate electrode 32c is provided on the upper surface of the first semiconductor element 32a.

[0055] The first conductive strip 32b connects the first semiconductor element 32a to the third conductor layer 60. In this embodiment, the first conductive strip 32b is connected to the pad formation portion 61 of the third conductor layer 60, described later. Figure 6 As shown, such a first conductive band 32b is formed to extend in a straight line along an orthogonal direction.

[0056] In this embodiment, such as Figure 6As shown, the power device D includes four first switching sections 32. That is, four first semiconductor elements 32a are provided. Two of these four first semiconductor elements 32a are configured to be closer to the output terminal pad 67 formed on the pad forming section 61 than the other two first semiconductor elements 32a. These two first semiconductor elements 32a configured relatively close to the output terminal pad 67 are arranged in an orthogonal direction with the reference axis L centered between them. In addition, the two first semiconductor elements 32a configured relatively far from the output terminal pad 67 are also arranged in an orthogonal direction with the reference axis L centered between them.

[0057] The first conductive strip 32b connected to the first semiconductor element 32a relatively close to the output terminal pad 67 is formed to be longer than the first conductive strip 32b connected to the first semiconductor element 32a relatively far from the output terminal pad 67. As a result, the inductance of the first conductive strip 32b connected to the first semiconductor element 32a relatively far from the output terminal pad 67 is greater than the inductance of the first conductive strip 32b connected to the first semiconductor element 32a relatively close to the output terminal pad 67. When all first switch portions 32 have the same shape, there is a situation where the current flows more biased towards the first switch portion 32 the closer it is to the output terminal pad 67. As described above, by increasing the inductance of the first conductive strip 32b connected to the first semiconductor element 32a relatively far from the output terminal pad 67, the current flowing through each first switch portion 32 can be made more uniform.

[0058] However, the first conductive strip 32b connected to the first semiconductor element 32a relatively close to the output terminal pad 67 can also be formed to have the same length as the first conductive strip 32b connected to the first semiconductor element 32a relatively far from the output terminal pad 67. In the event of an abnormal current flowing through the strip, which is much larger than normal, by making all the first conductive strips 32b the same length, it is possible to suppress the abnormal current from flowing into a portion of the first conductive strips 32b.

[0059] Each second switch section 33 includes a second semiconductor element 33a (semiconductor element) and a second conductive strip 33b (second connection wiring). The second semiconductor element 33a is, for example, a SiC-MOSFET type semiconductor chip. Alternatively, the second semiconductor element 33a may also be a semiconductor chip formed of other materials such as Si (silicon) or GaN (gallium nitride). A gate electrode 33c is provided on the upper surface of the second semiconductor element 33a.

[0060] The second conductive strip 33b connects the second semiconductor element 33a to the second conductor layer 50. For example... Figure 6As shown, such a second conductive band 33b is formed to extend in a straight line along an orthogonal direction.

[0061] In this embodiment, such as Figure 6 As shown, the power device D includes four second switching sections 33. That is, four second semiconductor elements 33a are provided. Two of these four second semiconductor elements 33a are configured to be closer to the negative terminal pad 51 of the second conductor layer 50 than the other two second semiconductor elements 33a. These two second semiconductor elements 33a configured relatively close to the negative terminal pad 51 are arranged in an orthogonal direction with the reference axis L centered between them, thus sandwiching the reference axis L in the middle. In addition, the two second semiconductor elements 33a configured relatively far from the negative terminal pad 51 are also arranged in an orthogonal direction with the reference axis L centered between them, thus sandwiching the reference axis L in the middle.

[0062] The second conductive strip 33b connected to the second semiconductor element 33a relatively close to the negative terminal pad 51 is formed to be longer than the second conductive strip 33b connected to the second semiconductor element 33a relatively far from the negative terminal pad 51. As a result, the inductance of the second conductive strip 33b connected to the second semiconductor element 33a relatively far from the negative terminal pad 51 is greater than the inductance of the second conductive strip 33b connected to the second semiconductor element 33a relatively close to the negative terminal pad 51. In the case where all second switch sections 33 have the same shape, there is a situation where the current flows more biased towards the second switch section 33 relatively closer to the negative terminal pad 51. As described above, by increasing the inductance of the second conductive strip 33b connected to the second semiconductor element 33a relatively far from the negative terminal pad 51, the current flowing through each second switch section 33 can be made more uniform.

[0063] However, the second conductive strip 33b connected to the second semiconductor element 33a relatively close to the negative terminal pad 51 can also be formed to have the same length as the second conductive strip 33b connected to the second semiconductor element 33a relatively far from the negative terminal pad 51. In the event of an abnormal current flowing through the strip, which is much larger than normal, by making all the second conductive strips 33b the same length, it is possible to suppress the abnormal current from flowing into a portion of the second conductive strips 33b.

[0064] In addition, such as Figure 6 As shown, the first semiconductor element 32a and the second semiconductor element 33a, located on one side (e.g., the right side) of the reference axis L in the orthogonal direction, are arranged to overlap when viewed from the direction along the reference axis. Additionally, the first semiconductor element 32a and the second semiconductor element 33a, located on the other side (e.g., the left side) of the reference axis L in the orthogonal direction, are also arranged to overlap when viewed from the direction along the reference axis.

[0065] By configuring the first semiconductor element 32a and the second semiconductor element 33a in this way, the semiconductor elements are arranged linearly along the reference axis direction on the left and right sides of the reference axis L, respectively. Therefore, for example, compared to the case where the distances of the first semiconductor element 32a and the second semiconductor element 33a from the reference axis L are not uniform, strain caused by stress due to thermal expansion and contraction of the power device D can be suppressed.

[0066] The first gate wiring 34 is disposed relative to each of the first semiconductor elements 32a. That is, the first gate wiring 34 is disposed corresponding to each of the first semiconductor elements 32a. In this embodiment, four first gate wirings 34 are disposed, the same number as the first semiconductor elements 32a. Each first gate wiring 34 is connected to the gate electrode 32c of the first semiconductor element 32a and to the first gate wiring connection conductor layer 70 (described later as one of the conductor layers 31). That is, one end of each first gate wiring 34 is connected to the gate electrode 32c, and the other end is connected to the first gate wiring connection conductor layer 70.

[0067] The second gate wiring 35 is disposed relative to each of the second semiconductor elements 33a. That is, the second gate wiring 35 is disposed corresponding to each of the second semiconductor elements 33a. In this embodiment, four second gate wirings 35 are disposed, the same number as the second semiconductor elements 33a. Each second gate wiring 35 is connected to the gate electrode 33c of the second semiconductor element 33a and to the second gate wiring connection conductor layer 80 (described later as one of the conductor layers 31). That is, one end of each second gate wiring 35 is connected to the gate electrode 33c, and the other end is connected to the second gate wiring connection conductor layer 80.

[0068] Figure 7 It means Figure 6 A schematic diagram of the insulating substrate 30 and the conductor layer 31. (See attached diagram.) Figure 7 As shown, the power device D has five conductor layers 31: a first conductor layer 40, a second conductor layer 50, a third conductor layer 60, a first gate wiring connection conductor layer 70, and a second gate wiring connection conductor layer 80.

[0069] The first conductor layer 40 is the conductor layer 31 that connects to the positive electrode side lead frame 10. For example... Figure 7 As shown, the first conductor layer 40 is divided into a first portion 41 and a second portion 42. The first portion 41 and the second portion 42 are formed in a shape that is linearly symmetrical about the reference axis L.

[0070] Furthermore, in this embodiment, the first portion 41 and the second portion 42 are formed separately with a gap between them. In the orthogonal direction, the second conductor layer 50, the third conductor layer 60, the first gate wiring connection conductor layer 70, and the second gate wiring connection conductor layer 80 are located between these first portions 41 and second portions 42.

[0071] For ease of explanation, in this embodiment, the first part 41 is located to the left of the reference axis L, and the second part 42 is located to the right of the reference axis L. Furthermore, for ease of explanation, in the direction of the reference axis, the side connected to the positive electrode lead frame 10 is designated as the front side, and the side opposite to the front side is designated as the inner side.

[0072] like Figure 7 As shown, the first portion 41 has a positive terminal pad 43, a first switch connection portion 44, and a connection portion 45. The positive terminal pad 43 is the portion connected to one of the positive side lead frames 10 and is located at the outermost edge of the first conductor layer 40. The first switch connection portion 44 is the portion connecting the first conductive strip 32b of the first switch portion 32 and is located at the innermost edge of the first conductor layer 40. The connection portion 45 is formed to extend along the reference axis and connects the positive terminal pad 43 to the first switch connection portion 44. The first switch connection portion 44 is the portion that is bonded to the first semiconductor element 32a of the first switch portion 32. A first conductor layer connection wire 20 (control terminal wire 3a8) is connected to the first switch connection portion 44. Thus, an ECU of the substrate unit 3b can detect the voltage of the first portion 41.

[0073] Furthermore, the second portion 42 includes a positive terminal pad 46, a first switch connection portion 47, and a connection portion 48. The positive terminal pad 46 is the portion connecting to the other positive-side lead frame 10 and is located at the outermost edge of the first conductor layer 40. The first switch connection portion 47 is the portion connecting to the first conductive strip 32b of the first switch portion 32 and is located at the innermost edge of the first conductor layer 40. The connection portion 48 is formed extending along a reference axis and connects the positive terminal pad 46 to the first switch connection portion 47. The first switch connection portion 47 is the portion that bonds to the first semiconductor element 32a of the first switch portion 32. A first conductor layer connection wire 20 (control terminal wire 3a8) is connected to the first switch connection portion 47. Thus, an ECU, for example, in the substrate unit 3b can detect the voltage of the second portion 42.

[0074] Such a first conductor layer 40 has a pair of first switch connection portions (first switch connection portion 44 and first switch connection portion 47) arranged such that the third conductor layer 60 is sandwiched between each other in an orthogonal direction. The third conductor layer 60 has pad forming portions 61, which will be described later. The pair of first switch connection portions (first switch connection portion 44 and first switch connection portion 47) are arranged such that the pad forming portions 61 of the third conductor layer 60 are sandwiched between each other.

[0075] The second conductor layer 50 is a conductor layer 31 connected to the negative terminal lead frame 11. The second conductor layer 50 has a negative terminal pad 51 connected to the negative terminal lead frame 11. For example... Figure 7 As shown, the negative terminal pad 51 is located at the very front of the conductor layer 31, between the positive terminal pad 43 of the first portion 41 and the positive terminal pad 46 of the second portion 42. The second conductor layer 50 is connected to the second conductive strip 33b of the second switch portion 33. A second conductor layer connecting wire 21 (control terminal wire 3a8) is connected to the second conductor layer 50. Thus, an ECU of the substrate unit 3b can detect the voltage of the second conductor layer 50.

[0076] The third conductor layer 60 is the conductor layer 31 that connects to the output side lead frame 12. The third conductor layer 60 has a pad forming portion 61, two second switch portion connection portions (second switch portion connection portion 62 and second switch portion connection portion 63), an intermediate connection portion 64, and two protruding portions (protruding portion 65 and protruding portion 66).

[0077] The pad forming portion 61 is the portion having the output terminal pad 67. The pad forming portion 61 is formed such that the output terminal pad 67 is located at the innermost part in the direction of the reference axis. For example... Figure 7 As shown, the pad forming portion 61 is disposed in an orthogonal direction between the first switch portion connection portion 44 and the first switch portion connection portion 47.

[0078] The second switch connection portion 62 is located to the left of the reference axis L, between the connection portion 45 of the first conductor layer 40 and the second conductor layer 50. The second switch connection portion 62 is the portion that is joined to the second semiconductor element 33a of the second switch portion 33.

[0079] The second switch connection portion 63 is located to the right of the reference axis L, between the connection portion 48 of the first conductor layer 40 and the second conductor layer 50. The second switch connection portion 63 is the portion that is joined to the second semiconductor element 33a of the second switch portion 33.

[0080] This third conductor layer 60 has a pair of second switch connection portions (second switch connection portion 62 and second switch connection portion 63) arranged such that the second conductor layer 50 is sandwiched between each other in an orthogonal direction. In addition, the third conductor layer 60 has a pad forming portion 61 sandwiched between a pair of first switch connection portions (first switch connection portion 44 and first switch connection portion 47) in an orthogonal direction and provided with an output terminal pad 67.

[0081] The intermediate connection portion 64 connects the pad forming portion 61 to each of the second switch portion connection portions (second switch portion connection portion 62 and second switch portion connection portion 63). The intermediate connection portion 64 is formed to branch into two branches from the pad forming portion 61 toward the front side, one branch of which is connected to the second switch portion connection portion 62, and the other branch of which is connected to the second switch portion connection portion 63.

[0082] The protruding portion 65 is a portion that protrudes forward from the second switch connection portion 62 along the reference axis. Similarly, the protruding portion 66 is a portion that protrudes forward from the second switch connection portion 63 along the reference axis. A third conductor layer connecting wire 22 (control terminal wire 3a8) is connected to one of these protruding portions 65 and 66. Therefore, an ECU in the substrate unit 3b, for example, can detect the voltage of the third conductor layer 60.

[0083] In such a conductor layer 31, such as Figure 7 As shown, the output terminal pad 67 and the negative terminal pad 51 are arranged on the reference axis L. Furthermore, as... Figure 6 As shown, the positions of the multiple (4) first switch sections 32 on the side (inside) of the center position P of the output terminal pad 67 and the negative terminal pad 51 in the direction of the reference axis are symmetrically arranged relative to the reference axis L.

[0084] Furthermore, each first switch section 32 connects its first switch section connection portion to the pad forming portion 61. The first switch section 32 located on the left side of the reference axis L connects its first switch section connection portion 44 located on the left side of the reference axis L to the pad forming portion 61. The first switch section 32 located on the right side of the reference axis L connects its first switch section connection portion 47 located on the right side of the reference axis L to the pad forming portion 61.

[0085] Furthermore, multiple (four) second switch sections 33 are symmetrically arranged relative to the reference axis L, positioned closer to the negative terminal pad 51 (front side) than the center position P. Each second switch section 33 connects its second switch section connection portion to the second conductor layer 50. The second switch section 33 located to the left of the reference axis L connects its second switch section connection portion 62 located to the left of the reference axis L to the second conductor layer 50. The second switch section 33 located to the right of the reference axis L connects its second switch section connection portion 63 located to the right of the reference axis L to the second conductor layer 50.

[0086] The first gate wiring connection conductor layer 70 is a conductor layer 31 that connects multiple first gate wirings 34. Additionally, first gate wiring connection conductor layer wires 23 (control terminal wires 3a8) are connected to the first gate wiring connection conductor layer 70. Therefore, a driving voltage can be applied from the substrate cell 3b to all the first gate wirings 34 (i.e., the first semiconductor element 32a) via the first gate wiring connection conductor layer 70.

[0087] like Figure 7 As shown, the first gate wiring connection conductor layer 70 is formed in a straight line extending along the reference axis direction and is arranged to overlap with the reference axis L. Furthermore, the pad forming portion 61 of the third conductor layer 60 is formed to surround the entire first gate wiring connection conductor layer 70 with a gap S1. That is, in this embodiment, the portion to the right of the reference axis L and the portion to the left of the reference axis L of the pad forming portion 61 are interconnected on both the front and back sides of the first gate wiring connection conductor layer 70. Therefore, uneven current flow through the pad forming portion 61 can be suppressed.

[0088] The second gate wiring connection conductor layer 80 is a conductor layer 31 that connects multiple second gate wirings 35. Additionally, second gate wiring connection conductor layer wires 24 (control terminal wires 3a8) are connected to the second gate wiring connection conductor layer 80. Therefore, a driving voltage can be applied from the substrate cell 3b to all the second gate wirings 35 (i.e., the second semiconductor element 33a) via the second gate wiring connection conductor layer 80.

[0089] like Figure 7 As shown, the second gate wiring connection conductor layer 80 is formed in a straight line extending along the reference axis direction and is arranged to overlap with the reference axis L. Furthermore, the second conductor layer 50 is formed to surround the entire second gate wiring connection conductor layer 80 with a gap S2. That is, in this embodiment, the portion of the second conductor layer 50 to the right of the reference axis L and the portion to the left of the reference axis L are interconnected on the front and inner sides of the second gate wiring connection conductor layer 80, respectively. Therefore, uneven current flow through the second conductor layer 50 is suppressed.

[0090] In this embodiment, the power device D forms the aforementioned bridge arm R. The first conductor layer 40, the third conductor layer 60, and the first switching section 32 of the power device D form the upper arm HA. Furthermore, the second conductor layer 50, the third conductor layer 60, and the second switching section 33 of the power device D form the lower arm LA.

[0091] In the power conversion device 1 of this embodiment, which includes such a power device D, when power is supplied from battery B to motor M, the direct current output from battery B is converted into alternating current by the inverter circuit E (power conversion circuit) of power conversion device 1. Furthermore, the alternating current generated by inverter circuit E is supplied to motor M.

[0092] Figure 8 This is a schematic diagram illustrating the current flow in the power device D when a drive current is supplied from battery B to motor M. When a drive voltage is applied to the first semiconductor element 32a of the first switching section 32, the current flows from the first conductor layer 40 to the third conductor layer 60. That is, when a drive voltage is applied to the first semiconductor element 32a of the first switching section 32, the current flows in the first switching section 32 toward the reference axis L.

[0093] Furthermore, when a driving voltage is applied to the second semiconductor element 33a of the second switching section 33, current flows from the third conductor layer 60 to the second conductor layer 50. That is, when a driving voltage is applied to the second semiconductor element 33a of the second switching section 33, current flows in the second switching section 33 toward the reference axis L.

[0094] At this time, the distance from the output terminal (source) of the second switch section 33 to the negative side lead frame 11 becomes the same short distance as the distance from the output terminal (source) of the first switch section 32 to the output side lead frame 12.

[0095] The power device D of this embodiment described above is a semiconductor substrate having an upper arm HA and a lower arm LA forming a bridge arm R. Furthermore, the power device D of this embodiment includes an insulating substrate 30, a conductor layer 31 formed on one side of the insulating substrate 30, and semiconductor elements (a first semiconductor element 32a and a second semiconductor element 33a) mounted on the conductor layer 31.

[0096] Furthermore, the power device D in this embodiment includes a first conductor layer 40, a second conductor layer 50, a third conductor layer 60, a plurality of first switching units 32, and a plurality of second switching units 33. The first conductor layer 40 is a conductor layer 31 having a positive terminal pad 43 connected to the positive side lead frame 10. The second conductor layer 50 is a conductor layer 31 having a negative terminal pad 51 connected to the negative side lead frame 11. The third conductor layer 60 is a conductor layer 31 having an output terminal pad 67 connected to the output side lead frame 12. The first switching units 32 connect the first conductor layer 40 and the third conductor layer 60 and have a first semiconductor element 32a. The second switching units 33 connect the second conductor layer 50 and the third conductor layer 60 and have a second semiconductor element 33a.

[0097] Furthermore, the output terminal pad 67 and the negative terminal pad 51 are arranged on the reference axis L. The first conductor layer 40 has a pair of first switch connection portions (first switch connection portion 44 and first switch connection portion 47), which are arranged in an orthogonal direction along one side of the insulating substrate 30 to sandwich the third conductor layer 60 between each other. The third conductor layer 60 has: a pair of second switch connection portions 63, which are arranged to sandwich the second conductor layer 50 between each other in an orthogonal direction; and a pad forming portion 61, which is sandwiched in an orthogonal direction by the pair of first switch connection portions (first switch connection portion 44 and first switch connection portion 47) and is provided with the output terminal pad 67.

[0098] Multiple first switch portions 32 are arranged symmetrically with respect to the reference axis L at positions relative to the center P of the output terminal pad 67 and the negative terminal pad 51, closer to the output terminal pad 67. The first switch portion connection portions (first switch portion connection portion 44 and first switch portion connection portion 47) are connected to the pad forming portion 61. Multiple second switch portions 33 are arranged symmetrically with respect to the reference axis L at positions relative to the center P of the negative terminal pad 51. The second switch portion connection portions 63 are connected to the second conductor layer 50.

[0099] According to the power device D of this embodiment, a plurality of first switching units 32 connect a first conductor layer 40 having a positive terminal pad 43 and a third conductor layer 60 having an output terminal pad 67, functioning as part of the upper arm HA. Additionally, a plurality of second switching units 33 connect a second conductor layer 50 having a negative terminal pad 51 and a third conductor layer 60, functioning as part of the lower arm LA.

[0100] Furthermore, in the power device D according to this embodiment, the output terminal pad 67 and the negative terminal pad 51 are arranged on the reference axis L, and the first switch connection portion (first switch connection portion 44 and first switch connection portion 47) of the first conductor layer 40 is provided in such a way that it sandwiches the pad forming portion 61 of the third conductor layer 60. Therefore, in the first switch portion 32, current flows from the side away from the reference axis L toward the reference axis L.

[0101] Furthermore, according to the power device D of this embodiment, the second switch connection portion 63 of the third conductor layer 60 is provided such that the second conductor layer 50 having the negative terminal pad 51 is sandwiched between it. Therefore, in the second switch portion 33, current also flows from the side away from the reference axis L toward the reference axis L.

[0102] The path from the current convergence of the plurality of first switch sections 32 arranged in a manner sandwiching the reference axis L to the current convergence of the plurality of second switch sections 33 arranged in a manner sandwiching the reference axis L can be shortened. Therefore, the power device D of this embodiment can suppress the increase of either the parasitic inductance of the upper arm HA or the parasitic inductance of the lower arm LA, and has a structure that is less prone to oscillation. Therefore, the power device D of this embodiment can suppress the occurrence of oscillation.

[0103] Furthermore, in the power device D of this embodiment, each first switching section 32 includes a first semiconductor element 32a and a first conductive strip 32b. The first semiconductor element 32a is a semiconductor element mounted on the first switching section connection portion (first switching section connection portion 44 and first switching section connection portion 47). The first conductive strip 32b connects the first semiconductor element 32a to the pad forming portion 61. Each second switching section 33 includes a second semiconductor element 33a and a second conductive strip 33b. The second semiconductor element 33a is a semiconductor element mounted on the second switching section connection portion 63. The second conductive strip 33b connects the second semiconductor element 33a to the second conductor layer 50.

[0104] In this embodiment, the power device D can adjust the inductance of the first switching section 32 and the second switching section 33 by adjusting the lengths of the first conductive strip 32b and the second conductive strip 33b, respectively.

[0105] Furthermore, the power device D in this embodiment includes multiple first gate wirings 34, a first gate wiring connection conductor layer 70, multiple second gate wirings 35, and a second gate wiring connection conductor layer 80. The first gate wirings 34 are correspondingly disposed with each first semiconductor element 32a and connected to the gate electrode 32c of the first semiconductor element 32a. The first gate wiring connection conductor layer 70 is a conductor layer 31 connecting the multiple first gate wirings 34. The second gate wirings 35 are correspondingly disposed with each second semiconductor element 33a and connected to the gate electrode 33c of the second semiconductor element 33a. The second gate wiring connection conductor layer 80 is a conductor layer 31 connecting the multiple second gate wirings 35.

[0106] According to the power device D of this embodiment, multiple first gate wirings 34 are connected to a single first gate wiring connection conductor layer 70. Therefore, by applying a driving voltage to the first gate wiring connection conductor layer 70, multiple first switching units 32 can be driven at once.

[0107] Furthermore, in the power device D of this embodiment, multiple second gate wirings 35 are connected to a single second gate wiring connection conductor layer 80. Therefore, by applying a driving voltage to the second gate wiring connection conductor layer 80, multiple second switching units 33 can be driven at once.

[0108] Furthermore, in the power device D of this embodiment, the first gate wiring connection conductor layer 70 is arranged to overlap with the reference axis L. Additionally, the pad formation portion 61 of the third conductor layer 60 is formed to surround the entire first gate wiring connection conductor layer 70 with a gap between it and the rest of the device.

[0109] In the power device D of this embodiment, the portion to the right of the reference axis L and the portion to the left of the reference axis L of the pad forming portion 61 are interconnected on the near front and inner sides of the first gate wiring connection conductor layer 70. Therefore, uneven current flow through the pad forming portion 61 can be suppressed.

[0110] Furthermore, in the power device D of this embodiment, the second gate wiring connection conductor layer 80 is arranged to overlap with the reference axis L. Additionally, the second conductor layer 50 is formed to surround the entire second gate wiring connection conductor layer 80 with a gap between them.

[0111] In the power device D of this embodiment, the portion to the right of the reference axis L and the portion to the left of the reference axis L of the second conductor layer 50 are interconnected on the near-front and inner sides of the second gate wiring connection conductor layer 80. Therefore, uneven current flow through the second conductor layer 50 is suppressed.

[0112] Furthermore, in the power device D of this embodiment, the inductance of the first conductive strip 32b connected to the first semiconductor element 32a that is relatively close to the output terminal pad 67 is greater than the inductance of the first conductive strip 32b connected to the first semiconductor element 32a that is relatively far away from the output terminal pad 67.

[0113] According to this embodiment of the power device D, the inductance of the first conductive strip 32b connected to the first semiconductor element 32a which is relatively far from the output terminal pad 67 is large, so the current flowing through each of the first switching sections 32 can be uniformized.

[0114] Furthermore, in the power device D of this embodiment, the inductance of the second conductive strip 33b connected to the second semiconductor element 33a that is relatively close to the negative terminal pad 51 is greater than the inductance of the second conductive strip 33b connected to the second semiconductor element 33a that is relatively far away from the negative terminal pad 51.

[0115] According to this embodiment of the power device D, the inductance of the second conductive strip 33b connected to the second semiconductor element 33a which is relatively far from the output terminal pad 67 is large, so the current flowing through each of the second switching sections 33 can be uniformized.

[0116] Furthermore, in the power device D of this embodiment, the first semiconductor element 32a and the second semiconductor element 33a, located on one side of the reference axis L in the orthogonal direction, are arranged to overlap when viewed from the direction along the reference axis. Additionally, the first semiconductor element 32a and the second semiconductor element 33a, located on the other side of the reference axis L in the orthogonal direction, are also arranged to overlap when viewed from the direction along the reference axis.

[0117] According to this embodiment, the power device D can suppress strain caused by the stress during thermal expansion and contraction of the power device D, compared to the case where the distances of the first semiconductor element 32a and the second semiconductor element 33a from the reference axis L are not uniform.

[0118] Furthermore, in the power device D of this embodiment, the first conductor layer 40 has a first portion 41 and a second portion 42. The first portion 41 has one of a pair of first switch portion connection portions (first switch portion connection portion 44 and first switch portion connection portion 47). The second portion 42 has the other of a pair of first switch portion connection portions (first switch portion connection portion 44 and first switch portion connection portion 47) and is formed separately from the first portion 41.

[0119] In the power device D according to this embodiment, the first portion 41 and the second portion 42 are separated, and the first conductor layer 40 does not need to have a portion connecting the first portion 41 and the second portion 42. Therefore, the first conductor layer 40 can be miniaturized, and thus the power device D can be miniaturized.

[0120] In addition, in the power device D of this embodiment, the third conductor layer 60 has protrusions (protrusions 65 and protrusions 66) that protrude from each of the second switch connection portions 63 along the reference axis direction toward the side opposite to the second switch portion 33.

[0121] According to the power device D of this embodiment, the connecting wire 22 of the third conductor layer can be shortened. Furthermore, by forming protruding portions at the second switch connection portion 62 and the second switch connection portion 63, the third conductor layer 60 can be formed into a symmetrical shape. Therefore, strain caused by stress due to thermal expansion and contraction of the power device D can be suppressed.

[0122] Furthermore, the power conversion device 1 of this embodiment includes a power device D. Therefore, the power conversion device 1 of this embodiment can suppress oscillations occurring in the power device D.

[0123] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. The shapes, combinations, etc. of the constituent components shown in the above embodiments are examples, and various modifications can be made based on design requirements, etc., without departing from the spirit of the present invention.

[0124] For example, in the above embodiments, an example of applying the semiconductor substrate of the present invention to a power device D has been described. However, the present invention is not limited thereto. For example, the semiconductor substrate may also be applied to semiconductor substrates other than those used in power devices.

[0125] Furthermore, in the above embodiment, an example of placing the power device D in a power conversion device 1 equipped with an inverter circuit E has been described. However, the present invention is not limited thereto. For example, the power device D can also be applied to power conversion devices such as DC / DC converters.

[0126] Furthermore, in the above embodiment, the power module 3a has been described with a structure having three power devices D. However, the present invention is not limited thereto. For example, the power module 3a may also have a structure with more power devices D.

[0127] Furthermore, the above embodiment describes a structure in which one electric motor is connected to the power conversion device 1 relative to this embodiment. However, the present invention is not limited thereto. For example, a structure in which two electric motors are connected to the power conversion device 1 can be adopted. In such a case, the power conversion device has two inverter circuits. Therefore, for example, in the power module 3a, a total of six power devices D, equivalent to two inverter circuits, can also be included.

[0128] Furthermore, in the above embodiment, the structure of power module 3a without a buck-boost circuit has been described. However, the present invention is not limited thereto. For example, the power module 3a may also be configured to have a buck-boost circuit between battery B and inverter circuit E.

[0129] For example, in the above embodiment, a structure was described in which the first semiconductor element 32a and the second semiconductor element 33a, located on one side of the reference axis L in the orthogonal direction, are arranged in a manner that overlaps when viewed from the direction along the reference axis. Furthermore, in the above embodiment, a structure was described in which the first semiconductor element 32a and the second semiconductor element 33a, located on the other side of the reference axis L in the orthogonal direction, are arranged in a manner that overlaps when viewed from the direction along the reference axis. However, the present invention is not limited to this. A structure in which the first semiconductor element 32a and the second semiconductor element 33a are arranged without overlapping when viewed from the direction along the reference axis can also be used.

[0130] Furthermore, the above-described embodiments can also be described, for example, as in the following notes.

[0131] (Note 1)

[0132] A semiconductor substrate has an upper arm and a lower arm forming a bridge arm, characterized in that it comprises an insulating substrate, a conductor layer formed on one side of the insulating substrate, and a semiconductor element mounted on the conductor layer. The semiconductor substrate includes: a first conductor layer having a positive terminal pad for connecting a positive terminal; a second conductor layer having a negative terminal pad for connecting a negative terminal; a third conductor layer having an output terminal pad for connecting an output terminal; a plurality of first switching portions connecting the first conductor layer and the third conductor layer, and having the semiconductor element; a plurality of second switching portions connecting the second conductor layer and the third conductor layer, and having the semiconductor element; the output terminal pad and the negative terminal pad are arranged on a reference axis; the first conductor layer has a pair of first switching portion connection portions, which are connected to the reference axis on a surface along one side of the insulating substrate. The third conductor layer is configured to sandwich each other in an orthogonal direction, having a pair of second switch connection portions and a pad forming portion. The pair of second switch connection portions are configured in the orthogonal direction to sandwich the second conductor layer. The pad forming portion is sandwiched by a pair of first switch connection portions in the orthogonal direction and has the output terminal pad. A plurality of first switches are symmetrically arranged relative to the reference axis at a position closer to the output terminal pad than the center position of the output terminal pad and the negative terminal pad along the reference axis. The first switch connection portions are connected to the pad forming portion. A plurality of second switches are symmetrically arranged relative to the reference axis at a position closer to the negative terminal pad than the center position along the reference axis. The second switch connection portions are connected to the second conductor layer.

[0133] (Note 2)

[0134] According to the semiconductor substrate described in Appendix 1, each of the first switch portions includes: a first semiconductor element, which is the semiconductor element mounted on the connection portion of the first switch portion; and a first connection wiring that connects the first semiconductor element to the pad forming portion; and each of the second switch portions includes: a second semiconductor element, which is the semiconductor element mounted on the connection portion of the second switch portion; and a second connection wiring that connects the second semiconductor element to the second conductor layer.

[0135] (Note 3)

[0136] According to Appendix 2, the semiconductor substrate is characterized by comprising: a plurality of first gate lines, which are disposed corresponding to each of the first semiconductor elements and are respectively connected to the gate electrode of the first semiconductor element; a first gate line connecting conductor layer, which is the conductor layer connected to the plurality of first gate lines; a plurality of second gate lines, which are disposed corresponding to each of the second semiconductor elements and are respectively connected to the gate electrode of the second semiconductor element; and a second gate line connecting conductor layer, which is the conductor layer connected to the plurality of second gate lines.

[0137] (Note 4)

[0138] According to Appendix 3, the semiconductor substrate is characterized in that the first gate wiring connection conductor layer is arranged to overlap with the reference axis, and the pad forming portion of the third conductor layer is formed to surround the entire first gate wiring connection conductor layer with a gap.

[0139] (Note 5)

[0140] According to Appendix 3 or 4, the semiconductor substrate is characterized in that the second gate wiring connection conductor layer is arranged to overlap with the reference axis, and the second conductor layer is formed in such a way that it surrounds the entire second gate wiring connection conductor layer with a gap.

[0141] (Note 6)

[0142] According to any one of Appendices 2 to 5, the semiconductor substrate is characterized in that the inductance of the first connection wiring connected to the first semiconductor element that is relatively close to the output terminal pad among the plurality of first semiconductor elements is greater than the inductance of the first connection wiring connected to the first semiconductor element that is relatively far away from the output terminal pad.

[0143] (Note 7)

[0144] According to any one of Appendices 2 to 6, the semiconductor substrate is characterized in that the inductance of the second connection wiring connected to the second semiconductor element that is relatively close to the negative terminal pad among a plurality of second semiconductor elements is greater than the inductance of the second connection wiring connected to the second semiconductor element that is relatively far from the negative terminal pad.

[0145] (Note 8)

[0146] The semiconductor substrate according to any one of Appendices 2 to 7 is characterized in that the first semiconductor element and the second semiconductor element located on one side of the reference axis in the orthogonal direction are arranged to overlap when viewed from the direction along the reference axis, and the first semiconductor element and the second semiconductor element located on the other side of the reference axis in the orthogonal direction are arranged to overlap when viewed from the direction along the reference axis.

[0147] (Note 9)

[0148] The semiconductor substrate according to any one of Appendices 1 to 8 is characterized in that the first conductor layer has: a first portion having one of a pair of first switch portion connection portions; and a second portion having the other of a pair of first switch portion connection portions, and formed separately from the first portion.

[0149] (Postscript 10)

[0150] The semiconductor substrate according to any one of Appendices 1 to 9 is characterized in that the third conductor layer has a protruding portion that protrudes from each of the second switch portion connection portions along the reference axis direction toward the side opposite to the second switch portion.

[0151] (Note 11) A power conversion device having a power conversion circuit formed of semiconductor elements, characterized in that it comprises a semiconductor substrate as described in any one of Notes 1 to 10, the semiconductor substrate having the semiconductor elements.

[0152] Explanation of reference numerals in the attached figures

[0153] 1: Power conversion device

[0154] 2: Inverter housing

[0155] 3: Intelligent Power Module

[0156] 3a: Power Module

[0157] 3a1: Module housing

[0158] 3a2: Radiator

[0159] 3a3: Positive side busbar

[0160] 3a4: Negative side busbar

[0161] 3a5: Output side busbar

[0162] 3a6: Lead frame

[0163] 3a7: Control terminal

[0164] 3a8: Control terminal wire

[0165] 3b: Substrate unit

[0166] 4: Capacitor Module

[0167] 10: Positive side lead frame (positive terminal)

[0168] 11: Negative electrode side lead frame (negative terminal)

[0169] 12: Output side lead frame (output terminal)

[0170] 20: First conductor layer connecting wire

[0171] 21: Second conductor layer connecting wire

[0172] 22: Third conductor layer connecting wire

[0173] 23: First gate wiring connection conductor layer wire

[0174] 24: Second gate wiring connection conductor layer wire

[0175] 30: Insulating substrate

[0176] 31: Conductor layer

[0177] 32: First switch section

[0178] 32a: First semiconductor element (semiconductor element)

[0179] 32b: First conductive strip (first connecting wire)

[0180] 32c: Gate electrode

[0181] 33: Second Switch Section

[0182] 33a: Second semiconductor element (semiconductor element)

[0183] 33b: Second conductive strip (first connecting wiring)

[0184] 33c: Gate electrode

[0185] 34: First gate wiring

[0186] 35: Second gate wiring

[0187] 40: First conductor layer

[0188] 41: First part

[0189] 42: Second part

[0190] 43: Positive terminal pad

[0191] 44: Connection part of the first switch section

[0192] 45: Connection part

[0193] 46: Positive terminal pad

[0194] 47: Connection part of the first switch section

[0195] 48: Connection part

[0196] 50: Second conductor layer

[0197] 51: Negative terminal pad

[0198] 60: Third conductor layer

[0199] 61: Pad formation area

[0200] 62: Connection part of the second switch section

[0201] 63: Connection part of the second switch section

[0202] 64: Intermediate connecting part

[0203] 65: Protruding parts

[0204] 66: Protruding parts

[0205] 67: Output terminal pads

[0206] 70: First gate wiring connection conductor layer

[0207] 80: Second gate wiring connection conductor layer

[0208] B: Battery

[0209] BU: Busbar

[0210] D: Power devices (semiconductor substrates)

[0211] E: Inverter circuit

[0212] HA: Upper Arm

[0213] L: Reference axis

[0214] LA: Lower arm

[0215] M: Electric motor

[0216] P: Center position

[0217] R: Bridge arm

[0218] S1: Gap

[0219] S2: Gap

Claims

1. A semiconductor substrate provided with an upper arm and a lower arm forming a bridge arm, characterized by provided with an insulating substrate, a conductor layer formed on one side of a surface of the insulating substrate, a semiconductor element mounted on the conductor layer, the semiconductor substrate is provided with: a first conductor layer which is the conductor layer having a positive terminal pad connected to a positive terminal; a second conductor layer which is the conductor layer having a negative terminal pad connected to a negative terminal; a third conductor layer which is the conductor layer having an output terminal pad connected to an output terminal; a plurality of first switch sections connecting the first conductor layer and the third conductor layer and having the semiconductor element; a plurality of second switch sections connecting the second conductor layer and the third conductor layer and having the semiconductor element, the output terminal pad and the negative terminal pad are arranged on a reference axis, the first conductor layer has a pair of first switch section connection sites arranged to sandwich the third conductor layer between each other in a direction orthogonal to the reference axis along one side of a surface of the insulating substrate, the third conductor layer has a pair of second switch section connection sites arranged to sandwich the second conductor layer between each other in the orthogonal direction and a pad formation site sandwiched by the pair of first switch section connection sites in the orthogonal direction and provided with the output terminal pad, a plurality of the first switch sections are arranged symmetrically with respect to the reference axis at positions on the output terminal pad side relative to a center position of the output terminal pad and the negative terminal pad in a direction along the reference axis, a plurality of the second switch sections are arranged symmetrically with respect to the reference axis at positions on the negative terminal pad side relative to the center position in the direction along the reference axis.

2. The semiconductor substrate according to claim 1, characterized by each of the first switch sections is provided with: a first semiconductor element which is the semiconductor element mounted on the first switch section connection site; and a first connection wiring connecting the first semiconductor element and the pad formation site, each of the second switch sections is provided with: a second semiconductor element which is the semiconductor element mounted on the second switch section connection site; and a second connection wiring connecting the second semiconductor element and the second conductor layer.

3. The semiconductor substrate of claim 2, wherein provided with: a plurality of first gate wirings provided corresponding to each of the first semiconductor elements and connected to gate electrodes of the first semiconductor elements, respectively; a first gate wiring connection conductor layer which is the conductor layer connected to the plurality of first gate wirings; a plurality of second gate wirings provided corresponding to each of the second semiconductor elements and connected to gate electrodes of the second semiconductor elements, respectively; a second gate wiring connection conductor layer which is the conductor layer connected to the plurality of second gate wirings.

4. The semiconductor substrate according to claim 3, wherein the first gate wiring connection conductor layer is arranged so as to overlap the reference axis, the pad formation site of the third conductor layer is formed so as to surround the entire first gate wiring connection conductor layer with a gap therebetween.

5. The semiconductor substrate according to claim 3 or 4, wherein the second gate wiring connection conductor layer is arranged so as to overlap the reference axis, the second conductor layer is formed so as to surround the entire second gate wiring connection conductor layer with a gap therebetween.

6. The semiconductor substrate according to any one of claims 2 to 4, wherein the inductance of the first connection wiring connected to the first semiconductor element relatively close to the output terminal pad among the plurality of first semiconductor elements is greater than the inductance of the first connection wiring connected to the first semiconductor element relatively far from the output terminal pad.

7. The semiconductor substrate according to any one of claims 2 to 4, wherein the inductance of the second connection wiring connected to the second semiconductor element relatively close to the negative terminal pad among the plurality of second semiconductor elements is greater than the inductance of the second connection wiring connected to the second semiconductor element relatively far from the negative terminal pad.

8. The semiconductor substrate according to any one of claims 2 to 4, wherein the first semiconductor element and the second semiconductor element on one side of the reference axis in the orthogonal direction are arranged so as to overlap when viewed in a direction along the reference axis direction, the first semiconductor element and the second semiconductor element on the other side of the reference axis in the orthogonal direction are arranged so as to overlap when viewed in a direction along the reference axis direction.

9. The semiconductor substrate according to any one of claims 1 to 4, wherein the first conductor layer has: a first portion having one of the pair of first switch portion connection sites; a second portion having the other of the pair of first switch portion connection sites and formed separately from the first portion.

10. The semiconductor substrate according to any one of claims 1 to 4, wherein the third conductor layer has a protruding portion protruding from each of the second switch portion connection sites toward the opposite side of the second switch portion along the reference axis direction.

11. A power conversion device having a power conversion circuit formed of semiconductor elements, characterized by comprising the semiconductor substrate according to any one of claims 1 to 4, the semiconductor substrate having the semiconductor elements. ​ ​ ​ ​ ​ ​ ​ ​

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