Visualized PCB Impedance Uniformity Testing and Analysis Method

Abstract

This invention discloses a visualization-based PCB impedance uniformity testing and analysis method, relating to the field of PCB impedance uniformity testing. The method includes: using a TDR device to acquire the impedance values ​​and coordinate information of test points on the PCB board surface, and mapping the coordinate information of each test point to its impedance value, generating an impedance spatial distribution heatmap through interpolation; identifying and marking abnormal points in the impedance spatial distribution heatmap, and determining whether the impedance anomaly type is an etching anomaly or a non-etching anomaly based on the spatial distribution characteristics of the marked abnormal points and their significant peak intervals; and generating a joint deviation data set reflecting the corresponding deviation between the two by spatially comparing the linewidth distribution map and the impedance heatmap, and calculating the baseline adjustment amount of the area to be compensated to generate process compensation instructions. This achieves visualization of impedance distribution, anomaly type diagnosis, and closed-loop compensation of process parameters, improving the efficiency of PCB impedance uniformity analysis.

Description

Technical Field

[0001] This invention belongs to the field of PCB impedance uniformity testing technology, and relates to a visualization-based PCB impedance uniformity testing and analysis method. Background Technology

[0002] PCBs, or printed circuit boards, require impedance control during their manufacturing process to ensure the integrity of high-speed signals, especially for high-frequency, high-density interconnect boards. Impedance deviations can lead to signal reflection, crosstalk, and other problems, affecting the performance of the final product.

[0003] Traditional impedance control methods have the following technical bottlenecks: First, existing impedance testing usually relies on sampling measurements of a limited number of test points. The resulting data is often presented as a discrete data list. This point-to-surface approach makes it difficult to identify the overall outline and spatial distribution pattern of abnormal areas and to grasp the spatial pattern of impedance uniformity.

[0004] Secondly, in the actual production process, impedance testing and subsequent process adjustments are disconnected. Existing technologies lack statistical analysis of impedance uniformity in the diagnosis of abnormal causes, making it impossible to infer root cause classification based on impedance uniformity. This not only results in low diagnostic efficiency but also makes it easier to cause batch defects.

[0005] Finally, existing technologies rely heavily on globally unified process compensation values ​​for adjusting process parameters, lacking impedance uniformity data to support joint process compensation. This adjustment method suffers from poor stability, affects production efficiency, and makes it difficult to accumulate effective adjustment strategies. Summary of the Invention

[0006] In view of this, in order to solve the problems mentioned in the background art, the present invention provides a visualization-based method for PCB impedance uniformity testing and analysis.

[0007] The objective of this invention can be achieved through the following technical solution: a visualization-based PCB impedance uniformity test and analysis method, including: S1, using a TDR device to scan the impedance data and coordinate information of test points on the PCB board.

[0008] S2. Associate and map the coordinate information of each test point with the corresponding impedance value, and generate an impedance spatial distribution heat map by interpolation. In the impedance spatial distribution heat map, mark the abnormal points that exceed the preset impedance tolerance zone.

[0009] S3. Identify the spatial distribution characteristics of the marked abnormal points and determine the type of impedance abnormality based on the spatial distribution characteristics. If the marked abnormal points are concentrated in the edge or center area of ​​the PCB board, they are determined to be etching abnormalities.

[0010] S4. If the marked abnormal points are randomly distributed on the board surface, they are determined to be non-etching abnormalities.

[0011] S5. If the etching is determined to be abnormal, obtain the linewidth distribution map of the PCB board, compare the linewidth distribution map with the impedance spatial distribution heat map, and adjust the compensation parameters of the etching process according to the comparison results.

[0012] S6. If the abnormality is determined to be non-etching, the dielectric layer thickness fluctuation of the PCB board is detected, and the abnormality type is determined based on the dielectric layer thickness fluctuation.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The present invention uses TDR equipment to obtain the impedance value and coordinate information of the test points on the PCB board, and maps the coordinate information of each test point with the corresponding impedance value. By interpolation, an impedance spatial distribution heat map is generated, which solves the problem of relying on discrete point sampling to measure impedance values, realizes the visualization of the continuous spatial distribution pattern of impedance on the PCB board, and can intuitively reflect the spatial law of impedance uniformity.

[0014] (2) The present invention identifies and marks abnormal points in the impedance spatial distribution heat map. Based on the spatial distribution characteristics of the marked abnormal points and their significant peak intervals, the impedance abnormality type is determined to be etching abnormality or non-etching abnormality. This solves the problem of the disconnect between impedance testing and process adjustment, realizes the correlation between impedance spatial distribution data and process root causes, and improves diagnostic efficiency.

[0015] (3) This invention generates a set of joint deviation data reflecting the corresponding relationship between the line width distribution map and the impedance heat map by spatially comparing the line width distribution map and the impedance heat map, and calculates the benchmark adjustment amount of the area to be compensated based on this data to generate process compensation instructions. This solves the problem of lack of data support for process adjustment, ensures that the adjustment is highly targeted, improves production efficiency, and facilitates the accumulation of adjustment strategies for different impedance uniformity problems, avoiding blind adjustment. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a diagram illustrating the implementation steps of the method of the present invention.

[0018] Figure 2 This is a flowchart of the PCB board impedance abnormality area distribution analysis and etching abnormality judgment process of the present invention.

[0019] Figure 3 This is a flowchart of the PCB board etching compensation screening and etching equipment control instruction generation process of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Please see Figure 1 As shown, the present invention provides a visualization-based PCB impedance uniformity test and analysis method, including: S1, using a TDR device to scan the impedance data and coordinate information of test points on the PCB board surface.

[0022] The TDR device acquires the raw impedance data of test points in different areas on the PCB board and establishes a one-to-one correspondence between impedance values ​​and spatial coordinates, providing a highly reliable basic data source for subsequent generation of impedance spatial distribution heatmaps, anomaly identification, and anomaly type determination.

[0023] Based on this, using a TDR device to scan the impedance data and coordinate information of test points on the PCB board includes: identifying key electrical functional areas and physical structural feature areas on the board based on the PCB board design information.

[0024] The impedance characteristics of different areas on a PCB vary significantly due to differences in electrical functions and physical structure. Impedance fluctuations in critical electrical function areas determine signal transmission quality, while impedance anomalies are prone to occur in physical structural feature areas due to manufacturing process variations. Therefore, it is necessary to first identify key testing areas based on the design documents. Specifically, the PCB design documents are analyzed to automatically identify critical electrical function areas based on signal type and frequency, while physical structural feature areas are identified based on the PCB board's graphic characteristics. Critical electrical function areas include, but are not limited to, high-speed signal traces, critical power distribution network lines, and sensing signal interface areas; physical structural feature areas include, but are not limited to, the areas around irregularly shaped vias, high-density packaging areas, and board edges and connector areas.

[0025] Test points are placed at equal intervals along the critical wiring path in the critical electrical function area. Test points are placed at equal intervals along concentric circular paths with increasing radius around the geometric center of the physical structural feature area. Test points are then placed evenly in the remaining area according to a rectangular grid.

[0026] It should be noted that critical electrical functional areas are prone to impedance anomalies due to uneven etching solution concentration and over-etching at trace edges. These anomalies typically exhibit continuous gradual changes or localized abrupt changes along the trace path. By placing test points at equal intervals along the critical trace path, continuous sampling of impedance data at each location along the trace path can be achieved, capturing the impedance variation trend along the trace direction and ensuring that impedance anomalies in critical areas are not missed. For example, test points can be spaced 2–3 mm apart along the trace.

[0027] The unique geometric structure of the physical structural feature region causes the influence of manufacturing process fluctuations to radiate outwards. By placing test points at equal intervals along concentric circular paths with increasing radii around the geometric center of the physical structural feature region, it is possible to locate the radiation boundary of impedance anomalies through test points along paths with different radii. For example, test points can be generated on each of the virtual concentric circles with an increasing radius of 3mm, with angles divided by 30°.

[0028] The remaining area consists of ordinary regions that are neither electrically critical nor structurally significant. Their impedance characteristics are typically uniformly distributed due to manufacturing process variations. By evenly distributing test points in a rectangular grid, it is possible to reasonably control the number of test points while ensuring test coverage in this area, avoiding oversampling and data redundancy, and balancing test accuracy and efficiency. For example, the rectangular grid in the remaining area can be set at 8–10 mm.

[0029] The test probes of the TDR device are moved sequentially to each test point and make electrical contact.

[0030] It should be added that TDR equipment, based on the time-domain reflectometry principle, injects high-frequency probe signals into PCB test points and captures the characteristics of the reflected signals to analyze the impedance characteristics of the test points. This adapts to the high-speed signal transmission scenarios on PCBs, effectively avoiding impedance measurement deviations caused by the operating frequency limitations of traditional impedance testers. Furthermore, TDR equipment can be linked with an XY-axis motion slide to synchronously trigger impedance measurement and position coordinate acquisition. Moreover, the TDR testing process is a non-destructive contact measurement, meeting the online quality inspection requirements of PCB mass production.

[0031] When a stable electrical contact is formed, the TDR device is triggered to measure the impedance value and position coordinates of each test point.

[0032] Specifically, the TDR device is triggered to send a high-speed step signal to the probe, and the reflected waveform is analyzed. The characteristic impedance value of the point is calculated and output in real time. At the same time, the feedback from the servo encoder is read to obtain the coordinates of the current probe tip in the platform coordinate system.

[0033] In the specific implementation of the above scheme, the formation of stable electrical contact can be determined when the contact resistance is less than 5Ω and the coefficient of variation of the contact resistance is less than 1% within 100ms of continuous monitoring, and the rise time of the reflected signal received by the TDR device is stable in the range of 50ps to 100ps.

[0034] S2. Associate and map the coordinate information of each test point with the corresponding impedance value, and generate an impedance spatial distribution heat map by interpolation. In the impedance spatial distribution heat map, mark the abnormal points that exceed the preset impedance tolerance zone.

[0035] After collecting and storing the impedance data and corresponding coordinates of each test point on the PCB board using a TDR device, an impedance spatial distribution heatmap is generated to clearly quantify the spatial differences in impedance values ​​on the board surface in order to intuitively present the spatial distribution pattern of impedance on the board surface. The specific steps are as follows: Associate and store the impedance value of each test point with its corresponding coordinates.

[0036] Unify the position coordinates of each test point to the coordinate system of the PCB design drawing, and create a grid of points within the outline boundary area of ​​the PCB board.

[0037] As an optional implementation of the above operation, the following process for creating a grid dot matrix is ​​provided: S01, along the two vertical directions of the PCB board outline boundary area, generate a series of parallel virtual reference lines at equal intervals, and obtain the intersection points between the virtual reference lines.

[0038] S02. Filter out all intersection points located within the PCB board outline boundary area and define each intersection point as a grid point.

[0039] S03. Record the coordinates of all grid points to form a regularly distributed grid, where the coordinates of each grid point are the calculation location of the impedance value to be determined.

[0040] Using the current grid point as the center, select test points within the search radius whose Euclidean distance from the grid point is less than or equal to the search radius, and use them as nearby known points.

[0041] In one embodiment of the present invention, the search radius is adaptively determined based on the spatial distribution density of all test points on the PCB board. Specifically, firstly, the average nearest neighbor distance *d* between all pairs of test points is calculated; then, it is multiplied by a neighbor number coefficient *k*, where *k* typically ranges from 1.5 to 3.0, to obtain the initial search radius *r*; finally, if this radius ensures that more than 95% of the grid points can find at least three known neighbor points, then this value is determined as the final search radius. For example, if the average nearest neighbor distance of the test points is 2.0 mm, and *k* = 2.0, then the calculated search radius is 4.0 mm. This method allows the search radius to adapt to the actual test point layout, avoiding inaccurate interpolation results due to a fixed radius.

[0042] Calculate the distance between each neighboring known point and the corresponding impedance difference. Divide the distance values ​​into intervals and calculate half of the average of the squared impedance differences within each interval as the semivariance of the interval.

[0043] The process of dividing the distance values ​​into intervals involves dividing the calculated distances between all adjacent known point pairs into several continuous intervals according to a preset distance interval, so as to statistically analyze impedance differences at the same or similar distance scales. For example, distances between 0 and 0.1 mm form one group, distances between 0.1 and 0.2 mm form another group, and so on.

[0044] Curve fitting was performed on the distance interval and the corresponding semivariogram value to obtain the dependence of impedance difference on distance.

[0045] Specifically, the median point of each distance interval is first used as the distance independent variable for that interval. The corresponding semivariance value is used as the dependent variable. This forms a set of discrete data points to be fitted. Then, a pre-defined theoretical variogram model that can characterize the spatial correlation decay law is selected. Next, the least squares method is used as the parameter estimation criterion, and through numerical iterative optimization, a set of optimal theoretical model parameters is found that makes the model suitable for all... The theoretical semivariance value calculated at the point of intersection differs from the actual value. The sum of squares of the differences is minimized. Finally, the determined theoretical model function is fitted. A quantitative expression for the dependence of impedance difference on distance.

[0046] For example, if a spherical model is selected , , where h represents the Euclidean distance between any two test points in space. , , The parameters to be determined are obtained using the least squares method, which is implemented through an optimization program. , , The specific value that makes the function curve most closely approximate all Data points. Parameters obtained from the fitting. This is called variable range. This is the base value.

[0047] Based on the dependency relationship, each neighboring known point is assigned a contribution weight. The impedance value of each neighboring known point is multiplied by its corresponding contribution weight and then summed to obtain the impedance value of the current grid point.

[0048] To assign contribution weights to each neighboring known point based on dependency relationships, an optimal set of weights is obtained using a spatial correlation model. The specific process is as follows: First, the fitted theoretical variogram model is used as a quantitative expression for the spatial dependency relationship. Based on this model function, the spatial covariance between each pair of neighboring known points is calculated. And the spatial covariance from each neighboring known point to the current grid point to be interpolated. The relationship between covariance and semivariance is as follows: Where h is the Euclidean distance between the two test points, and c(0) is the sill value of the theoretical model, i.e. .

[0049] Subsequently, a system of Kriging equations is constructed to solve for the weights. This system follows two criteria: first, unbiasedness, requiring the sum of all weights to be 1; and second, minimizing the estimated variance under this constraint. This leads to a linear system of equations containing n+1 equations, where n is the number of known neighboring points, in matrix form. The coefficient matrix A consists of the spatial covariance between each pair of known neighboring points, plus additional rows and columns introduced by the unbiased constraint; the vector to be solved... It contains n contribution weights and a Lagrange multiplier μ; the constant term vector B consists of the spatial covariance from each neighboring known point to the current interpolation grid point and the unbiased constraint constant.

[0050] Finally, the matrix equations are solved using numerical methods. This allows us to obtain the optimal contribution weight assigned to each known neighboring point.

[0051] Assign a corresponding color to the impedance value of each grid point to generate a heat map of impedance spatial distribution.

[0052] Specifically, a color mapping rule is defined for the entire impedance range. For example, the ideal value of 50Ω is set to green, 48Ω to light blue, 52Ω to light red, 45Ω to dark blue, and 55Ω to dark red. All grid nodes are traversed, and the estimated impedance value of each node is converted into the corresponding color according to the above rule. The colors of all nodes are filled according to their positions to generate a continuous color image, namely the impedance spatial distribution heatmap.

[0053] The preset impedance tolerance band refers to the allowable deviation range set around the design target impedance value. It can be directly adopted from the impedance tolerance requirements specified in the PCB design document, or the maximum impedance deviation range that does not affect the normal operation of the circuit can be determined through system signal integrity simulation and set as the tolerance band.

[0054] This invention generates a continuous heatmap by associating the impedance data of discrete test points with spatial coordinates and interpolating them. This helps to intuitively present the overall distribution trend of impedance on the PCB board and enables rapid location and visual diagnosis of impedance uniformity problems by automatically marking abnormal points.

[0055] S3. Identify the spatial distribution characteristics of the marked abnormal points and determine the type of impedance abnormality based on the spatial distribution characteristics. If the marked abnormal points are concentrated in the edge or center area of ​​the PCB board, they are determined to be etching abnormalities.

[0056] See Figure 2 As shown, the step of determining an etching anomaly involves analyzing the spatial clustering characteristics of the anomaly points and associating the distribution pattern with the root cause of potential process defects. The specific execution process is as follows: Identify the connected regions of all anomaly points from the impedance spatial distribution thermal map and define them as anomaly regions.

[0057] Calculate the average boundary coordinates of each abnormal region to obtain its geometric centroid coordinates, and calculate the Euclidean distance between the centroid of each abnormal region and the geometric center of the plate surface to form an abnormal region distance dataset.

[0058] Divide the range of the farthest distance from the geometric center of the panel to the panel outline into several equally spaced intervals. Traverse the abnormal region distance dataset, count the number of abnormal regions contained in each equally spaced interval as the frequency of that interval, and calculate the average frequency of all equally spaced intervals.

[0059] In one embodiment of the present invention, the example of dividing the range of the farthest distance from the geometric center of the panel to the panel outline into several equally spaced intervals can be divided into 10 equally spaced intervals.

[0060] Calculate the ratio of the frequency to the average frequency for each equally spaced interval, and identify equally spaced intervals with a ratio greater than the significance threshold as significant peak intervals.

[0061] In one embodiment of the present invention, the significance threshold is used to identify whether there is a statistically significant clustering phenomenon of abnormal regions at a specific radial distance. A quantitative discrimination standard needs to be set. The specific steps are as follows: First, within the outline of the PCB board, a computer simulation generates multiple sets of data, such as 10,000 sets, which are the same as the total number of abnormal regions measured in the current actual test. Second, for each set of simulated data, the distance calculation, interval division and frequency statistics steps are repeated, and the maximum frequency ratio that may occur in each interval is recorded. Finally, from the maximum ratio obtained from these 10,000 simulations, the 95th or 99th percentile is taken as the significance threshold.

[0062] Statistical hypothesis testing is used to determine whether the frequency of abnormal regions within a specific distance interval deviates significantly from the expected level under random distribution, thereby providing statistical evidence for judging whether the clustering phenomenon is caused by non-random factors.

[0063] Define the edge and center areas of the board surface based on the PCB design information.

[0064] Specifically, the edge region is defined as a continuous annular region extending inward from the PCB board edge contour, with a width of M% of the shortest side length of the board surface. For example, M is a value of 5 to 20. The center region is defined as a rectangular region centered on the geometric center of the board surface, with a side length of N% of the shortest side length of the board surface. For example, N is a value of 10 to 30, or a circular region with a diameter of N% of the shortest side length of the board surface.

[0065] If a significant peak range falls within the edge or center region, the abnormal points are determined to be concentrated in the corresponding region, and the impedance anomaly type is determined to be an etching anomaly.

[0066] Based on the understanding of the physical mechanism of PCB etching process, the cause of etching anomalies is the regional fluctuation of the etching process, such as uneven spray pressure of etching solution. The influence range of such fluctuations has a clear regionality, which will cause the abnormal points to be concentrated in the corresponding area. As a result, the frequency of the abnormal area in a certain equidistant interval is much higher than the average frequency, forming a significant peak interval. That is, the significant peak interval is a necessary process characteristic of etching anomalies. Therefore, when the statistically identified significant peak interval falls into these physical areas that are strongly correlated with typical process deviations, the causal relationship between the abnormal distribution pattern and the etching process can be established, thereby determining the anomaly type as etching anomaly.

[0067] S4. If the marked abnormal points are randomly distributed on the board surface, they are determined to be non-etching abnormalities.

[0068] Specifically, when no significant peak intervals are identified, the marked abnormal points are determined to be randomly distributed on the board surface, that is, the impedance abnormality type is determined to be non-etching abnormality.

[0069] The causes of non-etching anomalies are all random factors without fixed rules, such as random fluctuations in dielectric layer thickness and variations in the microscopic properties of dielectric materials. The resulting anomalies will not be concentrated in specific areas of the board surface, but will only be uniformly distributed in each equally spaced interval. The ratio of the frequency of each interval to the average frequency is lower than the significance threshold, and no significant peak interval can be formed. This is the inherent spatial distribution characteristic of non-etching anomalies. Based on the above process correlation and feature correspondence, when no significant peak interval is identified, both regionally fluctuating etching anomalies are ruled out, and the random distribution characteristics of non-etching anomalies are completely matched. Therefore, it is determined that the marked anomalies are randomly distributed, and the impedance anomaly type is non-etching anomaly.

[0070] S5. If the etching is determined to be abnormal, obtain the linewidth distribution map of the PCB board, compare the linewidth distribution map with the impedance spatial distribution heat map, and adjust the compensation parameters of the etching process according to the comparison results.

[0071] After determining that an etching anomaly is present, in order to establish the correlation between impedance spatial anomaly and the physical dimensions of the conductors to guide subsequent precise process compensation, the step of obtaining the PCB board surface linewidth distribution map is performed. Specifically, this includes: controlling the image sensor of the optical inspection equipment to scan the PCB board surface, acquiring digital images, and registering the coordinate system of the digital images to a coordinate system consistent with the PCB design file.

[0072] Along the design direction of the target traverse, extract the grayscale profile line perpendicular to the traverse direction. The position where the grayscale value first changes sharply from high to low is the candidate left edge point, and the position where the grayscale value last changes sharply from low to high is the candidate right edge point.

[0073] It should be noted that PCB conductors are usually made of highly reflective copper, and their surface reflectivity is higher than that of the surrounding solder mask or substrate area. In the digital image acquired by optical inspection equipment, they appear as high grayscale values. The substrate is usually a dark insulating material. There is a grayscale difference between the PCB conductor and the substrate in the optical image. Their physical boundary is shown as a step change in grayscale on the grayscale profile line. By identifying the abrupt change point, the physical edge pixel position of the conductor in the image can be located.

[0074] The geometric center positions of all candidate left and right edge points are determined as the left and right edge positions of the conductor segment.

[0075] The pixel distance is calculated based on the left and right edge positions. According to the calibration parameters of the optical detection equipment, the pixel distance is converted into the actual physical line width value and the corresponding coordinates are recorded.

[0076] By associating the actual line width value with its coordinates, a line width distribution map is generated through spatial interpolation.

[0077] This invention obtains spatial distribution data of actual linewidth through optical scanning and image processing, which helps to transform abstract impedance anomaly problems into measurable physical size deviation maps of conductors, thereby providing a dimensional basis for locating defect areas in subsequent etching processes and implementing compensation.

[0078] One implementation step of spatially comparing the linewidth distribution map with the impedance spatial distribution heatmap is as follows: Under the unified PCB design coordinate system, the impedance spatial distribution heatmap and the linewidth distribution map are mesh registered and aligned.

[0079] The difference between the measured impedance value and the target impedance value at each grid point is calculated as the impedance deviation, and the difference between the measured line width value and the designed line width value is calculated as the line width deviation.

[0080] By correlating the impedance deviation and linewidth deviation at the same grid point, a set of joint deviation data reflecting the relationship between impedance and linewidth deviation at each location is generated.

[0081] This invention compares and correlates the linewidth distribution map with the impedance spatial distribution heat map in a gridded manner under a unified coordinate system, which is beneficial to directly establish the spatial relationship between physical linewidth manufacturing error and electrical impedance performance deviation, thereby providing a data set for determining the specific location of etching process non-uniformity.

[0082] See Figure 3 As shown, to implement closed-loop control of the etching process based on the joint deviation data set, the following steps are performed to adjust the compensation parameters of the etching process: According to the joint deviation data set, all data points with the same sign as the impedance deviation and line width deviation are selected, and clustered according to spatial coordinates to form several spatially continuous sets. The PCB board area covered by each set is defined as the area to be compensated.

[0083] Generally, when the linewidth is greater than the design value, the impedance tends to be lower than the design value, i.e., the impedance deviation is negative; conversely, the impedance tends to be higher, i.e., the impedance deviation is positive. Therefore, the fact that the impedance deviation and linewidth deviation have the same sign indicates a theoretical correlation between the electrical performance anomaly and the physical dimensional anomaly at that location in terms of direction of change. They are highly likely caused by the same physical root cause: deviations in the wire etching process. Screening such data points can focus on coupling anomalies directly caused by the etching process, excluding those caused by other irrelevant factors.

[0084] The specific implementation method for clustering by spatial coordinates to form several spatial continuous sets is as follows: First, the data points with the same sign as the impedance deviation and line width deviation are selected as clustering objects. Each data point carries spatial coordinates based on the PCB design coordinate system and the corresponding deviation value.

[0085] Next, considering the need to accurately identify spatially continuous deviation areas, density clustering was selected. The key parameters were set according to the spacing of the test points on the PCB board: the neighborhood radius was set to 5mm to match half of the maximum spacing of the test points, ensuring that deviation data points in adjacent areas could be associated, and the minimum number of points was set to 3 to avoid misjudging isolated points of single or two random deviations as continuous areas.

[0086] Then, during clustering, the set of unclustered data points is initialized first. Each unclustered point is traversed, and all similar data points within the neighborhood radius of the point are selected by Euclidean distance calculation. If the number of data points in the neighborhood is greater than or equal to the minimum number of points, the point and its neighborhood points are marked as the initial cluster. Then, the neighborhood of each point in the initial cluster is recursively traversed, and points that meet the conditions are included in the cluster to expand the cluster boundary until no new points can be added, forming a spatially continuous cluster. Otherwise, it is judged as an isolated noise point and excluded. The above process is repeated until all unclustered points have been traversed. The final cluster is a spatially continuous set. Then, the minimum and maximum X coordinates and the minimum and maximum Y coordinates of all data points in each cluster are taken to form the rectangular coordinate range corresponding to the cluster. The PCB board area covered by this range is defined as the area to be compensated.

[0087] Calculate the average line width deviation of all data points within each area to be compensated, and define this average value as the baseline adjustment amount for that area.

[0088] For the area to be compensated where the baseline adjustment is positive, a control command is generated to increase the spray pressure or etching solution flow rate of the corresponding etching equipment area. The adjustment range is positively correlated with the baseline adjustment.

[0089] For the area to be compensated where the baseline adjustment is negative, a control command is generated to reduce the spray pressure or etching solution flow rate of the corresponding etching equipment area. The adjustment range is positively correlated with the absolute value of the baseline adjustment.

[0090] It should be noted that a positive baseline adjustment indicates that the measured linewidth is greater than the design linewidth, meaning the linewidth is too large. This also implies insufficient etching and inadequate material removal in that area. Therefore, etching needs to be enhanced, i.e., by increasing the spray pressure or the etching solution flow rate.

[0091] A negative baseline adjustment indicates that the measured linewidth is smaller than the design linewidth, meaning the linewidth is too small, which also implies over-etching in that area. Therefore, etching needs to be reduced, i.e., the spray pressure or etching solution flow rate needs to be decreased.

[0092] The adjustment range is determined by the product of the absolute value of the baseline adjustment and the spray pressure adjustment coefficient or the etching solution flow rate adjustment coefficient. The specific process for obtaining the spray pressure adjustment coefficient and the etching solution flow rate adjustment coefficient is as follows: First, select more than 50 PCB samples of the same model and substrate as the target PCB, fix the etching solution concentration, temperature and other parameters, and construct an experimental matrix with different pressures, different flow rates and groups as variables. Then, after etching each group of parameters, use optical equipment to measure the line width deviation and record the changes in spray pressure and flow rate, forming more than 100 data pairs of spray pressure and flow rate changes in each group. Then, use the 3σ criterion to remove outliers, with a retention rate of more than 90%. Linear fitting is performed on the purified data using the least squares method to solve for the optimal solutions of the spray pressure adjustment coefficient and the etching solution flow rate adjustment coefficient. Finally, take the extreme value of the line width deviation and calculate the adjustment range according to the coefficient.

[0093] S6. If the abnormality is determined to be non-etching, the dielectric layer thickness fluctuation of the PCB board is detected, and the abnormality type is determined based on the dielectric layer thickness fluctuation.

[0094] After determining that the impedance anomaly is a non-etching anomaly, in order to diagnose the process defects related to the dielectric layer, the detection steps for the dielectric layer thickness fluctuation amplitude of the PCB board are as follows: control the laser displacement sensor to scan the PCB board surface and obtain its dielectric layer thickness distribution dataset.

[0095] Specifically, firstly, the laser displacement sensor is controlled to scan the copper foil reference area on the PCB board to obtain the height data of the reference plane and define it as a zero-thickness reference plane. Then, the dielectric area is scanned point by point. For each scan point, the distance from its surface to the probe is measured and compared with the distance value of the zero-thickness reference plane. Finally, the dielectric layer thickness of each scan point is the absolute value of the difference between the average distance value of the zero-thickness reference plane and the distance value of the current point on the dielectric layer surface. Traversing all scan points constitutes the dielectric layer thickness distribution dataset.

[0096] Based on the dielectric layer thickness distribution dataset, the maximum and minimum thickness values ​​are identified, and the difference between the two is calculated as the dielectric layer thickness fluctuation range.

[0097] By extracting the two extreme values ​​from the thickness distribution data and calculating their range, the total thickness deviation range of the dielectric layer across the entire plate surface can be reflected, thus providing a single numerical value to macroscopically characterize the overall uniformity level of the lamination or coating process. A small fluctuation indicates concentrated thickness distribution and good process uniformity; a large fluctuation indicates a systemic problem in the process that leads to significant thickness differences.

[0098] The specific steps for determining the anomaly type based on the fluctuation range of the dielectric layer thickness are as follows: If the fluctuation range of the dielectric layer thickness is within the standard range of dielectric thickness uniformity, it is initially determined that it is caused by the variation of the spatial properties of the dielectric material.

[0099] The standard range for dielectric thickness uniformity is mainly determined based on the corresponding industry product standards. For example, if the nominal thickness of the dielectric layer used in a PCB is 100μm, according to industry product standards, the allowable standard range for thickness uniformity is set to be less than or equal to 20μm.

[0100] If the measured dielectric constant of a PCB board deviates from its global average value, it is determined that the dielectric material performance is abnormal.

[0101] Preferably, the dielectric constant of the PCB board is measured using the parallel plate capacitor method, and the dielectric constant is calculated by back-calculating the capacitance formula of the parallel plate capacitor.

[0102] The dielectric material of PCB boards in the same batch should have uniform physical and chemical properties. The dielectric constant, as its inherent electrical property, should be consistent. The global average value of the dielectric constant can characterize the normal reference state of the dielectric constant of the batch of materials. If the measured value deviates from the reference, it indicates that there is microscopic composition or structural inhomogeneity in the dielectric material, and therefore it is judged as abnormal dielectric material performance.

[0103] If the thickness fluctuation of the dielectric layer exceeds the standard range, it is determined to be an abnormality in the lamination process.

[0104] The uniformity of PCB dielectric layer thickness is directly determined by the lamination process. The standard range for dielectric thickness uniformity is the allowable fluctuation range of dielectric layer thickness when the lamination process is normal. If the thickness fluctuation exceeds this range, it indicates an abnormal lamination process.

[0105] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0106] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0107] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0109] Finally, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A visualization-based method for testing and analyzing PCB impedance uniformity, characterized by: include: Use a TDR device to scan the impedance data and coordinate information of test points on the PCB board. The coordinate information of each test point is associated with the corresponding impedance value and mapped. An impedance spatial distribution heat map is generated by interpolation. In the impedance spatial distribution heat map, abnormal points that exceed the preset impedance tolerance zone are marked. The impedance values ​​of each test point are associated with and stored with their corresponding coordinates; the coordinates of each test point are unified to the coordinate system of the PCB design drawing, and a grid of points is created within the outline boundary area of ​​the PCB board; with the current grid point as the center, test points whose Euclidean distance from the grid point is less than or equal to the search radius are selected as nearby known points. Calculate the distance values ​​between each neighboring known point and their corresponding impedance differences. Divide the distance values ​​into intervals and calculate half of the average of the squared impedance differences within each interval as the semivariance of the interval. Perform curve fitting on the distance intervals and the corresponding semivariance values ​​to obtain the dependence of impedance differences on distance. Assign contribution weights to each neighboring known point based on the dependence. Multiply the impedance value of each neighboring known point by its corresponding contribution weight and sum the results to obtain the impedance value of the current grid point. Assign a corresponding color to the impedance value of each grid point to generate a heatmap of impedance spatial distribution. Identify the spatial distribution characteristics of the marked abnormal points, and determine the type of impedance abnormality based on the spatial distribution characteristics. If the marked abnormal points are concentrated in the edge or center area of ​​the PCB board, they are determined to be etching abnormalities. The connected regions of all anomalies are identified from the impedance spatial distribution heatmap and defined as anomaly regions. The average boundary coordinates of each anomaly region are calculated to obtain its geometric centroid coordinates. The Euclidean distance between the centroid of each anomaly region and the geometric center of the panel is calculated to form an anomaly region distance dataset. The range of the farthest distance from the geometric center of the panel to the panel outline is divided into several equally spaced intervals. The anomaly region distance dataset is traversed, and the number of anomalies contained in each equally spaced interval is counted as the frequency of that interval. The average frequency of all equally spaced intervals is calculated. The ratio of the frequency of each equally spaced interval to the average frequency is calculated one by one. The equally spaced intervals with a ratio greater than the significance threshold are identified as significant peak intervals. The edge and center regions of the board are defined based on the PCB design information. If a significant peak interval falls into the edge or center region, the abnormal points are determined to be concentrated in the corresponding region, and the impedance abnormality type is determined to be an etching abnormality. If the marked abnormal points are randomly distributed on the board surface, they are determined to be non-etching abnormalities; If the etching is determined to be abnormal, the linewidth distribution map of the PCB board is obtained, the linewidth distribution map is compared with the impedance spatial distribution heat map, and the compensation parameters of the etching process are adjusted according to the comparison results. If the abnormality is determined to be non-etching, the fluctuation range of the dielectric layer thickness on the PCB board is detected, and the type of abnormality is determined based on the fluctuation range of the dielectric layer thickness.

2. The PCB impedance uniformity test and analysis method based on visualization according to claim 1, characterized in that: The process of scanning the impedance data and coordinate information of test points on the PCB board using a TDR device includes: Based on the design information of the PCB board, identify the key electrical functional areas and physical structural feature areas on the board surface; Test points are placed at equal intervals along the critical wiring path in the key electrical function area. Test points are placed at equal intervals along concentric circular paths with increasing radius around the geometric center of the physical structural feature area. Test points are placed evenly in the remaining area according to a rectangular grid. The test probes of the TDR device are moved sequentially to each test point and make electrical contact. When a stable electrical contact is formed, the TDR device is triggered to measure the impedance value and position coordinates of each test point.

3. The PCB impedance uniformity test and analysis method based on visualization according to claim 2, characterized in that: The steps for determining if an etching anomaly is not an etching anomaly are as follows: When no significant peak intervals are identified, the marked abnormal points are determined to be randomly distributed on the board surface, i.e., the impedance abnormality type is determined to be non-etching abnormality.

4. The PCB impedance uniformity test and analysis method based on visualization according to claim 1, characterized in that: The process of obtaining the linewidth distribution map of the PCB board includes: The image sensor of the optical inspection equipment is controlled to scan the PCB board surface, acquire digital images, and register the coordinate system of the digital images to the same coordinate system as the PCB design file; Along the design direction of the target traverse, extract the grayscale profile line perpendicular to the traverse direction. The position where the grayscale value first changes sharply from high to low is the candidate left edge point, and the position where the grayscale value last changes sharply from low to high is the candidate right edge point. The geometric center positions of all candidate left and right edge points are determined as the left and right edge positions of the target traverse. Pixel distance is calculated based on the left and right edge positions. According to the calibration parameters of the optical inspection equipment, the pixel distance is converted into the actual physical line width value and the corresponding coordinates are recorded. By associating the actual line width value with its coordinates, a line width distribution map is generated through spatial interpolation.

5. The PCB impedance uniformity test and analysis method based on visualization according to claim 1, characterized in that: The steps for spatially comparing the linewidth distribution map with the impedance spatial distribution heatmap are as follows: Under the unified PCB design coordinate system, the impedance spatial distribution heatmap and the line width distribution map are mesh registered and aligned. The difference between the measured impedance value and the target impedance value at each grid point is calculated as the impedance deviation, and the difference between the measured line width value and the designed line width value is calculated as the line width deviation. By correlating the impedance deviation and linewidth deviation at the same grid point, a set of joint deviation data reflecting the relationship between impedance and linewidth deviation at each location is generated.

6. The PCB impedance uniformity test and analysis method based on visualization according to claim 5, characterized in that: The steps for adjusting the compensation parameters of the etching process are as follows: Based on the joint deviation data set, all data points with the same sign as the impedance deviation and line width deviation are selected and clustered according to spatial coordinates to form several spatially continuous sets. The PCB board area covered by each set is defined as the area to be compensated. Calculate the average line width deviation of all data points within each area to be compensated, and define this average value as the baseline adjustment amount for that area. For the area to be compensated where the baseline adjustment is positive, a control command is generated to increase the spray pressure or etching solution flow rate of the corresponding etching equipment area. The adjustment range is positively correlated with the baseline adjustment. For the area to be compensated where the baseline adjustment is negative, a control command is generated to reduce the spray pressure or etching solution flow rate of the corresponding etching equipment area. The adjustment range is positively correlated with the absolute value of the baseline adjustment.

7. The PCB impedance uniformity test and analysis method based on visualization according to claim 1, characterized in that: The steps for detecting the dielectric layer thickness fluctuation of the PCB board are as follows: The laser displacement sensor is controlled to scan the PCB board surface to obtain a dataset of its dielectric layer thickness distribution. Based on the dielectric layer thickness distribution dataset, the maximum and minimum thickness values ​​are identified, and the difference between the two is calculated as the dielectric layer thickness fluctuation range.

8. The PCB impedance uniformity test and analysis method based on visualization according to claim 1, characterized in that: The method of determining the anomaly type based on the fluctuation range of the dielectric layer thickness includes: If the fluctuation range of the dielectric layer thickness is within the standard range of dielectric thickness uniformity, it is preliminarily determined that it is caused by the variation of the spatial properties of the dielectric material; If the measured dielectric constant of a PCB board deviates from its global average value, it is determined that the dielectric material performance is abnormal. If the thickness fluctuation of the dielectric layer exceeds the standard range, it is determined to be an abnormality in the lamination process.

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