Transmitting circuit suitable for USB Type-C interface

Abstract

The invention provides a sending circuit suitable for a USB Type-C interface, and the circuit comprises a main control circuit, a control logic circuit, an output stage, and a band-gap reference, the band-gap reference is used for providing a reference voltage for the control logic circuit, and the control logic circuit is used for receiving and processing a to-be-sent signal outputted by the main control circuit; and the output stage is used for executing the to-be-sent signal processed by the control logic circuit. By using the transmitting circuit provided by the invention, an additional LDO is not needed, and the area is smaller; and the rising / falling time of the output signal can be adjusted, so that various voltage requirements can be met.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a sending circuit suitable for a USB Type-C interface. BACKGROUND

[0002] The USB Type-C interface is a mainstream interface used by smart phones, notebook computers, earphones and other devices, and has the characteristics of small size, support for forward and reverse insertion and high transmission rate. The sending circuit of the USB Type-C interface mainly includes core components such as control logic and an output stage. The control logic is responsible for protocol processing, state detection and instruction issuing, and the output stage is responsible for implementing voltage / current output and high-speed data transmission. In the prior art, a bandgap reference and an additional low dropout regulator (LDO) are usually used to provide a stable reference voltage that is not affected by temperature to the control logic and the output stage. However, the use of the LDO increases the area of the sending circuit to some extent, and the rise / fall time of the output signal provided by the LDO cannot be adjusted, which cannot directly adapt to the multi-voltage requirement of the Type-C.

[0003] Therefore, it is necessary to provide a sending circuit suitable for the USB Type-C interface, which has a smaller area and an adjustable output signal. SUMMARY

[0004] To solve the problems in the prior art, the application provides a sending circuit suitable for a USB Type-C interface, which does not require an additional LDO and the rise / fall time of the output signal can be adjusted to adapt to various voltage requirements.

[0005] The application solves the above technical problems by adopting the following technical solutions: A sending circuit suitable for a USB Type-C interface, comprising a master control circuit, a control logic circuit, an output stage and a bandgap reference, wherein the bandgap reference is used to provide a reference voltage V BG to the control logic circuit, the control logic circuit is used to receive and process a to-be-sent signal output by the master control circuit, and the output stage is used to execute the to-be-sent signal processed by the control logic circuit.

[0006] Further, the control logic comprises a second P-type MOS transistor PM1, a third P-type MOS transistor PM2, a fourth P-type MOS transistor PM3, a second N-type MOS transistor NM1, a third N-type MOS transistor NM2, a fourth N-type MOS transistor NM3, a first capacitor C0, a second capacitor C1, a first current source I0, a second current source I1, a third current source I2, a fourth current source I3 and a fifth current source I4. The output stage comprises a first P-type MOS PM0, a first N-type MOS NM0, a fifth N-type MOS NM4, a sixth current source I5, and a signal output terminal CC.

[0007] Further, one end of the first current source I0 is connected to a power supply voltage VCC, and the other end is connected to the source of the fourth P-type MOS PM3 and the gate of the fifth N-type MOS NM4, respectively; The gate of the fourth P-type MOS PM3 is connected to the bandgap reference, the drain of the fourth P-type MOS PM3 is connected to the drain and the gate of the fourth N-type MOS NM3, respectively, and the source of the fourth N-type MOS NM3 is grounded; One end of the second current source I1 is connected to the power supply voltage VCC, and the other end is connected to the source of the second P-type MOS PM1. The gate of the second P-type MOS PM1 is connected in parallel to the gate of the second N-type MOS NM1 at the signal output terminal of the main control circuit, for receiving a to-be-sent signal DATA. The drain of the second P-type MOS PM1 is connected in parallel to the drain of the second N-type MOS NM1 at the gate of the first P-type MOS PM0 and the first capacitor C0. The source of the second N-type MOS NM1 is connected to the third current source I2, and the opposite end of the third current source I2 connected to the source of the second N-type MOS NM1 is grounded. One end of the fourth current source I3 is connected to the power supply voltage VCC, and the other end is connected to the source of the third P-type MOS PM2. The gate of the third P-type MOS PM2 is connected in parallel to the gate of the third N-type MOS NM2 at the signal output terminal of the main control circuit, for receiving a to-be-sent signal DATA. The drain of the third P-type MOS PM2 is connected in parallel to the drain of the third N-type MOS NM2 at the gate of the first N-type MOS NM0 and the second capacitor C1. The source of the third N-type MOS is connected to the fifth current source I4, and the opposite end of the fifth current source I4 connected to the source of the third P-type MOS PM2 is grounded. The source of the first P-type MOS is connected to the power supply voltage VCC, the drain of the first P-type MOS is connected to the drain of the fifth N-type MOS NM4, the gate of the fifth N-type MOS NM4 is connected between the first current source I0 and the source of the fourth P-type MOS PM3, and the source of the fifth N-type MOS is connected to the first capacitor C0 and the signal output terminal CC, respectively. The drain of the first N-type MOS NM0 is connected to the second capacitor C0, the source of the fifth N-type MOS, and the signal output terminal CC, respectively, and the source of the first N-type MOS is grounded. The sixth current source I5 is connected at one end to the source of the fifth N-type MOS tube NM4, the drain of the first N-type MOS tube and the signal output terminal CC, and grounded at the other end.

[0008] Further, the first current source I0, the second current source I1, the third current source I2, the fourth current source I3, the fifth current source I4 and the sixth current source I5 are adjustable in size; the capacitance of the first capacitor C0 and the second capacitor C1 is fixed.

[0009] Further, the high level of the signal output terminal CC is regulated by the bandgap voltage VBG provided by the bandgap reference, BG the gate-source voltage VGS_PM3 of the fourth P-type MOS tube, GS_PM3 the gate-source voltage VGS_NM4 of the fifth N-type MOS tube, GS_NM4 the first current source I0 and the sixth current source I5.

[0010] Further, the regulation method of the high level of the signal output terminal CC is as follows: the high level of the signal output terminal CC is regulated by the bandgap voltage VBG provided by the bandgap reference, V BG +|V GS_PM3 |-|V GS_NM4 | ; wherein V BG is a 1.2V bandgap voltage provided by the bandgap reference; |V GS_PM3 | is the absolute value of the gate-source voltage VGS_PM3 of the fourth P-type MOS tube; |V GS_NM4 | is the absolute value of the gate-source voltage VGS_NM4 of the fifth N-type MOS tube; The greater the first current source I0 is, |V GS_PM3 | the higher the high level of the output signal is; The greater the sixth current source I5 is, |V GS_NM4 | the lower the high level of the output signal is.

[0011] Further, the rising and falling time of the signal output terminal CC can be regulated by the rising and falling slope of the gate voltage V G_PM0 of the first P-type MOS tube and the gate voltage V G_NM0 of the first N-type MOS tube.

[0012] Further, the signal output end CC outputs the adjustment method of the rising and falling time of the signal: The greater the second current source I1, the faster the first capacitor C0 charges, and the faster the gate voltage V G_PM0 of the first P-type MOS PM0 rises; The greater the third current source I2, the faster the first capacitor C0 discharges, and the faster the gate voltage V G_PM0 of the first P-type MOS PM0 falls; By adjusting the second current source I1 and the third current source I2, the rising / falling slope of the gate voltage V G_PM0 of the first P-type MOS PM0 can be adjusted; The greater the fourth current source I3, the faster the second capacitor C1 charges, and the faster the gate voltage V G_NM0 of the first N-type MOS NM0 rises; The greater the fifth current source I4, the faster the second capacitor C1 discharges, and the faster the gate voltage V G_NM0 of the first N-type MOS NM0 falls; By adjusting the fourth current source I3 and the fifth current source I4, the rising / falling slope of the gate voltage V G_NM0 of the first N-type MOS NM0 can be adjusted.

[0013] The application provides a sending circuit suitable for a USB Type-C interface, which does not need an additional LDO, has a smaller area, and can adjust the rising / falling time of an output signal, and is suitable for various voltage requirements.

[0014] The application also provides a fast charging chip, which comprises the sending circuit suitable for the USB Type-C interface.

[0015] The application also provides a portable device, which comprises the fast charging chip. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The application provides a module schematic diagram of the sending circuit suitable for the USB Type-C interface.

[0017] Figure 2 The application provides a circuit structure schematic diagram of the sending circuit suitable for the USB Type-C interface. DETAILED DESCRIPTION

[0018] The application will be further described below in combination with the drawings and specific embodiments.

[0019] In one embodiment, a transmitting circuit suitable for a USB Type-C interface, such as Figure 1 As shown, it includes a main control circuit, a control logic circuit, an output stage, and a bandgap reference; the bandgap reference is used to provide a reference voltage V to the control logic circuit. BG Reference voltage V BG The voltage is 1.2V; the control logic circuit is used to receive and process the signal to be transmitted output by the main control circuit; the output stage is used to execute the signal to be transmitted after being processed by the control logic circuit.

[0020] The control logic circuit includes a second P-type MOSFET PM1, a third P-type MOSFET PM2, a fourth P-type MOSFET PM3, a second N-type MOSFET NM1, a third N-type MOSFET NM2, a fourth N-type MOSFET NM3, a first capacitor C0, a second capacitor C1, a first current source I0, a second current source I1, a third current source I2, a fourth current source I3, and a fifth current source I4. The output stage includes a first P-type MOSFET PM0, a first N-type MOSFET NM0, a fifth N-type MOSFET NM4, a sixth current source I5, and a signal output terminal CC.

[0021] One end of the first current source I0 is connected to the supply voltage VCC, and the other end is connected to the source of the fourth P-type MOSFET PM3 and the gate of the fifth N-type MOSFET NM4, respectively. The gate of the fourth P-type MOSFET PM3 is connected to the bandgap reference; the drain of the fourth P-type MOSFET PM3 is connected to the drain and gate of the fourth N-type MOSFET NM3; the source of the fourth N-type MOSFET NM3 is grounded. One end of the second current source I1 is connected to the supply voltage VCC, and the other end is connected to the source of the second P-type MOSFET PM1. The gate of the second P-type MOSFET PM1 and the gate of the second N-type MOSFET NM1 are connected in parallel to the signal output terminal of the main control circuit to receive the signal DATA to be transmitted. The drain of the second P-type MOSFET PM1 and the drain of the second N-type MOSFET NM1 are connected in parallel between the gate of the first P-type MOSFET PM0 and the first capacitor C0. The source of the second N-type MOSFET NM1 is connected to the third current source I2. The opposite end of the third current source I2 connected to the source of the second N-type MOSFET NM1 is grounded. The fourth current source I3 has one end connected to the power supply voltage VCC and the other end connected to the source of the third P-type MOS PM2. The gate of the third P-type MOS PM2 is connected in parallel with the gate of the third N-type MOS NM2 to the signal output end of the main control circuit for receiving the signal DATA to be transmitted. The drain of the third P-type MOS PM2 is connected in parallel with the drain of the third N-type MOS NM2 to the gate of the first N-type MOS NM0 and between the first capacitor C0 and the second capacitor C1. The source of the third N-type MOS is connected to the fifth current source I4, and the opposite end of the fifth current source I4 connected to the source of the third P-type MOS PM2 is grounded. The source of the first P-type MOS PM0 is connected to the power supply voltage VCC, and the drain of the first P-type MOS PM0 is connected to the drain of the fifth N-type MOS NM4. The gate of the fifth N-type MOS NM4 is connected between the first current source I0 and the drain of the fourth P-type MOS PM3. The source of the fifth N-type MOS is connected to the first capacitor C0 and the signal output end CC respectively. The drain of the first N-type MOS NM0 is connected to the second capacitor C0, the source of the fifth N-type MOS, and the signal output end CC respectively. The source of the first N-type MOS is grounded. The sixth current source I5 has one end connected to the source of the fifth N-type MOS NM4, the drain of the first N-type MOS NM0, and the signal output end CC, and the other end grounded.

[0022] The first current source I0, the second current source I1, the third current source I2, the fourth current source I3, the fifth current source I4, and the sixth current source I5 are adjustable in size. The capacitance of the first capacitor C0 and the second capacitor C1 is fixed.

[0023] In another embodiment, an output signal adjusting method based on the above-mentioned transmitting circuit structure is also provided.

[0024] In this embodiment, the high level of the signal output end CC output signal is adjusted by the bandgap voltage VBG provided by the bandgap reference, BG the gate-source voltage VGS of the fourth P-type MOS PM3, GS_PM3 the gate-source voltage VGS of the fifth N-type MOS NM4, GS_NM4 the first current source I0, and the sixth current source I5.

[0025] The specific adjusting method of the high level of the signal output end CC output signal is as follows: The high level of the signal output end CC output signal is V BG +|V GS_PM3 |-|V GS_NM4 | ; where VBG is the bandgap voltage provided by the bandgap reference.BG 1.2V bandgap voltage provided for bandgap reference; |V GS_PM3 | absolute value of gate-source voltage V GS_PM3 of the fourth P-type MOS PM3; |V GS_NM4 | absolute value of gate-source voltage V GS_NM4 of the fifth N-type MOS NM4; The greater the first current source I0 is, |V GS_PM3 | The greater the first current source I0 is, The greater the sixth current source I5 is, |V GS_NM4 | The greater the sixth current source I5 is,

[0026] In actual testing, when the high-level voltage of the waveform emitted by the signal output terminal CC is lower than 1.2V, the current of the first current source I0 can be adjusted to increase the high-level voltage to 1.2V; when the high-level voltage of the waveform emitted by the signal output terminal CC is greater than 1.2V, the sixth current source I5 can be adjusted to decrease the high-level voltage to 1.2V.

[0027] In another embodiment, a method for adjusting the rising and falling time of the output signal based on the above-mentioned transmitting circuit structure is also provided. The rising and falling time of the output signal of the transmitting circuit can be adjusted to ensure that the voltage change rate of the output signal meets the fast charging protocol specification, improve the compatibility of the transmitting circuit to different fast charging protocols, support multiple application scenarios; at the same time, avoid triggering overvoltage / undervoltage protection.

[0028] In this embodiment, the rising and falling time of the output signal of the signal output terminal CC can be adjusted by the rising and falling slope of the gate voltage V G_PM0 of the first P-type MOS PM0 and the gate voltage V G_NM0 of the first N-type MOS.

[0029] Specifically, the greater the second current source I1 is, the faster the first P-type MOS PM0 is charged, and the faster the gate voltage V G_PM0 of the first P-type MOS PM0 rises; The greater the third current source I2 is, the faster the first P-type MOS PM0 discharges, and the faster the gate voltage V G_PM0 of the first P-type MOS PM0 falls; Therefore, by adjusting the second current source I1 and the third current source I2, the gate voltage VG_PM0 The rising / falling slope; The larger the fourth current source I3, the faster it charges the second capacitor C1, and the higher the gate voltage V of the first N-type MOSFET NM0. G_NM0 The faster it rises; The larger the fifth current source I4, the faster the second capacitor C1 discharges, and the faster the gate voltage V of the first N-type MOSFET NM0. G_NM0 The faster the descent; The gate voltage V of the first N-type MOSFET NM0 can be adjusted by regulating the fourth current source I3 and the fifth current source I4. G_NM0 The rising / falling slope.

[0030] In actual testing, if the waveform emitted from the signal output terminal CC has a slow slope from low to high, the third current source I2 and the fifth current source I4 can be increased simultaneously. When the third current source I2 is increased, the gate voltage of the first P-type MOSFET PM0 is released to ground more quickly, and the first P-type MOSFET PM0 turns on. When the fifth current source I4 is increased, the gate voltage of the first N-type MOSFET NM0 is released to ground more quickly, and the first N-type MOSFET NM0 turns off. Therefore, by simultaneously increasing the third current source I2 and the fifth current source I4, the turn-on of the first P-type MOSFET PM0 and the turn-off of the first N-type MOSFET NM0 can be accelerated, thereby making the rising slope steeper. Conversely, decreasing the current of the third current source I2 and the fifth current source I4 can reduce the turn-on speed of the first P-type MOSFET PM0 and the turn-off speed of the first N-type MOSFET NM0, thereby making the rising slope gentler.

[0031] If the waveform emitted from the signal output terminal CC has a too gentle slope from high to low, the second current source I1 and the fourth current source I3 can be increased simultaneously. When the second current source I1 is increased, the gate voltage of the first P-type MOSFET PM0 is pulled up to VCC more quickly, and the first P-type MOSFET is turned off. When the fourth current source I3 is increased, the gate voltage of the first N-type MOSFET NM0 is pulled up to VCC more quickly, and the first N-type MOSFET NM0 is turned on. Therefore, by increasing the second current source I1 and the fourth current source I3 simultaneously, the turn-on of the first N-type MOSFET NM0 and the turn-off of the first P-type MOSFET PM0 can be accelerated, thus making the downward slope steeper. Conversely, decreasing the current of the second current source I1 and the fourth current source I3 can reduce the turn-on speed of the first N-type MOSFET NM0 and the turn-off speed of the second P-type MOSFET PM0, thus making the downward slope gentler.

[0032] The embodiment also provides a fast charging chip, including the above-described transmitting circuit suitable for a USB Type-C interface.

[0033] The embodiments also provide a portable device comprising the aforementioned fast charging chip. For example, the portable device can be a charger, a charging cable, a power bank, etc. provided with the aforementioned fast charging chip.

[0034] The above embodiments and drawings are only an explanation and illustration of the technical scheme of the present application, and should not be considered as a limitation of the specific embodiments of the present application. For those skilled in the art of the present application, simple deductions or substitutions made without departing from the technical scheme concept of the present application still belong to the protection scope of the present application.

Claims

1. A transmitting circuit suitable for a USB Type-C interface, characterized in that, It includes a main control circuit, a control logic circuit, an output stage, and a bandgap reference. The bandgap reference is used to provide a reference voltage to the control logic circuit, and the control logic circuit is used to receive and process the signal to be transmitted output by the main control circuit. The output stage is used to execute the signal to be sent after it has been processed by the control logic circuitry.

2. The transmitting circuit for a USB Type-C interface according to claim 1, characterized in that, The control logic circuit includes a second P-type MOSFET, a third P-type MOSFET, a fourth P-type MOSFET, a second N-type MOSFET, a third N-type MOSFET, a fourth N-type MOSFET, a first capacitor, a second capacitor, a first current source, a second current source, a third current source, a fourth current source, and a fifth current source. The output stage includes a first P-type MOSFET, a first N-type MOSFET, a fifth N-type MOSFET, a sixth current source, and a signal output terminal.

3. The transmitting circuit for a USB Type-C interface according to claim 2, characterized in that, One end of the first current source is connected to the power supply voltage, and the other end is connected to the source of the fourth P-type MOS transistor and the gate of the fifth N-type MOS transistor, respectively. The gate of the fourth P-type MOS transistor is connected to the bandgap reference; the drain of the fourth P-type MOS transistor is connected to the drain and gate of the fourth N-type MOS transistor respectively; the source of the fourth N-type MOS transistor is grounded. One end of the second current source is connected to the power supply voltage, and the other end is connected to the source of the second P-type MOSFET; the gate of the second P-type MOSFET and the gate of the second N-type MOSFET are connected in parallel to the signal output terminal of the main control circuit for receiving the signal to be transmitted; the drain of the second P-type MOSFET and the drain of the second N-type MOSFET are connected in parallel between the gate of the first P-type MOSFET and the first capacitor; the source of the second N-type MOSFET is connected to the third current source; the opposite end of the third current source connected to the source of the second N-type MOSFET is grounded. One end of the fourth current source is connected to the power supply voltage, and the other end is connected to the source of the third P-type MOS transistor; the gate of the third P-type MOS transistor and the gate of the third N-type MOS transistor are connected in parallel to the signal output terminal of the main control circuit for receiving the signal to be transmitted; the drain of the third P-type MOS transistor and the drain of the third N-type MOS transistor are connected in parallel between the gate of the first N-type MOS transistor and the second capacitor; the source of the third N-type MOS transistor is connected to the fifth current source, and the opposite end of the fifth current source connected to the source of the third N-type MOS transistor is grounded; The source of the first P-type MOS transistor is connected to the power supply voltage, and the drain of the first P-type MOS transistor is connected to the drain of the fifth N-type MOS transistor; the gate of the fifth N-type MOS transistor is connected between the first current source and the source of the fourth P-type MOS transistor; the source of the fifth N-type MOS transistor is connected to the first capacitor and the signal output terminal respectively. The drain of the first N-type MOS transistor is connected to the second capacitor, the source of the fifth N-type MOS transistor, and the signal output terminal, respectively; the source of the first N-type MOS transistor is grounded. One end of the sixth current source is connected to the source of the fifth N-type MOS transistor, the drain of the first N-type MOS transistor, and the signal output terminal, while the other end is grounded.

4. The transmitting circuit for a USB Type-C interface according to claim 3, characterized in that, The sizes of the first current source, the second current source, the third current source, the fourth current source, the fifth current source, and the sixth current source are adjustable; the capacitance values ​​of the first capacitor and the second capacitor are fixed.

5. The transmitting circuit suitable for a USB Type-C interface according to claim 4, characterized in that, The high level of the signal output at the CC terminal is adjusted by the bandgap voltage provided by the bandgap reference, the gate-source voltage of the fourth P-type MOS transistor, the gate-source voltage of the fifth N-type MOS transistor, the first current source, and the sixth current source.

6. The transmitting circuit for a USB Type-C interface according to claim 5, characterized in that, The method for adjusting the high level of the output signal at the signal output terminal is as follows: The high level of the output signal at the CC terminal = V BG +|V GS_PM3 |-| V GS_NM4 | ; Where V BG A 1.2V bandgap voltage is provided for the bandgap reference; |V GS_PM3 | The gate-source voltage V of the fourth P-type MOS transistor GS_PM3 The absolute value; |V GS_NM4 | V is the gate-source voltage of the fifth N-type MOS transistor. GS_NM4 The absolute value; The larger the first current source is... |V GS_PM3 | The larger the value, the higher the high level of the output signal; The larger the sixth current source is... |V GS_NM4 | The larger the value, the lower the high level of the output signal.

7. The transmitting circuit for a USB Type-C interface according to claim 6, characterized in that, The rise and fall times of the output signal can be adjusted by the rise and fall slopes of the gate voltage of the first P-type MOS transistor and the gate voltage of the first N-type MOS transistor.

8. The transmitting circuit for a USB Type-C interface according to claim 7, characterized in that, The method for adjusting the rise and fall times of the output signal at the signal output terminal is as follows: The larger the second current source, the faster it charges the first capacitor, and the faster the gate voltage of the first P-type MOS transistor rises. The larger the third current source, the faster the first capacitor discharges, and the faster the gate voltage of the first P-type MOS transistor drops. The rise / fall slope of the gate voltage of the first P-type MOS transistor can be adjusted by adjusting the second current source and the third current source. The larger the fourth current source, the faster it charges the second capacitor, and the faster the gate voltage of the first N-type MOS transistor rises. The larger the fifth current source, the faster the second capacitor discharges, and the faster the gate voltage of the first N-type MOS transistor drops. The rise / fall slope of the gate voltage of the first N-type MOS transistor can be adjusted by adjusting the fourth current source and the fifth current source.

9. A fast charging chip, characterized in that, Includes a transmitting circuit suitable for a USB Type-C interface as described in any one of claims 1 to 8.

10. A portable device, characterized in that, Includes the fast charging chip as described in claim 9.

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