Memory controller, apparatus, system, operating method thereof, and

Abstract

The embodiment of the invention provides a memory controller, a memory device, a memory system, an operation method thereof and a storage medium. The memory controller comprises: an interface; the processor is configured to obtain a statistical result corresponding to the physical page under the first reading voltage; the statistical result comprises a first number of bits representing that the physical page is flipped in two reading results under the first reading voltage and the reading voltage of which the voltage difference with the first reading voltage is smaller than a preset voltage, and / or a second number of bits representing that the physical page is failed to read under the first reading voltage; the first reading voltage is smaller than a mean value of a threshold voltage interval corresponding to a middle storage state of the physical page; and judging the read interference state of the physical page according to a statistical result.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory controller, device, system, operating method thereon, and storage medium. Background Technology

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND flash memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erase speed, and retention characteristics. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a memory controller, device, system, operating method thereon, and storage medium.

[0004] In a first aspect, embodiments of this application provide a memory controller coupled to at least one memory device, the memory device including multiple word lines, each word line coupled to multiple memory cells, the multiple memory cells forming at least one physical page; the memory controller includes a processor configured to: acquire statistical results corresponding to the physical page under a first read voltage; the statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage with a voltage difference from the first read voltage less than a preset voltage, and / or a second number of bits that failed to read the physical page under the first read voltage; the average value of a threshold voltage range corresponding to the intermediate storage state of the physical page where the first read voltage is less than the first read voltage; and determine the read interference state of the physical page based on the statistical results.

[0005] In some embodiments, the processor is further configured to: determine whether the read interference state of the physical page is poor based on the relationship between statistical results and a preset threshold; and perform a data migration operation on the physical page if the read interference state of the physical page is determined to be poor.

[0006] In some embodiments, the preset threshold includes a first threshold and / or a second threshold; the processor is configured to determine that the read interference state of the physical page is poor based on a first quantity being greater than the first threshold and / or a second quantity being greater than the second threshold.

[0007] In some embodiments, the multiple storage states of a physical page include a first storage state and a second storage state with the lowest average threshold voltage range; the first threshold voltage is the average threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average threshold voltage range corresponding to the second storage state when the physical page is writing data; and the first read voltage is between the first threshold voltage and the second threshold voltage.

[0008] In some embodiments, the storage unit includes multiple bits of storage data, and the multiple bits of storage data in the storage unit are read through multiple read voltages; the processor is configured to set the read mode to a single-level read mode before acquiring the statistical results corresponding to the physical page under the first read voltage; the single-level read mode includes reading at least one bit of storage data stored in the storage unit through a first-level read voltage.

[0009] In some embodiments, the processor is configured to acquire a first read voltage and a preset threshold, respectively.

[0010] In some embodiments, the processor is configured to: obtain a first read voltage and a preset threshold from the memory device when the memory controller is powered on; both the first read voltage and the preset threshold are fixed values.

[0011] In some embodiments, the processor is configured to: when the memory controller is powered on, obtain an initial value of a first read voltage and an initial value of a preset threshold from the memory device, respectively; modify the initial value of the first read voltage and / or the initial value of the preset threshold by setting a feature command to obtain the first read voltage and the preset threshold.

[0012] In some embodiments, the memory controller further includes an interface coupled to the processor; the interface is configured to receive statistical results corresponding to physical pages transferred from the memory device under a first read voltage; or, the interface is configured to receive read results corresponding to physical pages transferred from the memory device under the first read voltage and a second read voltage, or read results corresponding to the first read voltage; the processor is configured to perform calculations and statistics on the read results to obtain statistical results.

[0013] Secondly, embodiments of this application provide a memory system, characterized in that it includes: one or more memory devices; and a memory controller as described in embodiments of this application, which is coupled to the memory devices and controls the memory devices.

[0014] In some embodiments, the memory controller is configured to: during a data inspection of the memory device, send a first instruction, the first instruction instructing the acquisition of statistical results of physical pages; the memory device is configured to: in response to the first instruction, acquire the statistical results of physical pages and send information including the statistical results of physical pages to the memory controller; the memory controller is further configured to: determine whether the read interference state of the physical page is poor based on the statistical results and a preset threshold; and perform a data migration operation on the physical page if the read interference state of the physical page is poor.

[0015] Thirdly, embodiments of this application provide a memory device, the memory device comprising: multiple word lines; each word line coupled to multiple memory cells, the multiple memory cells forming at least one physical page; peripheral circuitry coupled to the multiple word lines and configured to: acquire statistical results corresponding to the physical page under a first read voltage; the statistical results including a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage where the voltage difference from the first read voltage is less than a preset voltage, and / or a second number of bits that failed to be read under the first read voltage; the average value of a threshold voltage range corresponding to the intermediate storage state of the physical page where the first read voltage is less than the average value of the threshold voltage range; and determining the read interference state of the physical page based on the statistical results.

[0016] In some embodiments, the peripheral circuit is further configured to: determine whether the read interference state of the physical page is poor based on the relationship between the statistical results and the preset threshold; and perform a data migration operation on physical pages whose read interference state is determined to be poor.

[0017] In some embodiments, the preset threshold includes a first threshold and / or a second threshold; the peripheral circuit is configured to determine that the read interference state of the physical page is poor based on a first quantity being greater than the first threshold and / or a second quantity being greater than the second threshold.

[0018] In some embodiments, the multiple storage states of a physical page include a first storage state and a second storage state with the lowest average threshold voltage range; the first threshold voltage is the average threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average threshold voltage range corresponding to the second storage state when the physical page is writing data; and the first read voltage is between the first threshold voltage and the second threshold voltage.

[0019] In some embodiments, the storage unit includes multiple bits of storage data, and the multiple bits of storage data in the storage unit are read by multiple read voltages; the peripheral circuitry is configured to set the read mode to a single-level read mode before acquiring the statistical results corresponding to the physical page under the first read voltage; the single-level read mode includes reading at least one bit of storage data stored in the storage unit by a first-level read voltage.

[0020] In some embodiments, the peripheral circuitry is configured to acquire a first read voltage and a preset threshold.

[0021] In some embodiments, the peripheral circuitry is configured to: obtain a first read voltage and a preset threshold from the memory cell when the memory device is powered on; both the first read voltage and the preset threshold are fixed values.

[0022] In some embodiments, the peripheral circuit is configured to: when the memory device is powered on, obtain the initial value of the first read voltage and the initial value of the preset threshold from the memory cell respectively; modify the initial value of the first read voltage and / or the initial value of the preset threshold by setting a feature command to obtain the first read voltage and the preset threshold.

[0023] In some embodiments, multiple memory cells coupled to word lines form multiple physical pages; the multiple physical pages contain multiple target physical pages; the peripheral circuitry is configured to: apply a first read voltage to a selected word line among the multiple word lines; for each target physical page among the multiple target physical pages coupled to the selected word line, determine the read interference state of the corresponding target physical page based on the statistical results corresponding to the corresponding target physical page under the first read voltage; after completing the read interference state assessment of all target physical pages coupled to the selected word line, float the selected word line.

[0024] In some embodiments, the statistical result includes a first quantity; the peripheral circuit is configured to: read the stored data of the physical page under a first read voltage to obtain a first result; adjust the first read voltage to obtain an adjusted read voltage, and read the stored data of the physical page under the adjusted read voltage to obtain a second result; perform logical operations on the first result and the second result to obtain a third result; and count the number of bits in the third result that represent the second result being flipped compared to the first result to obtain a first quantity.

[0025] In some embodiments, the peripheral circuitry includes: a first latch, a second latch, and a third latch; the first latch is configured to store a first result; the second latch is configured to store a second result; and the third latch is configured to store a third result.

[0026] Fourthly, embodiments of this application provide a memory system comprising: one or more memory devices as described in embodiments of this application; and a memory controller coupled to and controlling the memory devices.

[0027] In some embodiments, the memory controller is configured to: during a data inspection of the memory device, send a second instruction, the second instruction indicating the acquisition of the read interference status of a physical page; the memory device is configured to: in response to the second instruction, acquire the statistical results corresponding to the physical page under a first read voltage, determine whether the read interference status of the physical page is poor based on the relationship between the statistical results and a preset threshold; and send information including the read interference status of the physical page to the memory controller; the memory controller is further configured to: perform a data shifting operation on the physical page if the read interference status of the physical page is poor.

[0028] In some embodiments, the memory controller is configured to: during a data inspection of the memory device, send a third instruction, the third instruction instructing the acquisition of the read interference status of all target physical pages coupled to the word line; the memory device is configured to: in response to the third instruction, acquire the statistical result corresponding to each target physical page coupled to the word line under a first read voltage, determine whether the read interference status of each target physical page is poor based on the relationship between the statistical result and a preset threshold; and send information including the read interference status of all physical pages coupled to the word line to the memory controller; the memory controller is further configured to: perform a data shifting operation on all target physical pages coupled to the word line if the read interference status of all target physical pages coupled to the word line is poor.

[0029] Fifthly, embodiments of this application provide an operation method for a memory system. The operation method includes: during a data inspection of the memory device of the memory system, the memory controller of the memory system acquires statistical results corresponding to a physical page under a first read voltage; the statistical results include a first number of bits that flipped in two read results (one under the first read voltage and the other under a read voltage with a voltage difference less than a preset voltage), and / or a second number of bits that failed to be read under the first read voltage; the average value of a threshold voltage range corresponding to the intermediate storage state of the physical page where the first read voltage is less than the threshold voltage range; and determining the read interference state of the physical page based on the statistical results.

[0030] Sixthly, embodiments of this application provide an operation method for a memory system. The operation method includes: during a data inspection process performed on a memory device of the memory system by the memory controller, the memory device acquires statistical results corresponding to a physical page under a first read voltage; the statistical results include a first number of bits that flipped in two read results (one under the first read voltage and the other under a read voltage with a voltage difference less than a preset voltage), and / or a second number of bits that failed to be read under the first read voltage; the average value of a threshold voltage range corresponding to a storage state where the first read voltage is less than the middle storage state of the physical page; and determining the read interference state of the physical page based on the statistical results.

[0031] In a seventh aspect, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the operation method provided in embodiments of this application.

[0032] In various embodiments of this application, a first number of bits that flipped in two reading results of a physical page under a specific first reading voltage (the first reading voltage is less than a second preset reading voltage) and a reading voltage with a voltage difference from the first reading voltage less than the preset voltage, and / or a second number of bits that failed to be read at the first reading voltage, are obtained. This obtained data is compared with a preset threshold to determine the data interference state of the physical page. The direct comparison method in this application is simple and does not require complex decoding processes such as Low-Density Parity-Check (LDPC) to quickly determine the data interference state of the physical page. Furthermore, the first and / or second numbers are statistical results, which occupy less storage space and do not require a large amount of input / output (I / O) transmission, resulting in low power consumption during the judgment process. Attached Figure Description

[0033] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0034] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of this application;

[0035] Figure 2A This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of this application;

[0036] Figure 2B This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of this application;

[0037] Figure 3A This is a top view schematic diagram of the distribution of memory cells coupled to each word line according to an embodiment of this application;

[0038] Figure 3B This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of this application;

[0039] Figure 4 This is a cross-sectional schematic diagram of a storage cell array including storage strings according to an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of an exemplary memory controller including a memory cell array and peripheral circuitry according to an embodiment of this application;

[0041] Figure 6A schematic diagram of the read operation flow of a memory system is shown in one embodiment of this application;

[0042] Figure 7 This is a schematic diagram of an exemplary composition structure of a memory system provided in an embodiment of this application;

[0043] Figure 8 A schematic diagram of the threshold voltage distribution corresponding to each storage state of an exemplary TLC provided in an embodiment of this application;

[0044] Figure 9 A schematic diagram of an exemplary data read interference state judgment operation flow of a memory controller provided in an embodiment of this application;

[0045] Figure 10 A schematic diagram of the threshold voltage distribution corresponding to each memory state in an exemplary TLC experiencing read interference problems, as provided in an embodiment of this application. Figure 1 ;

[0046] Figure 11 A schematic diagram (2) showing the threshold voltage distribution corresponding to each storage state in an exemplary TLC experiencing read interference problems, provided in an embodiment of this application.

[0047] Figure 12 A schematic diagram of an exemplary memory device including multiple word lines and multiple bit lines provided for an embodiment of this application;

[0048] Figure 13 A schematic diagram illustrating the interaction between a memory controller and a memory device in a memory system provided according to an embodiment of this application;

[0049] Figure 14 A schematic diagram illustrating an exemplary implementation process of a data inspection operation related to read interference, provided as an embodiment of this application;

[0050] Figure 15 A schematic flowchart illustrating an exemplary data inspection process for testing read interference, provided as an embodiment of this application;

[0051] Figure 16 This application provides an embodiment of an operational method in which a memory system is configured to perform an operation. Figure 1 ;

[0052] Figure 17 This is a schematic diagram of the implementation flow of an operation method in which a memory system is configured to perform an embodiment of this application;

[0053] Figure 18 This is a schematic diagram of the composition structure of a storage medium provided in an embodiment of this application. Detailed Implementation

[0054] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0056] Furthermore, the accompanying drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0057] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “ / the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0059] The memory devices in the embodiments of this application include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0060] Figure 1A block diagram of an exemplary system 100 with a memory controller according to some aspects of this application is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory controllers 104 and 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory controller 104.

[0061] According to some embodiments, memory controller 106 is coupled to memory controller 104 and host 108 and is configured to control memory controller 104. Memory controller 106 can manage data stored in memory controller 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0062] In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment in a solid state disk (SSD) or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0063] The memory controller 106 can be configured to control the operation of the memory controller 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory controller 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory controller 104.

[0064] The memory controller 106 may also perform any other suitable function, such as formatting the memory controller 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0065] Memory controller 106 and one or more memory controllers 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, memory system 102 can be implemented and packaged into different types of end electronic products.

[0066] In such Figure 2AIn one example shown, memory controller 106 and a single memory controller 104 can be integrated into memory card 202. Memory card 202 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 202 may also include a connection between memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0067] In such Figure 2B In another example shown, memory controller 106 and multiple memory controllers 104 may be integrated into SSD 206. SSD 206 may also include interfaces for connecting SSD 206 to a host computer (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0068] Figure 3A An exemplary schematic diagram of a storage cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3A As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each pair of memory cell rows is separated by a gate isolation structure and a top-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple blocks, and multiple second gate isolation structures can divide the blocks into multiple finger regions. A top-select gate isolation structure located in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two slits. Different slits can be selected or deselected by applying a selection voltage or deselection voltage to their respective top selection gates (TSGs). Figure 3A The storage block shown contains 6 storage chips. In actual applications, the number of storage chips in a storage block is not limited to this.

[0069] In some embodiments, each memory block may be coupled with multiple word lines, and each word line, coupled with multiple memory cells of a memory slice, constitutes one or more physical pages, wherein the number of physical pages is related to the number of bits of memory contained in the memory cells. For example, Figure 3AIn each memory chip, all memory cells (with a storage bit width of one bit) are coupled together to form a physical page.

[0070] Figure 3B A schematic circuit diagram of an exemplary memory controller 300, including peripheral circuitry, according to some aspects of this application is shown. The memory controller 300 may be... Figure 1 An example of a memory controller 104 is provided. The memory controller 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0071] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell, TLC), four bits per cell (also referred to as a quad-level cell, QLC), five bits per cell (also referred to as a penta-level cell, PLC), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0072] It should be noted that the storage state mentioned here is the same as the storage state of the storage cell in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has two storage states (i.e., two memory states), which include one programming state and one erase state. Another example is an MLC type storage cell with four storage states, including one erase state and three programming states. Yet another example is a TLC type storage cell with eight storage states, including one erase state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, including one erase state and fifteen programming states.

[0073] like Figure 3B As shown, each memory string 308 may include a lower selection transistor (BSG) 310 (also known as a source-side selection transistor) at its source end and an upper selection transistor (TSG) 312 (also known as a drain-side selection transistor) at its drain end. BSG 310 and TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0074] like Figure 3BAs shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some implementations, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0075] refer to Figure 3B Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0076] Figure 4 A cross-sectional schematic diagram of an exemplary memory cell array 301, including a memory string 308 exemplified by NAND, is shown according to some aspects of this application. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0077] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0078] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0079] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0080] Return to reference Figure 3BThe peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0081] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory cell array 301 (write data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory strings 308 by applying a bit line voltage obtained from voltage generator 510.

[0082] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages obtained from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to obtain word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0083] Control logic 512 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0084] In memory devices, data is stored in floating-gate transistors, with the floating gate surrounded by insulators on the top and bottom.

[0085] The principle behind the data retention problem is that, over time, electrons stored in the floating gate can "escape" through the insulating layer under the influence of the intrinsic electric field. This escape becomes increasingly easier as the insulation of the insulator deteriorates (due to increased write cycles). When the number of escaped electrons reaches a certain threshold, it causes a bit "0" to flip to a bit "1". When the number of bit flips exceeds the error correction capability, user data loss occurs.

[0086] The principle behind the read disturb problem is as follows: When reading data, in order to ensure that other floating gate transistors are turned on, a conduction voltage needs to be applied to other unselected word lines. This causes these transistors to be slightly "programmed." As the number of reads increases, more and more electrons enter the floating gate transistors, which may eventually lead to bit flips (flipping from 1 to 0). When the number of flipped bits exceeds the error correction capability, user data loss will occur.

[0087] While both data retention and read interference problems can cause bit flips in the data stored in a memory device, the directions of these bit flips are opposite: read interference injects additional electrons, causing a bit to flip from "1" to "0"; while data retention results in the loss of electrons, causing a bit to flip from "0" to "1". In some embodiments, from the perspective of the threshold voltage distribution, read interference shifts the threshold voltage distribution at least partially to the right, while data retention shifts the threshold voltage distribution at least partially to the left.

[0088] When the threshold voltage shifts significantly to the left or right, the probability of read errors is very high when reading data from the storage unit using the original read voltage. In this case, error correction codes are used for error correction. The error correction codes involved in the embodiments of this application include, but are not limited to, Low Density Parity-check Code (LDPC). The following description uses LDPC as an example only.

[0089] Figure 6 A schematic diagram illustrating an exemplary read operation flow of a memory system is shown. Combined with... Figure 6 As shown, when the memory controller controls the memory device to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read operation fails, it performs a read retry operation. If the read retry operation fails, it performs a soft decode operation (soft decision decoding). If the soft decode operation fails, it performs a Redundant Array of Independent Disks (RAID) operation. If the RAID operation fails, the read operation stops and fails because it cannot correct errors. The memory controller sends a read fail signal to the host 108.

[0090] In some implementations, rereading can typically be performed by querying a retry table provided by the manufacturer. The rereading operation is essentially an error correction mechanism. The retry table stores the read offset voltages corresponding to different conditions (such as data retention, read interference, etc.) to provide a reference voltage for reading data. By querying the retry table, the system attempts to read each memory cell again at a read voltage that deviates from the normal threshold voltage, and then uses an error correction algorithm to correct the error and attempt to read the data correctly.

[0091] Data in memory devices needs to avoid Uncorrectable Error Correction Code (UECC) errors, or data error recovery failures, caused by read interference. This requires data inspection (or background inspection, typically performed when the memory system is idle). However, due to the large number of physical pages in a memory device, it's difficult to inspect the read status of all physical pages; only sampling inspection is possible. With the rise of flash memory products such as QLCs and PLCs, read operation times have become increasingly longer, leading to higher inspection costs. Quickly identifying read interference presents a significant challenge. Furthermore, when scanning for read interference, the corresponding entry in the reread table is typically used. If a piece of data experiences a data retention problem but not a read interference problem, the inspection will show a reread operation failure, thus mistakenly triggering garbage collection (GC). Here, garbage collection involves reading valid data from one or more memory blocks and rewriting it to other memory blocks.

[0092] In response to one or more of the aforementioned problems, in a first aspect, embodiments of this application propose a memory controller, such as... Figure 7 As shown, the memory controller 106 is coupled to at least one memory device 104. The memory device 104 includes multiple word lines, each word line being coupled to multiple memory cells, and the multiple memory cells forming at least one physical page. The memory controller 106 includes: an interface 1060; and a processor 1063, coupled to the interface 1060 and configured to: acquire statistical results corresponding to the physical page under a first read voltage; the statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage where the voltage difference from the first read voltage is less than a preset voltage, and / or a second number of bits that failed to read the physical page under the first read voltage; the average value of the threshold voltage range corresponding to the middle storage state of the physical page where the first read voltage is less than the middle storage state; and determine the read interference state of the physical page based on the statistical results.

[0093] Figure 7 A schematic diagram of the composition structure of a memory system is shown, illustrating a memory controller. (For example...) Figure 7As shown, the memory controller 106 is coupled to the memory device 104 and is used to control the memory device 104 to perform read, write, erase, and other operations. The memory controller 106 may include a processor 1063; the processor 1063 is used to control the memory controller 106 and the memory device 104 as a whole. In some specific embodiments, the processor 1063 may include one or more units with logic operation capabilities, such as a single-core or multi-core central processing unit (CPU) and / or a microcontroller unit (MCU).

[0094] In some embodiments, the memory controller 106 may further include an interface 1060 for data interaction with external devices. In some specific embodiments, the interface 1060 may include a host interface (I / F) 1061 and a memory interface (I / F) 1062; wherein, the host interface 1061 is a connection interface between the host 108 and the memory controller 106, allowing the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104, and is used to implement data transfer between the memory controller 106 and the memory device 104.

[0095] In some embodiments, the memory controller 106 may further include an error correction module 1064, a cache 1067, a garbage collection (GC) module 1068, and a bus 1069. The error correction module 1064 may further include an encoding unit 1065 and a decoding unit 1066; the encoding unit 1065 encodes the data to be stored to obtain verification data, and the decoding unit 1066 decodes the verification data to detect and correct possible erroneous data during data transmission. The cache 1067 is used to cache data. In some specific embodiments, the cache 1067 may be a volatile memory device with relatively fast read / write speeds, such as Static Random-Access Memory (SRAM) and / or Dynamic Random-Access Memory (DRAM). The garbage collection module 1068 is used to read out valid data from some storage blocks, rewrite it, and then mark these storage blocks to obtain new spare storage blocks after the storage space of the memory device reaches a certain threshold.

[0096] In some embodiments, the memory controller 106 may also include other modules not listed, such as a wear leveling module, a bad block management module, an SLC cache module, etc.

[0097] In some embodiments, the memory device may include NAND flash memory. The structure of the memory device can be referred to the foregoing. Figure 3B This will not be elaborated upon here.

[0098] In some embodiments, the memory device includes a plurality of memory blocks, each memory block may be coupled with a plurality of word lines, and each word line may be divided into multiple segments by the aforementioned gate isolation structure (first gate isolation structure or second gate isolation structure) and upper select gate isolation structure. Figure 3A The memory chips shown can be selected or deselected by applying a selection voltage or deselection voltage to their respective top selection gates (TSGs). Multiple memory cells coupled to a memory chip on each word line constitute one or more physical pages, where the number of physical pages is the same as the number of bits of memory contained in the memory cell. For example, if the memory cell is an SLC, multiple memory cells coupled to a memory chip on each word line constitute one physical page; if the memory cell is an MLC, multiple memory cells coupled to a memory chip on each word line constitute two physical pages; if the memory cell is a TLC, multiple memory cells coupled to a memory chip on each word line constitute three physical pages, namely the next page (LP), the middle page (MP), and the previous page (UP); and if the memory cell is a QLC, multiple memory cells coupled to a memory chip on each word line constitute four physical pages.

[0099] In some embodiments, the memory device includes multiple memory blocks, each memory block may be coupled with multiple word lines, and all memory cells coupled to each word line constitute one or more physical pages, wherein the number of physical pages is the same as the number of bits of memory contained in the memory cell. For example, if the memory cell is an SLC, multiple memory cells coupled to each word line constitute one physical page; if the memory cell is a TLC, multiple memory cells coupled to each word line constitute three physical pages. It should be noted that in this embodiment, instead of the aforementioned division into memory regions and memory slices, the top select gates (TSGs) corresponding to each word line are all connected together.

[0100] In this embodiment, the processor 1063 obtains the statistical results corresponding to the physical page under the first read voltage, and determines the read interference state of the physical page based on the statistical results, so as to provide data support for whether to move the data in the physical page.

[0101] Here, read interference status can be understood as the degree of progress of read interference on the data stored in the physical page, which can be divided into two or more levels. In some specific embodiments, this degree of progress can be divided into two levels: poor and non-poor.

[0102] In some embodiments, the processor 1063 is further configured to: determine whether the read interference state of a physical page is poor based on the relationship between statistical results and a preset threshold; and perform a data migration operation on the physical page if the read interference state of the physical page is determined to be poor.

[0103] Here, based on the aforementioned principle of read interference, the degree of read interference progression can be divided according to the electron injection situation. Data read interference can include a "poor" or first read interference state and a "non-poor" or second read interference state. The amount of electrons injected in the second read interference state (non-poor) is less than the amount of electrons injected in the first read interference state. That is to say, the electron injection situation in the first read interference state (poor) is more severe. In some specific embodiments, when the read interference state of a physical page is the first read interference state (poor), a data migration operation is performed on the data stored in that physical page.

[0104] In some embodiments, the processor 1063 is further configured to: determine that the read interference status of the physical page is non-degraded, and not perform a data migration operation on the physical page, that is, not take further operations on the storage unit where the physical page is located due to data degradation caused by read interference during the current data inspection.

[0105] In some specific embodiments, the processor 1063 is configured to: determine the read interference status of a physical page based on the absolute values ​​of statistical results and a preset threshold. Here, the determined read interference status can also be the degree of progress of read interference of the data stored in the physical page. This degree of progress can be divided into multiple levels. For example, the aforementioned "inferior" and "non-inferior" can correspond to two of these levels, and there can be more other intermediate levels. The subsequent operations corresponding to one or more different levels can be different. For example, if an intermediate level between "inferior" and "non-inferior" is defined, then physical pages determined to be at this intermediate level can be marked as key inspection targets and prioritized for inspection in subsequent data inspections.

[0106] It should be noted that, for the case where storage slices are divided, the minimum processing object for read interference judgment involved in the embodiments of this application can be the data stored in multiple storage cells coupled to a single word line and a single storage slice; for the case where storage slices are not divided, the minimum processing object for read interference judgment involved in the embodiments of this application can be the data stored in all storage cells coupled to a single word line.

[0107] Taking the case of partitioned memory chips as an example, for SLC, multiple memory cells coupled to one memory chip by one word line correspond to one physical page. In this case, obtaining the statistical result of the physical page under the first read voltage is the statistical result of that physical page under the first read voltage. For TLC, multiple memory cells coupled to one memory chip by one word line correspond to three physical pages. In this case, obtaining the statistical result of the physical page under the first read voltage is the target physical page among the three physical pages (the memory bits used to distinguish between the first and second memory states, as discussed later, correspond to physical pages). Figure 8 (See the next page of the example) for the statistical results corresponding to the first read voltage. It should be noted that the target physical page here is related to the set voltage value of the first read voltage, and is not a fixed physical page.

[0108] In other words, in this embodiment of the application, obtaining the statistical results corresponding to the physical page under the first read voltage can specifically involve obtaining the statistical results corresponding to the target physical page under the first read voltage among at least one physical page corresponding to a word line. For an SLC without memory chips, the physical page corresponding to a word line is the target physical page; for a memory ternary array with memory chips and multiple memory bits, the number of physical pages corresponding to a word line is the product of the number of memory chips and the number of memory bits, and the word line corresponds to the same number of target physical pages as the number of memory chips.

[0109] As previously mentioned, from the threshold voltage distribution diagram, read interference causes at least a partial rightward shift in the threshold voltage distribution. In some specific implementations, read interference shifts the portion of the threshold voltage distribution in lower storage states to the right, while the portion in higher storage states shifts to the right only slightly, or not at all. In some specific implementations, read interference causes a certain degree of rightward shift in the threshold voltage distribution for all storage states. It is understandable that, since lower storage states correspond to fewer electrons, when the injection amount is constant, the change caused by the injection amount to the storage states corresponding to the smaller number of electrons is more significant; that is, the rightward shift of the threshold voltage distribution in lower storage states is more pronounced. Based on this, in determining the state of read interference in this embodiment, the statistical results obtained are based on the first read voltage, where the voltage value is less than the average of the threshold voltage range corresponding to the middle storage states of the physical page.

[0110] In some specific embodiments, the storage unit may include N bits (N is a positive integer greater than 1), and N storage bits correspond to 2^N bits. N There are several memory states, and the average threshold voltage range corresponding to the middle memory state of a physical page can be 2. NThe midpoint of the threshold voltage range corresponding to a certain storage state located in the middle of the -1 order read voltage. For example, taking TLC as an example, the storage cell includes 3 storage bits, and the 3 storage bits correspond to 8 storage states (in order of increasing threshold voltage distribution: state 0 P0, state 1 P1, ..., state 7 P7).

[0111] Here, the first read voltage is less than the average of the threshold voltage range corresponding to the middle storage state of the physical page, meaning the first read voltage falls within the threshold range corresponding to a lower storage state. In some specific embodiments, the first read voltage is less than the average of the total threshold voltage range corresponding to the multiple storage states where the word-line coupled memory cells can be programmed.

[0112] In some specific embodiments, the multiple storage states of a physical page include a first storage state and a second storage state with the lowest average threshold voltage range; the first threshold voltage is the average threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average threshold voltage range corresponding to the second storage state when the physical page is writing data; and the first read voltage is between the first threshold voltage and the second threshold voltage.

[0113] Here, the multiple storage states of a physical page can be understood as multiple storage states that a storage unit can be programmed into. Taking TLC as an example, such as... Figure 8 As shown, the multiple storage states of a physical page are P0 to P7. The first storage state and the second storage state can be understood as the P0 state and the P1 state, respectively. The first threshold voltage can be understood as the median voltage in the threshold voltage range of the P0 state. Figure 8 The dashed line in the P0 state corresponds to the threshold voltage. The second threshold voltage can be understood as the median voltage in the threshold voltage range of the P1 state. Figure 8 The threshold voltage corresponding to the dashed line in state P1. The first read voltage needs to be located at the dashed line corresponding to the median of the threshold voltage in state P0 and the dashed line corresponding to the median of the threshold voltage in state P1. In some specific embodiments, the first read voltage can be located at the boundary between P0 and P1; or there can be a voltage range between P0 and P1, and the first read voltage can be located within that voltage range. For example, the first read voltage can be the median of the threshold voltage in state P0 and the median of the threshold voltage in state P1.

[0114] It should be noted that the memory states mentioned above in the description of the first and second read voltages are the memory states corresponding to the writing of data. The first and second memory states mentioned above are also the two lowest memory states corresponding to the writing of data, not the two lowest memory states corresponding to the read interference.

[0115] Here, the statistical results corresponding to the first read voltage may include a first number of bits that flipped in the two read results of the physical page under the first read voltage and under a read voltage where the voltage difference with the first read voltage is less than a preset voltage; and / or a second number of bits that failed to be read in the physical page under the first read voltage.

[0116] In some specific embodiments, the statistical results corresponding to the first read voltage may include a first number of bits that are flipped in two read results, one under the first read voltage and the other under a read voltage where the voltage difference from the first read voltage is less than a preset voltage.

[0117] Here, a reading voltage whose voltage difference from the first reading voltage is less than a preset voltage can be understood as a voltage near the first reading voltage. It should be noted that the voltage near the first reading voltage can be either higher or lower than the first reading voltage, as long as the difference is less than the preset voltage. In some specific embodiments, the preset voltage ranges from 6mV to 22mV; for example, the preset voltage can be 6mV, 11mV, 16mV, or 22mV.

[0118] In some embodiments, the memory controller further includes an interface coupled to the processor; the interface is configured to: receive statistical results corresponding to the physical pages transmitted from the memory device under a first read voltage; or, the interface is configured to: receive read results corresponding to the physical pages transmitted from the memory device under the first read voltage and a second read voltage, or read results corresponding to the first read voltage; the processor is configured to perform calculations and statistics on the read results to obtain statistical results.

[0119] In some specific embodiments, the read results at the first read voltage and its vicinity can be obtained separately, and an XOR operation can be performed on the two read results. The first quantity is obtained by counting the values ​​of "1" in the XOR operation result. The memory device acts as the execution entity to perform the read operation at the first read voltage and its vicinity to obtain the read results; the XOR operation and the count are performed by the memory device or the memory controller. In subsequent embodiments, the method of the memory device obtaining the first quantity through internal hardware will be further elaborated.

[0120] In some specific embodiments, the statistical results corresponding to the first read voltage may include a second number of bits representing the physical page that failed to be read under the first read voltage.

[0121] Here, the bits that failed to read under the first read voltage can be understood as bits in the physical page whose threshold voltage is less than the first read voltage when the first read voltage is applied to the word line coupled to the physical page. In some specific embodiments, the displayed value of bits whose threshold voltage is less than the first read voltage can be "1", and the second count can be obtained by counting the number of "1"s read under the first read voltage. The memory device performs the read operation of the first read voltage as the execution subject to obtain the read result; the memory device or memory controller performs the count of "1"s as the execution subject.

[0122] It is understandable that having the memory device perform the XOR operation and the count of "1" directly, i.e., obtaining the first and second quantities directly from the memory device, can reduce the amount of data transmitted and save the transmission time between the memory device and the memory controller compared to directly sending the read results to the memory controller.

[0123] In some embodiments, when acquiring the first and second quantities, the read mode of the memory device needs to be set to Single Level Read (SLR). Here, in Single Level Read mode, the read operation reads one bit of stored data within a physical page. For example, when reading the next page LP, the first-order read voltage between P0 and P1 is used to determine whether the corresponding bit of stored data for the next page is 0 or 1.

[0124] In some embodiments, the storage unit includes multiple bits of storage data, and the multiple bits of storage data in the storage unit are read through multiple read voltages; the processor is configured to set the read mode to a single-level read mode before acquiring the statistical results corresponding to the physical page under the first read voltage; the single-level read mode includes reading at least one bit of storage data stored in the storage unit through a first-level read voltage.

[0125] Here, the first read voltage and the voltage near the first read voltage can both be understood as first-order read voltages. For a storage cell with multiple bits, when reading under the first read voltage and the voltage near the first read voltage, in single-level read mode, the data obtained is the data on one storage bit in the corresponding physical page.

[0126] In some specific embodiments, the statistical results corresponding to the first read voltage may include a first number of bits that flipped in two read results, one under the first read voltage and the other under a read voltage with a voltage difference less than a preset voltage, and a second number of bits that failed to be read in the first read voltage.

[0127] Here, the first quantity and the second quantity, and their acquisition methods, can be understood by referring to the aforementioned explanations and acquisition methods of the first quantity and the second quantity.

[0128] The preset thresholds differ depending on the statistical results obtained. When the obtained statistical result is a first quantity, the preset threshold used for comparison is the first threshold; when the obtained statistical result is a second quantity, the preset threshold used for comparison is the second threshold.

[0129] Both the first and second thresholds can be adjusted according to actual conditions, and both can vary within a certain range. It is understandable that setting the first and second thresholds more stringently allows data to be moved when the read interference situation is not too severe; setting them more leniently allows data to be moved at a very low frequency triggered by read interference.

[0130] In some embodiments, the first threshold may be the number of bits that flipped in two read results under the read voltage corresponding to the critical point of read interference-triggered soft decoding operation, and the value near the read voltage, as well as the value near the data. In some specific embodiments, the first threshold includes the number of bits that flipped in two read results under the second read voltage corresponding to the read interference-triggered soft decoding being enabled, and under a read voltage where the voltage difference from the second read voltage is less than a preset voltage.

[0131] Here, read interference causes the threshold voltage to shift to the right. In some embodiments, when the failure bit rate count of the read result reaches a preset count (e.g., 400), it is considered that hard decoding can no longer complete error correction and soft decoding needs to be enabled, i.e., the critical point for triggering soft decoding is reached. At this time, the voltage shifted to the right that causes the soft decoding to be triggered is derived. Then, the read voltage corresponding to the read interference triggering soft decoding operation is obtained by using the default read voltage and the voltage shifted to the right. The read voltage at this time is the second read voltage. Afterward, the read results under the second read voltage and the voltages near it can be obtained respectively, and the two read results are XORed. The first threshold is obtained by counting the value of "1" in the XOR result.

[0132] In some specific embodiments, the preset voltage ranges from 6mV to 22mV. For example, the preset voltage can be 6mV, 11mV, 16mV, or 22mV.

[0133] In some embodiments, the second threshold may be the sum of the number of bits at the read voltage corresponding to the critical point when the threshold voltage is less than the threshold voltage at which read interference triggers the soft decoding operation, and a value near that sum. In some specific embodiments, the second threshold includes the number of bits that failed to be read at the second read voltage corresponding to the read interference triggering soft decoding operation being enabled.

[0134] Here, the number of bits that failed to be read under the second read voltage is the sum of the bits whose threshold voltage is less than the second read voltage. In some embodiments, the second read voltage can also be obtained in the manner described above; then, the sum of the bits whose threshold voltage is less than the second read voltage is obtained.

[0135] The methods for obtaining the first quantity and the second quantity, as well as the setting principles for the first read voltage and the preset threshold (including the first and second thresholds), have been previously described. In some embodiments, the processor 1063 is configured to acquire the first read voltage and the preset threshold, respectively. Here, the first read voltage and the preset threshold can be fixed values; or they can be values ​​that can be adjusted according to the actual situation of the memory device. The first read voltage and the preset threshold can be acquired once when the memory controller is powered on, or they can be acquired as needed each time a trigger command is received. The various cases of the first read voltage and the preset threshold described above can be arbitrarily combined without conflict.

[0136] In some specific embodiments, the processor 1063 is configured to: when the memory controller is powered on, obtain a first read voltage and a preset threshold from the memory device, respectively; the first read voltage and the preset threshold are both fixed values.

[0137] Here, in accordance with the aforementioned setting principles, the first read voltage and the preset threshold can be stored in the memory device first, so that when the memory controller is powered on, they can be loaded from the memory device into the cache 1067 of the memory controller.

[0138] In some specific embodiments, the processor 1063 is configured to: when the memory controller is powered on, obtain the initial value of the first read voltage and the initial value of the preset threshold from the memory device, respectively; modify the initial value of the first read voltage and / or the initial value of the preset threshold by setting a feature command to obtain the first read voltage and the preset threshold.

[0139] Here, the setting feature command can directly configure the protocol on the memory device side. The memory device stores the initial value of the first read voltage and the initial value of the preset threshold, or the default value. If it is necessary to adjust the initial value of the first read voltage and / or the initial value of the preset threshold in the future, it can be adjusted through the setting feature command.

[0140] The following will explain in detail how to use the relationship between the first and / or second quantities included in the statistical results and the first and / or second thresholds included in the preset thresholds to determine the reading interference state.

[0141] In some embodiments, the preset threshold includes a first threshold and / or a second threshold; the processor is configured to determine that the read interference state of the physical page is poor (first read interference state) based on a first quantity being greater than the first threshold and / or a second quantity being greater than the second threshold.

[0142] In some embodiments, the processor is further configured to determine that the read interference state of the physical page is non-inferior (second read interference state) based on a first quantity being less than or equal to a first threshold or based on a second quantity being less than or equal to a second threshold.

[0143] Figure 9 A schematic diagram of an exemplary read interference state determination operation flow for a memory controller is shown. For example, as... Figure 9 As shown, when the memory controller performs data inspection on the memory device, especially during data scanning for read interference problems, the processor 1063 of the memory controller can execute steps S901 to S911.

[0144] Execution step S901: Start the process of reading the interference status judgment.

[0145] Next, step S902 is executed: obtain the first read voltage. The principles for setting and obtaining the first read voltage can be understood by referring to the preceding description.

[0146] Next, step S903 is executed: obtain a preset threshold M. Here, the obtained preset threshold M may include a first threshold M1 and / or a second threshold M2. The principles for setting and obtaining the preset threshold can be understood by referring to the preceding description.

[0147] Here, both the first read voltage and the preset threshold can be obtained from the cache 1067 of the memory controller. It should be noted that steps S902 and S903 can be performed with step S903 preceding step S902; or steps S902 and S903 can be executed together.

[0148] Next, step S904 is executed: enable single-level read mode. The specific read method of single-level read mode can be understood with reference to the preceding description. In some specific embodiments, before obtaining statistical results, the processor 1063 of the memory controller is configured to send a single-level read mode setting command to the memory device; the memory device 104 is configured to: enter single-level read mode in response to the mode setting command, and, in single-level read mode, obtain statistical results under a first read voltage.

[0149] Next, step S905 is executed: obtaining statistical result N. Here, the obtained statistical result N may include a first quantity N1 and / or a second quantity N2, and the obtained statistical result needs to correspond to the aforementioned preset threshold. The processor 1063 of the memory controller can obtain the statistical result N fed back by the memory device.

[0150] Next, step S906 is executed: the obtained statistical result N is compared with the preset threshold M.

[0151] Next, step S907 is executed: determine the relationship between the statistical result N and the preset threshold M.

[0152] When the statistical result N is greater than the preset threshold M, it indicates that the data stored in the physical page has experienced a relatively serious read interference problem. There is a high probability that the software decoding operation will fail, and a more complex error correction process needs to be entered. At this time, step S908 is executed: the data read interference in the physical page is judged to be inferior, i.e., the first read interference state.

[0153] When the statistical result N is less than or equal to the preset threshold M, it means that the read interference problem of the data stored in the physical page is still within an acceptable range. The probability of software decoding failure is low, and there is no need to enter a more complex error correction process. At this time, step S909 is executed: the read interference state of the data stored in the physical page is determined to be non-inferior, i.e., the second read interference state.

[0154] After executing step S908 or S909, step S910 is executed to return the test result, i.e., output the judgment result, for other control processes to make corresponding decisions. For example, the decision to trigger garbage collection, i.e., whether to perform data migration, is based on read interference. In some specific embodiments, the data migration operation is performed on the physical page based on the read interference state of the physical page as the first read interference state. In this way, during data inspection, only the states of the lowest two storage states need to be checked, which can avoid the situation of erroneous garbage collection triggered due to read interference.

[0155] After completing step S910, step S911 is executed to end the judgment process of reading interference status.

[0156] It should be noted that after garbage collection is triggered, the data in the storage unit where the physical page is located can be moved immediately, or the data in the storage unit where the physical page is located can be marked first, and then garbage collection can be performed together with the marked data in other locations at an appropriate time.

[0157] In some specific embodiments, the statistical result includes a first quantity, and the preset threshold includes a first threshold; the processor is configured to: determine that the physical page is in a poor state, i.e., a first read interference state, based on the first quantity being greater than the first threshold; and determine that the physical page is in a non-poor state, i.e., a second read interference state, based on the first quantity being less than or equal to the first threshold.

[0158] Figure 10 A schematic diagram illustrating the threshold voltage distribution for each storage state of a TLC is shown. It should be noted that... Figure 10 The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. The solid line curve represents the threshold voltage distribution of each memory state during data writing, while the dashed line curve represents the threshold voltage distribution of each memory state after read interference occurs. The following will combine... Figure 10 This embodiment details the specific read interference state judgment operation process. Specifically:

[0159] Step a1: Set the first read voltage to a certain intermediate position between the first storage state P0 and the second storage state P1 (e.g., ...). Figure 10 (The position of the example line with the dashed line).

[0160] Step a2: Set a comparison threshold. The comparison threshold can be a first threshold M1, which can be the number of bits that flipped in the two read results under the second read voltage and the voltage near the critical point when the read interference triggers the start of the soft decoding operation.

[0161] Step a3: Enable single-level read mode and set the read voltage for the read operation of the memory device to the first read voltage.

[0162] Step a4: Obtain the number of bits that flipped in the two read results under the first read voltage and its vicinity through circuit operation in the memory device or external statistics, i.e., the first quantity N1.

[0163] Step a5: Compare with the set first threshold. If the first quantity N1 is greater than the first threshold M1, the read interference state of the data stored in the physical page is determined to be inferior, i.e., the first read interference state, and garbage collection is triggered at this time. If the first quantity N1 is less than or equal to the first threshold M1, the read interference state of the data stored in the physical page is determined to be non-inferior, i.e., the second read interference state, and garbage collection is not required at this time.

[0164] Step a6: Return the test results. Here, the test results represent the determined read interference status.

[0165] In some specific embodiments, the statistical result includes a second quantity, and the preset threshold includes a second threshold; the processor is configured to: determine that the physical page is in a poor state, i.e., a first read interference state, based on the second quantity being greater than the second threshold; and determine that the physical page is in a non-poor state, i.e., a second read interference state, based on the second quantity being less than or equal to the second threshold.

[0166] Figure 11 A schematic diagram illustrating the threshold voltage distribution for each storage state of a TLC is shown. It should be noted that... Figure 11 The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. The solid line curve represents the threshold voltage distribution of each memory state during data writing, while the dashed line curve represents the threshold voltage distribution of each memory state after read interference occurs. The following will combine... Figure 11 This embodiment details the specific read interference state judgment operation process. Specifically:

[0167] Step b1: Set the first read voltage to a certain intermediate position between the first storage state P0 and the second storage state P1 (e.g., ...). Figure 11 (The position of the example line with the dashed line).

[0168] Step b2: Set a comparison threshold. The comparison threshold here can be a second threshold M2, which can be the sum of the number of "1"s on the left side of the second read voltage when the read interference triggers the start threshold of the soft decoding operation.

[0169] Step b3: Enable single-level read mode and set the read voltage for the read operation of the memory device to the first read voltage.

[0170] Step b4: Obtain the total number of "1"s to the left of the first read voltage, i.e., the second quantity N2, through circuit operations in the memory device or external statistics.

[0171] Step b5: Compare with the set second threshold. If the second quantity N2 is greater than the second threshold M2, the read interference state of the data stored in the physical page is determined to be inferior, i.e., the first read interference state, and garbage collection is triggered at this time. If the second quantity N2 is less than or equal to the second threshold M2, the data read interference of the data stored in the physical page is determined to be non-inferior, i.e., the second read interference state, and garbage collection is not required at this time.

[0172] Step b6: Return the test results. Here, the test results represent the determined read interference status.

[0173] In some specific embodiments, the statistical results include a first quantity and / or a second quantity, and the preset thresholds include a first threshold and a second threshold; the processor is configured to: determine that the physical page is in a poor state, i.e., a first read interference state, based on the first quantity being greater than the first threshold and the second quantity being greater than the second threshold; and determine that the physical page is in a non-poor state, i.e., a second read interference state, based on the first quantity being less than or equal to the first threshold or based on the second quantity being less than or equal to the second threshold.

[0174] In this embodiment, the specific operation process for determining the read interference state is as follows:

[0175] Step c1: Set the first read voltage to a certain intermediate position between the first storage state P0 and the second storage state P1 (e.g., ...). Figure 11 (The position of the example line with the dashed line).

[0176] Step c2: Set a comparison threshold. The comparison threshold can be a first threshold M1 and a second threshold M2. The first threshold can be the number of bits that flipped in the two read results under the second read voltage and the voltage near the critical point when the read interference triggers the soft decoding operation. The second threshold can be the sum of the number of "1"s on the left side of the second read voltage when the read interference triggers the soft decoding operation.

[0177] Step c3: Enable single-level read mode and set the read voltage for the read operation of the memory device to the first read voltage.

[0178] Step c4: Through circuit operation in the memory device, obtain the number of bits that flipped in the two read results under the first read voltage and the voltage near it, which is the first quantity N1 and the sum of the number of "1"s on the left side of the first read voltage, which is the second quantity N2.

[0179] Step c5: Compare the first quantity with the first threshold, and compare the second quantity with the second threshold. If the first quantity N1 is greater than the first threshold M1 and the second quantity N2 is greater than the second threshold M2, then the read interference state of the data stored in the physical page is determined to be inferior, i.e., the first read interference state, and garbage collection is triggered at this time. If the first quantity N1 is less than or equal to the first threshold M1 or the second quantity N2 is less than or equal to the second threshold M2, then the read interference state of the data stored in the physical page is determined to be non-inferior, i.e., the second read interference state, and garbage collection is not required at this time.

[0180] Step c6: Return the test results. Here, the test results represent the determined read interference status.

[0181] In various embodiments of this application, the read interference state of the physical page is determined by acquiring a first number of bits that flipped in two read results under a first read voltage and a read voltage with a voltage difference less than a preset voltage, and / or a second number of bits that failed to be read under the first read voltage. The acquired data is then compared with a preset threshold. The direct comparison method in this application is simple and does not require complex decoding processes such as LDPC to quickly determine the read interference state of the physical page. Furthermore, the acquired first and / or second numbers are statistical results, which occupy less storage space and do not require extensive I / O transfers. The power consumption of the judgment process is also low. Moreover, applying the scheme of this application to the inspection process only requires checking the states of the two lowest storage states, thus avoiding accidental garbage collection caused by read interference. This effectively solves the problem of long system-level read interference inspection time and effectively avoids accidental garbage collection operations.

[0182] Secondly, embodiments of this application propose a memory system 102, such as... Figure 7 The memory system 102 includes: one or more memory devices 104; and a memory controller 106 as provided in the embodiments of this application, which is coupled to and controls the memory devices 104.

[0183] In some embodiments, the composition of the memory system can be referenced. Figure 7 The memory controller 106 and memory device 104 included in the memory system 102 can be understood with reference to the preceding description, and will not be repeated here. In some specific embodiments, the memory system may include a solid-state drive.

[0184] In some embodiments, the memory controller 106 is configured to: send a first instruction during a data inspection of the memory device 104, the first instruction instructing the acquisition of statistical results of physical pages; the memory device 104 is configured to: in response to the first instruction, acquire the statistical results of physical pages and send information including the statistical results of physical pages to the memory controller 106; the memory controller 106 is further configured to: determine whether the read interference state of the physical page is poor based on the statistical results and a preset threshold; and perform a data migration operation on the physical page if the read interference state of the physical page is poor.

[0185] In this embodiment, during data inspection, the memory device acquires statistical results of physical pages under a first read voltage and transmits these results to the memory controller. The processor of the memory controller compares the statistical results with a preset threshold and determines the read interference state of the physical pages. Based on the read interference state determination, it decides whether to trigger a garbage collection (GC) operation. If the read interference state of a physical page is considered poor, a data migration operation is performed on the physical page. This embodiment of the application provides a simple, fast, and low-power method for determining the read interference state. By only checking the states of the two lowest memory states, it avoids accidental garbage collection triggered due to read interference, effectively solving the problem of long system-level read interference inspection time and effectively preventing accidental garbage collection operations.

[0186] In some specific embodiments, such as Figure 13 As shown, the memory controller 106 sends a first command to the memory device 104, and the memory device 104 responds to the first command by feeding back statistical results under the first read voltage.

[0187] Thirdly, embodiments of this application propose a memory device 104, which includes: multiple word lines; each word line coupled to multiple memory cells, the multiple memory cells forming at least one physical page; peripheral circuitry 302, coupled to the multiple word lines and configured to: acquire statistical results corresponding to the physical page under a first read voltage; the statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage where the voltage difference from the first read voltage is less than a preset voltage, and / or a second number of bits that failed to be read under the first read voltage; the average value of the threshold voltage range corresponding to the intermediate storage state of the physical page where the first read voltage is less than the threshold voltage range; and determine the read interference state of the physical page based on the statistical results.

[0188] It should be noted that this embodiment differs from the previous embodiments in that the statistical results are compared with a preset threshold and the read interference status of the physical page is determined by the peripheral circuit of the memory device (more specifically, the control logic of the peripheral circuit).

[0189] Here, the structure of the memory device 104 can be referred to the foregoing. Figure 3B This will not be elaborated upon here.

[0190] In some embodiments, the peripheral circuit is further configured to: determine whether the read interference state of the physical page is poor based on the relationship between statistical results and a preset threshold; the physical page whose read interference state is determined to be poor will be subject to a data migration operation.

[0191] In some embodiments, the preset threshold includes a first threshold and / or a second threshold; the peripheral circuit is configured to determine that the read interference state of the physical page is poor based on a first quantity being greater than the first threshold and / or a second quantity being greater than the second threshold.

[0192] In some embodiments, the peripheral circuitry is configured to determine that the read interference state of the physical page is non-inferior based on a first quantity being less than or equal to a first threshold or based on a second quantity being less than or equal to a second threshold.

[0193] In some embodiments, the first threshold includes the number of bits that flipped in two read results under the second read voltage corresponding to the start of read interference-triggered soft decoding and under the read voltage where the voltage difference with the second read voltage is less than a preset voltage; the second threshold includes the number of bits that failed to be read under the second read voltage corresponding to the start of read interference-triggered soft decoding.

[0194] In some embodiments, the multiple storage states of a physical page include a first storage state and a second storage state with the lowest average threshold voltage range; the first threshold voltage is the average threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average threshold voltage range corresponding to the second storage state when the physical page is writing data; and the first read voltage is between the first threshold voltage and the second threshold voltage.

[0195] In some embodiments, the storage unit includes multiple bits of storage data, and the multiple bits of storage data in the storage unit are read by multiple read voltages; the peripheral circuitry is configured to set the read mode to a single-level read mode before acquiring the statistical results corresponding to the physical page under the first read voltage; the single-level read mode includes reading at least one bit of storage data stored in the storage unit by a first-level read voltage.

[0196] Here, the first reading voltage, preset voltage, second reading voltage, first quantity, second quantity, first threshold, and second threshold involved in this embodiment can all be understood by referring to the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0197] In some embodiments, the peripheral circuitry is configured to acquire a first read voltage and a preset threshold.

[0198] Here, following the aforementioned setting principle, the first read voltage and the preset threshold can be stored in the memory cell of a designated area of ​​the memory device. The peripheral circuit of the memory device can directly obtain the first read voltage and the preset threshold from the memory cell of the designated area.

[0199] In some embodiments, the peripheral circuitry is configured to: obtain a first read voltage and a preset threshold from the memory cell when the memory device is powered on; both the first read voltage and the preset threshold are fixed values.

[0200] In some embodiments, the peripheral circuit is configured to: when the memory device is powered on, obtain the initial value of the first read voltage and the initial value of the preset threshold from the memory cell respectively; modify the initial value of the first read voltage and / or the initial value of the preset threshold by setting a feature command to obtain the first read voltage and the preset threshold.

[0201] In some embodiments, multiple memory cells coupled to each word line form multiple physical pages; the multiple physical pages include multiple target physical pages; the peripheral circuit is configured to: apply a first read voltage to a selected word line among the multiple word lines; for each target physical page among the multiple target physical pages coupled to the selected word line, determine the read interference state of the corresponding target physical page according to the statistical results corresponding to the corresponding target physical page under the first read voltage; after completing the read interference state of all target physical pages coupled to the selected word line, float the selected word line.

[0202] In some embodiments, multiple memory cells coupled to a memory chip on each word line constitute one or more physical pages. The number of physical pages formed by all memory cells coupled to each word line is related to the number of bits stored in the memory cell and the number of memory chips contained in the memory block. When the number of bits stored in a memory cell is multiple, multiple memory cells coupled to a memory chip on each word line constitute multiple physical pages, among which there is a target physical page; that is, each memory chip corresponds to one target physical page. Here, the target physical page is related to a set voltage value of the first read voltage and is not a fixed physical page. When the first read voltage involves a threshold range corresponding to the first and second memory states, the target physical page is the physical page corresponding to the memory bit used to distinguish between the first and second memory states, as described on the next page.

[0203] For example, if the storage cell is a TLC and the storage block contains 6 storage chips, then the number of physical pages formed by all storage cells coupled to each word line is 18, and 6 of these 18 physical pages are target physical pages corresponding to the 6 storage chips.

[0204] The embodiments of this application can realize the read interference state of all memory cell columns of an entire word line at one time. Figure 12 A schematic diagram of an exemplary memory device is shown, comprising multiple word lines and multiple top selection gates (TSGs), wherein one top selection gate (TSG) controls whether a corresponding string is selected. The following will be combined with... Figure 12 This embodiment details the specific read interference state judgment operation process. Specifically:

[0205] Step d1: Set the first reading voltage N.

[0206] Step d2: Set a preset threshold M for comparison. This preset threshold can be adjusted using the set feature command.

[0207] Step d3: Enable single-level read mode.

[0208] Step d4: Apply the set first reading voltage to the selected word line.

[0209] Step d5: Obtain the statistical results of the physical pages corresponding to the current memory chip (string) under the first read voltage, such as the first number N. At this time, the voltage applied to the TSG coupled to the current string is the selection voltage, and the voltage applied to the TSG coupled to the other strings is the deselection voltage.

[0210] Step d6: Compare N and M. If N > M, then the read interference state of the memory cell coupled to the current memory chip is inferior, i.e., the first read interference state, which can be recorded as "1"; otherwise, the read interference state of the current string is non-inferior, i.e., the second read interference state, which can be recorded as "0".

[0211] Step d7: While maintaining the application of the first read voltage on the selected word line, switch to the next string of the selected word line. For example, change the voltage applied to the TSG coupled to the current string from the selection voltage to the deselection voltage, change the voltage applied to the TSG coupled to the next string from the deselection voltage to the selection voltage, and keep the voltage applied to the TSG coupled to the remaining strings at the deselection voltage.

[0212] Step d8: Repeat steps d5-d7 to obtain the reading interference status of all strings of the selected character line.

[0213] Step d9: Make the selected text line float.

[0214] Step d10: Return the test results. Here, the test results represent the read interference status of all strings determined by the selected character line.

[0215] In some embodiments, if the read interference state of the string determined by an entire word line has both "1" and "0", the entire word line can return "1" as long as there is "1". In other words, the data of the memory cells coupled to the entire word line need to be moved.

[0216] In some embodiments, if the read interference state of the strings included in an entire word line is both "1" and "0", a read interference state map of the entire word line can be created to provide detailed feedback on the read interference state of all strings. Finally, a data migration can be performed based on the corresponding algorithm.

[0217] In some embodiments, the statistical result includes a first quantity; the peripheral circuit is configured to: read the stored data of the physical page under a first read voltage to obtain a first result; adjust the first read voltage to obtain an adjusted read voltage, and read the stored data of the physical page under the adjusted read voltage to obtain a second result; perform logical operations on the first result and the second result to obtain a third result; and count the number of bits in the third result that represent the second result being flipped compared to the first result to obtain a first quantity.

[0218] In some specific embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch; the first latch is configured to store a first result; the second latch is configured to store a second result; and the third latch is configured to store a third result.

[0219] Here, the execution entity generating the first quantity is a memory device. The memory device can generate the first quantity using latches in its page cache. Specifically, the first result under the first read voltage is stored in the first latch; the second result under the read voltage after the first read voltage is adjusted according to a preset step size (here, the preset step size can be slightly smaller than the aforementioned preset voltage, such as 5mV to 20mV; for example, the preset step size can be 5mV, 10mV, 15mV, or 20mV) is stored in the second latch; and the first result and the second result are XORed using a third latch to obtain the first quantity. The first quantity can be directly used by the peripheral circuit, or the first quantity can be cached in a cache latch first, and then sent from the cache latch to the memory controller.

[0220] In this way, the read data (first result) under the first read voltage can be directly used and stored in the page cache. This data is XORed with the read data (second result) under a voltage near the first read voltage in the page cache. No additional operations or additional cache space are required, making the solution simple.

[0221] In this embodiment, the progression of data read interference in the memory cell of the memory device is quickly determined through circuit operations (page cache operations) to determine whether GC should be triggered. The memory device quickly obtains the number of flips between two read results under the first read voltage and its vicinity through circuit operations, and then compares it with a preset threshold. If it is greater than the preset threshold, the read interference state is determined to be the first read interference state, and GC needs to be triggered; otherwise, it is determined to be the second read interference state, and GC does not need to be triggered. In this way, the speed of determining the state of read interference is greatly improved (taking QLC as an example, the time consumed is reduced from about 100us to about 50us). At the same time, since the amount of data interaction is small, the power consumed in the whole process is very small, which helps the system reduce power consumption.

[0222] Fourthly, embodiments of this application provide a memory system 102, which includes: one or more memory devices 104 provided in this application; and a memory controller 106, which is coupled to and controls the memory devices 104.

[0223] In some embodiments, the composition of the memory system can be referenced. Figure 7 The memory controller 106 and memory device 104 included in the memory system 102 can be understood with reference to the preceding description, and will not be repeated here. In some specific embodiments, the memory system may include a solid-state drive.

[0224] It should be noted that the memory system involved in this embodiment differs from the memory system involved in the previous embodiments in that: in the memory system involved in the previous embodiments, the memory controller performs the comparison of statistical results with a preset threshold and the determination of the read interference state of physical pages; in the memory system involved in this embodiment, the peripheral circuit of the memory device performs the comparison of statistical results with a preset threshold and the determination of the read interference state of physical pages.

[0225] In some embodiments, the memory controller 106 is configured to: during a data inspection of the memory device, send a second instruction, the second instruction indicating the acquisition of the read interference status of a physical page; the memory device 104 is configured to: in response to the second instruction, acquire the statistical results corresponding to the physical page under a first read voltage, determine whether the read interference status of the physical page is poor based on the relationship between the statistical results and a preset threshold; and send information including the read interference status of the physical page to the memory controller 106; the memory controller 106 is further configured to: perform a data migration operation on the physical page if the read interference status of the physical page is poor.

[0226] In this embodiment of the application, during the data inspection process, the memory device is used to obtain the statistical results of a physical page of a word line under the first read voltage, and to compare the statistical results with a preset threshold and determine the read interference state of the physical page. The determination results are sent to the memory controller, and the memory controller decides whether to trigger GC operation based on the determination results.

[0227] In some embodiments, the memory controller 106 is configured to: during a data inspection of the memory device, send a third instruction, the third instruction instructing the acquisition of the read interference status of all physical pages coupled to the word line; the memory device 104 is configured to: in response to the third instruction, acquire statistical results corresponding to all target physical pages coupled to the word line under a first read voltage, determine whether the read interference status of the target physical pages is poor based on the relationship between the statistical results and a preset threshold; and send information including the read interference status of all target physical pages coupled to the word line to the memory controller 106; the memory controller 106 is further configured to: perform a data migration operation on all target physical pages coupled to the word line if all target physical pages coupled to the word line are poor.

[0228] In other words, based on the fact that all target physical pages coupled to the word line are inferior, a data migration operation is performed on all memory cells coupled to the word line.

[0229] In this embodiment of the application, during the data inspection process, the memory device is used to obtain the statistical results of all target physical pages of the word line under the first read voltage, and to compare the statistical results with a preset threshold and determine the read interference status of the physical pages. The determination results are sent to the memory controller, and the memory controller decides whether to trigger GC operation based on the determination results.

[0230] In some specific embodiments, such as Figure 13 As shown, the memory controller 106 sends a second or third command to the memory device 104, and the memory device 104 responds to different commands by reporting different levels of data read interference status.

[0231] Figure 14 This is a schematic diagram illustrating an exemplary implementation process for a data inspection operation related to read interference, provided as an embodiment of this application. Figure 14The diagram illustrates the Flash Translation Layer (FTL), Flash Control Layer (FCL), and the flash memory itself. The FTL primarily translates or maps the host logical address space to the flash physical address space. It also handles issues specific to flash memory characteristics, such as garbage collection, bad block management, wear leveling, read interference handling, and data retention. The FCL connects the FTL and the flash memory, managing the data stored in the flash. The read interference data inspection process includes: the FTL translates the host logical address space to the flash physical address; the FCL sends the physical address of the flash memory to be inspected to the flash memory; the flash memory feeds back the statistical result N under the first read voltage to the FCL; the FCL compares the statistical result N with a preset threshold M; if N > M, the corresponding physical address is fed back to the FTL, and the FTL adds this physical address to the garbage collection task.

[0232] It should be noted that the FTL and FLC can be located inside the memory controller; or the FTL can be located on the host side and the FLC can be located in the memory device (flash memory).

[0233] Figure 15 This is a schematic flowchart illustrating an exemplary data inspection process for testing read interference, provided as an embodiment of this application. Figure 15 As shown, perform the following steps:

[0234] Step e1: Fill the disk. Here, filling the disk can be understood as filling all the storage space in the memory device of the memory system with data.

[0235] Step e2: Repeatedly read the same logical block address (LBA). Here, repeatedly reading the same logical block address can shorten the time when read interference problems occur.

[0236] Step e3: Power-on Idle. Here, power-on Idle can be understood as powering on the memory system and performing the data inspection operation regarding read interference provided in the embodiments of this application when the memory system is in an idle state.

[0237] Step e4: Trace detection. Here, the trace detection log can be understood as the event log of the tracer at least during the data inspection operation.

[0238] In the detection of step e4, it can be found that in the whole process: 1. SLR is enabled, and after the read command (e.g., 00h_addr_30h) is issued, there is not a large amount of data transmission on the IO bus; 2. The duration of the R / B pin being busy is less than the duration of a normal read operation; 3. Some data may be moved to other locations later (when reading these data, the physical location corresponding to these data has changed before and after the data inspection).

[0239] Fifthly, embodiments of this application propose an operation method for a memory controller, wherein the memory controller is coupled to at least one memory device, the memory device including multiple word lines and multiple memory cells coupled to each word line, the multiple memory cells forming at least one physical page; the method includes: acquiring statistical results corresponding to the physical page under a first read voltage; the statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage where the voltage difference from the first read voltage is less than a preset voltage, and / or a second number of bits that failed to be read under the first read voltage; the average value of a threshold voltage range corresponding to the middle storage state of the physical page where the first read voltage is less than the first read voltage; and determining the read interference state of the physical page based on the statistical results.

[0240] In some embodiments, determining the read interference status of a physical page based on statistical results includes: determining whether the read interference status of the physical page is poor based on the relationship between the statistical results and a preset threshold; the method further includes: performing a data migration operation on the physical page based on the determination that the read interference status of the physical page is poor.

[0241] In some embodiments, the preset threshold includes a first threshold and / or a second threshold; determining whether the read interference state of the physical page is poor based on the relationship between the statistical results and the preset threshold includes: determining that the read interference state of the physical page is poor based on a first quantity being greater than the first threshold and / or a second quantity being greater than the second threshold.

[0242] In some embodiments, the multiple storage states of a physical page include a first storage state and a second storage state with the lowest average threshold voltage range; the first threshold voltage is the average threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average threshold voltage range corresponding to the second storage state when the physical page is writing data; and the first read voltage is between the first threshold voltage and the second threshold voltage.

[0243] In some embodiments, the storage unit includes a storage bit with multiple bits, and the multiple bits of stored data in the storage unit are read by multiple read voltages; the method further includes: before obtaining the statistical results corresponding to the physical page under the first read voltage, setting the read mode to a single-level read mode; the single-level read mode includes reading at least one bit of stored data stored in the storage unit by a first-level read voltage.

[0244] In some embodiments, obtaining the statistical results corresponding to the physical page under the first read voltage includes: receiving the statistical results corresponding to the physical page under the first read voltage transmitted from the memory device; or, receiving the read results corresponding to the physical page under the first read voltage and the second read voltage, or the read results corresponding to the physical page under the first read voltage, and performing calculations and statistics on the read results to obtain the statistical results.

[0245] In some embodiments, the method further includes: acquiring a first read voltage and a preset threshold, respectively.

[0246] In some embodiments, obtaining the first read voltage and the preset threshold respectively includes: obtaining the first read voltage and the preset threshold from the memory device when the memory controller is powered on; the first read voltage and the preset threshold are both fixed values.

[0247] In some embodiments, obtaining the first read voltage and the preset threshold includes: when the memory controller is powered on, obtaining the initial value of the first read voltage and the initial value of the preset threshold from the memory device; and modifying the initial value of the first read voltage and / or the initial value of the preset threshold by setting a feature command to obtain the first read voltage and the preset threshold.

[0248] Sixthly, embodiments of this application propose an operation method for a memory system, such as... Figure 16 As shown, the operation method of this memory system includes:

[0249] Step 1601: During the data inspection of the memory device of the memory system, the memory controller of the memory system obtains the statistical results corresponding to the physical page under the first read voltage; the statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage with a voltage difference of less than a preset voltage, and / or a second number of bits that failed to be read under the first read voltage; the first read voltage is less than the average value of the threshold voltage range corresponding to the middle storage state of the physical page; the memory device includes multiple word lines and multiple memory cells coupled to each word line, and the multiple memory cells form at least one physical page.

[0250] Step 1602: The memory controller determines the read interference status of the physical page based on the statistical results.

[0251] In some embodiments, determining the read interference status of a physical page based on statistical results includes: the memory controller determining whether the read interference status of the physical page is poor based on the relationship between the statistical results and a preset threshold; the method further includes: performing a data migration operation on the physical page based on the determination that the read interference status of the physical page is poor.

[0252] In some embodiments, the preset threshold includes a first threshold and / or a second threshold; determining whether the read interference state of the physical page is poor based on the relationship between the statistical results and the preset threshold includes: determining that the read interference state of the physical page is poor based on a first quantity being greater than the first threshold and / or a second quantity being greater than the second threshold.

[0253] In some embodiments, the multiple storage states of a physical page include a first storage state and a second storage state with the lowest average threshold voltage range; the first threshold voltage is the average threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average threshold voltage range corresponding to the second storage state when the physical page is writing data; and the first read voltage is between the first threshold voltage and the second threshold voltage.

[0254] In some embodiments, the storage unit includes multiple bits of storage data, and the multiple bits of stored data in the storage unit are read by multiple read voltages; the method further includes setting the read mode to a single-level read mode before obtaining the statistical results corresponding to the physical page under the first read voltage; the single-level read mode includes reading at least one bit of stored data stored in the storage unit by a first-level read voltage.

[0255] In some embodiments, obtaining the statistical results corresponding to the physical page under the first read voltage includes: receiving the statistical results corresponding to the physical page under the first read voltage transmitted from the memory device; or, receiving the read results corresponding to the physical page under the first read voltage and the second read voltage, or the read results corresponding to the first read voltage, and performing calculations and statistics on the read results to obtain the statistical results. In some embodiments, the method further includes: obtaining the first read voltage and a preset threshold, respectively.

[0256] In some embodiments, obtaining the first read voltage and the preset threshold respectively includes: obtaining the first read voltage and the preset threshold from the memory device when the memory controller is powered on; the first read voltage and the preset threshold are both fixed values.

[0257] In some embodiments, obtaining the first read voltage and the preset threshold includes: when the memory controller is powered on, obtaining the initial value of the first read voltage and the initial value of the preset threshold from the memory device; and modifying the initial value of the first read voltage and / or the initial value of the preset threshold by setting a feature command to obtain the first read voltage and the preset threshold.

[0258] In a seventh aspect, embodiments of this application propose an operation method for a memory device, the memory device including multiple word lines; multiple memory cells coupled to each word line, the multiple memory cells forming at least one physical page; the method includes:

[0259] Obtain the statistical results corresponding to the physical page under the first read voltage; the statistical results include a first number of bits that flipped in two read results, one under the first read voltage and the other under a read voltage where the voltage difference between the first read voltage and the first read voltage is less than a preset voltage, and / or a second number of bits that failed to be read under the first read voltage; the first read voltage is less than the average value of the threshold voltage range corresponding to the middle storage state of the physical page; based on the statistical results, determine the read interference state of the physical page.

[0260] In some embodiments, the memory device determines the read interference status of a physical page based on statistical results, including: determining whether the read interference status of the physical page is poor based on the relationship between the statistical results and a preset threshold; the method further includes: the physical page whose read interference status is determined to be poor will be subject to a data migration operation.

[0261] In some embodiments, the preset threshold includes a first threshold and / or a second threshold; determining whether the read interference state of the physical page is poor based on the relationship between the statistical results and the preset threshold includes: determining that the read interference state of the physical page is poor based on a first quantity being greater than the first threshold and / or a second quantity being greater than the second threshold.

[0262] In some embodiments, the multiple storage states of a physical page include the storage state with the highest average value of the threshold voltage range; the first read voltage is greater than the average value of the threshold voltage range corresponding to the highest storage state of the physical page when data is written.

[0263] In some embodiments, the plurality of storage states include a first storage state and a second storage state with the lowest average threshold voltage range; the first threshold voltage is the average threshold voltage range corresponding to the first storage state when data is written to the physical page; the second threshold voltage is the average threshold voltage range corresponding to the second storage state when data is written to the physical page; and the first read voltage is between the first threshold voltage and the second threshold voltage.

[0264] In some embodiments, the method further includes: acquiring a first read voltage and a preset threshold, respectively.

[0265] In some embodiments, obtaining the first read voltage and the preset threshold respectively includes: obtaining the first read voltage and the preset threshold from the memory cell respectively when the memory device is powered on; the first read voltage and the preset threshold are both fixed values.

[0266] In some embodiments, obtaining the first read voltage and the preset threshold respectively includes: when the memory device is powered on, obtaining the initial value of the first read voltage and the initial value of the preset threshold respectively from the memory cell;

[0267] The initial value of the first read voltage and / or the initial value of the preset threshold are modified by setting the feature command to obtain the first read voltage and the preset threshold.

[0268] In some embodiments, multiple memory cells coupled to each word line form multiple physical pages; the multiple physical pages contain multiple physical pages; the method further includes: applying a first read voltage to a selected word line among the multiple word lines; for each target physical page among the multiple target physical pages coupled to the selected word line, determining the ground interference state of the corresponding target physical page according to the statistical results corresponding to the corresponding target physical page under the first read voltage; after completing the read interference state of all target physical pages coupled to the selected word line, floating the selected word line.

[0269] In some embodiments, the statistical result includes a first quantity; obtaining the first quantity includes: reading the storage data of a physical page under a first read voltage to obtain a first result; adjusting the first read voltage to obtain an adjusted read voltage, and reading the storage data of a physical page under the adjusted read voltage to obtain a second result; performing logical operations on the first result and the second result to obtain a third result; and counting the number of bits in the third result that represent the second result being flipped compared to the first result to obtain the first quantity.

[0270] Eighthly, embodiments of this application propose an operation method for a memory system, such as... Figure 17 As shown, the operation method of this memory system includes:

[0271] Step 1701: During the data inspection of the memory device of the memory system, the memory controller of the memory system obtains the statistical results corresponding to the physical page under the first read voltage; the statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage where the voltage difference with the first read voltage is less than a preset voltage, and / or a second number of bits that failed to be read under the first read voltage; the first read voltage is less than the average value of the threshold voltage range corresponding to the middle storage state of the physical page; the memory device includes multiple word lines and multiple memory cells coupled to each word line, and the multiple memory cells form at least one physical page.

[0272] Step 1702: The memory device determines the read interference status of the physical page based on the statistical results.

[0273] In some embodiments, the memory device determines the read interference state of a physical page based on statistical results, including: the memory device determines whether the read interference state of the physical page is poor based on the relationship between the statistical results and a preset threshold; the method further includes: the memory controller performs a data migration operation on the physical page based on the physical page's read interference state being a first read interference state.

[0274] In some embodiments, the preset threshold includes a first threshold and / or a second threshold; determining whether the read interference state of the physical page is poor based on the relationship between the statistical results and the preset threshold includes: determining that the read interference state of the physical page is poor based on a first quantity being greater than the first threshold and / or a second quantity being greater than the second threshold.

[0275] In some embodiments, the multiple storage states of a physical page include a first storage state and a second storage state with the lowest average threshold voltage range; the first threshold voltage is the average threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average threshold voltage range corresponding to the second storage state when the physical page is writing data; and the first read voltage is between the first threshold voltage and the second threshold voltage.

[0276] In some embodiments, the storage unit includes multiple bits of storage data, and the multiple bits of stored data in the storage unit are read by multiple read voltages; the method further includes setting the read mode to a single-level read mode before obtaining the statistical results corresponding to the physical page under the first read voltage; the single-level read mode includes reading at least one bit of stored data stored in the storage unit by a first-level read voltage.

[0277] In some embodiments, the method further includes: acquiring a first read voltage and a preset threshold, respectively.

[0278] In some embodiments, obtaining the first read voltage and the preset threshold respectively includes: obtaining the first read voltage and the preset threshold from the memory cell respectively when the memory device is powered on; the first read voltage and the preset threshold are both fixed values.

[0279] In some embodiments, obtaining the first read voltage and the preset threshold respectively includes: when the memory device is powered on, obtaining the initial value of the first read voltage and the initial value of the preset threshold respectively from the memory cell; modifying the initial value of the first read voltage and / or the initial value of the preset threshold by setting a feature command to obtain the first read voltage and the preset threshold.

[0280] In some embodiments, multiple memory cells coupled to each word line form multiple physical pages; the multiple physical pages contain multiple physical pages; the method further includes: applying a first read voltage to a selected word line among the multiple word lines; for each target physical page among the multiple target physical pages coupled to the selected word line, determining the read interference state of the corresponding target physical page according to the statistical results corresponding to the corresponding target physical page under the first read voltage; after completing the read interference state of all target physical pages coupled to the selected word line, floating the selected word line.

[0281] In some embodiments, the statistical result includes a first quantity; obtaining the first quantity includes: reading the storage data of a physical page under a first read voltage to obtain a first result; adjusting the first read voltage to obtain an adjusted read voltage, and reading the storage data of a physical page under the adjusted read voltage to obtain a second result; performing logical operations on the first result and the second result to obtain a third result; and counting the number of bits in the third result that represent the second result being flipped compared to the first result to obtain the first quantity.

[0282] Ninthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the operation method provided in embodiments of this application.

[0283] In some specific embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0284] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0285] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0286] As an example, executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located at one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0287] Figure 18 This is a block diagram illustrating a readable storage medium provided in an embodiment of this application. This application provides a readable storage medium 1800 storing executable instructions 1801. When executed by a processor, these executable instructions 1801 can implement the memory system operation method described above. The operation method includes: during data inspection of the memory device in the memory system, the memory controller acquires statistical results corresponding to physical pages under a first read voltage; the memory controller or the memory device determines the read interference state of the physical page based on the relationship between the statistical results and a preset threshold; and the memory controller performs a data shifting operation on the physical page based on the read interference state being a first read interference state.

[0288] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0289] The above are merely preferred embodiments of this application and do not limit the scope of this patent application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of this application.

Claims

1. A memory controller, characterized in that, Coupled to at least one memory device, the memory device including multiple word lines, each word line being coupled to multiple memory cells, the multiple memory cells forming at least one physical page; The memory controller includes a processor, the processor being configured to: Obtain the statistical results corresponding to the physical page under the first read voltage; the statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage where the voltage difference between the physical page and the first read voltage is less than a preset voltage, and / or a second number of bits that failed to read the physical page under the first read voltage; the first read voltage is less than the average value of the threshold voltage range corresponding to the middle storage state of the physical page; and Based on the statistical results, the read interference status of the physical page is determined.

2. The memory controller according to claim 1, characterized in that, The processor is also configured to: Based on the relationship between the statistical results and the preset threshold, it is determined whether the read interference state of the physical page is poor; and Based on the judgment that the read interference status of the physical page is poor, a data migration operation is performed on the physical page.

3. The memory controller according to claim 2, characterized in that, The preset threshold includes a first threshold and / or a second threshold; The processor is configured to: The physical page is determined to be in a poor read interference state based on the first quantity being greater than the first threshold and / or based on the second quantity being greater than the second threshold.

4. The memory controller according to claim 1, characterized in that, The physical page has multiple storage states, including a first storage state and a second storage state with the lowest average value in the threshold voltage range; The first threshold voltage is the average of the threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average of the threshold voltage range corresponding to the second storage state when the physical page is writing data; the first read voltage is between the first threshold voltage and the second threshold voltage.

5. The memory controller according to claim 1, characterized in that, The storage unit includes multiple storage bits, and the multiple stored data bits of the storage unit are read through multi-stage read voltages; The processor is configured to: Before obtaining the statistical results corresponding to the physical page under the first read voltage, the read mode is set to single-level read mode; single-level read mode includes reading at least one bit of stored data stored in the memory cell through the first-order read voltage.

6. The memory controller according to claim 1, characterized in that, The memory controller also includes an interface coupled to the processor; The interface is configured to receive statistical results corresponding to the physical page under the first read voltage, transmitted from the memory device; or, The interface is configured to receive the read results of the physical page transmitted from the memory device under the first read voltage and the second read voltage, respectively, or the read results under the first read voltage. The processor is configured to perform calculations and statistics on the read results to obtain the statistical results.

7. The memory controller according to claim 2, characterized in that, The processor is configured to: The first read voltage and the preset threshold are obtained respectively.

8. The memory controller according to claim 7, characterized in that, The processor is configured to: When the memory controller is powered on, the first read voltage and the preset threshold are obtained from the memory device, respectively; both the first read voltage and the preset threshold are fixed values.

9. The memory controller according to claim 7, characterized in that, The processor is configured to: When the memory controller is powered on, the initial value of the first read voltage and the initial value of the preset threshold are obtained from the memory device, respectively. and The first reading voltage and the preset threshold are obtained by modifying the initial value of the first reading voltage and / or the initial value of the preset threshold by setting a feature command.

10. A memory system, characterized in that, include: One or more memory devices; as well as The memory controller as claimed in any one of claims 1 to 9 is coupled to and controls the memory device.

11. The memory system according to claim 10, characterized in that, The memory controller is configured to: during a data inspection of the memory device, send a first instruction, the first instruction instructing the acquisition of statistical results of the physical pages; The memory device is configured to: in response to the first instruction, acquire statistics of the physical pages and send information including the statistics of the physical pages to the memory controller; The memory controller is further configured to: determine whether the read interference state of the physical page is poor based on the statistical results and a preset threshold; and perform a data migration operation on the physical page if the read interference state of the physical page is poor.

12. A memory device, characterized in that, include: Multiple letter lines; Each word line is coupled to multiple memory cells, which together form at least one physical page; The peripheral circuitry, coupled to the multiple word lines, is configured as follows: Obtain the statistical results corresponding to the physical page under the first read voltage; the statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage where the voltage difference between the physical page and the first read voltage is less than a preset voltage, and / or a second number of bits that failed to be read under the first read voltage; the first read voltage is less than the average value of the threshold voltage range corresponding to the middle storage state of the physical page; and Based on the statistical results, the read interference status of the physical page is determined.

13. The memory device according to claim 12, characterized in that, The peripheral circuit is also configured to: Based on the relationship between the statistical results and the preset threshold, it is determined whether the read interference status of the physical page is poor; if the read interference status is determined to be poor, the physical page will be subject to a data migration operation.

14. The memory device according to claim 13, characterized in that, The preset threshold includes a first threshold and / or a second threshold; The peripheral circuit is configured as follows: The physical page is determined to be in a poor read interference state based on the first quantity being greater than the first threshold and / or based on the second quantity being greater than the second threshold.

15. The memory device according to claim 12, characterized in that, The physical page has multiple storage states, including a first storage state and a second storage state with the lowest average value in the threshold voltage range; The first threshold voltage is the average of the threshold voltage range corresponding to the first storage state when the physical page is writing data; the second threshold voltage is the average of the threshold voltage range corresponding to the second storage state when the physical page is writing data; the first read voltage is between the first threshold voltage and the second threshold voltage.

16. The memory device according to claim 12, characterized in that, The storage unit includes multiple storage bits, and the multiple stored data bits of the storage unit are read through multi-stage read voltages; The peripheral circuit is configured as follows: Before obtaining the statistical results corresponding to the physical page under the first read voltage, the read mode is set to single-level read mode; single-level read mode includes reading at least one bit of stored data stored in the memory cell through the first-order read voltage.

17. The memory device according to claim 13, characterized in that, The peripheral circuit is configured as follows: Obtain the first read voltage and the preset threshold.

18. The memory device according to claim 17, characterized in that, The peripheral circuit is configured as follows: When the memory device is powered on, the first read voltage and the preset threshold are obtained from the memory cell respectively; both the first read voltage and the preset threshold are fixed values.

19. The memory device according to claim 17, characterized in that, The peripheral circuit is configured as follows: When the memory device is powered on, the initial value of the first read voltage and the initial value of the preset threshold are obtained from the memory cell, respectively. and The first reading voltage and the preset threshold are obtained by modifying the initial value of the first reading voltage and / or the initial value of the preset threshold by setting a feature command.

20. The memory device according to claim 12, characterized in that, The multiple memory cells coupled by the word lines form multiple physical pages; the multiple physical pages contain multiple target physical pages; The peripheral circuit is configured as follows: The first read voltage is applied to the selected word line among the multiple word lines; for each target physical page among the multiple target physical pages coupled to the selected word line, the read interference state of the corresponding target physical page is determined according to the statistical results corresponding to the first read voltage; After completing the read interference state of all target physical pages coupled to the selected word line, the selected word line is floated.

21. The memory device according to claim 12, characterized in that, The statistical results include the first quantity; the peripheral circuit is configured as follows: The stored data of the physical page is read under the first read voltage to obtain a first result; The first read voltage is adjusted to obtain an adjusted read voltage. The stored data of the physical page is read under the adjusted read voltage to obtain a second result. Perform logical operations on the first and second results to obtain the third result; and The first number is obtained by counting the number of bits in the third result that represent the second result being flipped compared to the first result.

22. The memory device according to claim 21, characterized in that, The peripheral circuit includes: a first latch, a second latch, and a third latch; The first latch is configured to store the first result; The second latch is configured to store the second result; The third latch is configured to store the third result.

23. A memory system, characterized in that, include: One or more memory devices as described in any one of claims 12 to 22; as well as A memory controller, which is coupled to and controls the memory device.

24. The memory system according to claim 23, characterized in that, The memory controller is configured to: during a data inspection of the memory device, send a second instruction, the second instruction indicating the acquisition of the read interference status of the physical page; The memory device is configured to: in response to the two instructions, acquire the statistical results corresponding to the physical page under the first read voltage, determine whether the read interference state of the physical page is poor based on the relationship between the statistical results and a preset threshold, and send information including the read interference state of the physical page to the memory controller; The memory controller is also configured to perform a data migration operation on the physical page if the read interference state of the physical page is poor.

25. The memory system according to claim 24, characterized in that, The memory controller is configured to: during a data inspection of the memory device, send a third instruction indicating the acquisition of the read interference status of all target physical pages coupled to the word line; The memory device is configured to: in response to the third instruction, acquire statistical results corresponding to each target physical page coupled to the word line under a first read voltage, determine whether the read interference state of each target physical page is poor based on the relationship between the statistical results and a preset threshold, and send information including the read interference state of all target physical pages coupled to the word line to the memory controller; The memory controller is further configured to perform a data migration operation on all target physical pages coupled to the word line if the read interference state of all target physical pages coupled to the word line is poor.

26. A method for operating a memory system, characterized in that, include: During the data inspection process of the memory devices in the memory system, the memory controller of the memory system acquires the statistical results corresponding to the physical pages under the first read voltage. The statistical results include a first number of bits that flipped in two read results of the physical page under the first read voltage and under a read voltage with a voltage difference from the first read voltage less than a preset voltage, and / or a second number of bits that failed to be read in the physical page under the first read voltage. The first read voltage is less than the average value of the threshold voltage range corresponding to the middle storage state of the physical page. and Based on the statistical results, the read interference status of the physical page is determined.

27. A method for operating a memory system, characterized in that, include: During the data inspection process of the memory device in the memory system, the memory controller of the memory system acquires the statistical results corresponding to the physical page under a first read voltage. The statistical results include a first number of bits that flipped in two read results: one under the first read voltage and the other under a read voltage with a voltage difference less than a preset voltage. The second number of bits that failed to be read in the physical page under the first read voltage is less than the average value of the threshold voltage range corresponding to the middle storage state of the physical page. and Based on the statistical results, the read interference status of the physical page is determined.

28. A computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the operating method as described in claim 26 or 27.

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