Semiconductor memory device and control method thereof

Abstract

An object of the present invention is to provide a semiconductor memory device capable of suppressing an increase in manufacturing cost of an external device and a method of controlling the same, the semiconductor memory device including: a calibration circuit performing a ZQ calibration operation; and a resistor section for serving as a reference resistor in a ZQ calibration operation; in addition, a control method of a semiconductor memory device including a resistor portion as a reference resistor in a ZQ calibration operation includes a step in which a calibration circuit of the semiconductor memory device performs the ZQ calibration operation using the resistor portion.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor memory device and a control method thereof. BACKGROUND

[0002] In a conventional semiconductor memory device, in order to match the impedance of a transmission path to the output impedance of an output circuit, a known method is to connect a resistance (external resistance) provided outside the semiconductor memory device to a ZQ terminal of the semiconductor memory device, and to perform ZQ calibration (for example, Japanese Patent Application Publication No. 2007-123987). SUMMARY

[0003] In the conventional technology, since the external resistance needs to be connected to the ZQ terminal, the manufacturing cost of an external device (external system) including the external resistance can increase. In addition, if the semiconductor memory device is provided with a plurality of silicon dies (memory dies) such as a Dual Die Package (DDP), since different external resistances for the plurality of silicon dies need to be connected, the manufacturing cost of the external device (external system) including the external resistances can further increase.

[0004] In view of the above problem, the present application provides a semiconductor memory device and a control method thereof capable of suppressing an increase in the manufacturing cost of an external device.

[0005] To solve the above problem, the present application provides a semiconductor memory device including: a calibration circuit that performs a ZQ calibration operation; and a resistance portion that functions as a reference resistance in the ZQ calibration operation.

[0006] According to this application, since the ZQ calibration operation can be performed using the resistance portion provided on the semiconductor memory device, the need to provide an external resistance for ZQ calibration on an external device can be eliminated. By this, an increase in the manufacturing cost of the external device due to the provision of the external resistance can be suppressed.

[0007] In addition, the present application provides a control method of a semiconductor memory device including a resistance portion that functions as a reference resistance in a ZQ calibration operation, the control method of the semiconductor memory device including a step of performing a ZQ calibration operation by a calibration circuit of the semiconductor memory device using the resistance portion.

[0008] According to the semiconductor memory device and the control method thereof of the present application, an increase in the manufacturing cost of an external device can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 Fig. 1 is a block diagram illustrating the structure of a semiconductor memory device according to an embodiment of the present application.

[0010] Figure 2 Fig. 1 is a configuration example of a resistance unit.

[0011] Figure 3 Fig. 2 is a configuration example of a resistance value adjustment unit (a) corresponding to a resistance value of the resistance unit, Figure 3 Fig. 3 is a timing chart of one example of a voltage value corresponding to the resistance value of the resistance unit (b).

[0012] Figure 4 Fig. 4 is a timing chart of one example of an output voltage of the calibration circuit in a calibration operation.

[0013] Symbol explanation

[0014] 1: semiconductor storage device

[0015] 10: memory die

[0016] 11: calibration circuit

[0017] 12: resistance unit

[0018] 20: ZQ terminal

[0019] R1: first resistor

[0020] R2: second resistor

[0021] RN: Nth resistor

[0022] SW1: first switch unit

[0023] SW2: second switch unit

[0024] SW3: third switch unit

[0025] U1, U2, Uj: resistance unit

[0026] P1-Pi: P-channel MOSFET

[0027] VDD: operating voltage

[0028] 12a, 12b: resistor

[0029] C: comparator

[0030] V1, Vin, V: voltage

[0031] Vref: reference voltage

[0032] Vout: output voltage DETAILED DESCRIPTION

[0033] Reference Figure 1, the semiconductor storage device 1 is a Dynamic Random Access Memory (DRAM) such as a Double-Data-Rate 4 Synchronous Dynamic Random Access Memory (DDR4 SDRAM), and includes one or more memory dies (die) 10. Further, in the present embodiment, the semiconductor storage device 1 is provided with one ZQ terminal 20 for each of the one or more memory dies 10. In addition, although Figure 1 The case where the semiconductor storage device 1 is provided with one memory die 10 is shown, but the semiconductor storage device 1 can include a plurality of memory dies 10. Further, for simplicity of explanation, other known structures of the semiconductor storage device 1 (for example, a power supply circuit, a command decoder, an address decoder, a clock generator, and the like) are not shown here.

[0034] In the present embodiment, the memory die 10 includes a calibration circuit 11 and a resistance portion 12.

[0035] The calibration circuit 11 includes a plurality of P-channel Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) P1 to Pi (i is an integer of 2 or more), and is configured to perform a ZQ calibration operation. The source terminal of each of the P-channel MOSFETs P1 to Pi is connected to an operating voltage VDD, and the drain terminal of each of the P-channel MOSFETs P1 to Pi is connected to the resistance portion 12 through a node N. Further, the gate terminal of each of the P-channel MOSFETs P1 to Pi is input with a control signal for controlling ON / OFF control of each of the P-channel MOSFETs P1 to Pi.

[0036] In addition, in the present embodiment, although the case where the calibration circuit 11 includes a plurality of P-channel MOSFETs P1 to Pi is taken as one example, the calibration circuit 11 can include a plurality of N-channel MOSFETs instead of the plurality of P-channel MOSFETs P1 to Pi, can include a plurality of other transistors, or can include a plurality of switching circuits. Further, the calibration operation performed in the calibration circuit 11 will be described later.

[0037] The resistance portion 12 is configured to serve as a reference resistance in the ZQ calibration operation. Further, in the present embodiment, the resistance portion 12 includes, for example, a plurality of resistors R1 to Rn (n is an integer of 2 or more) as shown in FIG. 2. The resistance portion 12 is configured to include a plurality of resistors R1 to Rn, and each of the plurality of resistors R1 to Rn has a resistance value different from those of the other resistors. Figure 2The resistor units U1 to Uj (j is an integer greater than or equal to 2) are shown in parallel with the calibration circuit 11. Multiple resistor units U1 to Uj can be used to construct the reference resistor in the ZQ calibration operation.

[0038] In this embodiment, each of the multiple resistor units U1 to Uj contains multiple (e.g., Figure 2 In the example shown, there are four resistors connected in series: 12a, 12b, the first resistor R1, the second resistor R2, and multiple resistors (such as...). Figure 2 In the example shown, there are three switch sections SW1, SW2, and SW3. Furthermore, the structures of the multiple resistor units U1 to Uj are as follows: one end of the Nth (N is an integer greater than 1) switch section SWN is connected to one end of the Nth resistor RN; one end of the (N+1)th switch section SW(N+1) is connected to the other end of the Nth resistor; and the other ends of the Nth switch section SWN and the (N+1)th switch section SW(N+1) are interconnected. Specifically, in... Figure 2 In the example shown, one end of the first (N=1) switch section SW1 is connected to one end of the first resistor R1, one end of the second switch section SW2 is connected to the other end of the first resistor R1, and the other ends of the first switch section SW1 and the second switch section SW2 are connected to each other. Furthermore, one end of the second (N=2) switch section SW2 is connected to one end of the second resistor R2, one end of the third switch section SW3 is connected to the other end of the second resistor R2, and the other ends of the second switch section SW2 and the third switch section SW3 are connected to each other.

[0039] Furthermore, although this embodiment uses the case where each of the multiple resistor units U1 to Uj has three switching sections SW1, SW2, and SW3 as an example, the number of switching sections in each of the multiple resistor units U1 to Uj can be two or less, or four or more. Moreover, the number of switching sections in each of the multiple resistor units U1 to Uj can be the same or different among the multiple resistor units U1 to Uj.

[0040] Furthermore, in this embodiment, although the case where each of the multiple resistor units U1 to Uj has four resistors 12a, 12b, a first resistor R1, and a second resistor R2 is used as an example for illustration, the number of resistors provided in each of the multiple resistor units U1 to Uj can be three or less, or five or more. In addition, the number of resistors provided in each of the multiple resistor units U1 to Uj can be the same or different among the multiple resistor units U1 to Uj.

[0041] In the present embodiment, the plurality of resistance units U1 to Uj are each configured to have a resistance value corresponding to any one of the plurality of switch sections SW1, SW2, and SW3 that is in an on state. Specifically, the plurality of resistance units U1 to Uj are each controlled so that only one of the plurality of switch sections SW1, SW2, and SW3 is in an on state. For example, when the first switch section SW1 of the resistance unit U1 is in an on state and the second switch section SW2 and the third switch section SW3 are in off states, the resistance value of the resistance unit U1 is represented by the sum of the resistance values of the resistors 12a and 12b. Further, when the second switch section SW2 of the resistance unit U1 is in an on state and the first switch section SW1 and the third switch section SW3 are in off states, the resistance value of the resistance unit U1 is represented by the sum of the resistance values of the resistors 12a, 12b, and R1. Furthermore, when the third switch section SW3 of the resistance unit U1 is in an on state and the first switch section SW1 and the second switch section SW2 are in off states, the resistance value of the resistance unit U1 is represented by the sum of the resistance values of the resistors 12a, 12b, R1, and R2. In this way, the plurality of resistance units U1 to Uj can each have different resistance values according to the switch section in an on state.

[0042] Further, in the present embodiment, the plurality of switch sections SW1, SW2, and SW3 are each configured to include a transfer transistor. In this way, by bringing any one of the P-channel MOSFET and the N-channel MOSFET that constitute the transfer transistor into an on state, the transfer transistor can be easily brought into an on state. Note that, here, although a case where the plurality of switch sections SW1, SW2, and SW3 each include a transfer transistor is described as one example, the plurality of switch sections SW1, SW2, and SW3 can be configured so that at least one of the plurality of switch sections SW1, SW2, and SW3 can include a switching circuit other than a transfer transistor (for example, a P-channel MOSFET or an N-channel MOSFET, or the like).

[0043] Further, the plurality of resistance units U1 to Uj can each include the same resistance value. In this way, the resistance units U1 to Uj including the same resistance value can be used to easily configure a reference resistance in the ZQ calibration operation. For example, if the resistance value of the resistance section 12 is 240Ω and the number of resistance units is 10, the resistance value of each resistance unit can be set to 2400Ω.

[0044] Here, an example of a method of adjusting the resistance value of each of the plurality of resistance units U1 to Uj is described with reference to Figure 3 Figure 3 ​As shown in (a), a certain voltage Vl is applied to the resistance unit Ul, and the other ends of the respective switch sections SWl, SW2, SW3 are connected to the input terminal of one end (+ side) of the comparator C. Further, the input terminal of the other end (- side) of the comparator C is input with a certain reference voltage Vref. Furthermore, the comparator C compares the voltage Vin input to the input terminal of one end (+ side) with the reference voltage Vref input to the input terminal of the other end (- side), and outputs the comparison result as an output voltage Vout. In the present embodiment, it is assumed that when the output voltage of the resistance unit Ul (i.e., the voltage Vin) is equal to the reference voltage Vref, the resistance unit Ul has a desired resistance value, and the case where the resistance value of the resistance unit Ul is adjusted is explained.

[0045] As Figure 3 As shown in (b), in the resistance unit Ul, first, the first switch section SWl is set to the on state, then the second switch section SW2 is set to the on state, and then the third switch section SW3 is set to the on state. Then, it is determined which one of the plurality of switch sections SWl, SW2, SW3 has the voltage Vin and the reference voltage Vref equal (in the case of the example shown in (b), the second switch section SW2) when set to the on state, and the determined switch section is set to the on state, thereby adjusting the resistance value of the resistance unit Ul. Further, for the other resistance units U2 to Uj, the resistance value can also be adjusted in the same manner. Figure 3 In the example shown in (b), it is the second switch section SW2), and the determined switch section is set to the on state, thereby adjusting the resistance value of the resistance unit Ul. Further, for the other resistance units U2 to Uj, the resistance value can also be adjusted in the same manner.

[0046] In addition, depending on characteristics such as process and temperature, the resistance values of the resistors 12a, 12b, the first resistor Rl, and the second resistor R2 provided in the plurality of resistance units Ul to Uj can be different for each of the plurality of resistance units Ul to Uj, and thus the switch section that has the input voltage Vin equal to the reference voltage Vref when set to the on state can be different for each of the plurality of resistance units Ul to Uj. Further, in the example shown in (b), although it is explained as an example that the first switch section SWl is first set to the on state, then the second switch section SW2 is set to the on state, and then the third switch section SW3 is set to the on state, the order in which the switch sections are set to the on state can be arbitrarily determined (for example, the third switch section SW3 can be first set to the on state, then the second switch section SW2 can be set to the on state, and then the first switch section SWl can be set to the on state). Figure 3

[0047] Returning to Figure 1 ​, the ZQ terminal 20 is a terminal that can be connected to an external resistance for a ZQ calibration operation. In addition, since the resistance portion 12 for use as a reference resistance in the ZQ calibration operation is provided within the semiconductor storage device 1, the ZQ terminal 20 does not necessarily include the same structure as in the conventional technology (i.e., a structure in which each can be connected to the calibration circuit 11 and the external resistance). In the present embodiment, the ZQ terminal 20 is provided in a state in which it is not connected to the calibration circuit 11 and the resistance portion 12.

[0048] In addition, in the conventional semiconductor storage device, a terminal (e.g., a DQ terminal) for data input and output is provided in addition to the ZQ terminal 20. Here, the terminal (pad) for data input and output needs to be formed to a size with which a probe pin (or also called a probe needle) of a probe card can be contacted in wafer testing. However, when the size of the terminal for data input and output (pad size) is made large, the charge and discharge current on the terminal for data input and output increases, and thus there is a concern that the power consumption of the semiconductor storage device increases. Furthermore, in addition to the terminal for data output used at the time of normal operation of the semiconductor storage device, it is also possible to consider providing a terminal for data output dedicated to wafer testing in the semiconductor storage device, but in this case, since a new terminal for data output dedicated to wafer testing needs to be newly provided in the semiconductor storage device (memory die), there is a concern that the size of the semiconductor storage device (memory die) increases.

[0049] Therefore, in the present embodiment, the ZQ terminal 20 is configured to be used for the input and output of data in wafer testing. By this, the size of the terminal for data output (DQ terminal) used at the time of normal operation of the semiconductor storage device 1 does not need to be made large, and thus it is possible to suppress an increase in the power consumption of the semiconductor storage device 1. Furthermore, since it is not necessary to provide a terminal for data output dedicated to wafer testing, it is possible to suppress an increase in the size of the semiconductor storage device 1 (memory die 10).

[0050] In the present embodiment, the ZQ terminal 20 can be connected to a data input and output circuit (omitted from illustration) that transmits and receives data between the semiconductor storage device 1 and an external device, such as a data signal (DQ) and a data strobe signal (DQS, / DQS). Furthermore, the ZQ terminal 20 can be formed to a size with which a probe pin of a probe card can be contacted in wafer testing. By this, the data input and output circuit of the semiconductor storage device 1 can transmit and receive data between the ZQ terminal 20 and the probe card in wafer testing, and can transmit and receive data between a terminal for data output (DQ terminal) and an external device at the time of normal operation. In addition, switching of the terminal for data transmission and reception can be performed, for example, by a switching circuit or the like.

[0051] In addition, although Figure 1 In the embodiment, one ZQ terminal 20 is provided for one memory die 10, but if the semiconductor storage device 1 includes a plurality of memory dies 10, one ZQ terminal 20 can be provided for each of the plurality of memory dies 10, or one common ZQ terminal 20 can be provided for the plurality of memory dies 10.

[0052] Reference is made to Figure 4 to describe a calibration operation performed in the calibration circuit 11 of the semiconductor storage device 1 of the embodiment. In the embodiment, the calibration circuit 11 performs the calibration operation using the resistance section 12. Here, a case is described in which the calibration operation is performed in the calibration circuit 11 when the voltage V of the node N in Figure 1 is equal to a specific voltage (e.g., VDD / 2) and the impedance between the resistance section 12 is integrated.

[0053] At the start of the calibration operation, the plurality of P-channel MOSFETs Pl to Pi are each in the off state. First, the P-channel MOSFET Pl is set to the on state, and the voltage V of the node N rises. Next, with the P-channel MOSFET Pl in the on state, the P-channel MOSFET P2 is set to the on state, and the voltage V of the node N further rises. Further, with the P-channel MOSFETs Pl and P2 in the on state, the P-channel MOSFET P3 is set to the on state, and the voltage V of the node N more further rises. In this way, by sequentially setting each of the plurality of P-channel MOSFETs Pl to Pi to the on state until the voltage V of the node N is equal to a specific voltage (e.g., VDD / 2), the calibration operation can be performed. In addition, although Figure 4 a case is described in which the calibration operation is performed when the voltage V of the node N rises to a specific voltage (e.g., VDD / 2), the calibration operation can also be performed when the voltage V of the node N falls to a specific voltage (e.g., VDD / 2) (i.e., each of the plurality of P-channel MOSFETs Pl to Pi is set to the on state at the start of the calibration operation, and is sequentially set to the off state until the voltage V of the node N is equal to a specific voltage (e.g., VDD / 2)).

[0054] In addition, the node N of the calibration circuit 11 can be connected to, for example, a terminal (pad) for a data signal (DQ) (omitted from the drawing) or a terminal (pad) for a data strobe signal (DQS, / DQS) (omitted from the drawing), and the like. In this way, the resistance obtained in the calibration operation (i.e., the combined resistance of the on resistance of at least one P-channel MOSFET of the plurality of P-channel MOSFETs Pl to Pi that is set to the on state) can be set as the output impedance.

[0055] As described above, according to the semiconductor storage device 1 and the control method thereof of the present embodiment, since the ZQ calibration operation can be performed using the resistance portion 12 provided in the semiconductor storage device 1, it is possible to eliminate the need for providing an external resistance for ZQ calibration in an external device. Thereby, it is possible to suppress an increase in manufacturing cost of the external device due to the provision of the external resistance.

[0056] The above-described embodiments are described in order to make the present application more readily understood, and are not intended to limit the present application thereto. Thus, each element disclosed in the above-described embodiments is included in the technical scope of the present application along with all design changes and equivalents thereof.

[0057] For example, although the case where the semiconductor storage device is a DRAM is described as one example in the above-described embodiments, the present application is not limited thereto. For example, the semiconductor storage device can be an SRAM (Static Random Access Memory) or a pSRAM (pseudo-Static Random Access Memory) or a flash memory or another semiconductor storage device.

[0058] Further, Figure 1 , Figure 2 The structures of the calibration circuit 11 and the resistance portion 12 shown in Figs. 1 to 6 are merely examples, and can be appropriately changed, and known structures or various other structures can be employed.

Claims

1. A semiconductor memory device, characterized in that, include: The calibration circuit performs ZQ calibration. as well as The resistor section is used as a reference resistor in the ZQ calibration operation.

2. The semiconductor memory device as claimed in claim 1, characterized in that, include: Terminals are used to connect to external resistors for the ZQ calibration operation, and these terminals are used for data input and output during wafer testing.

3. The semiconductor memory device as claimed in claim 2, characterized in that, The terminal was not connected to the calibration circuit or the resistor section.

4. The semiconductor memory device as claimed in claim 1, characterized in that, include: Multiple memory chips; The resistor is disposed in each of the plurality of memory chips.

5. The semiconductor memory device as claimed in claim 1, characterized in that, The resistor section includes multiple resistor units connected in parallel.

6. The semiconductor memory device as claimed in claim 5, characterized in that, Each of the plurality of resistor units includes the same resistance value.

7. The semiconductor memory device as claimed in claim 5, characterized in that, At least one of the plurality of resistor units includes a plurality of switching sections, and is configured to have a resistance value corresponding to the switching section in the conducting state when any one of the plurality of switching sections is in a conducting state.

8. The semiconductor memory device as claimed in claim 7, characterized in that, At least one of the plurality of switching sections includes a transmission transistor.

9. The semiconductor memory device as claimed in claim 7, characterized in that, The at least one resistor unit includes: Multiple resistors connected in series; The Nth switch section, one end of which is connected to one end of the Nth resistor among the plurality of resistors, where N is an integer greater than or equal to 1; and The (N+1)th switch is connected at one end to the other end of the Nth resistor; The other end of the Nth switch is connected to the other end of the N+1th switch.

10. The semiconductor memory device as claimed in claim 1, characterized in that, The semiconductor memory device is a dynamic random access memory.

11. A control method for a semiconductor memory device, characterized in that, The semiconductor memory device includes a resistor section for use as a reference resistor in ZQ calibration operations; The control method for the semiconductor memory device includes the step of the calibration circuit of the semiconductor memory device performing the ZQ calibration operation using the resistor section.

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