Duty cycle adjustment circuit, method and electronic device

Abstract

A duty cycle adjustment circuit, method and electronic device for outputting a pulse signal meeting system duty cycle requirements. The duty cycle adjustment circuit comprises a clock duty cycle correction circuit, a first inverter, an analog-to-digital conversion circuit, a comparator and a controller; the input end of the clock duty cycle correction circuit is connected with a signal source, and the output end is connected with the input end of the first inverter; the first input end of the analog-to-digital conversion circuit is connected with the output end of the clock duty cycle correction circuit, the second input end is connected with the output end of the first inverter, the first output end is connected with the first input end of the comparator, and the second output end is connected with the second input end of the comparator; the controller is used for adjusting the duty cycle of the output signal of the clock duty cycle correction circuit according to the output signal of the comparator. The signal output by the clock duty cycle correction circuit forms two signals with a phase difference of 180° through the first inverter, one of which is used as a reference signal, and the duty cycle is adjusted through the comparison result of the two signals.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a duty cycle adjustment circuit, method, and electronic device. Background Technology

[0002] Pulse signals are fundamental to ensuring the normal operation of equipment. For example, a chip operates at a certain frequency under the control of a pulse signal output by a clock signal, and switches in a switching circuit can also be turned on and off based on received pulse signals. Therefore, in order to ensure the stability of equipment operation, it is necessary to detect pulse signals.

[0003] The duty cycle of a pulse signal is a crucial performance indicator. Duty cycle typically refers to the ratio of the duration of a positive pulse to its period in an ideal pulse cycle sequence. For example, a duty cycle of 50% means that the width of the high-level clock cycle is the same as the width of the low-level clock cycle.

[0004] In related technologies, to test the duty cycle of a clock signal, a closed-loop integrator circuit is typically used to calculate the duty cycle of the pulse signal. This closed-loop integrator circuit includes multiple components, increasing the sources of circuit error and resulting in inaccurate calculations. Furthermore, because the closed-loop integrator circuit involves multiple computational stages, it results in a large circuit layout area and complex algorithms. Summary of the Invention

[0005] This application provides a duty cycle adjustment circuit, method, and electronic device for reducing the output pulse signal that meets the duty cycle requirements.

[0006] In a first aspect, embodiments of this application provide a duty cycle adjustment circuit, which can be connected to a signal source and adjust the signal output by the signal source into a pulse signal with a fixed duty cycle. The duty cycle adjustment circuit may include a clock duty cycle correction circuit, a first inverter, an analog-to-digital converter, a comparator, and a controller.

[0007] Specifically, the input terminal of the clock duty cycle correction circuit is connected to a signal source, and the output terminal of the clock duty cycle correction circuit is connected to the input terminal of the first inverter; the first input terminal of the analog-to-digital converter (ADC) is connected to the output terminal of the clock duty cycle correction circuit, the second input terminal of the ADC is connected to the output terminal of the first inverter, the first output terminal of the ADC is connected to the first input terminal of the comparator, and the second output terminal of the ADC is connected to the second input terminal of the comparator; the controller is connected to the control terminal of the comparator and the clock duty cycle correction circuit, and the controller is used to adjust the duty cycle of the output signal of the clock duty cycle correction circuit according to the output signal of the comparator.

[0008] Using the above circuit structure, the signal output by the clock duty cycle correction circuit can be converted into two signals with a 180° phase difference through the first inverter. Since the two signals have the same frequency and a 180° phase difference, one of the signals can be used as a reference signal. By comparing the two signals, the duty cycle of the clock duty cycle correction circuit output signal can be determined and adjusted. For example, taking a pulse signal with a 50% duty cycle output by the clock duty cycle correction circuit as an example, the values ​​of the two signals after being converted into digital voltage signals by the analog-to-digital converter circuit are the same. If the comparator outputs a high-level signal, it can be determined that the duty cycle of the clock duty cycle correction circuit signal has shifted. Therefore, the controller can use the state of the comparator output signal to adjust the clock duty cycle correction circuit until the clock duty cycle correction circuit outputs a signal that meets the duty cycle requirements, so that the devices connected to the back end can operate safely based on the above signal.

[0009] In one possible design, the duty cycle adjustment circuit further includes a transmission gate circuit connected between the output of the clock duty cycle correction circuit and the first input of the analog-to-digital conversion circuit. With this design, since the signal output from the clock duty cycle correction circuit may experience a certain degree of delay and signal distortion when passing through the first inverter, a transmission gate circuit can be configured on the line without the first inverter. The transmission gate circuit and the first inverter have identical internal components; therefore, they can produce the same delay and signal distortion, thereby achieving perfect matching of the waveforms and phases of the two signals and further improving the accuracy of the detection results.

[0010] In one possible design, the analog-to-digital converter (ADC) circuit can employ an ADC circuit topology or chip capable of processing multiple data streams in parallel. Alternatively, the ADC circuit can use two independent ADCs to perform ADC conversion on two signals. For example, the ADC circuit includes a first ADC and a second ADC.

[0011] The input terminal of the first analog-to-digital converter is connected to the output terminal of the clock duty cycle correction circuit, and the output terminal of the first analog-to-digital converter is connected to the first input terminal of the comparator; the input terminal of the second analog-to-digital converter is connected to the output terminal of the first inverter, and the output terminal of the second analog-to-digital converter is connected to the second input terminal of the comparator.

[0012] In one possible design, the first analog-to-digital converter and the second analog-to-digital converter include filters consisting of resistors and capacitors.

[0013] In one possible design, to prevent leakage faults from affecting the amplitude of signals on the line, the capacitors in the filter include MOS capacitors.

[0014] In one possible design, the capacitor also includes a MOM capacitor.

[0015] In one possible design, the duty cycle adjustment circuit further includes: a first switching circuit and a second switching circuit.

[0016] Wherein, the first input terminal of the first switching circuit is connected to the first output terminal of the analog-to-digital converter circuit, the second input terminal of the first switching circuit is connected to the second output terminal of the analog-to-digital converter circuit, and the output terminal of the first switching circuit is connected to the first input terminal of the comparator; the first input terminal of the second switching circuit is connected to the second output terminal of the analog-to-digital converter circuit, the second input terminal of the second switching circuit is connected to the first output terminal of the analog-to-digital converter circuit, and the output terminal of the second switching circuit is connected to the second input terminal of the comparator.

[0017] In one possible design, the first switching circuit includes a first switch and a second switch, the second switching circuit includes a third switch and a fourth switch, and the duty cycle adjustment circuit further includes a second inverter.

[0018] Wherein, the first terminal of the first switch is connected to the first output terminal of the analog-to-digital converter circuit, and the second terminal of the first switch is connected to the first input terminal of the comparator; the first terminal of the second switch is connected to the second output terminal of the analog-to-digital converter circuit, and the second terminal of the second switch is connected to the first input terminal of the comparator; the first terminal of the third switch is connected to the second output terminal of the analog-to-digital converter circuit, and the second terminal of the third switch is connected to the second input terminal of the comparator; the first terminal of the fourth switch is connected to the first output terminal of the analog-to-digital converter circuit, and the second terminal of the fourth switch is connected to the second input terminal of the comparator; the input terminal of the second inverter is connected to the control terminals of the first switch and the third switch, and the output terminal of the second inverter is connected to the control terminals of the second switch and the fourth switch.

[0019] Using the above circuit structure, the input signals of the comparator can be switched by configuring voltage signals of different levels. For example, taking the multiple switches that conduct when receiving a high-level voltage signal as an example, when outputting a high-level voltage signal, the first and third switches conduct because their control terminals receive a high-level voltage signal. At this time, the first input terminal of the comparator is connected to the first output terminal of the analog-to-digital converter (ADC), and the second input terminal of the comparator is connected to the second output terminal of the ADC. When outputting a low-level voltage signal, the control terminals of the second and fourth switches conduct because they receive a high-level voltage signal through the second inverter. At this time, the first input terminal of the comparator is connected to the second output terminal of the ADC, and the second input terminal of the comparator is connected to the first output terminal of the ADC. Therefore, by triggering voltage signals of different levels, the two input signals of the comparator can be switched. Furthermore, by switching the two signals for duty cycle detection, errors caused by the circuit components themselves can be eliminated, further improving the accuracy of the detection results.

[0020] In one possible design, the duty cycle adjustment circuit further includes a third inverter and a multiplexer.

[0021] Wherein, the input terminal of the third inverter is connected to the output terminal of the comparator, and the output terminal of the third inverter is connected to the first input terminal of the multiplexer; the second input terminal of the multiplexer is connected to the output terminal of the comparator, and the output terminal of the multiplexer is connected to the controller; the controller is specifically used to: adjust the duty cycle of the clock duty cycle correction circuit output signal according to the output signal of the multiplexer.

[0022] With the above design, when the input signal of the comparator is changed, the state represented by the comparator output signal also changes. In order to reduce the control difficulty of the controller, a multiplexer and a third inverter can be added. When the input signal of the comparator is changed, the output signal of the comparator is also inverted through the third inverter and the multiplexer. Thus, the control logic of the controller is the same before and after the input signal of the comparator is changed. Therefore, it is not necessary to configure an additional set of control instructions inside the controller, and the control difficulty of the controller can be reduced.

[0023] Secondly, embodiments of this application provide an electronic device that may include a signal source, multiple electronic components, and the aforementioned duty cycle adjustment circuit. The duty cycle adjustment circuit can provide pulse signals to the multiple electronic components.

[0024] Thirdly, embodiments of this application provide a duty cycle adjustment method, which can be executed by a controller in the aforementioned duty cycle adjustment circuit. The duty cycle adjustment method may include the following steps:

[0025] The clock duty cycle correction circuit is activated; when a low-level signal is detected from the comparator output, the clock duty cycle correction circuit is activated to increase the duty cycle of the output signal, and when a high-level signal is detected from the comparator output, the clock duty cycle correction circuit is activated to decrease the duty cycle of the output signal.

[0026] In one possible design, after the clock duty cycle correction circuit reduces the duty cycle of the output signal, the method further includes:

[0027] The input signal of the comparator is inverted, and the output signal of the comparator is continued to be detected;

[0028] When a high-level signal is detected from the comparator output, the clock duty cycle correction circuit is controlled to increase the duty cycle of the output signal; when a low-level signal is detected from the comparator output, the clock duty cycle correction circuit is controlled to decrease the duty cycle of the output signal.

[0029] Fourthly, embodiments of this application provide a computer device, including a memory, a processor chip, and a computer program stored in the memory and executable on the processor chip, wherein the processor chip executes the program to implement the steps of the duty cycle adjustment method described above.

[0030] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the aforementioned duty cycle adjustment steps.

[0031] Furthermore, the technical effects of the second to fifth aspects and any possible design can be found in the technical effects of different designs in the first aspect of the embodiments of this application, and will not be repeated here. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A schematic diagram of the duty cycle adjustment circuit provided in this application embodiment. Figure 1 ;

[0034] Figure 2 A schematic diagram of the duty cycle adjustment circuit provided in this application embodiment. Figure 2 ;

[0035] Figure 3 A schematic diagram of the structure of an RC filter provided in this application embodiment. Figure 1 ;

[0036] Figure 4 A schematic diagram of the structure of an RC filter provided in this application embodiment. Figure 2 ;

[0037] Figure 5 This is a schematic diagram of a transmission gate circuit provided in an embodiment of this application;

[0038] Figure 6 A schematic diagram of the duty cycle adjustment circuit provided in this application embodiment. Figure 3 ;

[0039] Figure 7 A schematic diagram of the duty cycle adjustment circuit provided in this application embodiment. Figure 4 ;

[0040] Figure 8 A schematic diagram of a comparator provided in an embodiment of this application;

[0041] Figure 9 A flowchart illustrating a duty cycle adjustment method provided in this application embodiment. Figure 1 ;

[0042] Figure 10 A flowchart illustrating a duty cycle adjustment method provided in this application embodiment. Figure 2 ;

[0043] Figure 11 This is a schematic diagram of the structure of a duty cycle adjustment device provided in an embodiment of this application;

[0044] Figure 12 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0045] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0046] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application. In the specification and claims, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, in the embodiments of this application, words such as "first" and "second" do not limit the quantity or execution order.

[0047] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. "Coupling" in this application can be understood as a direct connection or an indirect connection; for example, A coupled to B can mean that A and B are directly connected, or A and B are indirectly connected.

[0048] Figure 1 A schematic diagram of a duty cycle adjustment circuit provided in an embodiment of this application is shown below. Figure 1 The duty cycle adjustment circuit may include: a clock duty cycle correction circuit (DCC), a first inverter Z1, an analog-to-digital converter, a comparator Z2, and a controller.

[0049] The input of the DCC is connected to the signal source, and the output of the DCC is connected to the input of the first inverter Z1. The DCC can adjust the output signal of the external signal source into a pulse signal with a fixed duty cycle. For example, if the external signal is a clock signal, the DCC can adjust the duty cycle of the received clock signal to 50% after receiving it. The pulse signal output by the signal source is the signal to be measured, and the signal source can be the signal source of the device to which the duty cycle adjustment circuit belongs, or it can be the signal source of another device; this application does not impose further limitations. It should be noted that the DCC can adopt existing DCC circuit structures or chips in the industry, which will not be described in detail here.

[0050] The first input terminal of the analog-to-digital converter (ADC) is connected to the output terminal of the DCC (Digital Computer). The second input terminal of the ADC is connected to the output terminal of the first inverter Z1. The first output terminal of the ADC is connected to the first input terminal of the comparator Z2, and the second output terminal of the ADC is connected to the second input terminal of the comparator Z2. The ADC can convert one signal output from the DCC and one signal output from the first inverter Z1 into digital signals, which are then output to the two input terminals of the comparator Z2 for comparison and processing.

[0051] In practical applications, since the signal received at the second input terminal of the analog-to-digital converter (ADC) circuit is the DCC output signal inverted by the first inverter Z1, the signals received at the two input terminals of the ADC circuit are two signals with the same frequency and a 180° phase difference. Therefore, one signal output from the first inverter Z1 can be used as a reference signal, and the comparator Z2 outputs the comparison result of the two signals. The controller can be connected to the output terminal of comparator Z2 and the DCC, and can accurately detect whether the duty cycle of the DCC output signal has shifted by detecting the signal status of the comparator Z2 output. Furthermore, the controller can use the signal status of the comparator Z2 output to adjust the operating parameters of the DCC, thereby adjusting the duty cycle of the DCC output signal to ensure that the duty cycle of the output pulse signal meets the system requirements.

[0052] Specifically, taking a DCC outputting a pulse signal with a 50% duty cycle as an example, if the output pulse signal meets the requirements, the DC level signal after the DCC output signal passes through the analog-to-digital converter (ADC) will be half the amplitude of the high-level pulse signal. Similarly, the DC level signal after the first inverter Z1 passes through the ADC will also be half the amplitude of the high-level pulse signal. However, if the DCC output pulse signal deviates from this range—for example, if the duty cycle of the pulse signal is greater than 50%, the DC level obtained after the DCC output signal passes through the ADC will be greater than half the amplitude of the high-level pulse signal, and the duty cycle of the DCC output signal after inversion by the first inverter Z1 will be less than 50%. Therefore, the DC level obtained after the first inverter Z1 passes through the ADC will be less than half the amplitude of the high-level pulse signal. Consequently, comparator Z2 will output a high-level signal. Similarly, if the duty cycle of the pulse signal is less than 50%, the DC level obtained after analog-to-digital conversion of the DCC output signal is less than half the amplitude of the high-level pulse signal. The duty cycle of the DCC output signal after inversion by the first inverter Z1 is greater than 50%, and the DC level obtained after analog-to-digital conversion of the first inverter Z1 is also greater than half the amplitude of the high-level pulse signal. Comparator Z2 then outputs a low-level signal. Therefore, the controller can start the DCC and detect the output signal of comparator Z2 after startup. When a low-level signal is detected from comparator Z2, it can be determined that the duty cycle of the DCC output signal is less than the required duty cycle. The controller then controls the DCC to increase the duty cycle of the output signal, thereby enabling the DCC to output a pulse signal that meets the system requirements. Conversely, when a high-level signal is detected from comparator Z2, it can be determined that the duty cycle of the DCC output signal is greater than the required duty cycle. The controller then controls the DCC to decrease the duty cycle of the output signal, thereby enabling the DCC to output a pulse signal that meets the system requirements.

[0053] In practical applications, comparator Z2 cannot directly process analog pulse signals. Therefore, the signals received at the input of comparator Z2 are all signals processed by analog-to-digital conversion (ADC). The ADC can be a multi-channel ADC capable of parallel data conversion, or it can be implemented using two independent ADCs. For example, if the ADC consists of multiple independent ADCs, it can include a first ADC and a second ADC.

[0054] The input terminal of the first analog-to-digital converter (ADC) forms the first input terminal of the ADC circuit and is connected to the output terminal of the DCC. The output terminal of the first ADC forms the first output terminal of the ADC circuit and is connected to the first input terminal of the comparator Z2. The input terminal of the second ADC forms the second input terminal of the ADC circuit and is connected to the output terminal of the first inverter Z1. The output terminal of the second ADC forms the second output terminal of the ADC circuit and is connected to the second input terminal of the comparator Z2.

[0055] In practical applications, the first and second analog-to-digital converters can also use industry-standard analog-to-digital converter circuit topologies or chips.

[0056] In some implementations, see Figure 2 As shown, the first analog-to-digital converter and the second analog-to-digital converter can adopt an RC filter structure.

[0057] In one example, to avoid potential shifts on the line due to leakage, see [reference needed]. Figure 3 As shown, MOS capacitors can be used in RC filters. MOS capacitors can be composed of PMOS and NMOS capacitors, which can effectively reduce the impact of leakage current on the potential of signals on the line.

[0058] In another example, to reduce the size of the analog-to-digital converter, see [link to example]. Figure 4 As shown, the capacitors in an RC filter can also include MOM capacitors. When packaging an analog-to-digital converter (ADC), this can be achieved by placing a MOS capacitor at the bottom and stacking a MOM capacitor on top. Therefore, MOM capacitors can be configured without increasing the device size. Furthermore, by adding MOM capacitors to meet the system's capacitance requirements, the size of the MOS capacitors can be reduced, further reducing the overall device size of the ADC.

[0059] In some implementations, since the signal received at the second input of the analog-to-digital converter circuit is the output signal of the DCC output signal after passing through the first inverter Z1, the DCC output signal may experience a certain delay and distortion when passing through the first inverter Z1. To ensure that the phase and waveform of the two signals received at the input of the analog-to-digital converter circuit correspond, see [reference needed]. Figure 5 As shown, the duty cycle adjustment circuit provided in this embodiment may further include a transmission gate circuit connected between the output terminal of the DCC and the input terminal of the analog-to-digital converter circuit. The transmission gate circuit is only used for signal transmission, and both the first inverter Z1 and the transmission gate circuit are composed of devices such as MOSFETs. To ensure that the signal output by the DCC produces the same error and delay when passing through the transmission gate circuit and the first inverter Z1, the first inverter Z1 and the transmission gate circuit can be composed of MOSFETs of the same size and model, thereby ensuring the accuracy of the circuit detection results.

[0060] It should be noted that, Figure 5 The duty cycle adjustment circuit structure shown is only an example. In actual applications, other circuits or chips using the same components as the first inverter Z1 can also be used. This application does not impose any restrictions here.

[0061] In some implementations, due to factors such as the manufacturing process or application environment of comparator Z2, the output result of comparator Z2 may have a certain error. In order to improve the accuracy of the detection result, the duty cycle adjustment circuit provided in this application embodiment further includes a first switching circuit and a second switching circuit.

[0062] Specifically, the first input terminal of the first switching circuit is connected to the first output terminal of the analog-to-digital converter circuit, the second input terminal of the first switching circuit is connected to the second output terminal of the analog-to-digital converter circuit, and the output terminal of the first switching circuit is connected to the first input terminal of comparator Z2; the first input terminal of the second switching circuit is connected to the second output terminal of the analog-to-digital converter circuit, the second input terminal of the second switching circuit is connected to the first output terminal of the analog-to-digital converter circuit, and the output terminal of the second switching circuit is connected to the second input terminal of comparator Z2.

[0063] In practical applications, the signal received at the first input terminal of comparator Z2 can be controlled by controlling the state of the first switching circuit, and the signal received at the second input terminal of comparator Z2 can be controlled by controlling the state of the second switching circuit. Therefore, the controller can interchange the two signals connected to the input terminal of comparator Z2 using the first and second switching circuits, and then detect the signals received at the input terminal of comparator Z2 before and after the interchange. By interchanged signals received at the input terminal of comparator Z2 and detected separately, the influence of errors generated by comparator Z2 and other components in the circuit on the detection results can be eliminated, thereby improving the accuracy of the detection results.

[0064] In practical applications, the first and second switching circuits can be implemented using multiple switching devices or a single switching device. For example, when the first and second switching circuits use multiple switching devices to switch the input signal of comparator Z2, the first switching circuit may include a first switch K1 and a second switch K2, and the second switching circuit may include a third switch K3 and a fourth switch K4. To reduce the difficulty of switching between the two switching circuits, the duty cycle adjustment circuit also includes a second inverter Z3.

[0065] See Figure 6As shown, the first terminal of the first switch K1 is connected to the first output terminal of the analog-to-digital converter circuit, and the second terminal of the first switch K1 is connected to the first input terminal of the comparator Z2. The first terminal of the second switch K2 is connected to the second output terminal of the analog-to-digital converter circuit, and the second terminal of the second switch K2 is connected to the first input terminal of the comparator Z2. The first terminal of the third switch K3 is connected to the second output terminal of the analog-to-digital converter circuit, and the second terminal of the third switch K3 is connected to the second input terminal of the comparator Z2. The first terminal of the fourth switch K4 is connected to the first output terminal of the analog-to-digital converter circuit, and the second terminal of the fourth switch K4 is connected to the second input terminal of the comparator Z2. The input terminal of the second inverter Z3 is connected to the control terminals of the first switch K1 and the third switch K3, and the output terminal of the second inverter Z3 is connected to the control terminals of the second switch K2 and the fourth switch K4.

[0066] In practical use, the controller can provide enable signals EN to the control terminals of multiple switches in the first and second switching circuits, and control the state of the switches by controlling the level of the enable signals. (See also...) Figure 6 As shown, the control terminals of the first switch K1 and the third switch K3 receive the enable signal EN, and the second switch K2 and the fourth switch K4 receive the inverted signal of the enable signal EN. Therefore, the first switch K1 and the third switch K3 are simultaneously turned on, and the second switch K2 and the fourth switch K4 are simultaneously turned on. Taking the control terminal of the above switches receiving a high-level signal as an example, when the enable signal EN is a high-level signal, the control terminals of the first switch K1 and the third switch K3 receive a high-level signal and are turned on, while the control terminals of the second switch K2 and the fourth switch K4 receive a low-level signal and are turned off. At this time, the signal received at the first input terminal of comparator Z2 is INP, and the signal received at the second input terminal of comparator Z2 is INN. When the enable signal EN is both high and low level, the control terminals of the first switch K1 and the third switch K3 receive a low-level signal and are turned off, while the control terminals of the second switch K2 and the fourth switch K4 receive a high-level signal and are turned on. At this time, the signal received at the first input terminal of comparator Z2 is INN, and the signal received at the second input terminal of comparator Z2 is INP. Therefore, based on the above switching circuit structure, the input signal of comparator Z2 is switched by controlling the level of the enable signal EN.

[0067] It should be noted that, because switching the input signals of comparator Z2 requires two switches to be turned on simultaneously and the other two switches to be turned off simultaneously, therefore, Figure 6 The circuit structure shown uses an inverter to control the signal received by the control terminal of all switches. In practical applications, in order to control the two switch circuits to work independently, an inverter can be configured for each switch circuit, or the controller can be configured with an enable signal for each switch. This application does not impose any further limitations here.

[0068] The enable signal EN can be pre-stored in the memory of the controller, or it can be implemented through corresponding circuits and timers. Of course, the enable signal EN can also be implemented in other ways, which are not limited here.

[0069] It should be noted that, Figure 6 The first and second switch circuit structures shown are merely examples. In practical applications, other circuit topologies can also be used for the first and second switch circuits. For instance, single-pole double-throw (SPDT) switches can be used. Taking the first switch circuit as an example, the first input terminal of the SPDT switch is connected to the first output terminal of the analog-to-digital converter (ADC), the second input terminal of the SPDT switch is connected to the second output terminal of the ADC, and the output terminal of the SPDT switch is connected to the first input terminal of comparator Z2. The control terminal of the SPDT switch receives the enable signal EN. By controlling the level of the enable signal EN, the signal received at the input terminal of comparator Z2 can be interchanged. Of course, other devices in the industry that can achieve the above functions can also be used for the first and second switch circuits, and this application does not impose further limitations on them.

[0070] In practical applications, one signal output from the first inverter Z1 serves as a reference signal. When the signals at the input of comparator Z2 are interchanged, the state represented by the output signal of comparator Z2 is reversed. For example, taking a pulse signal with a 50% duty cycle set by the DCC as an example, when comparator Z2 outputs a high-level signal, it indicates that the duty cycle of the DCC output signal is less than 50%, and when comparator Z2 outputs a low-level signal, it indicates that the duty cycle of the DCC output signal is greater than 50%. Therefore, after the input signals of comparator Z2 are interchanged, the controller can continue to detect the output signal of comparator Z2. When a high-level signal is detected from comparator Z2, the DCC is controlled to increase the duty cycle of the output signal; when a low-level signal is detected from comparator Z2, the DCC is controlled to decrease the duty cycle of the output signal.

[0071] In some implementations, in order to reduce the control difficulty of the controller and reduce the algorithm complexity of the controller, the duty cycle adjustment circuit provided in this application embodiment may further include a third inverter Z4 and a multiplexer MUX.

[0072] See Figure 7 As shown, the input of the third inverter Z4 is connected to the output of the comparator Z2, and the output of the third inverter Z4 is connected to the first input of the MUX. The second input of the MUX is connected to the output of the comparator Z2, and the output of the MUX is connected to the controller. The controller can adjust the duty cycle of the DCC output signal based on the output of the MUX.

[0073] The control signal used to control the operating state of the MUX can be the enable signal EN output by the controller. When the enable signal EN is high, the signal output by comparator Z2 is directly output through the MUX. When the enable signal EN is low, causing the signal at the input of comparator Z2 to be swapped, the signal output by the MUX is the signal received at the second input, that is, the signal output by comparator Z2 is inverted and output. Thus, when the signal received at the input of comparator Z2 is swapped, the MUX also inverts the signal output by comparator Z2, so that the DCC state represented by the signal output by the MUX before and after the signal at the input of comparator Z2 is swapped is the same. Therefore, the controller does not need to configure the control logic after the comparator Z2 input signal is swapped, which can effectively reduce the complexity of the controller's control algorithm.

[0074] In practical applications, the first switching circuit, the second switching circuit, the second inverter Z3, the third inverter Z4, and the MUX can be used as individual devices, or they can be integrated into the comparator Z2. For example, see [link to relevant documentation]. Figure 8 The diagram shows the structure of comparator Z2 when the first switching circuit, the second switching circuit, the second inverter Z3, the third inverter Z4, and the MUX are integrated within it. It should be noted that... Figure 8 The comparator Z2 structure shown is only an example. In actual applications, comparator Z2 can also adopt other circuit topologies, which are not limited here.

[0075] Based on the same concept, embodiments of this application also provide an electronic device, which includes at least a signal source, the aforementioned duty cycle adjustment circuit, and multiple electronic components. The duty cycle adjustment circuit can provide pulse signals to the multiple electronic components.

[0076] The electronic device can be any device that requires a pulse signal. For example, when the electronic device is a radio frequency (RF) device, the duty cycle adjustment circuit can provide a local carrier signal for the RF state. When the electronic device is a power module driver, the duty cycle adjustment circuit can provide the carrier signal required to generate the drive signal. Of course, the electronic device can also be other functional devices, which will not be described in detail here.

[0077] Figure 9 This is a flowchart illustrating a duty cycle adjustment method provided in an embodiment of this application. This duty cycle adjustment method can be executed by the controller of the aforementioned duty cycle adjustment circuit. (See attached diagram.) Figure 9 As shown, the method includes the following steps.

[0078] S901: Controls the start of the clock duty cycle correction circuit. The controller can initialize the DCC and control the DCC circuit to operate normally.

[0079] S902: When a low-level signal is detected at the comparator output, the clock duty cycle correction circuit is controlled to increase the duty cycle of the output signal; when a high-level signal is detected at the comparator output, the clock duty cycle correction circuit is controlled to decrease the duty cycle of the output signal.

[0080] Specifically, in combination Figure 6 The duty cycle adjustment circuit structure shown, taking a DCC outputting a pulse signal with a 50% duty cycle as an example, when the DCC starts normally and outputs a 50% pulse signal, if the duty cycle of the output pulse signal meets the system requirements, the value of the digital signal received at the first input terminal of comparator Z2 is half the amplitude of the high-level pulse signal, and the value of the digital signal at the second input terminal of comparator Z2 is also half the amplitude of the high-level pulse signal. If the pulse signal output by the DCC deviates, for example, if the duty cycle of the pulse signal is greater than 50%, the amplitude of the digital signal received at the first input terminal of comparator Z2 is greater than half the amplitude of the high-level pulse signal, and the amplitude of the digital signal received at the second input terminal of comparator Z2 is less than half the amplitude of the high-level pulse signal. If the duty cycle of the pulse signal is less than 50%, the amplitude of the digital signal received at the first input terminal of comparator Z2 is less than half the amplitude of the high-level pulse signal, and the amplitude of the digital signal received at the second input terminal of comparator Z2 is greater than half the amplitude of the high-level pulse signal. Therefore, when the controller detects a low-level signal output from comparator Z2, it indicates that the duty cycle of the pulse signal output by DCC is less than 50%, and the controller increases the duty cycle of the output signal by controlling DCC. When the controller detects a high-level signal output from comparator Z2, it indicates that the duty cycle of the pulse signal output by DCC is greater than 50%, and the controller decreases the duty cycle of the output signal by controlling DCC.

[0081] In some implementations, to eliminate the influence of internal circuit components on the detection results, the input signal of comparator Z2 can be switched, and the duty cycle adjustment circuit can be controlled to perform detection before and after the switching. Specifically, after executing step S902, the input signal of comparator Z2 can be reversed by controlling the state of the switches in the first and second switching circuits, and the output signal of comparator Z2 can continue to be detected. Before the input signal of comparator Z2 is switched, the signal output by DCC is used as the signal to be measured, and the signal output by the first inverter Z1 is used as the reference signal. After the input signal of comparator Z2 is switched, the signal output by DCC is used as the reference signal, and the signal output by the first inverter Z1 is used as the signal to be measured. That is, when the input signal of comparator Z2 is switched, the state represented by the signal output by comparator Z2 is also reversed. Therefore, when a high-level signal is detected from the output of comparator Z2, the clock duty cycle correction circuit is controlled to increase the duty cycle of the output signal, and when a low-level signal is detected from the output of comparator Z2, the clock duty cycle correction circuit is controlled to decrease the duty cycle of the output signal.

[0082] In some implementations, to reduce control complexity and simplify the control algorithm, see [reference needed]. Figure 7 As shown, a third inverter Z4 and a MUX can be configured at the output of comparator Z2. Before the input signal of comparator Z2 is swapped, the output signal of comparator Z2 is directly output to the controller by controlling the level of the enable signal EN to be high. After the input signal of comparator Z2 is swapped, the output signal of comparator Z2 is inverted and then output to the controller by controlling the level of the enable signal EN to be low. Therefore, the signal received by the controller before and after the input signal of comparator Z2 is swapped represents the same state, and the same processing can be performed, without the need to configure two sets of control algorithms. The process of adjusting the input and output signals of comparator Z2 using the enable signal EN can be found in the above description, and will not be described in detail here.

[0083] Below, with Figure 7 Taking the duty cycle adjustment circuit structure shown as an example, and combining it with the enable signal EN, the flow of the duty cycle adjustment method is explained in detail. Figure 10 As shown, the main steps include the following:

[0084] S1001: Controls DCC initialization and ensures the enable signal EN is high.

[0085] S1002: Detect whether the MUX outputs a low-level signal. If yes, proceed to step S1003; otherwise, proceed to step S1005.

[0086] S1003: Control the DCC to increase the duty cycle of the output signal and continue to execute step 1004.

[0087] S1004: Detect whether the MUX outputs a high-level signal. If yes, proceed to step S1007; otherwise, return to step S1004.

[0088] S1005: Controls DCC to reduce the duty cycle of the output signal.

[0089] S1006: Detect whether the MUX outputs a low-level signal. If yes, proceed to step S1007; otherwise, return to step S1005.

[0090] S1007: Detect whether the enable signal EN is a high-level signal. If yes, proceed to step S1009; otherwise, proceed to step S1008.

[0091] S1008: The control enable signal EN is set to a high level, and the process returns to step 1002.

[0092] S1009: Duty cycle adjustment process complete.

[0093] Based on the same technical concept, this application provides a schematic diagram of the structure of a duty cycle adjustment device, as shown below. Figure 11 As shown, the duty cycle adjustment device includes:

[0094] Processing module 1101 is used to control the start of the clock duty cycle correction circuit;

[0095] The detection module 1102 is used to detect the output signal of the comparator.

[0096] The processing module 1101 is also configured to control the clock duty cycle correction circuit to increase the duty cycle of the output signal when the detection module 1102 detects a low-level signal output by the comparator, and to control the clock duty cycle correction circuit to decrease the duty cycle of the output signal when the detection module 1102 detects a high-level signal output by the comparator.

[0097] In some implementations, after the clock duty cycle correction circuit reduces the duty cycle of the output signal, the processing module 1101 is further configured to: control the input signal of the comparator to invert, and control the detection module 1102 to continue detecting the output signal of the comparator; when the detection module 1102 detects a high-level signal output by the comparator, control the clock duty cycle correction circuit to increase the duty cycle of the output signal, and when the detection module 1102 detects a low-level signal output by the comparator, control the clock duty cycle correction circuit to decrease the duty cycle of the output signal.

[0098] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 12 As shown, it includes at least one processor chip 1201 and a memory 1202 connected to at least one processor chip. In this embodiment, the specific connection medium between the processor chip 1201 and the memory 1202 is not limited. Figure 12 Taking the connection between processor chip 1201 and memory 1202 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0099] In this embodiment of the application, the memory 1202 stores instructions that can be executed by at least one processor chip 1201. By executing the instructions stored in the memory 1202, the at least one processor chip 1201 can perform the steps of the duty cycle adjustment method described above.

[0100] The processor chip 1201 serves as the control center of the computer device. It connects to various parts of the device via various interfaces and lines, and adjusts the duty cycle of the pulse signal by running or executing instructions stored in the memory 1202 and accessing data stored in the memory 1202. Optionally, the processor chip 1201 may include one or more processing units. The processor chip 1201 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the processor chip 1201. In some embodiments, the processor chip 1201 and the memory 1202 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0101] The processor chip 1201 can be a general-purpose processor, such as a graphics processing unit (GPU), general-purpose computing on graphics processing units (GPGPU), central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0102] Memory 1202, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 1202 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 1202 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. In the embodiments of this application, memory 1202 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0103] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the duty cycle adjustment method described above.

[0104] Based on the same inventive concept, this application provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the duty cycle adjustment method described above.

[0105] Those skilled in the art will understand that embodiments of the present invention can be provided as methods or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0106] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer apparatus or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0107] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer device or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0108] These computer program instructions may also be loaded onto a computer device or other programmable data processing equipment to cause a series of operational steps to be performed on the computer device or other programmable equipment to produce a process implemented by the computer device, thereby providing instructions that execute on the computer device or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0109] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0110] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A duty cycle adjustment circuit, characterized by, include: Clock duty cycle correction circuit, first inverter, analog-to-digital converter circuit, comparator and controller; The input terminal of the clock duty cycle correction circuit is used to connect to the signal source, and the output terminal of the clock duty cycle correction circuit is connected to the input terminal of the first inverter. The first input terminal of the analog-to-digital converter circuit is connected to the output terminal of the clock duty cycle correction circuit, the second input terminal of the analog-to-digital converter circuit is connected to the output terminal of the first inverter, the first output terminal of the analog-to-digital converter circuit is connected to the first input terminal of the comparator, and the second output terminal of the analog-to-digital converter circuit is connected to the second input terminal of the comparator. The controller is connected to the output of the comparator and the clock duty cycle correction circuit. The controller is used to adjust the duty cycle of the output signal of the clock duty cycle correction circuit according to the output signal of the comparator. The duty cycle adjustment circuit further includes: a first switching circuit and a second switching circuit; The first input terminal of the first switching circuit is connected to the first output terminal of the analog-to-digital converter circuit, the second input terminal of the first switching circuit is connected to the second output terminal of the analog-to-digital converter circuit, and the output terminal of the first switching circuit is connected to the first input terminal of the comparator. The first input terminal of the second switching circuit is connected to the second output terminal of the analog-to-digital converter circuit, the second input terminal of the second switching circuit is connected to the first output terminal of the analog-to-digital converter circuit, and the output terminal of the second switching circuit is connected to the second input terminal of the comparator. The duty cycle adjustment circuit also includes: a third inverter and a multiplexer; The input terminal of the third inverter is connected to the output terminal of the comparator, and the output terminal of the third inverter is connected to the first input terminal of the multiplexer. The second input terminal of the multiplexer is connected to the output terminal of the comparator, and the output terminal of the multiplexer is connected to the controller; The controller is specifically used to: adjust the duty cycle of the clock duty cycle correction circuit output signal according to the output signal of the multiplexer.

2. The circuit of claim 1, wherein, The duty cycle adjustment circuit also includes a transmission gate circuit connected between the output terminal of the clock duty cycle correction circuit and the first input terminal of the analog-to-digital conversion circuit.

3. The circuit of claim 1, wherein, The analog-to-digital conversion circuit includes: a first analog-to-digital converter and a second analog-to-digital converter; The input terminal of the first analog-to-digital converter is connected to the output terminal of the clock duty cycle correction circuit, and the output terminal of the first analog-to-digital converter is connected to the first input terminal of the comparator. The input terminal of the second analog-to-digital converter is connected to the output terminal of the first inverter, and the output terminal of the second analog-to-digital converter is connected to the second input terminal of the comparator.

4. The circuit according to claim 3, characterized in that, The first analog-to-digital converter and the second analog-to-digital converter include filters composed of resistors and capacitors.

5. The circuit according to claim 4, characterized in that, The capacitor includes a MOS capacitor.

6. The circuit according to claim 5, characterized in that, The capacitor also includes a MOM capacitor.

7. The circuit according to claim 1, characterized in that, The first switching circuit includes a first switch and a second switch, the second switching circuit includes a third switch and a fourth switch, and the duty cycle adjustment circuit further includes a second inverter; The first terminal of the first switch is connected to the first output terminal of the analog-to-digital converter circuit, and the second terminal of the first switch is connected to the first input terminal of the comparator. The first terminal of the second switch is connected to the second output terminal of the analog-to-digital converter circuit, and the second terminal of the second switch is connected to the first input terminal of the comparator. The first terminal of the third switch is connected to the second output terminal of the analog-to-digital converter circuit, and the second terminal of the third switch is connected to the second input terminal of the comparator. The first terminal of the fourth switch is connected to the first output terminal of the analog-to-digital converter circuit, and the second terminal of the fourth switch is connected to the second input terminal of the comparator. The input terminal of the second inverter is connected to the control terminals of the first switch and the third switch, and the output terminal of the second inverter is connected to the control terminals of the second switch and the fourth switch.

8. An electronic device, characterized in that, It includes a signal source, a duty cycle adjustment circuit as described in any one of claims 1 to 7, and a plurality of electronic components, wherein the duty cycle adjustment circuit is used to provide pulse signals to the plurality of electronic components.

9. A duty cycle adjustment method, characterized in that, The method, applied to the duty cycle adjustment circuit as described in any one of claims 1 to 7, comprises: The clock duty cycle correction circuit is activated. When a low-level signal is detected at the comparator output, the clock duty cycle correction circuit is controlled to increase the duty cycle of the output signal; and when a high-level signal is detected at the comparator output, the clock duty cycle correction circuit is controlled to decrease the duty cycle of the output signal.

10. The method according to claim 9, characterized in that, After the clock duty cycle correction circuit reduces the duty cycle of the output signal, the method further includes: The input signal of the comparator is inverted, and the output signal of the comparator is continued to be detected; When a high-level signal is detected from the comparator output, the clock duty cycle correction circuit is controlled to increase the duty cycle of the output signal; when a low-level signal is detected from the comparator output, the clock duty cycle correction circuit is controlled to decrease the duty cycle of the output signal.

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