Multi-gate distributed driving structure and switching circuit unit of GaN chip
By designing a multi-gate distributed drive structure for GaN chips, the problem of insufficient drive capability in high-speed applications was solved, the switching speed was improved and the energy loss was reduced, and the miniaturization and high power density of the product were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU INNPHY MICROELECTRONICS CO LTD
- Filing Date
- 2025-12-26
- Publication Date
- 2026-05-12
AI Technical Summary
Existing GaN chips suffer from insufficient driving capability in high-speed applications, resulting in transmission delays and crosstalk between gate arrays at different locations, which affects switching efficiency.
A multi-gate distributed driving structure is adopted. By designing multiple gates for the GaN HEMT module and electrically connecting them with independent driving modules, a tight mesh structure is formed, which shortens the signal transmission path and uses a stacked arrangement to reduce parasitic inductance.
It improves switching speed, reduces energy loss, and enables product miniaturization and high power density.
Smart Images
Figure CN121461958B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of GaN chip technology, and in particular to a multi-gate distributed driving structure and switching circuit unit for GaN chips. Background Technology
[0002] GaN chips, with their fast switching characteristics, are widely used in high-speed applications up to 500kHz and even exceeding 1MHz. In these high-speed applications, the size of passive components can be made smaller, helping to reduce the overall system size and effectively reduce costs. However, GaN chips in high-speed applications have very high requirements for driving capability, which means that the driving circuit must be able to quickly and accurately control the GaN chip to turn on and off.
[0003] However, most existing GaN chips reference the low-frequency application architecture of traditional silicon devices, merely replacing existing designs without specific design optimizations for high-frequency applications. While they can meet some basic application requirements to a certain extent, they do not fully utilize the high-speed performance advantages of GaN materials. Specifically, the external interface of currently commercially available GaN chips is mainly a gate electrode. For GaN chips with low resistance, the gate arrays at different locations relative to the gate electrode experience different propagation delays due to differences in parasitic inductance of the traces. In particular, the far-end gate array has a parasitic inductance on the order of nH relative to the gate electrode, resulting in different turn-on speeds between the near-end and far-end gate arrays. Furthermore, crosstalk loop currents may occur between the source and drain in different regions, further reducing switching speed and thus affecting switching efficiency. Summary of the Invention
[0004] The main objective of this invention is to provide a multi-gate distributed driving structure and switching circuit unit for GaN chips, thereby overcoming the shortcomings of the prior art.
[0005] To achieve the aforementioned objectives, the present invention employs the following technical solution.
[0006] The first aspect of the present invention provides a multi-gate distributed driving structure for a GaN chip, including a GaNHEMT module and a driving module connected to the GaN HEMT module. The GaN HEMT module has a plurality of gates, and the plurality of gates are spaced apart along a direction parallel to the surface of the GaN HEMT module, wherein each gate is electrically connected to the driving module.
[0007] In some more specific embodiments, the multi-gate distributed driving structure of the GaN chip further includes a gate bus, with multiple gates connected in parallel via the gate bus.
[0008] Furthermore, the multi-gate distributed driving structure includes a gate array, which includes multiple gate bars spaced apart from each other and a gate bus; the multiple gate bars are connected in parallel to each other through the gate bus and form a tight mesh structure that covers the entire surface of the GaN HEMT module.
[0009] For example, the plurality of gates include a first gate and a second gate, which are led out from the middle position of the gate array and maintain a left-right symmetrical layout.
[0010] In some more specific embodiments, the multi-gate distributed driving structure includes multiple driving modules, each of which is electrically connected to a corresponding gate.
[0011] Furthermore, at least two of the gates are electrically connected to the same drive module.
[0012] Furthermore, the multi-gate distributed driving structure includes multiple GaN HEMT modules, each of which is electrically connected to at least one driving module.
[0013] In some more specific solutions, the GaN HEMT module and the driver module are arranged in parallel on a single working plane. In other more specific solutions, the GaN HEMT module and the driver module are stacked.
[0014] In some more specific solutions, the GaN HEMT module and the driver module are integrated into the same chip, and the driver module uses HEMT devices.
[0015] A second aspect of the present invention provides a switching circuit unit including the multi-gate distributed driving structure of the GaN chip.
[0016] Compared with the prior art, the advantages of the present invention include at least the following:
[0017] Firstly, the multi-gate distributed driving structure of the GaN chip in this invention designs multiple gates for the GaN HEMT module and assigns an independent driver to each gate. This distributed driving approach shortens the trace length from the far end of the GaN HEMT module to the gate, significantly reducing the parasitic inductance from the far-end gate strip to the gate, thereby positively impacting chip performance. Specifically, each driver is responsible for driving a part of the GaN HEMT module, rather than a single driver driving the entire GaN HEMT module. This decentralized driving strategy not only improves switching speed but also reduces energy loss during the switching process.
[0018] Secondly, the multi-gate distributed driving structure of the GaN chip in this invention significantly shortens the distance between the GaN HEMT module and the driving module by stacking them, resulting in a very short signal transmission path. This leads to a substantial reduction in signal delay, effectively reducing signal transmission latency. This stacking method achieves vertical integration of the driver and the chip, greatly reducing the overall size compared to traditional planar layouts. This contributes to further miniaturization and high power density of the product. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the structure of a GaN HEMT module according to one embodiment of the present invention;
[0020] Figure 2 This is a schematic diagram of a multi-gate distributed driving structure for a GaN chip according to an embodiment of the present invention;
[0021] Figure 3 This is a schematic diagram of the structure of another GaN chip multi-gate distributed driving structure in one embodiment of the present invention;
[0022] Figure 4 This is a schematic diagram of a multi-gate distributed driving structure for a GaN chip in one embodiment of the present invention;
[0023] Figure 5 This is a circuit diagram of a multi-gate distributed driving structure for a GaN chip according to an embodiment of the present invention.
[0024] Figure 6 This is a schematic diagram of a multi-gate distributed driving structure for a GaN chip in one embodiment of the present invention.
[0025] Explanation of reference numerals in the attached figures:
[0026] 11. Gate bar; 12. Gate bus; 13. First gate; 14. Second gate; 19. Driver stage; 41. First connection trace; 42. Second connection trace; 15. First driver connection line; 16. Second driver connection line; 17. First driver chip; 18. Second driver chip; 20. First HEMT module driver; 21. First HEMT module connection line; 22. Second HEMT module driver; 23. Second HEMT module. Detailed Implementation
[0027] The following will provide a further explanation of the technical solution, its implementation process, and its principles.
[0028] Please refer to Figures 1-2An embodiment of the present invention provides a multi-gate distributed driving structure for a GaN chip, including a GaN HEMT module and a driving module connected to the GaN HEMT module.
[0029] In one embodiment, the GaN HEMT module and the driver module are arranged in parallel on a working plane. The GaN HEMT module has two gates, namely a first gate 13 and a second gate 14. The first gate 13 and the second gate 14 are spaced apart along a direction parallel to the surface of the GaN HEMT module. The driver module is an integrated structure, including a driver stage 19 and independently arranged first connection traces 41 and second connection traces 42.
[0030] Specifically, the first gate 13 and the second gate 14 are led out from the middle of the gate array. The gate array includes multiple gate strips 11 and gate bus 12. These gate strips 11 are connected in parallel through the gate bus 12 to form an extended gate array. The first gate 13 and the second gate 14 are connected in parallel through the gate bus 12, which enables the gate array to form a tight mesh structure, thereby effectively reducing the overall gate resistance and signal transmission delay. This not only improves the uniformity of current distribution but also ensures efficient signal transmission and stable circuit operation.
[0031] The gate bus 12 is implemented using a top-layer metal, meaning it is positioned above multiple gate strips 11. Therefore, its width can be wider than other metal layers, and the thickness of the metal layers can be significantly increased to ensure it can carry larger currents and provide lower resistance. The first gate 13 and the second gate 14 are connected to the multiple gate strips via a two-layer metal interconnect, with vias between each metal layer. This design effectively reduces resistance and improves current transmission efficiency. To meet the requirements of high-speed operation, the first gate 13 and the second gate 14 are led out from the center of the gate array and maintain a symmetrical layout to ensure balanced and stable signal transmission.
[0032] Specifically, the two gates control the left and right side gates respectively. If the number of gates increases, the layout needs to be adjusted accordingly. The basic principle of adjustment is to maintain left-right symmetry to ensure the overall structural balance. If the distance between the left and right sides is too great, the gates can be extended vertically to shorten the signal transmission path. However, excessive vertical extension may affect the overall layout's rationality. In this case, drive circuits can be added to the top and bottom sides to optimize signal control and transmission efficiency. Through this flexible layout adjustment, symmetry can be maintained while adapting to different gate numbers, ensuring stable operation.
[0033] In this embodiment, the driver stage 19 can be electrically connected to the first gate 13 using the first connection trace 41, and the driver stage 19 can be connected to the second gate 14 using the second connection trace 42. The driver stage 19, the first gate 13, the second gate 14, and the gate array are all encapsulated in a single package carrier 10.
[0034] In this embodiment, by setting multiple gates, the parasitic inductance from the far-end gate bar to the gate can be significantly reduced, resulting in a more uniform drive of the entire chip's gate array, improved switching speed, and reduced losses. The number and position of the gates can be adjusted according to the actual size of the GaN HEMT module and are not limited to this embodiment. The specific arrangement will vary depending on the package type. For chips requiring lower resistance, or in applications with higher frequencies and greater sensitivity to parasitic effects, more gates can be used to extract signals. Furthermore, the driver stage 19 can be laid flat with the GaN HEMT module in a first direction parallel to the substrate surface of the GaN HEMT module, which facilitates heat dissipation.
[0035] Please refer to Figure 3 In another embodiment, the GaN HEMT module and the driver module can be stacked. Specifically, the driver stage 19 and the GaN HEMT module are stacked in a second direction perpendicular to the substrate surface of the GaN HEMT module. In other words, the driver stage 19 is directly attached to the top of the GaN HEMT module. This stacking method significantly shortens the connection line length between the driver stage 19 and the GaN HEMT module, thereby greatly reducing the parasitic inductance from the far-end gate to the gate. Because the distance between the driver stage 19 and the GaN HEMT module is very close, the signal transmission path becomes very short, resulting in a significant reduction in signal delay, effectively reducing signal transmission latency. This stacking method achieves vertical integration of the driver and the chip, greatly reducing the overall size compared to existing planar layouts, which helps to achieve further miniaturization and high power density of the product.
[0036] Please refer to Figure 4 In another implementation, the multi-gate distributed drive structure includes two drive modules, with the first gate 13 and the second gate 14 electrically connected to a corresponding drive module, which can achieve more efficient signal distribution and management, thereby improving the overall drive performance.
[0037] Specifically, the two driving modules are a first driving circuit and a second driving circuit, respectively. The first and second driving circuits are independently configured to ensure driving flexibility and reliability. The first driving circuit consists of a first driving chip 17 and a first driving connection line 15, with the first driving connection line 15 electrically connecting the first driving chip 17 to the first gate 13. The second driving circuit consists of a second driving chip 18 and a second driving connection line 16, with the second driving connection line 16 electrically connecting the second driving chip 18 to the second gate 14. The first driving chip 17, the second driving chip 18, the first gate 13, the second gate 14, and the gate array are all packaged within a common package carrier 10, improving integration density. The first driving chip 17 and the second driving chip 18 are laid flat with the GaN HEMT module in a first direction, parallel to the substrate surface of the GaN HEMT module. The first gate 13 and the second gate 14 are connected to multiple gate strips to transmit driving signals to the gate strips, thereby controlling the conduction and cutoff of the GaN HEMT module. By setting multiple gates, the parasitic inductance from the far gate bar to the gate can be significantly reduced, resulting in a more uniform drive of the entire gate array of the chip, improving switching speed and reducing losses.
[0038] Please refer to Figure 5 A GaN HEMT module and a driver module can be integrated on the same chip, with the driver module employing a HEMT device. Specifically, the GaN chip includes at least one main switch (MM), which is connected to the driver module. The driver module includes a driver chip and driver connection lines, which electrically connect the driver chip to its gate. This embodiment integrates both the driver chip and the main switch (MM) on a GaN chip, thereby achieving efficient integration of the driver circuit and the power switch.
[0039] Furthermore, the driver chip includes a first driver transistor M0, a second driver transistor M1, a third driver transistor M2, and a fourth driver transistor M3. The device structure of the main switch transistor MM is designed according to the DRAIN voltage withstand requirement to ensure stable operation in high-voltage applications. The first driver transistor M0, the second driver transistor M1, the third driver transistor M2, and the fourth driver transistor M3 meet the VDD voltage withstand requirement; therefore, their withstand voltage length is shorter than that of the main switch transistor MM, which helps to reduce the overall chip size and improve integration. The entire GaN chip exposes four ports: GATE, DRAIN, SOURCE, and VDD. VDD is the power supply terminal for the driver, providing a stable power supply for the entire driver circuit.
[0040] The first driving transistor M0, the second driving transistor M1, the third driving transistor M2, and the fourth driving transistor M3 are different switching GaN devices that implement the driving module. These four devices form a driving module. Specifically, the drain of the first driving transistor M0 is connected to the power supply VDD, and its gate is connected to its drain. The drain of the second driving transistor M1 and the source of the first driving transistor M0 are connected to the first connection point. The gate (GATE) of the second driving transistor M1 is connected to the signal input terminal, and its source is connected to the common terminal (source). In this way, the second driving transistor M1 can control signal transmission. The drain of the third driving transistor M2 is connected to the power supply VDD, and its gate is connected to its drain. The drain of the fourth driving transistor M3 and the source of the third driving transistor M2 are connected to the second connection point. The gate of the fourth driving transistor M3 is connected to the first connection point, and its source is connected to the common source terminal. The gate of the main switching transistor MM is connected to the second connection point, its source is connected to the source of the fourth driving transistor M3, and its drain (DRAIN) serves as the output terminal.
[0041] The specific driving process is as follows: When the GATE terminal receives an appropriate voltage signal, transistor M1 determines whether to turn on or off based on the signal's level. Once transistor M1 turns on, a conductive path is formed between its drain and source, changing the node potential connected to M3, thus causing transistor M3 to also turn on. After transistor M3 turns on, it further controls the state of the main switch MM. When the main switch MM turns on, current can flow from the VDD power supply terminal, through M0, M2, and MM in sequence, finally flowing to the SOURCE terminal, thereby realizing power transfer and circuit conduction. In this way, the load (connected to the DRAIN terminal) can be powered or processed. Conversely, when a signal change at the GATE terminal causes transistor M1 to turn off, M3 will also turn off, which in turn causes transistor MM to turn off, thus cutting off the current path.
[0042] Please refer to Figure 6The multi-gate distributed drive structure may include two symmetrical GaN HEMT modules and two drive modules, with each GaN HEMT module electrically connected to at least one drive module. Specifically, the two GaN HEMT modules are a first HEMT module and a second HEMT module. The two drive modules are a first HEMT module driver 20 and a second HEMT module driver 22. The first HEMT module driver 20 and the second HEMT module driver 22 are independently configured to ensure the flexibility and reliability of the drive. This independent configuration can reduce mutual interference between modules and improve the system's response speed and control accuracy. The first HEMT module driver 20 is electrically connected to the first HEMT module via a first HEMT module connection line 21. The second HEMT module driver 22 is electrically connected to the second HEMT module via a second HEMT module connection line 23. Figure 6 This is the optimal technical solution, with two GaN HEMT modules arranged symmetrically from left to right, and an integrated driver module located in the middle, driving both GaN HEMT modules. This symmetrical layout design not only significantly reduces the impact of parasitic parameters and improves the overall circuit performance, but the integrated driver module also enables on-chip synchronization, ensuring that both GaN HEMT modules receive precise drive signals simultaneously. This achieves high-speed and synchronous drive circuit operation, further improving response speed and efficiency.
[0043] This invention effectively reduces the parasitic inductance between the far-end gate array and the gate electrode by employing multiple gate electrodes, thereby enabling the entire chip's gate array to be driven more uniformly. This improvement not only significantly increases switching speed but also drastically reduces energy loss. In practical applications, while it is acceptable to maintain a relatively consistent electrical signal transmission distance between each gate strip and its corresponding driving module, excessive pursuit of perfect consistency is unnecessary and could lead to wasted chip area, thus affecting overall performance. The core of this invention lies in its symmetrical layout. Specifically, one main switching GaN is arranged on each of the left and right sides, while two driving GaNs are arranged in the middle. This symmetrical layout not only optimizes the electrical signal transmission path but also further improves the chip's overall operating efficiency and stability.
[0044] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A multi-gate distributed driving structure for a GaN chip, comprising a GaN HEMT module and a driving module connected to the GaN HEMT module, characterized in that: The GaN HEMT module has multiple gates, and the multiple gates are spaced apart along a direction parallel to the surface of the GaN HEMT module, wherein each gate is electrically connected to a driving module. The multi-gate distributed driving structure includes a gate array, which includes multiple gate strips spaced apart from each other and a gate bus; the multiple gate strips are connected in parallel to each other through the gate bus to form a tight mesh structure covering the entire surface of the GaN HEMT module; multiple gates are connected in parallel through the gate bus. The plurality of gates include a first gate and a second gate, which are led out from the middle position of the gate array and maintain a left-right symmetrical layout; The gate bus uses a top layer of metal and is disposed above multiple gate bars; the first gate and the second gate are connected to the multiple gate bars by means of two layers of metal interconnection, and through holes are provided between each layer of metal; The GaN HEMT module and the driving module are stacked together.
2. The multi-gate distributed driving structure of the GaN chip according to claim 1, characterized in that, The multi-gate distributed driving structure includes multiple driving modules, each of which is electrically connected to a corresponding gate.
3. The multi-gate distributed driving structure for GaN chips according to claim 2, characterized in that, At least two of the gates are electrically connected to the same drive module.
4. The multi-gate distributed driving structure of the GaN chip according to claim 2, characterized in that, The multi-gate distributed driving structure includes multiple GaN HEMT modules, and each GaN HEMT module is electrically connected to at least one driving module.
5. The multi-gate distributed driving structure of the GaN chip according to any one of claims 1-4, characterized in that, The GaN HEMT module and the driving module are arranged in parallel on a working plane.
6. The multi-gate distributed driving structure of the GaN chip according to claim 1, characterized in that, The GaNHEMT module and the driving module are integrated in the same chip; and / or, the driving module uses a HEMT device.
7. A switching circuit unit, characterized in that, The GaN chip includes a multi-gate distributed driving structure as described in any one of claims 1-6.