Wiring board and method for manufacturing wiring board

Abstract

The invention provides a wiring substrate and a method for manufacturing the wiring substrate. A conductor layer and an insulating layer are well adhered. A wiring board according to an embodiment includes a first insulating layer (111), a first conductor layer (121) formed on the first insulating layer (111), and a second insulating layer formed on the first insulating layer (111) and the first conductor layer (121). The first conductor layer (121) includes wiring having a minimum value of wiring width of 3 [mu] m or less and a minimum value of wiring interval of 3 [mu] m or less, and a mesh-like uneven surface (Wrp) is formed on a side surface of the first conductor layer (121), and the mesh-like uneven surface (Wrp) is not formed on an upper surface of the first conductor layer (121).

Description

Technical Field

[0001] This invention relates to wiring substrates and methods for manufacturing wiring substrates. Background Technology

[0002] Patent Document 1 discloses a printed wiring substrate on which conductive circuits are formed on a resin insulating layer. The surface of the conductive circuits is roughened by a chemical solution, and a resin insulating layer is further formed on the conductive circuits.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2000-252622

[0004] In Patent Document 1, the surfaces (side and top surfaces) of the conductor circuit are roughened by etching based on a chemical solution. It is argued that achieving the target wiring thickness is sometimes difficult within the wiring contained in the conductor circuit. Summary of the Invention

[0005] The wiring substrate of the present invention includes: a first insulating layer; a first conductor layer formed on the first insulating layer; and a second insulating layer formed on the first insulating layer and the first conductor layer. The first conductor layer includes wiring with a minimum wiring width of 3 μm or less and a minimum wiring spacing of 3 μm or less. A mesh-like irregularity is formed on the side surface of the first conductor layer, but the mesh-like irregularity is not formed on the upper surface of the first conductor layer.

[0006] The method for manufacturing a wiring substrate according to the present invention includes the following steps: forming a metal film layer on a first insulating layer; forming a resist layer with openings on the metal film layer; and forming a plating film layer on the metal film layer within the openings. The step of forming the resist layer includes the following steps: exposing the resist layer by direct imaging exposure to form the openings with mesh-like irregularities on the sidewalls; the step of forming the plating film layer includes the following steps: forming an irregular shape on the side of the plating film layer, molding the mesh-like irregularities.

[0007] According to an embodiment of the present invention, a wiring substrate is provided, comprising a first conductor layer and a second insulating layer that are well bonded by forming a mesh-like irregularity on the side of a first conductor layer, and a wiring of a desired thickness formed on the upper surface of the first conductor layer without forming a mesh-like irregularity. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view illustrating an example of a wiring substrate according to one embodiment of the present invention.

[0009] Figure 2 yes Figure 1 An enlarged view of region II in the image.

[0010] Figure 3 This is a perspective view illustrating the conductor layer included in the wiring substrate of the embodiment.

[0011] Figure 4 This is a side view of the conductor layer included in the wiring substrate illustrating the embodiment.

[0012] Figure 5A It is shown Figure 1 A cross-sectional view of an example of a method for manufacturing a wiring substrate.

[0013] Figure 5B It is shown Figure 1 A cross-sectional view of an example of a method for manufacturing a wiring substrate.

[0014] Figure 5C It is shown Figure 1 A cross-sectional view of an example of a method for manufacturing a wiring substrate.

[0015] Figure 5D It is shown Figure 1 A cross-sectional view of an example of a method for manufacturing a wiring substrate.

[0016] Figure 5E It is shown Figure 1 A cross-sectional view of an example of a method for manufacturing a wiring substrate.

[0017] Figure 5F It is shown Figure 1 A cross-sectional view of an example of a method for manufacturing a wiring substrate.

[0018] Figure 5G It is shown Figure 1 A three-dimensional view of the resist layer in the manufacturing method of the wiring substrate shown.

[0019] Figure 5H It is shown Figure 1 A side view of the resist layer in the manufacturing method of the wiring substrate shown.

[0020] Figure 5I It is shown Figure 1 A diagram illustrating an example of a method for manufacturing a wiring substrate.

[0021] Figure 5J It is shown Figure 1 A diagram illustrating an example of a method for manufacturing a wiring substrate.

[0022] Figure 5K It is shown Figure 1 A diagram illustrating an example of a method for manufacturing a wiring substrate.

[0023] Figure 5L It is shown Figure 1 A diagram illustrating an example of a method for manufacturing a wiring substrate.

[0024] Figure 5M It is shown Figure 1 A diagram illustrating an example of a method for manufacturing a wiring substrate.

[0025] Figure 5N It is shown Figure 1 A diagram illustrating an example of a method for manufacturing a wiring substrate.

[0026] Figure 5O It is shown Figure 1 A diagram illustrating an example of a method for manufacturing a wiring substrate.

[0027] Label Explanation

[0028] 1: Wiring substrate; 11: Insulating layer; 12: Conductor layer; 13: Via conductor; 111: First insulating layer; 112: Second insulating layer; 121: First conductor layer; 122: Second conductor layer; 12a: Metal film layer; 12b: Plating film layer; 1F: First side; 1B: Second side; Lf, Lb: Solder resist layer; Wrp, Rrp: Undated and recessed; Wp, Rp: Raised portion; Wr, Rr: Recessed portion. Detailed Implementation

[0029] Next, a wiring substrate according to one embodiment will be described with reference to the accompanying drawings. Figure 1 This is a cross-sectional view of wiring substrate 1, showing one example of a wiring substrate according to one embodiment. Furthermore, the wiring substrate 1 shown is merely an example. The layered structure of the wiring substrate in this embodiment, as well as the number of conductor layers and insulating layers, are not limited to [specific details needed]. Figure 1 The diagram shows the stacked structure of the wiring substrate 1 and the respective numbers of conductor layers and insulating layers included in the wiring substrate 1. Furthermore, the accompanying drawings do not intend to show exact ratios of the structural elements, but rather depict them in a manner that facilitates understanding of the features of the invention.

[0030] The wiring substrate 1 has two surfaces perpendicular to its thickness direction (a first surface 1F and a second surface 1B opposite to the first surface 1F). The wiring substrate 1 has alternating layers of insulating layers 11 and conductor layers 12. The conductor layers 12, separated by an insulating layer 11, are connected to each other via conductors 13. In the illustrated example, the conductor layer 12 forming part of the first surface 1F is formed in a pattern with multiple conductor pads 12fp. The conductor layer 12 forming part of the second surface 1B is formed in a pattern with multiple conductor pads 12bp.

[0031] In addition, Figure 1In the description of the wiring substrate 1 shown, the first surface 1F side of the wiring substrate 1 is referred to as "upper" or "upper side", and the second surface 1B side of the wiring substrate 1 is referred to as "lower" or "lower side". In addition, among the various structural elements, the surface of the wiring substrate 1 facing the first surface 1F side is also referred to as the "upper surface", and the surface of the wiring substrate 1 facing the second surface 1B side is also referred to as the "lower surface".

[0032] The insulating layer 11 can be formed using insulating resins such as epoxy resin and phenolic resin. The insulating layer 11 may contain any of the following: fluoropolymer, liquid crystal polymer (LCP), fluorinated vinyl resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI).

[0033] Examples of conductors constituting conductor layer 12 and via conductor 13 include copper and nickel, with copper being preferred. Conductor layer 12 and via conductor 13 have a multilayer structure. Conductor layer 12 and via conductor 13 preferably have a two-layer structure comprising a metal film layer 12a comprising a sputtered or electroless copper film layer and a plating film layer 12b comprising an electroplated copper film layer.

[0034] The via conductor 13, penetrating the insulating layer 11 in the thickness direction, is formed by filling the through hole 11a of the insulating layer 11 with a conductive material. Figure 1 In this example, the via conductor 13 is integrally formed with the conductor layer 12 disposed on its upper side. Therefore, the via conductor 13 and the conductor layer 12 can be formed from the same metal film layer and the same plating film layer.

[0035] exist Figure 1 In this example, the wiring substrate 1 has a solder resist layer Lf formed on the uppermost insulating layer 11 and conductor layer 12, and a solder resist layer Lb formed below the lowermost insulating layer 11 and conductor layer 12. The solder resist layers Lf and Lb are formed, for example, using photosensitive polyimide resin or epoxy resin. An opening Lfa is formed in the solder resist layer Lf, through which the conductor pad 12fp is exposed. An opening Lba is formed in the solder resist layer Lb, through which the conductor pad 12bp is exposed. That is, the first surface 1F of the wiring substrate 1 includes the surface of the solder resist layer Lf and the surface of the conductor pad 12fp, and the second surface 1B of the wiring substrate 1 includes the surface of the solder resist layer Lb and the surface of the conductor pad 12bp.

[0036] The first surface 1F of the wiring substrate 1 constitutes a component mounting surface in the wiring substrate 1 that can connect to external electronic components. When the wiring substrate 1 itself is mounted on an external element such as an external wiring substrate (e.g., the motherboard of any electrical device), the second surface 1B of the wiring substrate 1, which is opposite to the component mounting surface, can be a connection surface that connects to the external element.

[0037] The conductor layer 12 included in the wiring substrate 1 is patterned with a prescribed conductor pattern. The conductor layer 12 contains relatively fine wiring and has a relatively high density of circuit wiring. Specifically, the conductor layer 12 of the wiring substrate 1 has high-density wiring, i.e., wiring FW, with a relatively small wiring width and wiring spacing (wiring interval). The minimum value of the wiring FW is 3 μm or less, and the minimum value of the wiring spacing is 3 μm or less. Furthermore, in the illustrated example, four of the multiple conductor layers 12 included in the wiring substrate 1 have wiring FW as high-density wiring. In the wiring substrate 1, any number of conductor layers 12 can have wiring FW. The number of conductor layers 12 having wiring FW as possessed by the wiring substrate 1 is not limited.

[0038] When the conductor layer 12 is formed to include the wiring FW as described above, it is sometimes preferable to form the via conductors 13 that connect the conductor layers 12 opposite each other across the insulating layer 11 with a fine spacing. Small-diameter via conductors 13 can be formed in the insulating layer 11 using through holes 11a. Therefore, the insulating layer 11 may contain inorganic fillers such as particles made of silicon dioxide (SiO2), alumina, or mullite, but to facilitate the formation of small-diameter through holes 11a, it is sometimes preferable that the insulating layer 11 does not contain inorganic fillers. Furthermore, the insulating layer 11 preferably does not contain a core material (reinforcing material) made of glass fiber, aramid fiber, etc. In the wiring substrate 1, the thickness of the insulating layer 11 is, for example, 3 μm to 15 μm, and the thickness of the conductor layer 12 is 5 μm or less.

[0039] Next, refer to Figures 2-4 The structure of the conductor layer 12 included in the wiring substrate 1 is described in detail. Furthermore, in reference to... Figures 2-4 In the explanation, for ease of explanation, the following will be used: Figure 2 The bottommost insulating layer shown is called the first insulating layer 111, and the conductor layer formed in contact with the upper surface of the first insulating layer 111 is called the first conductor layer 121. Furthermore, the insulating layers formed on the first conductor layer 121 and on the first insulating layer 111 exposed from the conductor pattern of the first conductor layer 121 are called the second insulating layer 112, and the conductor layer formed in contact with the upper surface of the second insulating layer 112 is called the second conductor layer 122.

[0040] exist Figure 2 The text is a jumbled collection of characters and phrases, seemingly from different sources and lacking coherent sentences. A direct translation wouldn Figure 1An enlarged view of region II, enclosed by a single-dotted line. As shown, a raised / lowered Wrp is formed on the side of the conductor pattern in the first conductor layer 121 containing the wiring FW. Specifically, as described later in the wiring substrate manufacturing method, the raised / lowered Wrp is obtained by molding a raised / lowered shape on the side of the plating film layer 12b to form the sidewall of the opening of the resist layer used for plating during the formation of the plating film layer 12b. Therefore, the raised / lowered Wrp is formed on the portion of the first conductor layer 121 formed by the plating film layer 12b, but not on the portion formed by the metal film layer 12a. Furthermore, the raised / lowered Wrp is not formed on the upper surface of the first conductor layer 121. Here, "molded" means forming a shape that reverses the raised / lowered shape on the object (in this case, the plating film layer 12b).

[0041] It is believed that by forming uneven Wrp on the side surface of the first conductor layer 121, the second insulating layer 112 covering the first conductor layer 121 is firmly and tightly bonded to the side surface of the first conductor layer 121. The upper surface of the first conductor layer 121 without the uneven Wrp has good flatness; therefore, it is believed that finer wiring FW can be formed with a thickness more faithful to the design value. Furthermore, the upper surface of the second insulating layer 112, located directly above the upper surface of the first conductor layer 121, can also be formed with good flatness. Therefore, it is believed that the conductor pattern of the second conductor layer 122, formed in contact with the upper surface of the second insulating layer 112, can also be formed with dimensions more faithful to the design value.

[0042] Next, refer to Figure 3 as well as Figure 4 The irregular Wrp formed on the side of the first conductor layer 121 is described in detail. Figure 3 Shown along Figure 2 A perspective view of the first conductor layer 121 as seen from the line of sight indicated by arrow III. Figure 4 The text shows how to use it along with... Figure 2 The side of the first conductor layer 121 is viewed through the line of sight perpendicular to arrow IV, showing the side of the first conductor layer 121. Additionally, Figure 3 and Figure 4 The second insulating layer 112 covering the first conductor layer 121 is omitted from the drawing.

[0043] like Figure 3 and Figure 4As shown, the uneven Wrp formed on the side of the first conductor layer 121 has a mesh-like shape. Specifically, the uneven Wrp is formed as a mesh-like uneven surface including multiple protrusions Wp and the boundaries between the multiple protrusions Wp, i.e., concave portions Wr. Here, "mesh-like" refers to a pattern formed by the boundaries between units corresponding to the opening portions of the mesh and units corresponding to the rope (strand) portions of the mesh. That is, the uneven Wrp has multiple protrusions Wp corresponding to multiple units of the mesh and concave portions Wr corresponding to the units of the mesh and the boundaries between the units.

[0044] like Figure 4 As shown, in the mesh-like unevenness Wrp formed on the side of the first conductor layer 121, the planar shape of each of the plurality of protrusions Wp corresponding to the mesh unit (in) Figure 4 Shapes identified within the field of view and planar area (in Figure 4 The area identified in the field of view is different. Furthermore, the extension direction of the groove-shaped recess Wr, which corresponds to the boundary between the mesh units, is not limited to a specific direction; the recess Wr extends in an irregular direction depending on the planar shape of the protrusion Wp. It is assumed that the first conductor layer 121 and the second insulating layer 112 (refer to...) extend in multiple different directions through the recess Wr. Figure 2 The tightness of the seal can achieve a more robust seal.

[0045] Specifically, the maximum planar area of ​​the protrusions Wp corresponding to the mesh units in the mesh-like unevenness Wrp formed on the side of the first conductor layer 121 is preferably 0.1 μm. 2 The following ensures that the number of protrusions Wp per unit area on the side surface of the first conductor layer 121 is greater than the desired number. Therefore, it is considered that the first conductor layer 121 and the second insulating layer 112 (see reference) can be integrated. Figure 2 A more secure and tighter seal.

[0046] The mesh-like uneven Wrp is preferably formed such that the shortest distance in the direction perpendicular to the side of the first conductor layer 121 between the highest point of the plurality of protrusions Wp constituting the uneven Wrp (the most prominent point in the direction perpendicular to the side of the first conductor layer 121) and the deepest point of the concave Wr (the most recessed point in the direction perpendicular to the side of the first conductor layer 121) in the direction perpendicular to the side of the first conductor layer 121 is 0.3 μm or more and 1.0 μm or less. It is believed that within this range of distance between the highest point of the protrusion Wp and the deepest point of the concave Wr, the width of the conductor pattern of the first conductor layer 121 more faithfully reflects the designed dimensions, and it is possible to achieve a connection between the first conductor layer 121 and the second insulating layer 112 (see reference 112). Figure 2 () good seal.

[0047] Furthermore, in the wiring substrate of the embodiment, any one of the conductor layers containing the wiring FW in the conductor layer 12 constituting the wiring substrate may have a mesh-like unevenness. Alternatively, mesh-like unevenness may be formed on all sides of the conductor layers included in the wiring substrate.

[0048] Next, refer to Figures 5A to 5O To manufacture Figure 1 Taking the example of wiring substrate 1 shown, a method for manufacturing a wiring substrate according to one embodiment will be described. Furthermore, the structural elements formed in the manufacturing method described below can be used in [various applications] unless otherwise specified. Figure 1 The wiring substrate 1 is formed from the materials exemplified as the materials of the corresponding structural elements in the description of the wiring substrate 1. Furthermore, in the following description of the manufacturing method of the wiring substrate 1, the side closest to the core material GS constituting the support substrate SP is referred to as "lower" or "lower side," and the side furthest from the support substrate SP is referred to as "upper" or "upper side." Therefore, the surface of each element constituting the wiring substrate 1 facing the support substrate SP is also referred to as the "lower surface," and the surface facing the side opposite to the support substrate SP is also referred to as the "upper surface." Additionally, in the description of the manufacturing method, the reference... Figures 2-4 Similarly, for ease of explanation, the insulating layer closest to the support substrate SP is referred to as the first insulating layer 111, the conductor layer formed on the first insulating layer 111 in contact with ground is referred to as the first conductor layer 121, the insulating layer formed on the first conductor layer 121 is referred to as the second insulating layer 112, and the conductor layer formed on the second insulating layer 112 in contact with ground is referred to as the second conductor layer 122.

[0049] First, such as Figure 5A As shown, a support substrate SP is prepared. In the wiring substrate manufacturing method of the embodiment, the support substrate SP used has good flatness on two surfaces perpendicular to its thickness direction. The support substrate SP includes, for example, a core material GS as a glass substrate, a first metal film layer ML1 stacked on both sides of the core material GS, and a second metal film layer ML2 stacked on the first metal film layer ML1 with an adhesive layer AL in between. The first metal film layer ML1 and the second metal film layer ML2 are metal film layers formed, for example, by chemical plating or sputtering. The first metal film layer ML1 and the second metal film layer ML2 are depicted as single layers in the figure, but may also contain multiple layers. For example, the first metal film layer ML1 and the second metal film layer ML2 may each have a double-layer structure composed of a titanium layer and a copper layer. The adhesive layer AL may, for example, contain an azobenzene polymer adhesive that can be attached or detached by light irradiation. In addition to a glass substrate, the support substrate SP may also include any of the following as the core material GS: a silicon substrate, a metal substrate, or a ceramic substrate.

[0050] Next, as Figure 5BAs shown, a conductor layer 12 having multiple conductor pads 12bp is formed on a support substrate SP. In the formation of the conductor layer 12 in contact with the support substrate SP, for example, an anti-plating agent is formed on a second metal film layer ML2, and openings corresponding to the formation areas of the conductor pads 12bp are formed on the anti-plating agent, for example, using photolithography. Next, a plating film is formed within the openings by electroplating the second metal film layer ML2 as a seed layer. After forming the plating film, the anti-plating agent is removed, and a... Figure 5B The state shown.

[0051] Next, as Figure 5C As shown, a first insulating layer 111 is laminated, covering the upper and side surfaces of the conductor layer 12 and the surface of the support substrate SP exposed from the conductor pattern of the conductor layer 12. For example, insulating resins such as epoxy resin and phenolic resin can be used as the first insulating layer 111. Fluoropolymers, liquid crystal polymers (LCP), fluorinated vinyl resins (PTFE), polyester resins (PE), and modified polyimide resins (MPI) can also be used. The first insulating layer 111 is formed by hot-pressing these resins, which are molded into a film. Next, the via conductor 13 (see reference) in the first insulating layer 111... Figure 1 The through hole 11a is formed at the formation location by irradiation, for example, by a carbon dioxide laser or an excimer laser.

[0052] Although not illustrated, the formation of the through-hole 11a based on laser irradiation such as a carbon dioxide laser can be achieved by simultaneously protecting the upper surface of the first insulating layer 111 with a protective film such as a polyethylene terephthalate (PET) film while irradiating with a laser. This forms both a protective film and the through-hole 11a in the first insulating layer 111. Furthermore, after forming the through-hole 11a, a descaling process can be performed to prevent a decrease in the sealing force of the via conductor 13 and an increase in resistance caused by processing modifications generated at the bottom of the through-hole 11a. The descaling process is preferably a dry descaling process using plasma gas. The descaling process can also be performed while the surface of the first insulating layer 111 is protected with a protective film such as a polyethylene terephthalate (PET) film.

[0053] In addition, Figure 5C And the following references Figures 5D to 5F , Figures 5I to 5O The diagram shows a laminate formed on one surface of a support substrate SP, while illustrations of laminates that could be formed on the opposite surface are omitted. However, it is also possible to form the same shape and number of laminates on the opposite surface of the support substrate SP, or to form conductor layers and insulating layers with different shapes and numbers than on one surface, or to omit such conductor layers and insulating layers.

[0054] Next, as Figure 5D As shown, a metal film layer 12a is formed on the inner wall of the through hole 11a and on the surface of the first insulating layer 111 by chemical plating or sputtering. Preferably, the metal film layer 12a can be a sputtered film formed by sputtering. Furthermore, if a protective film is provided on the surface of the first insulating layer 111 during the formation of the through hole 11a and / or during the desmearing process, the protective film can be peeled off before the formation of the metal film layer 12a.

[0055] Next, as Figure 5E As shown, a dry film resist, such as a photosensitive epoxy resin, is bonded onto the metal film layer 12a to form a resist layer RL. Next, the resist layer RL is exposed. In the wiring substrate manufacturing method of this embodiment, direct imaging exposure is performed during the exposure step of the resist layer RL. In direct imaging exposure, no photomask is used, and the resist layer RL is directly irradiated with irradiation light L. As the light source for the irradiation light L, a semiconductor laser with a wavelength of 350 nm to 410 nm or an ultra-high pressure mercury lamp can be used, for example. The conductor pattern (see reference) is formed according to the conductor pattern of the first conductor layer 121 to be formed on the first insulating layer 111. Figure 1 The corresponding pattern is drawn by scanning the illumination light L. During exposure, the illumination point of the illumination light L is repeatedly scanned multiple times for the portion of the resist layer RL that should be exposed. That is, the specific portion of the resist layer RL that should be exposed is repeatedly exposed by the illumination light L.

[0056] Next, as Figure 5F As shown, a conductor pattern is formed on the resist layer RL and a first conductor layer 121 to be formed on the first insulating layer 111 (see reference). Figure 1 The resist pattern corresponds to the above-mentioned exposure process of the resist layer RL. Specifically, after the exposure process of the resist layer RL is completed, for example, the resist layer RL is developed using a developing solution composed of an aqueous sodium carbonate solution containing surfactants, defoamers, and a small amount of organic solvent for promoting development, to form openings RLo. The openings RLo corresponding to the wiring FW to be formed on the first insulating layer 111 are formed such that the minimum width of the opening is 3 μm or less, and the minimum spacing between the openings is 3 μm or less.

[0057] Refer to the above Figure 5EIn the exposure of the resist layer RL described above, when the illumination light L illuminates the resist layer RL, a standing wave is generated by the illumination light L and the reflected light after the illumination light L is reflected by the metal film layer 12a. Due to the influence of this standing wave, the concentration of the photosensitive material contained in the resist layer RL varies in the thickness direction of the resist layer RL. In direct imaging exposure, scanning is performed while repeatedly illuminating the specific area to be exposed with the illumination light L. Multiple exposures based on this illumination light L are believed to cause irregular concentrations of the photosensitive material contained in the resist layer RL in both the thickness direction and the planar direction of the resist layer RL. Therefore, referring to the above... Figure 5F The sidewall (inner wall surface) of the opening RLo, which is formed as a result of the development of the resist layer RL, has an uneven shape caused by the irregular concentration of the photosensitive material.

[0058] Figure 5G Shown along Figure 5F A three-dimensional view showing the resist layer RL as seen from the line of sight of arrow G. Additionally, in Figure 5H The text shows how to use it along with... Figure 5F A side view of the sidewall of the opening RLo in the resist layer RL, viewed through a vertical arrow H. (See image for reference.) Figure 5G As shown, a bump Rrp is formed on the sidewall of the opening RLo of the resist layer RL. Specifically, the bump Rrp is formed as a mesh-like bump structure including multiple recesses Rr and convex portions Rp that serve as the boundaries between the multiple recesses Rr. That is, the bump Rrp has multiple recesses Rr corresponding to multiple units of the mesh and convex portions Rp corresponding to the units of the mesh and the boundaries between the units.

[0059] like Figure 5H As shown, in the mesh-like unevenness Rrp formed in the resist layer RL, the planar shape of each of the multiple recesses Rr corresponding to the mesh unit (in) Figure 5H The shapes recognized in the field of view are different. Additionally, the planar areas of the multiple recesses Rr corresponding to the mesh units (in...) Figure 5H The area identified in the field of view is different. The mesh-like unevenness Rrp can have a maximum planar area of ​​0.1μm for each concave part Rr. 2 The following method is used to form it. Furthermore, the extension direction of the protrusion Rp corresponding to the mesh cells and cell boundaries is not limited to a specific direction; the protrusion Rp extends in an irregular direction depending on the planar shape of the concave Rr. Moreover, the maximum value of the planar area of ​​the concave Rr in the concave-convex Rrp can be appropriately controlled by a reference. Figure 5E The explanation explains how to adjust the exposure conditions, such as the spot diameter, wavelength, and scanning speed of the illumination light L when directly imaging the photoresist layer RL using the illumination light L.

[0060] Next, as Figure 5I As shown, by electroplating the metal film layer 12a as the power supply layer, a plating film layer 12b is formed within the opening RLo of the resist layer RL. The interior of the through hole 11a is completely filled by the plating film layer 12b, forming a via conductor 13. The portion of the plating film layer 12b formed within the opening RLo that contacts the sidewall of the opening RLo is molded into a mesh-like textured surface Rrp (see reference). Figure 5G (The shape of)

[0061] Next, the resist layer RL is removed using an alkaline stripping solution. The removal of the resist layer RL creates a molded mesh-like textured surface (see reference). Figure 5G The sides of the metal film layer 12b, with its mesh-like uneven shape, are exposed. After removing the resist layer RL, portions of the metal film layer 12a not covered by the metal film layer 12b are removed by etching. The sides of the metal film layer 12a exposed by this etching do not have a mesh-like uneven shape. Figure 5J As shown, a first conductor layer 121 is formed having a double-layer structure consisting of a metal film layer 12a and a plated film layer 12b.

[0062] Next, as Figure 5K As shown, a second insulating layer 112 is formed on a first conductor layer 121 and a first insulating layer 111 exposed from the conductor pattern of the first conductor layer 121. Furthermore, a second conductor layer 122 is formed on the second insulating layer 112 using the same method as the formation of the first insulating layer 111 and the first conductor layer 121. During the formation of the second insulating layer 112, the uncured second insulating layer 112 enters the mesh-like, uneven recesses formed on the side of the first conductor layer 121, resulting in a good seal between the second insulating layer 112 and the first conductor layer 121. Furthermore, the upper surface of the first conductor layer 121, where the mesh-like uneven shape is not formed, has good flatness; therefore, the upper surface of the second insulating layer 112 is also formed with relatively good flatness. It is believed that the conductor pattern of the second conductor layer 122, formed in contact with the upper surface of the second insulating layer 112, can be formed to more faithfully reflect the design dimensions.

[0063] Next, as Figure 5L As shown, using the same method as the method for forming the first insulating layer 111 and the first conductor layer 121 described above, an insulating layer 11 and a conductor layer 12 of a desired number of layers are stacked on top of the second conductor layer 122 and the second insulating layer 112. The uppermost conductor layer 12 is formed as a pattern including conductor pads 12fp.

[0064] Next, as Figure 5MAs shown, the solder resist layer Lf is formed by forming a photosensitive epoxy resin and polyimide resin layer on the surface of the insulating layer 11 and the conductor layer 12, and the opening Lfa that defines the conductor pad 12fp is formed by photolithography.

[0065] Furthermore, in the wiring substrate manufacturing method of the embodiment, any one of the conductor layers containing fine wiring can be formed by a method including direct imaging exposure of a photoresist layer, and openings with a mesh-like uneven shape can be formed on the sidewalls. All conductor layers constituting the wiring substrate can also be formed by a method including forming mesh-like uneven openings by direct imaging exposure of a photoresist layer. Therefore, for example, in the illustrated example, the conductor layer 12 excluding the wiring FW (the conductor layer 12 in contact with the support substrate SP) can also be formed by a method including forming mesh-like uneven openings using direct imaging exposure. Additionally, the conductor layer 12 excluding the wiring FW can also be formed by a method including forming mesh-like uneven openings by direct imaging exposure of a photoresist layer.

[0066] Next, as Figure 5N As shown, the support substrate SP is removed. The lower surface of the second metal film layer ML2 under the conductor pad 12bp is exposed. During the removal of the support substrate SP, the second metal film layer ML2 of the support substrate SP is peeled off after the adhesive layer AL is softened by irradiation, for example, with a laser.

[0067] Next, the second metal film layer ML2 is removed by etching, exposing the lower surface of the conductor pad 12bp and the lower surface of the first insulating layer 111. A solder resist layer Lb is formed on the lower surfaces of the conductor pad 12bp and the first insulating layer 111 by forming photosensitive epoxy resin and polyimide resin layers on the surfaces of the insulating layer 11 and the conductor layer 12. Openings Lba defining the conductor pad 12bp are formed on the solder resist layer Lb using photolithography. The fabrication of the wiring substrate 1 is now complete.

[0068] The wiring substrate of the embodiments is not limited to having the structures illustrated in the figures, the structures illustrated in this specification, or the materials used. For example, the wiring substrate of the embodiments can have any number of insulating layers and conductor layers. In addition to conductor pads, conductor patterns may be included in the uppermost and lowermost conductor layers of the wiring substrate.

[0069] The method for manufacturing the wiring substrate in the embodiment is not limited to the one described above. Figures 5A to 5OThe methods described can be arbitrarily changed in terms of conditions, order, etc. The method for manufacturing a wiring substrate according to the embodiment may include at least the following steps: forming a resist layer with mesh-like openings on the sidewalls by direct imaging exposure on a metal film layer, and forming a plating film layer with molded mesh-like openings within the openings. Depending on the structure of the currently manufactured wiring substrate, some steps may be omitted, or other steps may be added.

Claims

1. A wiring substrate comprising: First insulating layer; A first conductor layer is formed on the first insulating layer; as well as A second insulating layer is formed on the first insulating layer and the first conductor layer. in, The first conductor layer includes wiring with a minimum wiring width of 3 μm and a minimum wiring spacing of 3 μm. A mesh-like pattern of irregularities is formed on the side surface of the first conductor layer. The mesh-like irregularities are not formed on the upper surface of the first conductor layer.

2. The wiring substrate according to claim 1, wherein, The first conductor layer includes a metal film layer in contact with the first insulating layer and a plating film layer formed on the metal film layer. The mesh-like irregularities are formed on the coated film layer, but not on the metal film layer.

3. The wiring substrate according to claim 1, wherein, The mesh-like protrusions have protrusions corresponding to the mesh units and recesses corresponding to the boundaries between the units.

4. The wiring substrate according to claim 3, wherein, The maximum planar area of ​​the unit is 0.1 μm. 2 the following.

5. The wiring substrate according to claim 3, wherein, The shortest distance between the deepest part of the concave portion and the highest part of the convex portion in a direction perpendicular to the side surface is more than 0.3 μm and less than 1.0 μm.

6. The wiring substrate according to claim 1, wherein, A second conductor layer is formed on the second insulating layer.

7. A method for manufacturing a wiring substrate, the method comprising the following steps: A metal film layer is formed on the first insulating layer; An open-ended resist layer is formed on the metal film layer; and A coating layer is formed on the metal film layer within the opening. in, The step of forming the resist layer includes the following steps: exposing the resist layer by direct imaging exposure to form the openings with mesh-like irregularities on the sidewalls. The step of forming the coating layer includes the following steps: forming a mesh-like uneven shape on the side of the coating layer.

8. The method for manufacturing a wiring substrate according to claim 7, wherein, The maximum planar area of ​​the mesh-like unevenness forming the mesh unit is 0.1 μm. 2 the following.

9. The method for manufacturing a wiring substrate according to claim 7, wherein, The step of forming the opening includes the following steps: forming an opening with a minimum width of 3 μm and a minimum spacing of 3 μm between the openings.

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