Wiring board

Abstract

The invention provides a wiring board which suppresses stripping of a via hole conductor and a conductor layer. A wiring board (1) according to an embodiment includes: a first conductor layer (21); an insulating layer (31) covering the first conductor layer (21); a second conductor layer (22) formed on the surface of the insulating layer (31); and a via hole conductor (4) which is formed inside a hole (5) penetrating the insulating layer (31) and connects the first conductor layer (21) and the second conductor layer (22). The hole (5) includes: a first portion (51) whose width is reduced on the first conductor layer (21) side; a second portion (52) which is located on the first conductor layer (21) side of the first portion (51) and which expands in width on the first conductor layer (21) side; and a third portion (53) which is located on the first conductor layer (21) side of the second portion (52) and has a reduced width on the first conductor layer (21) side.

Description

Technical Field

[0001] This invention relates to wiring substrates. Background Technology

[0002] Patent Document 1 discloses a wiring substrate comprising via conductors that fill vias through an insulating layer. To prevent cracking and peeling between the via conductor and the via pad, the bottom portion of the via conductor is formed of crystalline particles smaller than those forming other portions.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-17639

[0004] In the wiring substrate disclosed in Patent Document 1, precise control of conditions is required during electroplating to form the via bottom portion with smaller crystal particles, thus sometimes complicating the manufacturing process of the wiring substrate. Furthermore, it is believed that a useless interface is created between the via bottom portion, formed by crystal particles of different sizes, and other portions. However, if the via bottom portion is not formed by small crystal particles, cracks and peeling sometimes occur between the via conductor and the via pad. Summary of the Invention

[0005] The wiring substrate of the present invention includes: a first conductor layer; an insulating layer covering the first conductor layer; a second conductor layer formed on the surface of the insulating layer; and a via conductor formed inside a hole penetrating the insulating layer, connecting the first conductor layer and the second conductor layer. Furthermore, the via includes: a first portion that narrows in width on the side of the first conductor layer; a second portion located on the first conductor layer side of the first portion and widening in width on the side of the first conductor layer; and a third portion located on the first conductor layer side of the second portion and narrowing in width on the side of the first conductor layer.

[0006] According to embodiments of the present invention, in wiring substrates that are easy to manufacture, it is sometimes possible to suppress the peeling of via conductors from conductor layers. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view illustrating an example of a wiring substrate according to an embodiment.

[0008] Figure 2 yes Figure 1 An enlarged view of part II of the wiring board.

[0009] Figure 3 This is a photograph of the cross-section of the via conductor in the wiring substrate of the embodiment.

[0010] Figure 4This is a cross-sectional view showing a first modified example of the wiring substrate according to the embodiment.

[0011] Figure 5 This is a cross-sectional view showing a second modified example of the wiring substrate according to the embodiment.

[0012] Figure 6A This is a cross-sectional view illustrating an example of a wiring substrate in a manufacturing process.

[0013] Figure 6B This is a cross-sectional view illustrating an example of a wiring substrate in a manufacturing process.

[0014] Figure 6C This is a cross-sectional view illustrating an example of a wiring substrate in a manufacturing process.

[0015] Figure 6D This is a cross-sectional view illustrating an example of a wiring substrate in a manufacturing process.

[0016] Figure 6E This is a cross-sectional view illustrating an example of a wiring substrate in a manufacturing process.

[0017] Figure 6F This is a cross-sectional view illustrating an example of a wiring substrate in a manufacturing process.

[0018] Figure 6G This is a cross-sectional view illustrating an example of a wiring substrate in a manufacturing process.

[0019] Figure 6H This is a cross-sectional view illustrating an example of a wiring substrate in a manufacturing process.

[0020] Label Explanation

[0021] 1: Wiring substrate; 21: Conductor layer (first conductor layer); 22: Conductor layer (second conductor layer); 31-33: Insulating layer; 4, 41, 42: Via conductor; 4b: Plating film; 5, 50: Hole; 51: First part; 52: Second part; 53: Third part; 5a: Wall; B: Hole; L1: Length of the first part; L2: Length of the second part; L3: Length of the third part; W: Hole opening width; θ1: Inclination of the wall of the first part; θ2: Inclination of the wall of the second part. Detailed Implementation

[0022] <Basic Structure of Wiring Board in Implementation>

[0023] The wiring substrate of the present invention is described with reference to the accompanying drawings. Figure 1 Wiring substrate 1 is shown as an example of a wiring substrate used in an embodiment. Figure 2 Show Figure 1 An enlarged view of part II of the wiring substrate 1. Furthermore, the wiring substrates illustrated in the various figures referred to in the following description are merely examples of wiring substrates according to an embodiment. The layered structure of the wiring substrates of the embodiment is not limited to the layered structure of the wiring substrates shown in the figures, and the number of conductor layers and insulating layers included in the wiring substrates of the embodiment is not limited to the number of conductor layers and insulating layers included in the wiring substrates shown in the figures. In addition to the insulating layers and conductor layers present in the wiring substrates shown in the figures, the wiring substrates of the embodiment may include any number of insulating layers and conductor layers, and sometimes may not include all of the insulating layers and conductor layers present in the wiring substrates shown in the figures. Furthermore, in the figures referred to in the following description, specific parts are sometimes depicted in enlarged form for easier understanding of the disclosed embodiments. Therefore, there are cases where the size and length of each structural element are not depicted with accurate ratios to each other.

[0024] like Figure 1 As shown, the wiring substrate 1 includes conductor layers 21 to 24 and insulating layers 31 to 33. The conductor layers 21 to 24 and the insulating layers 31 to 33 are alternately stacked. The stacking direction of these conductor layers and insulating layers is the thickness direction of the wiring substrate 1, hereinafter also referred to as the "Z direction". Figure 1 In the middle, an insulating layer 31 is stacked in such a way that it covers one of the two surfaces of the conductor layer 21 perpendicular to the Z direction. On the side of the insulating layer 31 opposite to the conductor layer 21, the above-mentioned conductor layer and insulating layer are stacked in the order of conductor layer 22, insulating layer 32, conductor layer 23, insulating layer 33 and conductor layer 24.

[0025] In the following description of the wiring substrate of the embodiment, in the wiring substrate 1, the side of conductor layer 24 is also referred to as the "upper side" and the side of conductor layer 21 is also referred to as the "lower side". Therefore, in each conductor layer and each insulating layer, the surface facing the side opposite to conductor layer 21 or the surface facing conductor layer 24 is also referred to as the "upper surface", and the surface facing the side opposite to conductor layer 24 or the surface facing conductor layer 21 is also referred to as the "lower surface".

[0026] Each of the insulating layers 31 to 33 has a via conductor 4 that penetrates it. Each via conductor 4 is formed inside a hole 5 penetrating each insulating layer. Each via conductor 4 connects two conductor layers that sandwich the insulating layer (any one of insulating layers 31 to 33) through which it penetrates. For example, a via conductor 4 penetrating insulating layer 31 connects conductor layer 21 and conductor layer 22. Each via conductor 4 is integrally formed with the conductor layer above it. A via conductor 4 penetrating insulating layer 31 is integrally formed with conductor layer 22, a via conductor 4 penetrating insulating layer 32 is integrally formed with conductor layer 23, and a via conductor 4 penetrating insulating layer 33 is integrally formed with conductor layer 24.

[0027] In the description of the wiring substrate in the embodiment, the conductor layer that contacts the lower surface of each insulating layer is also referred to as the first conductor layer, and the conductor layer that contacts the upper surface of each insulating layer is also referred to as the second conductor layer. Figure 1 In the example, regarding each of the insulating layers 31 to 33, the conductor layer integrally formed with the via conductor 4 penetrating each insulating layer is also referred to as the second conductor layer, and the conductor layer connected to the second conductor layer through the via conductor 4 is also referred to as the first conductor layer. That is, regarding the insulating layer 31, conductor layer 21 can be the first conductor layer with respect to conductor layer 22, and conductor layer 22 can be the second conductor layer with respect to conductor layer 21. Similarly, regarding the insulating layer 32, conductor layer 22 can be the first conductor layer with respect to conductor layer 23, and conductor layer 23 can be the second conductor layer with respect to conductor layer 22. Furthermore, regarding the insulating layer 33, conductor layer 23 can be the first conductor layer with respect to conductor layer 24, and conductor layer 24 can be the second conductor layer with respect to conductor layer 23.

[0028] Thus, the wiring substrate of the embodiment such as wiring substrate 1 has a first conductor layer, such as conductor layer 21, an insulating layer covering the first conductor layer, such as insulating layer 31, and a second conductor layer formed on the surface of the insulating layer, such as conductor layer 22. Furthermore, the wiring substrate of this embodiment also has a via conductor 4 connecting the first conductor layer and the second conductor layer.

[0029] Figure 1 The wiring substrate 1 further includes solder resist 61 covering the lower surface of conductor layer 21 and the lower surface of insulating layer 31, and solder resist 62 covering the upper surface of conductor layer 24 and the upper surface of insulating layer 33. As an example, solder resists 61 and 62 are formed of photosensitive epoxy resin. Openings are formed on each solder resist to expose a predetermined area of ​​conductor layer 21 or conductor layer 24.

[0030] Conductor layers 21 to 24 and via conductor 4 are each formed of any metal having suitable conductivity. Examples of materials constituting these conductive elements include copper, nickel, gold, titanium, palladium, and tungsten. However, the materials of conductor layers 21 to 24 and via conductor 4 are not limited to these metals.

[0031] Conductor layers 21 to 24 and via conductor 4 in Figure 1 It is simplified and depicted as consisting of only one layer, but as Figure 2 As shown, it can also have a multilayer structure composed of two or more metal films. Figure 2 In this example, the conductor layer 21 and the via conductor 4 are composed of a lower layer and an upper layer, the lower layer being composed of a metal film 4a and the upper layer being composed of a plated film 4b. The metal film 4a may be, for example, a copper electroless plated film or a sputtered film, and the plated film 4b may be, for example, a copper electroplated film.

[0032] Insulating layers 31 to 33 are primarily formed of any insulating resin. Examples of insulating resins used to form insulating layers 31 to 33 include epoxy resins, bismaleimide triazine resins (BT resins), phenolic resins, fluoropolymers, liquid crystal polymers (LCPs), acrylic resins, fluorinated vinylidene (PTFE) resins, polyester (PE) resins, and modified polyimide (MPI) resins. These resins constituting insulating layers 31 to 33 are preferably photosensitive resins that react with light, exhibiting photocurability (negative type) by crosslinking upon exposure to ultraviolet light or the like, or photosolvability (positive type) by decomposition upon exposure to light. For example, the example resins primarily constituting insulating layers 31 to 33 may themselves be photosensitive, and insulating layers 31 to 33 may also contain a photosensitizer in addition to the example resins. The photosensitive resins constituting insulating layers 31 to 33 are sometimes more preferably negative type.

[0033] On the other hand, insulating layers 31 to 33 preferably do not contain inorganic particles, such as those composed of silicon oxide or aluminum oxide, which are typically used as fillers to adjust various properties, such as mechanical properties. Furthermore, insulating layers 31 to 33 preferably do not contain core materials such as glass fiber, which are typically used to improve mechanical strength. Moreover, the resins listed above as materials for insulating layers 31 to 33 are merely examples of materials capable of forming each insulating layer. Each insulating layer can be formed from any material that provides insulation to conductor layers 21 to 24 and can support conductor layers 21 to 24.

[0034] Furthermore, in the wiring substrate of the embodiment, such as Figure 2 As shown, the via 5 filled with the via conductor 4 has a first portion 51, a second portion 52, and a third portion 53. The first portion 51 is... Figure 2In the example, the portion 52 is narrower on the conductor layer 21 side compared to the conductor layer 22 side. The second portion 52 is wider on the conductor layer 21 side compared to the conductor layer 22 side, and is located on the conductor layer 21 side of the first portion 51. The third portion 53 is narrower on the conductor layer 21 side compared to the conductor layer 22 side, and is located on the conductor layer 21 side of the second portion 52. Furthermore, in the representation of the insulating layer 31 and the conductor layers 21 and 22 above and below it... Figure 2 As described above, conductor layer 21 is the first conductor layer, and conductor layer 22 is the second conductor layer. (Referring to...) Figure 2 Explanation and reference Figure 2 Similarly, this refers to the insulating layer 31 and the conductor layers 21 and 22 above and below it. Figures 3-5 In the description, conductor layer 21 is also labeled as first conductor layer 21, and conductor layer 22 is also labeled as second conductor layer 22.

[0035] In the wiring substrate of the embodiment, such as Figure 2 As shown above, the hole 5 filled by the via conductor 4 has a first portion 51, a second portion 52, and a third portion 53 whose widths are respectively reduced or increased compared to the side of the second conductor layer 22 on the side of the first conductor layer 21. The first portion 51 and the third portion 53 have their widths reduced towards the first conductor layer 21, while the second portion 52 has its width increased towards the first conductor layer 21. Furthermore, the "width" of each of the first portion 51, the second portion 52, and the third portion 53, i.e., the "width" of the hole 5, is the maximum value of the distance between any two points on the outer periphery of the hole 5 in any cut surface perpendicular to the Z direction.

[0036] The first part 51, the second part 52, and the third part 53 are arranged in series along the Z direction from the side of the second conductor layer 22 to the side of the first conductor layer 21.

[0037] Because hole 5 has Figure 2 As shown in the diagram, the first portion 51, the second portion 52, and the third portion 53 make it unlikely that cracks or peeling caused by pores will occur between the via conductor 4 formed within the hole 5 and the first conductor layer 21. For this reason, it can be cited that the via conductor 4 is unlikely to contain pores in the third portion 53 near the bottom of the hole 5. That is, it is speculated that when the via conductor 4 is formed by filling the hole 5 with the metal film 4a and the plating film 4b, due to the presence of the second portion 52, which has an increased width on the first conductor layer 21 side, plating solutions such as electroplating can easily penetrate deep into the hole 5. Therefore, it is believed that the metal film 4a and the plating film 4b can easily be formed in all corners of the hole 5.

[0038] Furthermore, it is speculated that due to the presence of a third portion 53 with a reduced width on the first conductor layer 21 side, it is difficult to generate [something] at the periphery of the hole 5 near the interface with the first conductor layer 21. Figure 2 The imaginary portion IM is shown by the dashed line. For example, if the second portion 52 reaches the first conductor layer 21, a tapering corner, like the imaginary portion IM, is formed in the hole 5 near the interface with the first conductor layer 21. When the hole 5 contains a portion like the imaginary portion IM, fresh plating solution has difficulty spreading to such a portion. Therefore, it is believed that the via conductor formed in a hole containing a portion like the imaginary portion IM is prone to contain unfilled portions such as pores near its bottom.

[0039] In contrast, in the wiring substrate 1 of the embodiment, the hole 5 has a third portion 53, making it difficult to produce... Figure 2 The via conductor 4 is a hypothetical portion like IM. That is, it is difficult for it to contain unfilled portions such as pores near its bottom. Therefore, in the wiring substrate of the embodiment, by utilizing the aforementioned effects of at least the second portion 52 and the third portion 53 in the hole 5, it is difficult for cracks, peeling, etc., to occur between the via conductor 4 and the first conductor layer 21. Therefore, it is believed that undesirable conditions such as peeling between the via conductor 4 and the first conductor layer 21 can be suppressed.

[0040] The hole 5 can have any opening shape, such as circular or elliptical, on both end faces and in a cross-section perpendicular to the Z direction. When the hole 5 has a circular or elliptical opening shape, the first portion 51 and the third portion 53 can have a reduced diameter on the first conductor layer 21 side, while the second portion 52 can have a larger diameter on the first conductor layer 21 side. Furthermore, in the first portion 51 and the third portion 53, the width of the hole 5 can decrease as it approaches the first conductor layer 21, while in the second portion 52, the width of the hole 5 can increase as it approaches the first conductor layer 21. That is, in the first portion 51 and the third portion 53, the width of the hole 5 can gradually decrease as it approaches the first conductor layer 21, while in the second portion 52, the width of the hole 5 can gradually increase as it approaches the first conductor layer 21. In this case, in the first part 51 and the third part 53, the width of the hole 5 may decrease continuously or in stages as it approaches the first conductor layer 21, while in the second part 52, the width of the hole 5 may increase continuously or in stages as it approaches the first conductor layer 21.

[0041] Additionally, the width W1 at the opening end (upper end) on the second conductor layer 22 side of the first part 51 can be greater than the width W2 at the opening end (lower end) on the first conductor layer 21 side, and the width W3 at the upper end of the second part 52 (in...) Figure 2 The width W2 at the middle part (which is the same as the width W2 at the middle part) can be smaller than the width W4 at the bottom part. Furthermore, the width W5 at the top of the third part 53 (which is the same as the width W2 at the middle part) can be smaller than the width W4 at the bottom part. Figure 2 The width of the middle section (same as the width W4) can also be greater than the width W6 at the bottom.

[0042] Furthermore, in the wiring substrate 1 of the embodiment, the wall surface 5a of the hole 5 may also be inclined inward toward the first conductor layer 21 towards the inside of the hole 5 in the first portion 51. Additionally, the wall surface 5a of the hole 5 may also be inclined outward toward the first conductor layer 21 in the second portion 52. Furthermore, the wall surface 5a of the hole 5 may also be inclined inward toward the first conductor layer 21 in the third portion 53. That is, the first portion 51 and the third portion 53 may be conical toward the first conductor layer 21, and the second portion 52 may be inverted conical toward the first conductor layer 21.

[0043] As an example, in Figure 2 An example of a hole 5, having a shape comprising a first portion 51, a second portion 52, and a third portion 53, is formed by irradiating each insulating layer with light such as ultraviolet light in a predetermined exposure pattern, and then removing the irradiated or unirradiated portions through development. That is, the via conductor 4 can be a so-called "light path." To facilitate the formation of the hole 5 using photolithography based on exposure and development, in the wiring substrate of the embodiment, as described above, each insulating layer, such as insulating layer 31, is preferably formed of a photosensitive resin. For the same reason, each insulating layer, such as insulating layer 31, is preferably formed of a resin that does not contain inorganic particles such as silicon oxide or aluminum oxide, referred to as "inorganic fillers." Furthermore, for the same reason, each insulating layer, such as insulating layer 31, is preferably formed of a resin that does not contain a core material such as glass fiber.

[0044] In the formation of the hole 5 based on photolithography, for example, compared with laser-based perforation, it is sometimes easier to form holes with a small width. Therefore, in the wiring substrate 1, the hole 5 can have a relatively small opening width. In addition, in the wiring substrate of the embodiment, as described above, cracks and peeling are less likely to occur between the via conductor 4 and the first conductor layer 21. Therefore, even if the width of the via conductor 4 is small, it is less likely to cause defects such as open circuit defects and increased resistance between the via conductor 4 and the first conductor layer 21. Therefore, the wiring substrate of the embodiment is considered suitable as a wiring substrate containing a small via conductor. For example, in the wiring substrate 1, the opening width W of the hole 5 at the interface between the insulating layer 31 and the second conductor layer 22 (in Figure 2 The width W1 of the hole 5 (which is the same as the upper end of the first part 51) can be 3 μm or more and 10 μm or less. By making the hole 5 have such a small opening width, the wiring substrate 1 can sometimes contain fine wiring patterns at high density.

[0045] exist Figure 2In the hole 5 of the wiring substrate 1 shown, in the thickness direction (Z direction) of the wiring substrate 1, the length L3 of the third portion 53 is shorter than the length L1 of the first portion 51 and shorter than the length L2 of the second portion 52. Therefore, the contact area between the via conductor 4 and the first conductor layer 21 does not become too small, and a suitable contact area can be maintained. As an example, relative to the thickness T31 of the insulating layer 31, the length L1 of the first portion 51 is about 30%, the length L2 of the second portion 52 is about 60%, and the length L3 of the third portion 53 is about 10%.

[0046] The thickness T31 of the insulating layer 31 is, for example, 3 μm or more and 15 μm or less. The aspect ratio of the via conductor 4 formed on the insulating layer 31 of such thickness is, for example, 1.0 or more and 3.0 or less. Furthermore, the aspect ratio of the via conductor 4 is a ratio expressed as (width W6 of the lower end of the third portion 53 of the hole 5) / (distance between the first conductor layer 21 and the second conductor layer 22).

[0047] In addition, Figure 2 In the holes 5 of the wiring substrate 1 shown, the inclination θ1 of the wall surface 5a of the hole 5 in the first portion 51 relative to the thickness direction (Z direction) of the wiring substrate 1 is greater than the inclination θ2 of the wall surface 5a of the hole 5 in the second portion 52 relative to the Z direction. Therefore, in the formation of the plated via conductor 4, it is assumed that the plating solution can easily enter the hole 5, and the via conductor 4 can be formed quickly. Furthermore, the inclination θ1 is determined by the arctangent of the absolute value of (length L1 of the first portion 51) / ((width W1 at the upper end of the first portion 51 - width W2 at the lower end) / 2). The inclination θ2 is determined similarly for the second portion 52.

[0048] In addition, Figure 2 In the hole 5 of the wiring substrate 1 shown, the second portion 52 is connected to the first portion 51, and the third portion 53 is connected to the second portion 52. Furthermore, the first portion 51 contacts the second conductor layer 22, and the third portion 53 contacts the first conductor layer 21. That is, Figure 2 In the example, the hole 5 is composed of a first part 51, a second part 52, and a third part 53; that is, it is composed only of the first part 51, the second part 52, and the third part 53. Therefore, it has the advantage of being easy to control so that gaps do not enter the third part 53.

[0049] Figure 3 A photograph of the cross-section of the via conductor 4 in an embodiment of the wiring substrate is shown. (See reference...) Figure 2 As explained, in Figure 3The via 5 filled by the via conductor 4 has: a first portion 51, which narrows in width on the side of the first conductor layer 21; a second portion 52, which is located on the side of the first conductor layer 21 of the first portion 51 and widens in width on the side of the first conductor layer 21; and a third portion 53, which is located on the side of the first conductor layer 21 of the second portion 52 and narrows in width on the side of the first conductor layer 21. Thus, the wiring substrate of the embodiment actually has a via conductor 4 formed in the via 5, which has a first portion 51, a second portion 52, and a third portion 53.

[0050] <First Variation>

[0051] exist Figure 4 The diagram shows the via conductor 41 and its surrounding portion in a first modified example of the wiring substrate according to the embodiment, where the through insulating layer 31 is visible. Figure 4 In a modified example, a via conductor 41 is formed inside the hole 5 penetrating the insulating layer 31. The via conductor 41 is formed of a metal film 4a and a plated film 4b filling the hole 5, connecting the first conductor layer 21 and the second conductor layer 22. The hole 5 and... Figure 2 The example shown also has a first part 51, a second part 52, and a third part 53. Furthermore, in Figure 4 In the example, the portion of the via conductor 41 filling the third part 53 in the coated film 4b does not contain a pore, while the portion filling the first part 51 contains a pore B. It is assumed that the pore B is contained in the first part 51 rather than the third part 53. Figure 4 In the first variation, compared to the case where there is a hole at the bottom of the via conductor in a conventional wiring substrate, it is difficult to cause peeling between the via conductor 41 and the first conductor layer 21. Furthermore, in Figure 4 In the first variation, the aperture B may replace the first portion 51 and be included in the second portion 52, or it may be included in both the first portion 51 and the second portion 52. It is believed that even in this case, since the third portion 53 does not contain the aperture, it is difficult to cause peeling between the via conductor 41 and the first conductor layer 21.

[0052] <Second Variation>

[0053] exist Figure 5 The diagram shows a via conductor 42 penetrating the insulating layer 31 and its surrounding portion in a second variation of the wiring substrate according to the embodiment. The via conductor 42 is formed inside the hole 50 penetrating the insulating layer 31, connecting the first conductor layer 21 and the second conductor layer 22. Figure 5The modified example includes a hole 50 that also has a first portion 51 with a reduced width on the first conductor layer 21 side, a second portion 52 located on the first conductor layer 21 side of the first portion 51 and with an increased width on the first conductor layer 21 side, and a third portion 53 located on the first conductor layer 21 side of the second portion 52 and with a reduced width on the first conductor layer 21 side.

[0054] and, Figure 5 The example hole 50 also has a fourth portion 54 whose width remains substantially constant from the side of the second conductor layer 22 to the side of the first conductor layer 21. That is, in the fourth portion 54, the width of the hole 50 is substantially constant from the upper end to the lower end of the fourth portion 54. Figure 5 In the example, hole 50 has a fourth portion 54 between the first portion 51 and the second portion 52. However, in the wiring substrate of the embodiment, when the hole for the via conductor, such as hole 50, has a parallel portion that does not change the width, the parallel portion may also be located between the second portion 52 and the third portion 53. Figure 5 As in the example, in the wiring substrate of the embodiment, the holes filled with via conductors may include parallel portions such as a fourth portion 54, in addition to the first portion 51, the second portion 52, and the third portion 53. Furthermore, in the wiring substrate of the embodiment, the holes filled with via conductors may include portions with increased or decreased diameters on the first conductor layer 21 side, in addition to the first portions 51 to the third portions 53.

[0055] <Method for Manufacturing a Wiring Substrate for an Embodiment>

[0056] Reference Figures 6A to 6H ,by Figure 1 Taking the wiring substrate 1 shown as an example, an example of a method for manufacturing the wiring substrate according to the embodiment will be described.

[0057] like Figure 6A As shown, a support substrate SP is prepared, comprising a core layer GS, and metal film layers ML1 and ML2 respectively stacked on both sides of the core layer GS. The core layer GS is made of, for example, glass or glass epoxy. The metal film layers ML1 and ML2 are single-layer or multi-layer metal films formed by chemical plating or sputtering, for example, using materials such as copper and titanium. The metal film layers ML1 and ML2 are bonded, for example, by an adhesive layer AL made of an adhesive whose adhesion changes with light.

[0058] Furthermore, in the following description, the side of the support substrate SP closest to the core layer GS is also referred to as "lower" or "lower side," and the side furthest from the core layer GS is also referred to as "upper" or "upper side." Therefore, the surface of the elements constituting the wiring substrate facing the support substrate SP is also referred to as the "lower surface," and the surface facing the side opposite to the support substrate SP is also referred to as the "upper surface."

[0059] Conductor layers 21 are formed on metal film layers ML2 on both sides of the prepared support substrate SP. During the formation of conductor layers 21, for example, a resist (not shown) with defined openings is formed on the metal film layer ML2. By electroplating the metal film layer ML2 as a power supply layer, a plating film is deposited within the openings of the resist. The resist is then removed. A conductor layer 21 comprising conductor patterns formed by the plating films deposited within the openings of the resist is formed.

[0060] After the conductor layer 21 is formed, an insulating layer 31 is formed covering the conductor layer 21. The insulating layer 31 is preferably formed of a photosensitive resin. Examples of photosensitive resins include epoxy resin, BT resin, or phenolic resin with added photosensitizer. In the formation of the insulating layer 31, as an example, a resin film layer composed of a resin such as epoxy resin constituting the insulating layer 31 is stacked on the conductor layer 21 and the metal film layer ML2, for example, temporarily cured to an intermediate reaction state such as stage B by heating. In one example, the photosensitive resin constituting the insulating layer 31 is negative. Hereinafter, the case where the photosensitive resin constituting the insulating layer 31 is negative will be used as an example to explain the hole 5 (refer to...). Figure 6D Method for forming insulating layer 31.

[0061] like Figure 6B As shown, on the insulating layer 31, in the via conductor 4 (refer to...) Figure 6G The exposure mask EM, which has a shielding portion EM1 at the formation location, is provided, for example, by laminating a dry film resist, exposing, and developing. Furthermore, in Figure 6B And the references thereafter Figure 6E and Figure 6H The diagram shows only one surface side of the support substrate SP, omitting the state of the other side. However, on the surface of the support substrate SP on the side that is omitted from the diagram, the insulating layers and conductor layers may be formed in the same manner as on the side shown, or they may not be formed.

[0062] exist Figure 6C The middle shows Figure 6B An enlarged view of the VIC section. (See attached image.) Figure 6CAs shown, an exposure light EL, such as ultraviolet light, is irradiated onto the insulating layer 31 via an exposure mask EM. The wavelength of the exposure light EL is selected based on the photosensitivity of the photosensitive resin constituting the insulating layer 31. The exposure light EL is irradiated onto the portion of the upper surface 31a of the insulating layer 31 exposed by the opening EM2 of the exposure mask EM. By adjusting the diffusion and irradiation angle of the exposure light EL, a portion of the exposure light EL transmitted into the insulating layer 31, namely the exposure light EL1, propagates within the insulating layer 31 in such a way that it extends to the portion directly below the shielding portion EM1 of the exposure mask EM. Therefore, the portion of the insulating layer 31 directly below the shielding portion EM1, near the opening EM2, is exposed by the exposure light EL1. In the insulating layer 31, which is composed of a negative-type photosensitive resin, the exposed portion undergoes cross-linking. Therefore, even the portion directly below the shielding portion EM1, in the area AR exposed by the exposure light EL1, undergoes the same cross-linking reaction as the portion directly below the opening EM2.

[0063] Here, it is assumed that the luminosity of the exposure light EL propagating within the insulating layer 31 gradually decreases in the portion near the conductor layer 21, away from the upper surface 31a of the insulating layer 31. Therefore, the exposed area AR in the portion directly below the shielding portion EM1 gradually decreases towards the conductor layer 21 in the portion away from the upper surface 31a. Consequently, in the insulating layer 31 directly below the shielding portion EM1, the area AN where no crosslinking reaction is observed gradually increases in the portion away from the upper surface 31a, as it approaches the conductor layer 21.

[0064] On the other hand, in the insulating layer 31, a small portion of the portion directly below the opening EM2 in the area near the conductor layer 21, directly below the shielding portion EM1, is exposed by reflected light EL2 from the exposure light EL1 reflected from the surface of the conductor layer 21. Therefore, the exposure area AR directly below the shielding portion EM1 expands in the portion near the conductor layer 21. That is, the area AN in the insulating layer 31 directly below the shielding portion EM1 closest to the conductor layer 21, where no cross-linking reaction is observed, shrinks. As a result, as... Figure 6C As shown, the region AN where the cross-linking reaction is not visible decreases in size within a certain range near the upper surface 31a of the insulating layer 31, becoming smaller closer to the conductor layer 21. Conversely, on the conductor layer 21 side, the region expands further closer to the conductor layer 21, and the closest minute portion of the conductor layer 21 decreases in size closer to the conductor layer 21. The region AN where the cross-linking reaction is not visible is removed in subsequent processes.

[0065] After irradiating the insulating layer 31 with exposure light EL, the exposure mask EM is removed using a suitable stripping agent. By developing after removing the exposure mask EM, the regions AN in the insulating layer 31 that do not show crosslinking reactions during the above exposure process are removed.

[0066] By removing regions AN that do not show cross-linking reactions, such as Figure 6D As shown, a hole 5 is formed in the insulating layer 31. As described above, the region AN that does not show a cross-linking reaction has three parts that either shrink or expand as they approach the conductor layer 21, thus forming... Figure 6D The hole 5 is shown in the diagram. Specifically, it is formed with a first portion 51 that narrows on the conductor layer 21 side, a second portion 52 that widens on the conductor layer 21 side, and a third portion 53 that narrows on the conductor layer 21 side. The second portion 52 is located on the conductor layer 21 side of the first portion 51, and the third portion 53 is located on the conductor layer 21 side of the second portion 52. Figure 6D In example hole 5, the second part 52 is connected to the first part 51, and the third part 53 is connected to the second part 52. Figure 6D The example hole 5 consists only of the first part 51, the second part 52, and the third part 53.

[0067] As described above, by appropriately selecting and adjusting the exposure light EL (refer to...) Figure 6C Irradiation conditions such as diffusion, irradiation angle, and luminosity can create conditions like... Figure 6D The hole 5 shown includes the first portion 51 to the third portion 53. Additionally, as previously referred to... Figure 5 The hole 50 with the fourth part 54 shown can also be formed by adjusting the irradiation conditions of the exposure light EL.

[0068] After the hole 5 is formed, a metal film 4a, for example made of copper, is formed on the upper surface 31a of the insulating layer 31 and inside the hole 5 by chemical plating or sputtering.

[0069] like Figure 6E As shown, the resist PR is deposited on the metal film 4a, for example, by laminating a dry film resist. An opening PO is formed on the resist PR, for example, by photolithography. The opening PO is disposed on the conductor layer 22 (see reference). Figure 6H The area where each conductor pattern is formed. An opening PO is also provided above the hole 5.

[0070] like Figure 6F As shown, inside the opening PO, a plating film 4b is deposited, for example, by electroplating a metal film 4a as a power supply layer. A plating film 4b is also deposited inside the hole 5 exposed in the opening PO, and the hole 5 is gradually filled by the plating film 4b. In the hole 5 having the first portion 51 to the third portion 53, as described above, the plating solution easily enters to the bottom of the hole 5, and there are no areas near the bottom where the plating solution cannot spread. Therefore, the hole 5 is easily filled to each corner of the third portion 53 by the plating film 4b. That is, it is difficult to generate unfilled portions such as pores near the interface between the bottom of the hole 5 and the conductor layer 21.

[0071] The coating film 4b fills the entire third portion 53, the entire second portion 52, and then the first portion 51. In the manufacturing of the wiring substrate according to this embodiment, because the second portion 52 has an expanded width on the conductor layer 21 side, the filling of the third portion 53 and the second portion 52 sometimes takes a relatively long time. In this case, after the second portion 52 is filled, before the first portion 51 is completely filled, the upper end of the first portion 51 is sometimes blocked by the coating film 4b deposited on the inner wall around the hole 5. Alternatively, by using an exposure light EL (see above) as described above... Figure 6C The adjustment of irradiation conditions to form the desired shape of the hole 5, and the adjustment of plating conditions, may cause the upper end of the first portion 51 to be blocked by the plating film 4b deposited on the inner wall around the hole 5 before the first portion 51 or the second portion 52 is completely filled. In this case, the referenced before the formation of the first portion 51 and / or the second portion 52... Figure 4 The aperture B shown is difficult to form in the third part 53 (especially near the interface with the conductor layer 21). Therefore, it is believed that in the wiring substrate of the embodiment, the via conductor 4 formed in the hole 5 (see reference) can be suppressed. Figure 6G Cracks and peeling between the conductor layer 21 and the conductor layer 22.

[0072] like Figure 6G As shown, from Figure 6F Starting from the state shown, a plating film 4b is continuously deposited through electroplating, thereby completely filling the hole 5 with the plating film 4b, and subsequently filling the opening PO of the resist plating PR to a specified depth. As a result, a via conductor 4 is formed within the hole 5, and a conductor layer 22 is formed within the opening PO (see reference). Figure 6H Each conductor pad of )

[0073] After the via conductor 4 is formed by the formation of the plating film 4b, the resist PR is removed using a suitable stripping solution. Then, the portion of the metal film 4a exposed by the removal of the resist PR is removed, for example, by etching. As a result, a conductor layer 22 is formed, consisting of conductor patterns formed within the openings PO of the resist PR.

[0074] like Figure 6H As shown, a via conductor 4 penetrating the insulating layer 32, conductor layer 23, and insulating layer 32 is further formed using the same method as the previously described method for forming the insulating layer 31, conductor layer 22, and via conductor 4. Furthermore, a via conductor 4 penetrating the insulating layer 33, conductor layer 24, and insulating layer 33 is formed using the same method as the method for forming the via conductor 4 penetrating the insulating layer 31, conductor layer 22, and insulating layer 31.

[0075] Solder resist 62 is formed on conductor layer 24 and insulating layer 33 (see reference). Figure 1 Solder resist 62 may be formed by any method, such as spraying, laminating, or coating, using photosensitive polyimide resin or epoxy resin. Alternatively, solder resist 62 may be formed not immediately after the formation of conductor layer 24, but after the removal of metal film layer ML2 of support substrate SP as described below.

[0076] Remove the core layer GS of the support substrate SP. The lower surface of the metal film layer ML2 of the support substrate SP is exposed. The core layer GS is removed, for example, after the adhesive layer AL is softened by laser irradiation, by peeling the metal film layer ML2 off the adhesive layer AL. Then, the metal film layer ML2 is removed by etching. The lower surface of the conductor layer 21 and the lower surface of the insulating layer 31 are exposed. Solder resist 61 (see reference) covers the exposed conductor layer 21 and insulating layer 31. Figure 1 It is formed by the same method as the formation method of solder resist 62.

[0077] like Figure 1 As shown, openings are formed in solder resists 61 and 62 to expose conductor layer 21 or conductor layer 24. These openings in the solder resists 61 and 62 are formed, for example, by photolithography or laser irradiation, which includes exposure and development processes. Through these processes, it is possible to manufacture... Figure 1 Wiring substrate 1 of the illustrated embodiment.

[0078] The wiring substrate of the embodiments is not limited to having the structures illustrated in the accompanying drawings and the structures, shapes, and materials illustrated in this specification. As described above, the wiring substrate of the embodiments can have any stacked structure. Holes filled with via conductors may also be formed in any insulating layer of the wiring substrate of the embodiments, the holes having three portions such as first portion 51 to third portion 53. In the wiring substrate of the embodiments, via conductors are formed in at least one insulating layer, the via conductors filling the holes having three portions such as first portion 51 to third portion 53. The wiring substrate of the embodiments may also not be... Figure 1 The so-called coreless substrate, such as the wiring substrate 1, may also include a core substrate and a multilayer formed on both sides thereof.

Claims

1. A wiring substrate comprising: First conductor layer; An insulating layer that covers the first conductor layer; A second conductor layer is formed on the surface of the insulating layer; as well as A via conductor, formed inside a hole penetrating the insulating layer, connects the first conductor layer and the second conductor layer. in, The hole includes: The first part has a reduced width on the side of the first conductor layer; The second portion, located on the first conductor layer side of the first portion, expands its width on the first conductor layer side; and The third part is located on the side of the first conductor layer of the second part, and its width is reduced on the side of the first conductor layer.

2. The wiring substrate according to claim 1, wherein, The insulating layer is formed of a photosensitive resin.

3. The wiring substrate according to claim 1, wherein, The insulating layer is formed of a resin that does not contain inorganic particles.

4. The wiring substrate according to claim 1, wherein, The via conductor is formed by a plated film filling the via. The portion of the coating that fills the third part does not contain pores, while the portion that fills the first part or the portion that fills the second part contains pores.

5. The wiring substrate according to claim 1, wherein, In the thickness direction of the wiring substrate, the third portion is shorter than the first portion and shorter than the second portion.

6. The wiring substrate according to claim 1, wherein, The inclination of the wall surface of the hole in the first part relative to the thickness direction of the wiring substrate is greater than the inclination of the wall surface of the hole in the second part relative to the thickness direction.

7. The wiring substrate according to claim 1, wherein, The opening width of the hole at the interface between the insulating layer and the second conductor layer is more than 3 μm and less than 10 μm.

8. The wiring substrate according to claim 1, wherein, The second part is connected to the first part. The third part is connected to the second part.

9. The wiring substrate according to claim 8, wherein, The hole is composed of the first part, the second part, and the third part.

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