Multi-bit gallium oxide floating gate memory, method of making and applications thereof

Abstract

The application provides a multi-bit gallium oxide floating gate memory, a preparation method and application thereof. The memory comprises a gallium oxide layer, a source electrode and a drain electrode, a gate dielectric layer, a plurality of floating gates, a plurality of control gates, and a tunneling layer. The gallium oxide layer comprises a plurality of gallium oxide channels. The plurality of floating gates are arranged correspondingly to the gallium oxide channels. The plurality of control gates are arranged correspondingly on the plurality of floating gates. The tunneling layer is arranged between the control gates and the floating gates. The control gate-tunneling layer-floating gate forms a first capacitor. The floating gate-gate dielectric layer-gallium oxide channel forms a second capacitor. The capacitance ratios of the plurality of first-second capacitor groups are different. The plurality of control gates are in equal potential and are connected in parallel. The application uses a floating gate structure to control the opening of the channel, stabilizes the storage of the tunneling of electrons, accurately controls the tunneling voltage by adjusting the capacitance ratio, controls the step-by-step opening of the channel, realizes the accurate programming of multi-bit, changes the voltage size of the parallel control gate, and obtains different storage windows, and the complexity of the circuit is significantly reduced.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic storage device technology, specifically relating to a multi-bit gallium oxide floating gate memory, its fabrication method, and its application. Background Technology

[0002] With the explosive growth of IoT sensor nodes and AI data volume, the traditional von Neumann architecture, due to the physical separation of sensing, storage, and computing units, inevitably leads to repeated data transmission between modules, resulting in high communication burden, increased power consumption, and decreased real-time performance. Inspired by biological retina and neuromorphic computing, sensor-memory-computing integration enables real-time storage and local computing at the data source, allowing for on-site extraction of key features, data compression, and parallel processing. This significantly improves the energy efficiency and speed of neural network inference and signal processing, and is considered an effective way to overcome the bottlenecks of existing architectures. Therefore, under the dual pressure of rapidly increasing demand for intelligent sensing and the limited energy efficiency of traditional systems, the development of sensor-memory-computing integrated chips based on new materials and devices has become highly necessary and urgent.

[0003] Gallium oxide (Ga2O3), an ultrawide bandgap semiconductor, has become an important candidate material for integrated sensing, memory, and computing due to its wide bandgap of up to 4.9 eV and excellent ultraviolet response characteristics. Ga2O3's absorption wavelength cutoff of 254 nm gives it a naturally selective response to solar-blind ultraviolet light, and it possesses the advantages of high signal-to-noise ratio and low false alarm rate. Oxygen vacancy defects in Ga2O3 endow devices with the potential for resistive switching memory. Existing research shows that Ga2O3-based photosynapses can achieve multi-functional integration from ultraviolet detection to logic operations, and have great potential in fields such as criminal investigation and space communication. Nevertheless, the development of Ga2O3 memories is still in its early stages, with relatively simple device structures, and resistive switching memories based on oxygen vacancy defects struggle to achieve multi-bit storage characteristics.

[0004] Specifically, this manifests in:

[0005] 1. The slow response speed of resistive switching memory based on oxygen vacancy defects limits the computational efficiency of integrated sensing, memory, and computing. Oxygen vacancies significantly extend carrier lifetime, making the resistive state transition dominated by defect capture / release, with response times often exceeding seconds, much slower than the microsecond-level fast response of Ga2O3 detectors.

[0006] 2. Point defects such as oxygen vacancies lack precise quantitative characterization schemes, making it difficult to program multi-bit storage by quantitatively customizing oxygen vacancy concentrations. Furthermore, photogenerated carriers trapped in oxygen vacancies are slowly released after the light source is turned off, leading to signal volatileness and making stable storage difficult.

[0007] Floating-gate transistors based on MoS2 provide an important approach for realizing multi-bit storage, and the specific scheme is as follows:

[0008] like Figure 1a and Figure 1b The figures show a schematic diagram of the MoS2 floating gate memory and a photograph of its actual appearance. The control gates G1, G2, and G3 are coplanar with the MoS2 channel. The floating gate is made of Pt metal, and the tunneling dielectric is Al2O3. The channel / floating gate equivalent capacitance Cn (n = 1, 2, 3) is in series with the floating gate / control gate equivalent capacitance CF. The tunneling dielectric layer voltage satisfies: V tunnel = V GS C F / (C F + C n That is, the tunneling voltage depends on the equivalent capacitive coupling ratio C. n / C F Since the capacitance formula satisfies C = εA / 4kπd, the capacitance ratio C can be achieved by changing the area of ​​the control gate. n / C F And precise control of tunneling voltage. Therefore, by selecting control gates of different sizes, different storage windows can be obtained, thereby achieving multi-bit storage characteristics.

[0009] However, while MoS2 memories with multi-floating-gate structures can achieve multi-bit programming, the programming process requires selecting different gates, which complicates the circuit design. Furthermore, the coplanar design of the control gate and channel significantly increases the device area, posing a significant challenge to miniaturization and integration in the context of the ever-increasing number of neural network computing nodes. Summary of the Invention

[0010] The main objective of this invention is to provide a multi-bit gallium oxide floating gate memory, its fabrication method, and its application, in order to overcome the shortcomings of the prior art.

[0011] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0012] In a first aspect, the present invention provides a multi-bit gallium oxide floating gate memory, comprising:

[0013] The gallium oxide layer includes a plurality of gallium oxide channels that are sequentially spaced apart along a first direction;

[0014] The source and drain are disposed at intervals along the second direction on the gallium oxide layer and electrically connected to each other through a plurality of gallium oxide channels, wherein the first direction intersects the second direction;

[0015] A gate dielectric layer is stacked on the gallium oxide layer;

[0016] Multiple floating gates are sequentially and spaced apart on the gate dielectric layer along the first direction, and each floating gate is correspondingly disposed with a gallium oxide channel;

[0017] Multiple control gates are respectively disposed on multiple floating gates, and a tunneling layer is disposed between any corresponding set of control gates and floating gates;

[0018] In this configuration, any one of the control gate-tunneling layer-floating gate forms a first capacitor, and the floating gate-gate dielectric layer-gallium oxide channel forms a second capacitor. The corresponding first capacitor and second capacitor form a series capacitor group, and the capacitance ratios of the multiple series capacitor groups are different; and the multiple control gates are connected in parallel at the same potential.

[0019] Secondly, the present invention also provides a method for fabricating the above-mentioned multi-bit gallium oxide floating gate memory, comprising:

[0020] A gallium oxide layer is grown on the substrate surface, and a source region and a drain region are defined on the gallium oxide layer;

[0021] A gate dielectric layer, a floating gate metal layer, and a tunneling layer are sequentially deposited on the gallium oxide layer in the region between the source and drain regions to form a sandwich layer.

[0022] The sandwich layer is patterned and etched to form a plurality of sandwich structures spaced apart along a first direction. Each sandwich structure includes a floating gate. The first direction intersects with a second direction, which is the arrangement direction of the source region and the drain region.

[0023] Multiple control gates are respectively provided in multiple patterned sandwich structures;

[0024] Mesa etching is performed on the region of the gallium oxide layer located between the source and drain regions to form multiple gallium oxide channels, each of which is correspondingly configured with a control gate.

[0025] Parallel gates are provided on the plurality of control gates to set the plurality of control gates in parallel at the same potential;

[0026] A source and a drain are respectively disposed on the source and drain regions of the gallium oxide layer;

[0027] In this configuration, any one of the control gate-tunneling layer-floating gate forms a first capacitor, and the floating gate-gate dielectric layer-gallium oxide channel forms a second capacitor. When forming the structural unit of the gallium oxide channel-gate dielectric layer-floating gate-tunneling layer-control gate, the corresponding first capacitor and second capacitor form a series capacitor group, and the capacitance ratios of the multiple series capacitor groups are different.

[0028] Thirdly, the present invention also provides the use of the above-mentioned multi-bit gallium oxide floating gate memory in the fabrication of integrated sensing, memory, and computing chips or information storage and computing devices.

[0029] Compared with the prior art, the beneficial effects of the present invention include at least the following:

[0030] The multi-bit gallium oxide floating gate memory proposed in this invention uses a floating gate structure to control channel opening. Stable storage comes from electron tunneling. The conduction band order of the tunneling layer and CG and FG can ensure stable charge storage. The tunneling voltage can be precisely controlled by adjusting the capacitance ratio by changing the control gate area and other conditions, thereby controlling the step-by-step opening of the gallium oxide channel and realizing precise multi-bit programming. Compared with MoS2 floating gate memory, the multi-bit gallium oxide floating gate memory proposed in this invention can obtain different storage windows by only changing the voltage of the parallel control gate. Compared with MoS2 floating gate memory, which requires selecting multiple gates to achieve multi-bit storage, the circuit complexity is significantly reduced.

[0031] The above description is merely an overview of the technical solution of the present invention. In order to enable those skilled in the art to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described below in conjunction with detailed drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1a This is a schematic diagram of the structure of the MoS2 floating gate memory provided in the background art of this invention;

[0034] Figure 1b These are microscopic images of the MoS2 floating gate memory provided in the background section of this invention.

[0035] Figure 2a This is a schematic cross-sectional view of a multi-bit gallium oxide floating gate memory provided in a typical embodiment of the present invention;

[0036] Figure 2b This is a top view schematic diagram of a multi-bit gallium oxide floating gate memory provided in a typical embodiment of the present invention;

[0037] Figure 3 This is a schematic flowchart of a method for fabricating a multi-bit gallium oxide floating gate memory provided in a typical embodiment of the present invention;

[0038] Figure 4a This is a schematic diagram of the equivalent circuit structure of a multi-bit gallium oxide floating gate memory provided in a typical embodiment of the present invention;

[0039] Figure 4b This is a schematic diagram of the charge distribution of a multi-bit gallium oxide floating gate memory under a gate voltage, provided in a typical embodiment of the present invention.

[0040] Figure 4c This is a schematic diagram of the charge distribution of a multi-bit gallium oxide floating gate memory under another gate voltage, provided in a typical embodiment of the present invention;

[0041] Figure 4d This is a schematic diagram of the charge distribution of a multi-bit gallium oxide floating gate memory under another gate voltage, provided in a typical embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of an ideal storage window for a multi-bit gallium oxide floating gate memory provided in a typical embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram illustrating the principle of an integrated sensing, storage, and computing application provided in a typical embodiment of the present invention. Detailed Implementation

[0044] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0045] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0046] This invention aims to propose a multi-bit gallium oxide floating gate memory based on Ga2O3 to overcome the shortcomings of traditional resistive switching memories, such as slow response speed and difficulty in achieving precise multi-bit programming due to oxygen vacancy defects. It also addresses the problems of existing MoS2 multi-floating gate memories, which rely on multiple gate selections, resulting in complex circuit design and a coplanar structure that hinders miniaturization and integration. By adopting a vertical structure design with parallel floating gates, multi-bit programming can be achieved under a single gate control. This not only possesses high-speed response and stable storage characteristics but also offers advantages in miniaturization and high integration, meeting the application requirements of artificial intelligence and neural network computing for high-efficiency in-memory computing devices.

[0047] To achieve the above objectives, embodiments of the present invention first provide a multi-bit gallium oxide floating gate memory, comprising:

[0048] The gallium oxide layer includes a plurality of gallium oxide channels that are sequentially spaced apart along a first direction;

[0049] The source and drain are disposed at intervals along the second direction on the gallium oxide layer and electrically connected to each other through a plurality of gallium oxide channels, wherein the first direction intersects the second direction;

[0050] A gate dielectric layer is stacked on the gallium oxide layer;

[0051] Multiple floating gates are sequentially and spaced apart on the gate dielectric layer along the first direction, and each floating gate is correspondingly disposed with a gallium oxide channel;

[0052] Multiple control gates are respectively disposed on multiple floating gates, and a tunneling layer is disposed between any corresponding set of control gates and floating gates;

[0053] In this configuration, any one of the control gate-tunneling layer-floating gate forms a first capacitor, and the floating gate-gate dielectric layer-gallium oxide channel forms a second capacitor. The corresponding first capacitor and second capacitor form a series capacitor group, and the capacitance ratios of the multiple series capacitor groups are different; and the multiple control gates are connected in parallel at the same potential.

[0054] There are various ways to adjust the capacitance ratio of multiple sets of first and second capacitors, including but not limited to:

[0055] In some implementations, the areas of the multiple control gates are different.

[0056] And / or, in some embodiments, the spacing between the plurality of control gates and the floating gates is different.

[0057] And / or, in some embodiments, the dielectric constant of the tunneling layer between the multiple sets of floating gates and the control gate is different.

[0058] The above-described exemplary adjustment method mainly changes the capacitance value of the first capacitor while keeping the capacitance value of the second capacitor consistent, thereby changing the capacitance ratio of the multiple series capacitor combinations and thus altering the tunneling voltage, providing multi-bit storage characteristics. Of course, other methods, such as keeping the capacitance value of the first capacitor consistent while adjusting the capacitance value of the second capacitor to be different (or changing both capacitors), can also achieve similar purposes and should fall within the feasible scope of this invention.

[0059] More specifically, the different capacitance changes mentioned above can be gradient-changed sequentially in a direction, that is, in some embodiments, the areas of the multiple floating gates are the same; and the areas of the multiple control gates increase or decrease gradient-changed along a first direction.

[0060] And / or, in some embodiments, the thickness of the tunneling layer increases or decreases in a gradient along a first direction.

[0061] And / or, in some embodiments, the dielectric constant of the dielectric material constituting the tunneling layer increases or decreases gradient along a first direction.

[0062] Of course, the gradient change methods described above are commonly used in device design and fabrication, for example... Figure 2a and Figure 2b The increase / decrease along the first direction is shown, but it is not limited to this. For example, it can increase first and then decrease along the first direction, or even have no regularity along the first direction. As long as the capacitance ratios of the multiple sets of series capacitors are different, multi-bit storage can be achieved based on the above principle.

[0063] The embodiment of the present invention focuses on changing the tunneling voltage by changing the control gate area, which is only one of the multi-bit control schemes. This scheme is relatively easy to implement. Other schemes include: keeping the control gate size consistent and gradually changing the tunneling layer thickness; or keeping the control gate size and tunneling layer thickness consistent and using different dielectric materials as the tunneling layer, etc.

[0064] Taking the change of tunneling layer thickness as an example, when the number of gallium oxide channels reaches 100 (i.e. 101 bits), the thickness of the tunneling layer between the 100 floating gates and the control gate needs to be gradient changed. In terms of process, it may require 100 etchings or the implementation of a controllable growth scheme. Compared with adjusting the control gate area, the process is more complicated and the process difficulty will increase, but this is still a feasible technical solution. The method of adjusting the dielectric constant of the tunneling layer is similar.

[0065] As some typical embodiments of the above technical solutions, in order to illustrate the advantages of the multi-bit gallium oxide floating gate memory provided by the present invention over traditional resistive switching memory and MoS2 floating gate memory, the working principle and multi-bit storage mechanism of the device will be described in detail below.

[0066] Device working principle:

[0067] Figure 4a A circuit connection diagram of a single floating gate structure is shown. (Example) Figure 4b As shown, the control gate / floating gate and the floating gate / gallium oxide channel can each be equivalent to two capacitors C. n (n = 1, 2, 3… represents multiple different gallium oxide channel locations) and C F Furthermore, from the perspective of circuit connection, this C n and C F They satisfy the series relationship. When a positive bias voltage (V) is applied to the control gate CG... CGWhen V increases, the CG potential rises, inducing a negative induced charge on the upper surface of the tunneling layer and an equal amount of positive induced charge on the lower surface. Due to the large number of electrons in the floating gate (FG), equal amounts of positive and negative induced charges are generated on the upper and lower surfaces of the gate dielectric under the control of the CG. At this point, the gallium oxide channel is in a depletion state. CG Further increasing the voltage, electrons in the floating gate (FG) tunnel through and are collected by the control gate (CG). The CG and FG then equalize their potentials, generating a negative induced charge on the upper surface of the gallium oxide channel, resulting in electron accumulation and thus opening the channel. Figure 4c As shown. If V is removed at this point... CG Because there are large conduction band steps between the tunneling layer and both CG and FG, electrons have difficulty returning from CG to FG, thus enabling stable signal storage, such as... Figure 4d As shown.

[0068] For multiple combinations of gallium oxide channel-floating gate-control gate with different capacitance ratios, C n (n = 1, 2, 3…) and C F When the series relationship is satisfied, the voltage of FG satisfies: V FG = V CG C F / (C F + C n That is, the FG voltage depends on the equivalent capacitance coupling ratio C. n / C F Since the capacitance formula satisfies C = εA / 4kπd, V can be precisely controlled by changing the area of ​​the control gate (or changing other relevant capacitance parameters). FG In a preferred embodiment of the invention, CGs with different areas are set, namely G1, G2, G3…G n And the area increases sequentially, the equivalent capacitive coupling ratio C1 / C F < C2 / C F < C3 / C F …then the tunneling voltage V FG1 > V FG2 >V FG3 … V FGn Tunneling voltage V tunnel = V CG – V FG Therefore, in V CG During the increase, G n The tunnels, G1, G2, G3, G3, G2, and G1, tunnel sequentially, thus connecting the different channels. For example... Figure 2b As shown, due to G1, G2, G3…G n They are connected in parallel, therefore G1, G2, G3…G can be controlled by simply changing the voltage of the parallel gates. nThe tunneling; furthermore, each gallium oxide channel in this invention has a corresponding individual control gate-floating gate structure for control. Therefore, in G1, G2, and G3…G… n During the sequential tunneling process, the corresponding gallium oxide channels also open one by one, resulting in an output current I. DS Gradually increase, thus achieving multi-bit storage.

[0069] Figure 5 The figure shows the ideal output current curve under this multi-bit storage mechanism. When there are three sets of capacitor banks-channels, by changing V... CG Three storage windows can be obtained. The specific number of windows depends on the structural design of the device, as long as each storage window can be clearly distinguished.

[0070] More specifically, the control gate is rectangular, and multiple control gates have the same gate width, with the gate length increasing or decreasing gradually along a first direction; the gate length direction of the control gate is parallel to a second direction. This structural design is a relatively easy implementation method to manufacture and design in this control method of changing the area of ​​the control gate.

[0071] Regarding specific design parameters, in some implementations, the maximum gate length of the multiple control gates is 40~50 μm, the minimum gate length is 2~5 μm, and the gate length variation gradient is 2~5 μm. Of course, the feasible design window is not limited to this, and those skilled in the art can adjust the parameters themselves based on the structural examples and principles described above.

[0072] In the above embodiments, since both the floating gate structure and the control gate are rectangular, the area can be changed by altering the length of the control gate. The lengths of control gates of different sizes satisfy a gradient variation. In this invention, the maximum size of the control gate is set to 40~50 μm, the minimum size is set to 2~5 μm, and the gradient is set to 5 μm.

[0073] Based on the working principle of the device, the tunneling voltage V of the device FG It is inversely proportional to the length of the control gate. Therefore, the gradient will affect the accuracy of device programming.

[0074] If the gradient is too small, the tunneling voltages of different channels will be similar, making it difficult to distinguish the input voltages during different bit programming; if the gradient is too large, it will increase the maximum tunneling voltage and increase device power consumption. In this invention, if C n ≈ C F The relative increase in tunneling voltage (V) FGn-1 – V FGn ) / V FGn≈ ±5%, which ensures that the device can achieve sufficient bit programming and accuracy (this is not limited to changing the capacitance ratio by controlling the area of ​​the gate; other equivalent ways of changing the capacitance value also have similar rules).

[0075] Furthermore, regarding how to form multiple independent gallium oxide channels, in some embodiments, the gallium oxide channels are fin channels. In a preferred embodiment, the gallium oxide layer is divided into multiple strips by trench etching, and each strip contains an independent gallium oxide channel; and / or, in some embodiments, the spacing between adjacent gallium oxide channels is 2~3 μm to ensure that there is no significant mutual interference while minimizing the device area.

[0076] Fin-shaped channels are a commonly used channel style in the field. Multiple fin-shaped channel structures can be fabricated using etching processes. The purpose of etching is to achieve electrical isolation between channels. Of course, the feasible implementation is not limited to this. If a fin-shaped channel structure is not used, more complex structures can be used, such as a floating structure. This involves using a wet etching method to laterally etch the bottom of the gallium oxide fin-shaped channel, separating the gallium oxide fin-shaped channel from the sapphire substrate and suspending it. Such a structure helps with heat dissipation under high storage density. Alternatively, ion implantation technology can also be used to achieve electrical isolation between gallium oxide channels. In this case, the device is a planar process, and F or N ions can be used for ion implantation. In various implementation methods, as long as multiple independent gallium oxide channels can be arranged side by side, it is acceptable, and the specific implementation form is not limited.

[0077] In some embodiments, a floating gate, a corresponding gate dielectric layer, and a tunneling layer cooperate to form a sandwich structure. The etch edge spacing between the control gate and the corresponding sandwich structure, and the etch edge spacing between the sandwich structure and the corresponding gallium oxide channel, are both above a set value, which is 200-300 nm. Typically, etching damage has a significant impact on the conduction characteristics of the channel. Therefore, in this preferred embodiment, the etch edge spacing between the control gate and the sandwich structure needs to be above 200-300 nm, and the etch edge spacing between the sandwich structure and the gallium oxide fin channel also needs to be above 200-300 nm to avoid the influence of etching damage. Of course, if the above structure is formed without etching (e.g., by growth, ion implantation, etc.), there is no problem of avoiding the influence of etching damage.

[0078] Regarding other structural and parameter characteristics, in some embodiments, the multi-bit gallium oxide floating gate memory further includes a parallel gate disposed between the source and the drain, the parallel gate being continuously disposed on a plurality of control gates along a first direction for connecting the plurality of control gates in parallel.

[0079] In some implementations, the source and drain electrodes form ohmic contacts with the source and drain regions of the gallium oxide layer, respectively, and the source and drain regions are respectively located at both ends of the gallium oxide channel.

[0080] In some embodiments, the material of the gate dielectric layer and the tunneling layer includes one or more combinations of HfO2, Al2O3, SiO2, and Si3N4.

[0081] In some implementations, the thickness of the gate dielectric layer and the tunneling layer is 5 nm to 15 nm.

[0082] In some embodiments, the thickness of the gallium oxide layer is 50 nm to 200 nm, and the doping concentration is 1 × 10⁻⁶. 16 cm -3 ~ 5×10 17 cm -3 .

[0083] In some embodiments, the thickness of the floating gate is 3 to 7 nm; and / or, the material of the floating gate includes metal.

[0084] In some embodiments, the multi-bit gallium oxide floating gate memory further includes a substrate on which the gallium oxide layer is disposed, the substrate being formed of a wide bandgap material having a bandgap larger than that of gallium oxide.

[0085] Specifically, gallium oxide layers can be grown on commercially available sapphire substrates. Alternative substrates include wide bandgap substrate materials such as diamond and AlN. Substrate bandgap greater than Ga2O3 can enable FPA (Flip-Panel Interconnect) for interconnection with readout circuits using flip-chip bonding.

[0086] Gallium oxide layers can be epitaxially and doped via MOCVD. Alternative growth and doping methods include commercially mature growth methods such as MBE, ALD, HVPE, and PECVD. Donor impurities Si can be replaced with shallow donor impurities such as Sn and H, and are not limited to these, as long as the corresponding functions are achieved.

[0087] In some embodiments, the multi-bit gallium oxide floating gate memory further includes a passivation layer that continuously covers at least the gallium oxide layer, the gate dielectric layer, the tunneling layer, the floating gate, and the control gate.

[0088] The above-described structural and parameter features are specific structures and parameters adopted in representative embodiments of the present invention. However, these are merely representative examples and do not imply that the feasible scope of the present invention is limited to the above-described structural and parameter features. The feasible scope of the technical solution provided by the present invention should be based on the key technical features summarized by the present invention and the corresponding principles provided by the present invention.

[0089] To obtain the aforementioned multi-bit gallium oxide floating gate memory, such as Figure 3 As shown, embodiments of the present invention also provide a method for fabricating a multi-bit gallium oxide floating gate memory, which includes the following steps:

[0090] A gallium oxide layer is grown on the substrate surface, and a source region and a drain region are defined on the gallium oxide layer;

[0091] A gate dielectric layer, a floating gate metal layer, and a tunneling layer are sequentially deposited on the gallium oxide layer in the region between the source and drain regions to form a sandwich layer.

[0092] The sandwich layer is patterned and etched to form a plurality of sandwich structures spaced apart along a first direction. Each sandwich structure includes a floating gate. The first direction intersects with a second direction, which is the arrangement direction of the source region and the drain region.

[0093] Multiple control gates are respectively provided in multiple patterned sandwich structures;

[0094] Mesa etching is performed on the region of the gallium oxide layer located between the source and drain regions to form multiple gallium oxide channels, each of which is correspondingly configured with a control gate.

[0095] Parallel gates are provided on the plurality of control gates to set the plurality of control gates in parallel at the same potential;

[0096] A source and a drain are respectively disposed on the source and drain regions of the gallium oxide layer;

[0097] In this configuration, any one of the control gate-tunneling layer-floating gate forms a first capacitor, and the floating gate-gate dielectric layer-gallium oxide channel forms a second capacitor. When forming the structural unit of the gallium oxide channel-gate dielectric layer-floating gate-tunneling layer-control gate, the corresponding first capacitor and second capacitor form a series capacitor group, and the capacitance ratios of the multiple series capacitor groups are different.

[0098] In some embodiments, the preparation method may further include the following steps:

[0099] The gallium oxide layer is etched to divide it into multiple independent fin-shaped gallium oxide channels, with the two ends of each channel connected to the source region and the drain region, respectively.

[0100] In some embodiments, the preparation method may further include the following steps:

[0101] A passivation layer is provided to continuously cover at least the gallium oxide layer, the gate dielectric layer, the tunneling layer, the floating gate, and the control gate.

[0102] The embodiments of the present invention also provide the use of the above-described multi-bit gallium oxide floating gate memory in the fabrication of integrated sensing, memory, and computing chips or information storage and computing devices.

[0103] A specific example is an information storage method, which includes applying different voltages to a control gate to make all gallium oxide channels non-conductive, or selectively conductive in some gallium oxide channels while the remaining gallium oxide channels are non-conductive, or conduct all gallium oxide channels, in order to adjust the source and drain currents and form multiple bit windows. By identifying the bit windows, the stored bit information of the multi-bit gallium oxide floating gate memory is obtained.

[0104] In further applications, the essence of sensor-memory-computing integration is to integrate computing units into memory arrays. Specifically, this is achieved by fully utilizing the cross-array structure of the memory array and employing Kirchhoff's laws and Ohm's law to complete the neural network algorithm. Therefore, each node in the neural network is composed of memory, and the weights of the nodes can be set by changing the bias voltage of each node. If the neural network only considers Kirchhoff's laws and Ohm's law, then the input only includes the dimension of electrical signals. If the memory has optical sensing capabilities, then the input includes both optical and electrical signals, theoretically enabling more efficient computation and signal processing—the concept of "sensor-memory-computing integration."

[0105] The multi-bit floating gate memory proposed in this invention uses gallium oxide (GaO), an ultra-wide bandgap semiconductor, for its channel. Therefore, the input includes not only electrical signals but also optical signals, utilizing GaO's solar-blind ultraviolet light response characteristics. Gallium oxide has a bandgap of 4.9 eV and an absorption cutoff edge of 254 nm. Since ultraviolet light in this band is almost non-existent in nature, the memory in this invention exhibits extremely low background interference when processing optical signals. A specific implementation scheme for the integrated sensing, memory, and computing based on the multi-bit GaO floating gate memory is as follows:

[0106] See Figure 6 As shown, all nodes in the neural network are multi-bit gallium oxide floating-gate memories. First, the weights of the neural network nodes are initialized by changing the gate voltage. Then, under the stimulation of electrical and optical signals, each node outputs a different current value, which is passed to the activation function. The activation function then judges and processes the output of each column.

[0107] Currently, in ultraviolet-sensing in-memory computing, neural network nodes typically employ resistive switching memories (RSMs), which utilize defects such as oxygen vacancies within the material to achieve short-term storage. However, due to the lack of accurate quantitative characterization methods for these defects, precise programming of RSMs is difficult. This invention proposes a multi-bit gallium oxide floating-gate memory, a device that achieves precise multi-bit programming by controlling the capacitive coupling ratio, and is also a non-volatile memory. Furthermore, since its storage characteristics are independent of material defects, the switching process between multiple conductance states is extremely rapid. The theoretical mobility of gallium oxide is 300 cm⁻¹. 2 The switching time is / V·s, so theoretically it can reach the nanosecond level. This is highly advantageous for high-speed signal processing.

[0108] The above content is merely an illustrative description of the specific application of the integrated sensing, memory, and computing architecture. The focus of this invention is to provide the above-mentioned device structure, its fabrication method, and application prospects, rather than being limited to how to specifically construct the integrated sensing, memory, and computing architecture. Regarding this architecture, there are already technical solutions available in the relevant fields. Those skilled in the art can achieve the above-mentioned technical effects by combining the multi-bit gallium oxide floating gate memory provided by this invention with existing architectures or by designing and developing their own corresponding integrated sensing, memory, and computing architectures. These solutions should also fall within the feasible application scope of this invention.

[0109] The technical solution of the present invention will be further described in detail below through several embodiments and in conjunction with the accompanying drawings. However, the selected embodiments are only for illustrating the present invention and do not limit the scope of the present invention.

[0110] Example 1

[0111] This embodiment provides a high-speed, multi-bit programmable multi-bit gallium oxide floating-gate memory, specifically including:

[0112] Sapphire substrate: Commercially available sapphire substrates (c-plane sapphire and sapphire with off-axis angle orientation are both acceptable) to reduce device costs;

[0113] Gallium oxide layer: thickness ranges from 50 nm to 200 nm, doping concentration ranges from 1 × 10⁻⁶. 16 cm -3 ~ 5×10 17 cm -3 The thickness and doping concentration of the gallium oxide layer directly determine the depletion capability of the floating gate structure for the channel.

[0114] n + -Ga2O3 source / drain regions: Located at both ends of the channel, n-type doping is achieved through ion implantation to optimize the ohmic contact between the source and drain electrodes. The doping concentration range is 5 × 10⁻⁶. 18 cm -3 ~ 5×10 19 cm-3 ;

[0115] Ohmic contact source / drain electrodes: Ti (20~50 nm) / Au (120~150 nm) are used as source / drain ohmic contact electrodes;

[0116] The HfO2 / Pt / HfO2 sandwich structure consists of a first layer of HfO2 directly contacting Ga2O3 as the gate dielectric, with a thickness of 5 nm to 15 nm; a second layer of Pt serving as the floating gate (FG) electrode, with a thickness of 3 to 7 nm; and a third layer of HfO2 serving as the tunneling layer, with a thickness of 5 nm to 15 nm.

[0117] Control Gates (CG): The control gates are G1, G2, G3…G n By changing the control gate G n The area (n = 1, 2, 3…) can be used to adjust the capacitive coupling ratio, thereby changing the voltage difference across the tunneling layer and enabling the multi-floating gate structure to tunnel step by step.

[0118] SiO2 passivation layer: A high-quality SiO2 passivation layer is prepared by PECVD to passivate etching damage and reduce device leakage current; the thickness is 200 nm ~ 300 nm.

[0119] Parallel gates: In this embodiment, to reduce the device area under a multi-gate selection structure and achieve miniaturization of neural network nodes, elongated parallel gates are used to connect the control gates in parallel; the parallel metals are Ni (30~70 nm) / Au (120~150 nm). Of course, other circuit interconnection methods can also be used to achieve equipotential parallel connection.

[0120] Example 2

[0121] This embodiment provides a feasible fabrication scheme for the multi-bit memory described in Embodiment 1 above. It is worth noting that this scheme is not unique, and alternative methods or materials will be described in the fabrication scheme, as follows:

[0122] (1) Ga2O3 ion implantation doping: The sapphire substrate can be either c-plane or beveled with an off-axis angle; after organic cleaning of the sapphire substrate, MOCVD epitaxy and doping of Ga2O3 thin film are performed; the thickness of Ga2O3 thin film is controlled between 50 nm and 200 nm; the epitaxial scheme of Ga2O3 thin film can be replaced by commercially mature growth schemes such as MBE, ALD, HVPE, and PECVD; the ohmic contact region is doped using ion implantation technology. + Doping reduces the contact resistance of the device;

[0123] (2) Preparation of Ga2O3 ohmic contact: A metal Ti (20~50nm) / Au (120~150nm) bilayer was deposited on the Ga2O3 film using an electron beam evaporation device and annealed in a nitrogen atmosphere for 1 min at a temperature of 475 °C.

[0124] (3) Preparation of HfO2 / Pt / HfO2 sandwich structure: First, a layer of HfO2 with a thickness of 5 nm ~ 15 nm was deposited on the surface of Ga2O3 film using ALD; a layer of Pt metal with a thickness of 3 ~ 7 nm was deposited on the surface of HfO2 using electron beam evaporation; finally, a layer of HfO2 with a thickness of 5 nm ~ 15 nm was deposited on the surface of Pt metal using ALD.

[0125] (4) Floating gate structure patterning: The HfO2 / Pt / HfO2 sandwich structure is patterned using ICP etching, and the shape is a rectangle parallel to the direction of carrier movement in the channel; the number of bits of the memory will be proportional to the number of bar structures (usually the number of bits is the number of bars + 1, for example, 3 bars correspond to the 4 bit states of: all off, 1 on, 2 on, and 3 on); the sandwich structure dimensions are: length range: 40 μm ~ 50 μm, width range: 2 μm ~ 3 μm.

[0126] (5) Fabrication of multi-size control gates: Control gate electrodes are fabricated on patterned sandwich structures using electron beam evaporation technology. The metal used is a Ni (20~50 nm) / Au (120~150 nm) bilayer metal. The size gradient of the control gate is reduced, with a maximum length of 40 μm ~ 50 μm, a minimum length of 2 μm ~ 5 μm, and a gradient of 5 µm.

[0127] (6) Fin-shaped channel mesa etching: In order to achieve multi-level conductivity states and obtain multi-bit storage characteristics, the Ga2O3 channel is etched to prepare a fin-shaped structure, while achieving the purpose of electrical isolation; etching can be carried out by ICP, RIE and other schemes.

[0128] (7) Preparation of SiO2 passivation layer: 200 nm ~ 300 nm SiO2 passivation layer is prepared by PECVD to suppress leakage current in the etched area; the passivation layer can be replaced by media such as Si3N4 and Al2O3.

[0129] (8) Parallel gate fabrication: Thickened electrodes are fabricated by electron beam evaporation and all control gate metals are connected in parallel; the thickened electrodes are made of four layers of metal, Ti / Cu / Ti / Au, with thicknesses of 20 nm ~ 50 nm, 500 nm ~ 1000 nm, 20 nm ~ 50 nm, and 50 nm ~ 100 nm, respectively.

[0130] Based on the above embodiments, it is clear that the multi-bit gallium oxide floating gate memory proposed in this invention uses a floating gate structure to control channel opening. Stable storage comes from electron tunneling. The conduction band order of the tunneling layer and CG and FG can ensure stable charge storage. The tunneling voltage can be precisely controlled by adjusting the capacitance ratio by changing the control gate area and other conditions, thereby controlling the step-by-step opening of the gallium oxide channel and realizing precise multi-bit programming. Compared with the MoS2 floating gate memory, the multi-bit gallium oxide floating gate memory proposed in this invention can obtain different storage windows by only changing the voltage of the parallel control gate. Compared with the MoS2 floating gate memory, which requires selecting multiple gates to achieve multi-bit storage, the circuit complexity is significantly reduced.

[0131] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A multi-bit gallium oxide floating gate memory, characterized in that, include: The gallium oxide layer includes a plurality of gallium oxide channels that are sequentially spaced apart along a first direction; The source and drain are disposed at intervals along the second direction on the gallium oxide layer and electrically connected to each other through a plurality of gallium oxide channels, wherein the first direction intersects the second direction; A gate dielectric layer is stacked on the gallium oxide layer; Multiple floating gates are sequentially and spaced apart on the gate dielectric layer along the first direction, and each floating gate is correspondingly disposed with a gallium oxide channel; Multiple control gates are respectively disposed on multiple floating gates, and a tunneling layer is disposed between any corresponding set of control gates and floating gates; In this configuration, any one of the control gate-tunneling layer-floating gate forms a first capacitor, and the floating gate-gate dielectric layer-gallium oxide channel forms a second capacitor. The corresponding first capacitor and second capacitor form a series capacitor group, and the capacitance ratios of the multiple series capacitor groups are different; and the multiple control gates are connected in parallel at the same potential.

2. The multi-bit gallium oxide floating gate memory according to claim 1, characterized in that: The areas of the multiple control gates are different; and / or the spacing between the multiple control gates and the floating gates is different; and / or the dielectric constant of the tunneling layer between the multiple sets of floating gates and the control gates is different.

3. The multi-bit gallium oxide floating gate memory according to claim 2, characterized in that: The areas of the plurality of floating gates are the same; and the areas of the plurality of control gates increase or decrease in a gradient along a first direction, and / or the thickness of the tunneling layer increases or decreases in a gradient along a first direction, and / or the dielectric constant of the dielectric material constituting the tunneling layer increases or decreases in a gradient along a first direction.

4. The multi-bit gallium oxide floating gate memory according to claim 3, characterized in that: The control gate is rectangular, and multiple control gates have the same gate width, with the gate length increasing or decreasing along a first direction; the gate length direction of the control gate is parallel to a second direction.

5. The multi-bit gallium oxide floating gate memory according to claim 4, characterized in that: The maximum gate length of the multiple control gates is 40~50 μm, the minimum gate length is 2~5 μm, and the gate length variation gradient is 2~5 μm.

6. The multi-bit gallium oxide floating gate memory according to claim 1, characterized in that: The gallium oxide channel is a fin-shaped channel; and / or the spacing between adjacent gallium oxide channels is 2~3 μm; And / or, one of the floating gates, together with the corresponding gate dielectric layer and tunneling layer, forms a sandwich structure, and the etching edge spacing between the control gate and the corresponding sandwich structure and the etching edge spacing between the sandwich structure and the corresponding gallium oxide channel are both above a set value, the set value being 200~300 nm.

7. The multi-bit gallium oxide floating gate memory according to claim 1, characterized in that: The multi-bit gallium oxide floating gate memory further includes a parallel gate disposed between the source and the drain, the parallel gate being continuously disposed on a plurality of control gates along a first direction for arranging the plurality of control gates in parallel; and / or, the source and drain respectively form ohmic contacts with the source region and drain region of the gallium oxide layer, the source region and drain region being respectively disposed at both ends of the gallium oxide channel; And / or, the material of the gate dielectric layer and the tunneling layer includes one or more combinations of HfO2, Al2O3, SiO2, and Si3N4; And / or, the thickness of the gate dielectric layer and the tunneling layer is 5 nm to 15 nm; And / or, the thickness of the gallium oxide layer is 50 nm to 200 nm, and the doping concentration is 1 × 10⁻⁶. 16 cm -3 ~ 5×10 17 cm -3 ; And / or, the thickness of the floating gate is 3~7 nm; and / or, the material of the floating gate includes metal; And / or, the multi-bit gallium oxide floating gate memory further includes a substrate, the gallium oxide layer being disposed on the substrate, the substrate being formed of a wide bandgap material having a bandgap larger than that of gallium oxide; And / or, the multi-bit gallium oxide floating gate memory further includes a passivation layer that continuously covers at least the gallium oxide layer, the gate dielectric layer, the tunneling layer, the floating gate, and the control gate.

8. A method for fabricating a multi-bit gallium oxide floating gate memory, characterized in that, include: A gallium oxide layer is grown on the substrate surface, and a source region and a drain region are defined on the gallium oxide layer; A gate dielectric layer, a floating gate metal layer, and a tunneling layer are sequentially deposited on the gallium oxide layer in the region between the source and drain regions to form a sandwich layer. The sandwich layer is patterned and etched to form a plurality of sandwich structures spaced apart along a first direction. Each sandwich structure includes a floating gate. The first direction intersects with a second direction, which is the arrangement direction of the source region and the drain region. Multiple control gates are respectively provided in multiple patterned sandwich structures; Mesa etching is performed on the region of the gallium oxide layer located between the source and drain regions to form multiple gallium oxide channels, each of which is correspondingly configured with a control gate. Parallel gates are provided on the plurality of control gates to set the plurality of control gates in parallel at the same potential; A source and a drain are respectively disposed on the source and drain regions of the gallium oxide layer; In this configuration, any one of the control gate-tunneling layer-floating gate forms a first capacitor, and the floating gate-gate dielectric layer-gallium oxide channel forms a second capacitor. When forming the structural unit of the gallium oxide channel-gate dielectric layer-floating gate-tunneling layer-control gate, the corresponding first capacitor and second capacitor form a series capacitor group, and the capacitance ratios of the multiple series capacitor groups are different.

9. The method for fabricating a multi-bit gallium oxide floating gate memory according to claim 8, characterized in that, Also includes: The gallium oxide layer is etched to divide it into multiple independent fin-shaped gallium oxide channels, with the two ends of each channel connected to the source region and the drain region, respectively. And / or, further comprising: providing a passivation layer to at least continuously cover the gallium oxide layer, the gate dielectric layer, the tunneling layer, the floating gate, and the control gate.

10. Use of the multi-bit gallium oxide floating gate memory according to any one of claims 1-6 in the fabrication of an integrated chip for sensing, memory, and computing or an information storage and computing device.

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