Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. Source / drain regions of a nanostructured transistor for a semiconductor device are formed such that the source / drain regions include a metal core. The metal core provides a larger surface area for the front side source / drain contact and the back side source / drain contact to be coupled to the source / drain region than where the source / drain region is fully filled with an epitaxially grown semiconductor material. The increased contact surface area provides a reduced contact resistance between the source / drain region and the source / drain contacts on the front side and on the rear side because the current flow path between the source / drain region and the source / drain contacts on the front side and on the rear side is less limited. The contact resistance between the source / drain regions and the source / drain contacts on the front and rear sides is reduced, enabling higher power efficiency of the nanostructured transistor and / or enabling an increase in switching speed of the nanostructured transistor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to semiconductor devices and methods of forming the same. Background Technology

[0002] As semiconductor device manufacturing advances and process node sizes shrink, transistors can become susceptible to short-channel effects (SCE) (such as hot carrier degradation, barrier reduction, and quantum confinement). Furthermore, as transistor gate lengths decrease for smaller technology nodes, source / drain (S / D) electron tunneling increases, which amplifies the transistor's cutoff current (the current flowing through the transistor's channel when it is in the off configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors (e.g., nanowires, nanosheets, and gate-all-around (GAA) devices) are potential candidates for overcoming short-channel effects at smaller technology nodes. Nanostructure transistors are highly efficient structures compared to other types of transistors, exhibiting reduced SCE and enhanced carrier mobility. Summary of the Invention

[0003] In one aspect, embodiments of this application provide a method comprising: forming a plurality of nanostructured channels arranged in a direction substantially perpendicular to a semiconductor layer of a semiconductor device; forming source / drain recesses adjacent to the plurality of nanostructured channels; partially filling the source / drain recesses with an epitaxial material to form source / drain regions in the source / drain recesses, wherein the source / drain regions include hollow cores; forming gate structures surrounding at least three sides of the plurality of nanostructured channels; filling the hollow cores of the source / drain regions with a material of a metal core; forming a first source / drain contact on a first side of the metal core; and forming a second source / drain contact on a second side of the metal core opposite to the first side.

[0004] In another aspect, embodiments of this application provide a method comprising: forming a plurality of nanostructured channels arranged in a semiconductor device along a first direction and extending in the semiconductor device along a second direction substantially perpendicular to the first direction; forming a source / drain region adjacent to the plurality of nanostructured channels in the second direction; forming a dielectric layer above the source / drain region; forming a gate structure surrounding at least three sides of the plurality of nanostructured channels; forming a first contact recess from a first side of the semiconductor device, penetrating the dielectric layer and entering the source / drain region, such that the bottom of the first contact recess is at a depth in the semiconductor device lower than that of the bottommost nanostructured channel among the plurality of nanostructured channels; forming a first source / drain contact in the first contact recess, such that the first source / drain contact extends into the source / drain region; forming a second contact recess from a second side of the semiconductor device opposite to the first side, extending into the source / drain region; and forming a second source / drain contact in the second contact recess, such that the second source / drain contact is coupled to the source / drain region.

[0005] In another aspect, embodiments of this application provide a semiconductor device comprising: a plurality of nanostructured channels arranged along a first direction and extending along a second direction, the second direction being substantially perpendicular to the first direction; a gate structure surrounding the plurality of nanostructured channels; a source / drain region adjacent to the side of the gate structure and adjacent to the ends of the plurality of nanostructured channels, the source / drain region comprising: a metal core; and one or more epitaxial layers laterally surrounding the metal core; a front source / drain contact located on the front side of the semiconductor device and electrically connected to a first side of the metal core of the source / drain region; and a rear source / drain contact located on the rear side of the semiconductor device and electrically connected to a second side of the metal core of the source / drain region opposite to the first side. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1A-1C This is a schematic diagram illustrating an example implementation of the fin definition process described in this article.

[0008] Figure 2 This is a schematic diagram of the formation process of the example dummy gate structure described in this article.

[0009] Figure 3 This is a schematic diagram illustrating an example implementation of the source / drain recess formation process described in this article.

[0010] Figure 4Aand Figure 4B This is a schematic diagram illustrating an example implementation of the internal spacer formation process described in this article.

[0011] Figure 5A and Figure 5B This is a schematic diagram illustrating an example implementation of the source / drain region formation process described in this article.

[0012] Figure 6 This is a schematic diagram illustrating an example implementation of the interlayer dielectric formation process described in this article.

[0013] Figure 7A and Figure 7B This is a schematic diagram of an example implementation of the gate replacement process described in this article.

[0014] Figure 8A-8I This is a schematic diagram illustrating an example implementation of the source / drain contact formation process described in this article.

[0015] Figure 9 This is a schematic diagram illustrating an example implementation of the semiconductor device described in this article.

[0016] Figure 10A-10I This is a schematic diagram illustrating an example implementation of the semiconductor device described herein.

[0017] Figure 11A-11G This is a schematic diagram illustrating an example implementation of the semiconductor device described herein.

[0018] Figure 12A-12F This is a schematic diagram illustrating an example implementation of the semiconductor device described herein.

[0019] Figure 13 This is a schematic diagram illustrating an example implementation of the semiconductor device described in this article.

[0020] Figure 14A-14F This is a schematic diagram illustrating an example implementation of the semiconductor device described herein.

[0021] Figure 15 This is a flowchart of an example process associated with forming the semiconductor device described herein.

[0022] Figure 16 This is a flowchart of an example process associated with forming the semiconductor device described herein. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, this document may use spatially relevant terms (e.g., "below," "under," "lower," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0025] Nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, GAA transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors) can overcome one or more of the aforementioned drawbacks of some types of transistors. However, the manufacturing challenges faced by nanostructured transistors can lead to performance problems, manufacturing yield issues, and / or device failures.

[0026] For example, as feature sizes decrease, various parts of a nanostructured transistor may become more susceptible to increased resistance. One such susceptible part is the connection between the source / drain regions and the source / drain contacts formed on these regions. As the dimensions (e.g., lateral width) of the source / drain regions and contacts decrease, the contact surface area between them decreases. This reduced contact surface area restricts electron flow between the source / drain regions and contacts, increasing current congestion around them. This increased current congestion leads to increased contact resistance between the source / drain regions and contacts. This can result in reduced power efficiency and / or reduced switching speed of the nanostructured transistor.

[0027] In some implementations described herein, a source / drain region is formed for a nanostructured transistor in a semiconductor device, such that a hollow core extends from the top of the source / drain region through the source / drain region to the bottom of the source / drain region. The hollow core is achieved through partial epitaxial growth of one or more epitaxial layers of the source / drain region. A metal core of the source / drain region is formed within the hollow core and electrically coupled to the front source / drain contact of the nanostructured transistor, such that conductive material is recessed within the source / drain region. This provides a larger contact surface area between the front source / drain contact and the source / drain region compared to a case where the source / drain region is completely filled with epitaxially grown semiconductor material. Furthermore, the metal core extending through the source / drain region enables the metal core to connect to the rear source / drain contact on the back side of the semiconductor device, thus electrically connecting the source / drain region to interconnect layers on the front and rear sides of the semiconductor device.

[0028] Because the current flow path between the source / drain region and the front and rear source / drain contacts is less restricted, the increased contact surface area provides reduced contact resistance between the source / drain region and the front and rear source / drain contacts. This reduced contact resistance enables higher power efficiency and / or greater switching speeds for nanostructured transistors. Furthermore, the metal core extending fully through the source / drain region allows a single metal silicide layer to be shared by the front and rear source / drain contacts, reducing the process complexity, time, and / or cost of forming semiconductor devices.

[0029] Alternatively and alternatively, by etching the source / drain regions so that the front source / drain contacts can be recessed within the source / drain regions, an increased contact surface area can be achieved between the source / drain regions of the nanostructure transistor in the semiconductor device and the front source / drain contacts. A multi-step etching process can be performed to form recesses in the source / drain regions such that the recesses extend at least below the top nanostructure channel of the nanostructure transistor. In some implementations, recesses can be formed in the source / drain regions such that the recesses extend below the bottom nanostructure channel of the nanostructure transistor. This allows the rear source / drain contacts to connect to the recessed portion of the front source / drain contacts and also allows the front and rear source / drain contacts to share the same metal silicide layer.

[0030] Figure 1A-1CThis is a schematic diagram of an example implementation 100 of the fin definition process described herein. Example implementation 100 includes an example of forming a fin structure and associated shallow trench isolation (STI) region for a semiconductor device 105 described herein. The semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include one or more nanostructure transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructure transistors. Example implementation 100 includes an example of forming a fin structure and associated STI region for the transistors of the semiconductor device 105.

[0031] Figure 1A-1C Each shows a perspective view of the semiconductor device 105 and a cross-sectional view along line AA in the perspective view. (See diagram below.) Figure 1A As shown, the processing of semiconductor device 105 is performed in conjunction with semiconductor substrate 110. Semiconductor substrate 110 includes: silicon (Si) substrate, substrate formed of a material including silicon, III-V compound semiconductor material substrate such as gallium arsenide (GaAs), silicon-on-insulator (SOI) substrate, germanium (Ge) substrate, silicon-germanium (SiGe) substrate, silicon carbide (SiC) substrate, or other types of semiconductor substrate.

[0032] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction generally perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes alternating layers of sacrificial nanostructure layer 120 and nanostructure channel layer 125 above the semiconductor substrate 110 in the vertical direction. Figure 1A The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 shown are examples, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are also within the scope of this disclosure.

[0033] The sacrificial nanostructure layer 120 enables the definition of a vertical distance between adjacent nanostructure channels formed by the nanostructure channel layer 125 and serves as a placeholder layer for the gate structure of the transistor of the subsequently formed semiconductor device 105 (formed around the nanostructure channels). The sacrificial nanostructure layer 120 includes a first material composition, and the nanostructure channel layer 125 includes a second material composition. In some implementations, the first and second material compositions are the same. In some implementations, the first and second material compositions are different. For example, the sacrificial nanostructure layer 120 may include silicon germanium (SiGe), and the nanostructure channel layer 125 may include silicon (Si). This allows the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 to be selectively etched depending on the type of etchant used (e.g., allowing the sacrificial nanostructure layer 120 but not the nanostructure channel layer 125 to be etched, or allowing the nanostructure channel layer 125 but not the sacrificial nanostructure layer 120 to be etched).

[0034] One or more types of deposition tools may be used to deposit and / or grow alternating layers of the stack 115 to include nanostructures (e.g., nanosheets) on the semiconductor substrate 110. For example, the deposition tools may be used to grow a sacrificial nanostructure layer 120 and / or a nanostructure channel layer 125 via epitaxial growth, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0035] One or more mask layers may be formed (e.g., using one or more deposition tools) on the layer stack 115. The mask layers may include a hard mask (HM) layer 130, a cap layer 135, an oxide layer 140, and / or a nitride layer 145. The mask layers may be used to perform fin patterning operations to form fin structures in the semiconductor substrate 110.

[0036] like Figure 1BAs shown, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate. This allows a fin structure 150 to extend over the semiconductor substrate 110. The fin structure 150 may extend in the y-direction within the semiconductor device 105 and may be aligned in the x-direction within the semiconductor device 105. The fin structure 150 includes portions 155 of the layer stack 115 on and / or above a fin portion 160 above the semiconductor substrate 110. The fin structure 150 can be formed by patterning one or more mask layers and etching the semiconductor substrate 110 based on the pattern formed in the one or more mask layers. The one or more mask layers can be patterned using photolithography techniques, including dual patterning or multiple patterning techniques. Etching tools can be used to etch the semiconductor substrate 110 based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0037] like Figure 1B As further illustrated, for different types of nanostructure transistors, some fin structures 150 can be formed with different widths. For example, a first subset 150a of the fin structures can be formed for p-type nanostructure transistors (e.g., p-type metal-oxide-semiconductor (PMOS) nanostructure transistors), and a second subset 150b of the fin structures can be formed for n-type nanostructure transistors (e.g., n-type metal-oxide-semiconductor (NMOS) nanostructure transistors). As another example, the first subset 150a of the fin structures can be formed for nanostructure transistors configured to operate at lower voltages, and the second subset 150b of the fin structures can be formed for nanostructure transistors configured to operate at higher voltages.

[0038] like Figure 1C As shown, the liner 165 and the STI region 170 are formed between adjacent fin portions 160 of the fin structure 150. The liner 165 and the STI region 170 may each comprise a dielectric material, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiO2), fluorine-doped silicate glass (FSG), low-k dielectric material and / or another suitable insulating material.

[0039] A deposition tool can be used to conformally deposit the liner (e.g., using ALD or another conformal deposition technique), and a dielectric layer can be deposited on the liner 165 (e.g., using CVD, PVD, ALD, and / or another suitable deposition technique) such that the dielectric layer completely fills the space between the fin structures 150 and extends above the top of the fin structures 150. A planarization tool can then be used to perform a planarization or polishing operation (e.g., a chemical mechanical planarization (CMP) operation) to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top of the nitride layer 145. The nitride layer 145 serves as a CMP stop layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form an STI region 170 such that the top surface of the STI region 170 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0040] As mentioned above, Figure 1A-1C Provided as an example only. Other examples may be provided. Figure 1A-1C The differences described in [the original text].

[0041] Figure 2 This is a schematic diagram of an example implementation 200 of the dummy gate formation process described herein. Example implementation 200 includes an example of forming a dummy gate structure 205 for a nanostructured transistor in a semiconductor device 105. In some implementations, the operations described in connection with example implementation 200 are combined with... Figure 1A-1C The process described above is executed afterward.

[0042] Figure 2 A perspective view of a semiconductor device 105 having a dummy gate structure 205 formed thereon is shown. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed on some portions of the fin structure 150 and some portions of the STI region 170. The dummy gate structure 205 extends in the x-direction and is aligned in the y-direction such that the dummy gate structure 205 is substantially perpendicular to the fin structure 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack in subsequent processing stages of the semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) recess in which the source / drain region of a nanostructured transistor is formed.

[0043] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 on and / or above the gate electrode layer 210, a spacer layer 220 on the opposite side of the gate electrode 210, and a gate dielectric layer 225 below the gate electrode 210. The gate electrode layer 210 includes polysilicon (PO) or another material. The hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or another material) and a nitride layer formed on the oxide layer (e.g., a pad nitride layer that may include silicon nitride (e.g., Si3N4) or another material). The spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or another suitable material. The gate dielectric layer 225 may include silicon oxide (e.g., SiO2). x (e.g., SiO2), silicon nitride (e.g., Si) x N y Materials such as Si3N4), high dielectric constant (high k) dielectric materials (e.g., dielectric materials with a dielectric constant greater than about 3.9) and / or another suitable material.

[0044] Various semiconductor processing techniques (such as depositing the layers of the dummy gate structure 205, patterning the layers of the dummy gate structure 205 to define the dummy gate structure 205) and / or other semiconductor processing techniques can be used to form the layers of the dummy gate structure 205.

[0045] Figure 2 Reference sections used in the subsequent figures described herein are further illustrated. Section AA lies in the xz plane (referred to as the y section) across the fin structure 150 in the source / drain region of semiconductor device 105. Section BB lies in the yz plane (referred to as the x section) perpendicular to section AA and across the dummy gate structure 205 and along the underlying fin structure 150. Section CC lies in the xz plane parallel to section AA and perpendicular to section BB, and along the dummy gate structure 205. For clarity, these reference sections are referenced in the subsequent figures. In some figures, some reference numerals for components or features shown may be omitted for ease of depiction to avoid obscuring other components or features.

[0046] As mentioned above, Figure 2 This is provided as an example. Other examples may be related to... Figure 2 The descriptions differ.

[0047] Figure 3 This is a schematic diagram of an example implementation 300 of the source / drain recess formation process described herein. Example implementation 300 includes an example of forming source / drain recesses 305 in the source / drain regions of a nanostructure transistor of a semiconductor device 105. Figure 3 from Figure 2 The diagram is illustrated from multiple angles, including Figure 2 Perspective view of section AA in the middle, Figure 2 Perspective view of section BB in the middle, and Figure 2 A perspective view of section CC in [the document / structure]. In some implementations, the operation described in conjunction with example implementation 300 is [in conjunction with / with / etc.]. Figure 1A-2 The process described above is executed afterward.

[0048] like Figure 3 As shown in sections AA and BB, during the etching operation, a source / drain recess 305 is formed through a portion 155 of the fin structure 150. The source / drain recess 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some implementations, the etching operation includes the use of plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0049] The source / drain recesses 305 also extend into a portion of the fin portion 160 of the fin structure 150. This results in the formation of a mesa region 310 in the fin structure 150. The sidewall of the portion of each source / drain recess 305 below the layer stack 115 corresponds to the sidewall of the mesa region 310. The mesa region 310 (also referred to as the base) refers to the region of the fin portion 160 of the fin structure 150 in which a nanostructured channel is defined from the nanostructured channel layer 125. The nanostructured channel 315 extends between adjacent source / drain recesses 305 and lies beneath the dummy gate structure 205 between adjacent source / drain recesses 305.

[0050] The nanostructured channel 315 includes a silicon-based nanostructure (e.g., nanosheets or nanowires, etc.) that serves as the semiconductor channel for a nanostructured transistor in the semiconductor device 105. In some implementations, the nanostructured channel 315 may include silicon-germanium (SiGe) or another silicon-based material. The nanostructured channel 315 is aligned in a direction generally perpendicular to the semiconductor substrate 110 (e.g., the z-direction). In other words, the nanostructured channel 315 is aligned or stacked vertically above the semiconductor substrate 110.

[0051] As mentioned above, Figure 3 This is provided as an example. Other examples may be related to... Figure 3 The descriptions differ.

[0052] Figure 4A and Figure 4BThis is a schematic diagram of an example implementation 400 of the internal spacer formation process described herein. Example implementation 400 includes an example of forming internal spacers between the ends of nanostructured channels 315 exposed in source / drain recesses 305. Figure 4A and Figure 4B from Figure 2 The diagram is illustrated from multiple angles, including Figure 2 Perspective view of section AA in the middle, Figure 2 Perspective view of section BB in the middle, and Figure 2 A perspective view of section CC in [the document / structure]. In some implementations, the operation described in conjunction with example implementation 400 is [in conjunction with / with / etc.]. Figure 1A-3 The process described above is executed afterward.

[0053] like Figure 4A As shown in sections AA and BB, during the etching operation, the ends of the sacrificial nanostructure layer 120 can be etched laterally (e.g., along the x-direction generally parallel to the length of the sacrificial nanostructure layer 120) to form a cavity 405 between the ends of the nanostructure channel 315 exposed in the source / drain recess 305. An etching tool can be used to perform a wet etching operation to selectively etch the ends of the sacrificial nanostructure layer 120 relative to the nanostructure channel 315 to form the cavity 405. Alternatively and / or alternatively, another etching technique, such as dry etching (e.g., gas-based etching), can be used.

[0054] like Figure 4B As shown in sections AA and BB, an internal spacer (InSP) 410 is formed in the cavity 405 at the end of the sacrificial nanostructure layer 120 exposed in the source / drain recess 305. The internal spacer 410 may be included to reduce parasitic capacitance in the nanostructure transistor and to protect the source / drain regions (subsequently formed in the source / drain recess 305) from etching during nanosheet release operations to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. The internal spacer 410 comprises silicon nitride (Si). x N y ), silicon dioxide (SiO) x ), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN) and / or another dielectric material.

[0055] To form the internal spacer 410, a dielectric material layer can be deposited in the cavity 405 and along the sidewalls and bottom surface of the source / drain recess 305 using a deposition tool. CVD, PVD, ALD, and / or another deposition technique can be used to deposit the dielectric material layer. Excess material of the dielectric material layer is then removed from the source / drain recess using an etching tool, leaving the remaining portion corresponding to the internal spacer 410. Alternatively, the internal spacer 410 can be selectively formed on the ends of the sacrificial nanostructure layer 120 using a precursor that is selectively bonded to the material of the sacrificial nanostructure layer 120 but not to the material of the fin portion 160 and the nanostructure channel 315.

[0056] As mentioned above, Figure 4A and Figure 4B Provided as an example only. Other examples may be related to... Figure 4A and Figure 4B The description differs from that in the text.

[0057] Figure 5A and Figure 5B This is a schematic diagram of an example implementation 500 of the source / drain region formation process described herein. Example implementation 500 includes an example of forming the source / drain regions of a nanostructure transistor of semiconductor device 105. Figure 5A and Figure 5B from Figure 2 The diagram is illustrated from multiple angles, including Figure 2 Perspective view of section AA in the middle, Figure 2 Perspective view of section BB in the middle, and Figure 2 A perspective view of section CC in [the document / structure]. In some implementations, the operation described in conjunction with example implementation 500 is [in conjunction with / with / etc.]. Figure 1A-4B The process described above is executed afterward.

[0058] like Figure 5A As shown in sections AA and BB, during the etching operation, the ends of the nanostructured channels 315 can be etched laterally (e.g., along the x-direction generally parallel to the length of the sacrificial nanostructured layer 120) to form recesses between adjacent internal spacers 410 in the vertical direction. This can be referred to as a channel push operation. Etching tools can be used to perform a wet etching operation to selectively etch the ends of the nanostructured channels 315 relative to the sacrificial nanostructured layer, thereby forming cavities 505. Alternatively and / or as an alternative, another etching technique, such as dry etching (e.g., gas-based etching), can be used.

[0059] like Figure 5BAs shown in sections AA and BB, the source / drain recess 305 is filled with one or more layers to form a source / drain region 505 within the source / drain recess 305. For example, a deposition tool may be used to deposit a first epitaxial layer 510 (sometimes referred to as "L1") at the bottom of the source / drain recess 305 and at the recessed end of the nanostructure channel 315. As another example, a deposition tool may be used to deposit a second epitaxial layer 515 (sometimes referred to as "L2") within the source / drain recess 305. The second epitaxial layer 515 may fill the remaining area in the source / drain recess 305 below the dummy gate structure 205 and may contact the first epitaxial layer 510 and the internal spacer 410 still exposed within the source / drain recess 305.

[0060] Depending on the context, the "source / drain region" may be referred to individually or collectively as the source or drain. The source / drain region 505 may be included on the opposite side of the dummy gate structure 205 such that the nanostructured channel 315 under the dummy gate structure 205 extends between and is electrically coupled to the source / drain region 505.

[0061] The first epitaxial layer 510 and the second epitaxial layer 515 of the source / drain region 505 may each comprise a semiconductor material, such as silicon (Si), silicon germanium (SiGe), silicon arsenide (SiAs), silicon phosphide (SiP), and / or another semiconductor material. The first epitaxial layer 510 and the second epitaxial layer 515 may each be doped with one or more dopants, such as arsenic (As), phosphorus (P), and / or boron (B).

[0062] For a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor, the first epitaxial layer 510 and the second epitaxial layer 515 of the source / drain region 505 may each comprise boron (B)-doped silicon germanium (SiGe). The germanium (Ge) concentration of the second epitaxial layer 515 may be greater than that of the first epitaxial layer 510. For example, the germanium (Ge) concentration of the second epitaxial layer 515 may be in the range of about 40% to about 60%, while the germanium (Ge) concentration of the first epitaxial layer 510 may be in the range of about 10% to about 20%. However, other values ​​and ranges are within the scope of this disclosure. The boron (B) dopant concentration of the second epitaxial layer 515 and the boron (B) dopant concentration of the first epitaxial layer 510 may each be in the range of about 5 × 10⁻⁶. 20 Up to approximately 5×10 21 Within the range. However, other values ​​and ranges are within the scope of this disclosure.

[0063] For an n-type metal-oxide-semiconductor (NMOS) nanostructure transistor, the first epitaxial layer 510 and the second epitaxial layer 515 of the source / drain region 505 may each comprise silicon (Si) doped with arsenic (As) and / or phosphorus (P). The dopant concentration of the second epitaxial layer 515 may be greater than that of the first epitaxial layer 510. For example, the dopant concentration of the second epitaxial layer 515 may be included in approximately 2 × 10⁻⁶. 21 Up to approximately 9×10 21 Within the range, the dopant concentration of the first epitaxial layer 510 can be included in approximately 1 × 10⁻⁶. 20 Up to approximately 1×10 21 Within the range. However, other values ​​and ranges are within the scope of this disclosure.

[0064] The first epitaxial layer 510 and the second epitaxial layer 515 of the source / drain region 505 can be formed by epitaxial growth, deposition (e.g., using CVD, PVD, ALD), and / or using one or more other deposition techniques. For example, a deposition tool can epitaxially grow a merging region 520 of the first epitaxial layer 510 at the bottom of the source / drain recess 305. The merging region 520 may include a continuous layer of epitaxially grown material extending from the mesa region 310 to the end of the bottommost nanostructure channel 315.

[0065] As another example, a deposition tool can epitaxially grow a plurality of discontinuous second epitaxial regions 525 of the first epitaxial layer 510 in a recess at the end of a nanostructured channel 315 above the merging region 520. The discontinuous second epitaxial regions 525 are regions of epitaxially grown material that do not contact each other (e.g., because they are separated by internal spacers 410) and do not contact the merging region 520. The second epitaxial layer 515 can be grown on portions of the internal spacers 410 exposed between the discontinuous second epitaxial regions 525 and between the merging region 520 and the discontinuous second epitaxial regions 525.

[0066] As mentioned above, Figure 5A and Figure 5B Provided as an example. Other examples may be related to... Figure 5A and Figure 5B The descriptions differ.

[0067] Figure 6 This is a schematic diagram of an example implementation 600 of the interlayer dielectric (ILD) formation process described herein. Figure 6 from Figure 2 The diagram is illustrated from multiple angles, including Figure 2 Perspective view of section AA in the middle, Figure 2 Perspective view of section BB in the middle, and Figure 2A perspective view of section CC in [the document / structure]. In some implementations, the operation described in conjunction with example implementation 600 is [in conjunction with...]. Figure 1A-5B The process described above is executed afterward.

[0068] like Figure 6 As shown in sections AA and BB, a dielectric layer 605 is formed over the source / drain region 505. The dielectric layer 605 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce and / or prevent damage to the source / drain region 505 during a gate replacement process that replaces the dummy gate structure 205. The dielectric layer 605 may be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0069] In some implementations, a contact etch stop layer (CESL) 610 is conformally deposited (e.g., by a deposition tool) over the source / drain region 505 prior to the formation of the dielectric layer 605. The dielectric layer 605 is then formed on the CESL 610. The CESL 610 can provide a mechanism to stop the etching process when forming contacts or vias in the source / drain region 505.

[0070] The dielectric layer 605 may include oxides (e.g., silicon oxide (SiO2)). x The dielectric layer 605 may be an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), silsesquioxane (HSQ), and / or another suitable dielectric material. In some implementations, the dielectric layer 605 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x amorphous fluorinated carbon (aC) x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbonate (SiOC) polymers, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE) and / or porous silica (SiO2) x The dielectric layer 605 can be deposited using deposition processes such as ALD, CVD, or another deposition technique.

[0071] CESL 610 can be formed from a dielectric material having different etch selectivity than adjacent layers or components. CESL 610 may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, CESL 610 may include or may be silicon nitride (Si). x N ySilicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbonate (SiCO), or combinations thereof. CESL 610 can be deposited using deposition processes such as ALD, CVD, or another deposition technique.

[0072] As mentioned above, Figure 6 Provided as an example. Other examples may be related to... Figure 6 The descriptions differ.

[0073] Figure 7A and Figure 7B This is a schematic diagram of an example implementation 700 of the replacement gate (RPG) process described herein. Example implementation 700 includes an example of a replacement gate process for replacing a dummy gate structure 205 with a high-k / metal gate structure (e.g., a replacement gate structure) for a nanostructured transistor of semiconductor device 105. Figure 7A and Figure 7B Each from Figure 2 The illustrations are presented from multiple angles, including Figure 2 Perspective view of section AA in the middle, Figure 2 Perspective view of section BB in the middle, and Figure 2 A perspective view of section CC in [the document / structure]. In some implementations, the operation described in conjunction with example implementation 700 is [in conjunction with / with / etc.]. Figure 1A-6 The process described above is executed afterward.

[0074] like Figure 7A As shown in sections BB and CC, the gate replacement process includes a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. Removing the dummy gate structure 205 leaves an opening (or recess) in the dielectric layer 605 and provides a channel to the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 can be removed in one or more etching operations. Such etching operations can include plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0075] like Figure 7AAs further shown, the gate replacement process includes a nanostructure release operation (e.g., a SiGe release operation). The nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon-germanium layer). This creates openings 705 between the nanostructure channels 315 (e.g., regions surrounding the nanostructure channels 315). The sacrificial nanostructure layer 120 can be removed through the space previously occupied by the dummy gate structure 205. The nanostructure release operation may include performing an etching operation using an etching tool to remove the sacrificial nanostructure layer 120 based on differences in etch selectivity between the materials of the sacrificial nanostructure layer 120 and the nanostructure channels 315, and between the materials of the sacrificial nanostructure layer 120 and the internal spacer 410. The internal spacer 410 may be used as an etch stop layer in the etching operation to protect the source / drain regions 505 from etching.

[0076] like Figure 7B As shown in sections BB and CC, the gate replacement operation includes forming a gate structure (e.g., a replacement gate structure) 710 in the openings 705 between the source / drain regions 505 and between the internal spacers 410. Specifically, the gate structure 710 fills the regions previously occupied by the sacrificial nanostructure layer 120 between and around the nanostructure channels 315, such that the gate structure 710 completely encloses and surrounds the nanostructure channels 315. This increases control over the nanostructure channels 315, increases the drive current of the nanostructure transistor(s) of semiconductor device 105, and / or reduces the short-channel effect (SCE) of the nanostructure crystal(s) of semiconductor device 104. The gate structure 710 may also fill spaces previously occupied by the dummy gate structure 205. Some portions of the gate structure 710 are formed between pairs of nanostructure channels 315 in an alternating vertical arrangement. In other words, the semiconductor device 105 comprises a vertically stacked arrangement of one or more alternating nanostructured channels 315 and portions of the gate structure 710, such as Figure 7B As shown.

[0077] Gate structures 710 may each include a gate dielectric layer 715 and a metal gate electrode 720. The metal gate electrode 720 may include one or more metallic materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), and / or titanium (Ti). Additionally and / or alternatively, gate structures 710 may each include one or more work function metal layers for tuning the work function of the metal gate electrode 720.

[0078] The gate dielectric layer 715 may be a conformal high-k dielectric liner deposited on the nanostructured channel 315 and the sidewalls of the internal spacer 410 prior to the formation of the gate electrode 720. Each gate structure 710 may include additional layers, such as interface layers, adhesive layers, and / or capping layers. The gate dielectric layer 715 may include one or more high-k dielectric materials, such as silicon nitride (Si). x N y ), Hafnium oxide (HfO) x ), Lanthanum oxide (LaO) x ) and / or another suitable high-k dielectric material.

[0079] Some source / drain regions 505 and gate structures 710 can be shared among two or more nanoscale transistors in semiconductor device 105. In these implementations, one or more source / drain regions 505 and gate structures 710 can be connected or coupled to multiple nanostructured channels 315, such as... Figure 7B As shown in the example. This allows multiple nanostructured channels 315 to be controlled by a single gate structure 710 and a pair of source / drain regions 505.

[0080] As mentioned above, Figure 7A and Figure 7B Provided as an example. Other examples may be related to... Figure 7A and Figure 7B The description differs from that in the text.

[0081] Figure 8A-8I This is a schematic diagram of an example implementation 800 of the source / drain contact formation process described herein. Specifically, example implementation 800 includes examples of forming front and rear source / drain contacts. The front source / drain contacts are formed such that they are recessed from a first side (e.g., the front side) of the semiconductor device 105 into the source / drain region 505 of the nanostructured transistor of the semiconductor device 105. The rear source / drain contacts are formed such that the rear source / drain region contacts are connected from a second side (e.g., the rear side) of the semiconductor device 105 opposite to the first side in the z-direction to the source / drain region. This enables lower contact resistance and lower current congestion between the source / drain region 505 and the front and rear source / drain contacts. Furthermore, this allows the front and rear source / drain contacts to share the same metal silicide layer, thereby reducing the process complexity of forming the nanostructured transistor.

[0082] Figure 8A-8I Each from Figure 2 The angle of section BB in the diagram is illustrated. In some implementations, the operation described in example implementation 800 is combined with... Figure 1A-7BThe operation described above is performed afterward.

[0083] like Figure 8A As shown, an etch stop layer (ESL) 805 may be formed above and / or on the dielectric layer 605, and above and / or on the top of the gate structure 710. Another dielectric layer 810 may be formed above and / or on the ESL 805.

[0084] ESL 805 may include one or more dielectric materials, such as silicon nitride (Si). x N y Silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbonate (SiCO), or combinations thereof. The dielectric layer 810 may be referred to as an ILD layer (e.g., an ILD1 layer) and may include one or more dielectric materials, such as oxides (e.g., silicon oxide (SiO2)). x (and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), silsesquioxane (HSQ), and / or another suitable dielectric material. In some implementations, dielectric layer 810 includes an ELK dielectric material.

[0085] Deposition tools can be used to deposit ESL 805 and / or dielectric layer 810 using PVD, ALD, CVD, and / or another suitable deposition technique. ESL 805 and / or dielectric layer 810 can be deposited in one or more deposition operations. In some implementations, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize ESL 805 and / or dielectric layer 810 after deposition.

[0086] like Figure 8B As shown, the contact recess 815 is formed to pass through the dielectric layer 810, through the ESL 805, through the dielectric layer 605, and into the source / drain region 505. The contact recess 815 may be referred to as a front contact recess because it is formed from the front side of the semiconductor device 105 and enters the semiconductor device 105. The "front side" of the semiconductor device 105 may refer to one side of the semiconductor substrate 110 over which a stack 115 of sacrificial nanostructure layer 120 and nanostructure channel layer 125 is formed. The fin portion 160 may extend the structure above the front side of the semiconductor substrate 110.

[0087] Perform a first etching operation using an etching tool to form the contact recess 815 to a first depth relative to the top of the source / drain region 505 (in Figure 8B(This is represented by dimension D1). The contact recess 815 can extend into the second epitaxial layer 515 of the source / drain region 505.

[0088] In some implementations, the pattern in the photoresist layer is used to form the contact recess 815. In these implementations, a deposition tool can be used to form the photoresist layer on the dielectric layer 810 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 810, ESL 805, dielectric layer 605, and / or the second epitaxial layer 515 of the source / drain region 505 based on the pattern to form the contact recess 815. In some implementations, the etching operation includes a dry etching operation (e.g., a plasma-based etching operation, a gas-based etching operation), a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the contact recess 815 on the pattern.

[0089] In some implementations, after the first etching operation, the first depth (size D1) by which the contact recess 815 extends into the source / drain region 505 can be included in the range of about 1 nanometer to about 9 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0090] like Figure 8C As shown, a sidewall liner 820 may be formed on the portion of the sidewall of the contact recess 815 above the source / drain region 505. The sidewall liner 820 may be formed as a protective liner that protects the sidewall of the contact recess 815 from etching during a subsequent second etching operation (causing the lateral width of the contact recess 815 to widen), thereby increasing the depth of the contact recess 815. Additionally and / or alternatively, the sidewall liner 820 may include a barrier liner included to reduce and / or prevent material diffusion from the source / drain contacts (e.g., formed in the contact recess 815) into the surrounding dielectric layer.

[0091] The sidewall liner 820 may include one or more dielectric materials. For example, the sidewall liner 820 may include silicon nitride (Si). x N yMaterials such as Si3N4, silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiOCN), and / or another suitable dielectric material. The material of the sidewall liner 820 may differ from the material of the source / drain region 505 (e.g., different from the semiconductor material of the second epitaxial layer 515) to provide etch selectivity between the sidewall liner 820 and the source / drain region 505. This allows the source / drain region 505 to be further etched in the second etch operation to increase the depth of the contact recess 815, while minimizing or eliminating the consumption of the sidewall liner 820.

[0092] To form the sidewall liner 820, a conformal layer of dielectric material can be deposited on the sidewalls of the contact recess 815 (e.g., corresponding to the exposed surfaces of dielectric layer 605, ESL 805, and dielectric layer 810) and on the bottom surface of the contact recess 816 (e.g., corresponding to the exposed surface of the second epitaxial layer 515 of the source / drain region 505). Deposition tools can be used to deposit the conformal layer of dielectric material using deposition techniques (e.g., ALD and / or CVD, etc.).

[0093] An etching tool can be used to trim a portion of the conformal layer of the dielectric material located on the bottom surface of the contact recess 815, thereby removing the conformal layer of the dielectric material from the surface of the second epitaxial layer 515 of the source / drain region 505. In this way, the surface of the second epitaxial layer 515 of the source / drain region 505 is again exposed through the contact recess 815, and the remaining portion of the conformal layer of the dielectric material on the sidewall of the contact recess 815 corresponds to the sidewall liner 820.

[0094] Anisotropic etching techniques can be used to trim the portion of the conformal layer of the dielectric material located on the bottom surface of the contact recess 815, such that the portion of the conformal layer of the dielectric material located on the sidewall of the contact recess 815 is retained as a sidewall liner 820. For example, plasma-based etching techniques (e.g., reactive ion etching (RIE) techniques) can be used to perform predominantly vertical (e.g., z-direction) etching to trim the conformal layer of the dielectric material. However, other etching techniques are within the scope of this disclosure.

[0095] like Figure 8D As shown, a second etching operation is performed (e.g., in the bonding process). Figure 8B Following the first etching operation, the depth of the contact recess 815 in the source / drain region 505 is increased from a first depth (size D1) to a second depth greater than the first depth (in...). Figure 8D(This is represented by dimension D2). Thus, after the second etching operation, the contact recess 815 extends through the second epitaxial layer 515 and into the merged region 520 of the first epitaxial layer 510 at the bottom of the source / drain region 505. For example, in the bonding... Figure 8B Following the first etching operation, the contact recess 815 can extend to the depth of the topmost nanostructure channel (e.g., nanostructure channel 315 in a vertical stack of nanostructure channels 315a-315c). In combination Figure 8D After the second operation, the contact recess 815 can extend to the depth of the mesa region 310 below the bottommost nanostructure channel (e.g., nanostructure channel 315 in a vertical stack of nanostructure channels 315a-315c).

[0096] In some implementations, the second depth is included in the range of about 10 nanometers to about 60 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some implementations, the ratio of the second depth to the first depth is included in the range of about 1.1:1 to about 60:1. However, other values ​​and ranges are within the scope of this disclosure.

[0097] The second etching operation can differ from the first etching operation because the first etching operation is performed using a first etchant, and the second etching step is performed using a second etchant, which is different from the first etchant. For example, the first etching operation can be performed using a plasma-based etchant, and the second etching operation can be performed using a gas-based etchant.

[0098] Different etchants can be used in the first and second etch operations to achieve different etch selectivity for the first and second etch operations. For example, a first etchant used in the first etch operation can be selected to achieve low etch selectivity between the dielectric layer (e.g., dielectric layer 605, ESL 805, dielectric layer 810) above the source / drain region 505 and the semiconductor material of the source / drain region 505 (e.g., the semiconductor material of the second epitaxial layer 515). This allows the contact recess 815 to be formed in the first etch operation to pass through the dielectric layer 605, ESL 805, dielectric layer 810 and enter the source / drain region 505.

[0099] For the second etching operation, a second etchant can be selected to achieve high etch selectivity between the dielectric layer (e.g., dielectric layer 605, ESL 805, dielectric layer 810, sidewall liner 820) above the source / drain region 505 and the semiconductor material of the source / drain region 505 (e.g., the semiconductor material of the first epitaxial layer 510, the semiconductor material of the second epitaxial layer 515). Specifically, a gas-based etchant, such as a chlorine-containing gas and / or another suitable gas-based etchant, can be used in the second etching operation such that the etching rate of the second etchant on the semiconductor material of the source / drain region 505 is greater than the etching rate of the second etchant on the dielectric material of the sidewalls of the contact recess 815 (e.g., the silicon nitride material of the sidewall liner 820). This allows for an increase in the depth of the contact recess 815 in the source / drain region 505, with minimal or no etching of the dielectric material on the sidewalls of the contact recess 815 (and therefore, minimal or no increase in the lateral width of the contact recess 815).

[0100] like Figure 8E As shown, a metal silicide layer 825 is formed at the bottom of the contact recess 815. Specifically, the metal silicide layer 825 can be formed from the surfaces of the source / drain regions 505 exposed in the contact recess 815 (e.g., the surface of the first epitaxial layer 510 of the source / drain regions 505, the surface of the second epitaxial layer 515 of the source / drain regions 505).

[0101] To form the metal silicide layer 825, a silicide process can be performed. The silicide process includes depositing (e.g., by CVD, ALD, PVD, and / or electroplating) a metal material layer on the exposed surfaces of the merged region 520 of the first epitaxial layer 510 in the source / drain region 505 and the exposed surfaces of the second epitaxial layer 515 in the contact recess 815 using a deposition tool. An annealing operation can be performed to increase the temperature of the metal material layer of the source / drain region 505, the exposed surfaces of the first epitaxial layer 510 and the second epitaxial layer 515, causing the metal material to diffuse into the exposed surfaces of the merged region of the first epitaxial layer 510 and into the exposed surfaces of the second epitaxial layer 515. This allows the metal silicide layer 825 to be formed. In other words, the exposed surface of the merged region of the first epitaxial layer 510 and the exposed surface of the second epitaxial layer 515 of the source / drain region 505 can be transformed from a semiconductor surface to a metal silicide surface.

[0102] In some implementations, the metal material layer includes titanium (Ti), and the metal silicide layer 825 includes titanium silicide (TiSi). In some implementations, the metal material layer includes ruthenium (Ru), and the metal silicide layer 825 includes ruthenium silicide (RuSi). In some implementations, the metal material layer includes cobalt (Co), and the metal silicide layer 825 includes cobalt silicide (CoSi).

[0103] The metal silicide layer 825 is formed with a thickness ranging from about 3.5 nanometers to about 7 nanometers. Figure 8E The dimension is represented as D3. However, other values ​​and ranges are within the scope of this disclosure. The lateral distance between the metal silicide layer 825 and the gate structure 710 laterally adjacent to the source / drain region 505 (in Figure 8E The dimension (denoted as D4) can be included in the range of about 2 nanometers to about 20 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0104] like Figure 8F As shown, the remaining area in the contact recess 815 can be filled with the material of the metal core 830 and the source / drain contact 835, such that the metal core 830 is laterally surrounded by one or more epitaxial layers 510, 515 of the source / drain region 505. The source / drain contact 835 may be referred to as a front-side source / drain contact because it is formed above the front side of the semiconductor device 105. The metal core 830 may correspond to the bottom of the source / drain contact 835, which is recessed within the source / drain region 505. The sidewall liner 820 may be located between the source / drain contact 835 and the dielectric layer 605, between the source / drain contact 835 and the ESL 805, and / or between the source / drain contact 835 and the dielectric layer 810.

[0105] The source / drain contact 835 may include a contact plug, via, conductive post, conductive pillar, and / or another type of conductive structure extending in the z-direction within the semiconductor device 105. The metal core 830 and the source / drain contact 835 may each comprise one or more conductive materials, such as tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), molybdenum (Mo), copper (Cu), and / or aluminum (Al). In some implementations, the metal core 830 and the source / drain contact 835 are formed of the same material. In some implementations, the metal core 830 and the source / drain contact 835 are formed of different materials.

[0106] The deposition tool can be used to deposit the material of the metal core 830 and the material of the source / drain contact 835 in the contact recess 815 using CVD, ALD, PVD, electroplating, and / or another suitable deposition technique. In some implementations, a seed layer is deposited in the contact recess 815, and the material of the source / drain contact 835 is deposited on the seed layer.

[0107] The metal core 830 of the source / drain region 505 effectively extends the source / drain contact 835 and the metal silicide layer 825 into the source / drain region 505 to a depth corresponding to dimension D2. The bottom of the metal core 830 may be located at a depth below the bottommost nanostructure channel 315 (e.g., nanostructure channel 315c) in the semiconductor device 105. Figure 8F (This is represented by dimension D5). This reduces the contact resistance between the source / drain contact 835 and the source / drain region 505 because the contact area between the source / drain contact 835 and the source / drain region 505 is increased. Furthermore, this reduces current congestion in the source / drain region 505 because the metal core 830 extends along the topmost nanostructured channel (e.g., nanostructured channel 315a), the middle nanostructured channel (e.g., nanostructured channel 315b), and the bottommost nanostructured channel (e.g., nanostructured channel 315c). This provides a more direct lateral travel path for charge carriers through the source / drain region 505 between the source / drain contact 835 and the nanostructured channel 315 (e.g., unlike the case where charge carriers must travel vertically in addition to horizontally to reach nanostructured channels 315a-315c).

[0108] like Figure 8G As shown, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. During the planarization operation, excess material is removed from the source / drain contacts 835, and the dielectric layer 810 can also be removed. The planarization operation can be stopped once ESL 805 is reached.

[0109] In some implementations, additional front-side processing operations can be performed on the front side of the semiconductor device 105. For example, a front-side interconnect layer (e.g., a front-side back-end region or a front-side back-end (BEOL) region) of the semiconductor device 105 can be formed over the device layer of the semiconductor device 105 containing nanostructured transistors (e.g., corresponding to the nanostructured channel 315, gate structure 710, and source / drain region 505). Source / drain contacts 835 can electrically connect the source / drain regions 505 of the nanostructured transistors to conductive structures in the front-side interconnect layer. This allows electrical signals and / or power to be routed between one or more conductive structures (not shown) in the front-side interconnect layer and the source / drain regions 505 via the source / drain contacts 835.

[0110] As another example, the front side of semiconductor device 105 can be bonded to another semiconductor device to form a three-dimensional (3D) stacked semiconductor device. Bonding structures above the front interconnect layer (e.g., bonding pads, bonding vias, bonding dielectric layers) can be bonded to bonding structures of other semiconductor devices.

[0111] like Figure 8H As shown, semiconductor device 105 can be flipped so that a back-side processing is performed on the back side of semiconductor device 105 (e.g., after the front-side processing of semiconductor device 104). The “back side” of semiconductor device 105 can refer to the side of semiconductor device 105 that is vertically opposite to the front side. In other words, the back side of semiconductor device 105 can refer to the side of semiconductor substrate 110 that is vertically opposite to the front side of the forming layer stack 115.

[0112] Back-side processing may include forming a contact recess 840 (e.g., a back-side contact recess) in the back side of the semiconductor device 105. The contact recess 840 may extend through a merging region 520 of the semiconductor substrate 110, the fin portion 160, and the first epitaxial layer 510 of the source / drain region 505, such that the bottom of the metal silicide layer 825 is exposed through the contact recess 840. In some implementations, the semiconductor substrate 110 is removed prior to forming the contact recess 840 (e.g., during a wafer polishing operation). In some implementations, the contact recess 840 extends into a portion of the metal silicide layer 825, such that the bottom surface of the contact recess 840 is recessed within the metal silicide layer 825.

[0113] In some implementations, the pattern in the photoresist layer is used to etch the semiconductor substrate 110, the fin portion 160, the merged region 520 of the first epitaxial layer 510 of the source / drain region 505, and / or the metal silicide layer 825 to form the contact recess 840. In these implementations, a deposition tool can be used to form the photoresist layer on the back side of the semiconductor device 105 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the semiconductor substrate 110, the fin portion 160, the merged region 520 of the first epitaxial layer 510 of the source / drain region 505, and / or the metal silicide layer 825 based on the pattern to form the contact recess 840. In some implementations, the etching operation includes dry etching (e.g., plasma-based etching, gas-based etching), wet chemical etching, and / or another type of etching. In some implementations, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-forming the contact recess 840.

[0114] like Figure 8H As further shown, the sidewall liner 845 may be formed on the portion of the sidewall of the contact recess 840 corresponding to the fin portion 160. The sidewall liner 845 may include one or more dielectric materials. For example, the sidewall liner 845 may include silicon nitride (Si). x N y For example, Si3N4), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiOCN) and / or another suitable dielectric material.

[0115] To form the sidewall liner 845, a conformal layer of dielectric material can be deposited on the sidewalls of the contact recess 840 (e.g., the exposed surface corresponding to the fin portion 160) and on the bottom surface of the contact recess 840 (e.g., the exposed surface corresponding to the first epitaxial layer 510 and the metal silicide layer 825). Deposition tools can be used to deposit the conformal layer of dielectric material using deposition techniques (e.g., ALD and / or CVD, etc.).

[0116] An etching tool can be used to trim the portion of the conformal layer of the dielectric material located on the bottom surface of the contact recess 840, thereby removing the conformal layer of the dielectric material from the surfaces of the first epitaxial layer 510 and the metal silicide layer 825. In this way, the surfaces of the first epitaxial layer 510 and the metal silicide layer 825 are again exposed through the contact recess 840, and the remaining portion of the conformal layer of the dielectric material on the sidewall of the contact recess 840 corresponds to the sidewall liner 845.

[0117] Anisotropic etching techniques can be used to trim the portion of the conformal layer of the dielectric material located on the bottom surface of the contact recess 840, such that the portion of the conformal layer of the dielectric material located on the sidewall of the contact recess 840 is retained as a sidewall liner 845. For example, plasma-based etching techniques (e.g., RIE techniques) can be used to perform predominantly vertical (e.g., z-direction) etching to trim the conformal layer of the dielectric material. However, other etching techniques are within the scope of this disclosure.

[0118] like Figure 8I As shown, the contact recess 840 can be filled with the material of the source / drain contact 850. The source / drain contact 850 can be referred to as the rear-side source / drain contact because it is formed above the rear side of the semiconductor device 105. The source / drain contact 850 can be formed such that it rests on and contacts the metal silicide layer 825. Thus, the metal silicide layer 825 is shared between the source / drain contacts 835 and 850, instead of performing a separate silicide process for each source / drain contact 835 and 850.

[0119] The source / drain contact 850 may include a contact plug, via, conductive post, conductive pillar, and / or another type of conductive structure extending in the z-direction within the semiconductor device 105. The source / drain contact 835 may include one or more conductive materials, such as tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), molybdenum (Mo), copper (Cu), and / or aluminum (Al).

[0120] Deposition tools can be used to deposit material of the source / drain contact 850 in the contact recess 840 using CVD, ALD, PVD, electroplating, and / or another suitable deposition technique. In some implementations, a seed layer is deposited in the contact recess 840, and the material of the source / drain contact 850 is deposited on the seed layer. In some implementations, planarization tools can be used to perform a planarization operation (e.g., CMP operation) to planarize the back side of the semiconductor device 105. During the planarization operation, excess material of the source / drain contact 850 can be removed.

[0121] As mentioned above, Figure 8A-8I Provided as an example. Other examples may be related to... Figure 8A-8I The descriptions differ.

[0122] Figure 9 This is a schematic diagram of an example implementation 900 of the semiconductor device 105 described herein. For example... Figure 9 As shown, example implementation 900 is similar to the example shown in Figures 1-8I. However, in example implementation 900, the merging region 520 of the first epitaxial layer 510 of the source / drain region 505 has a more pronounced U-shape compared to the merging region 520 of the second epitaxial layer 510 of the source / drain region 505 shown in Figures 5-8I. As a result, the bottom of the second epitaxial layer 515 of the source / drain region 505 extends below the bottommost nanostructure channel 315 (e.g., nanostructure channel 315c) and extends to the depth of the mesa region 310.

[0123] Because the merged region 520 of the first epitaxial layer 510 relative to the source / drain region 505 has a distinct U-shape, the metal silicide layer 825 is contained within (and formed therefrom) the second epitaxial layer 515 of the source / drain region 505. The metal silicide layer 825 contained within the second epitaxial layer 515 can achieve a lower resistance between the metal silicide layer 825 and the source / drain region 505.

[0124] As mentioned above, Figure 9 Provided as an example. Other examples may be related to... Figure 9 The descriptions differ.

[0125] Figure 10A-10I This is a schematic diagram illustrating an example implementation 1000 of the semiconductor device 105 described herein. Example implementation 1000 is similar to... Figure 1A-8I The process described. However, as Figure 10A As shown, one or more epitaxial layers 510, 515 of the source / drain region 505 partially fill the source / drain recess 305, such that a hollow core 1005 extends from the top of the source / drain region 505 into the source / drain region 505. The hollow core 1005 is a hollow region within the source / drain region 505 that is not filled with epitaxial material but with air. The hollow core 1005 is formed by the second epitaxial layer 515 not being fully integrated but rather along the sidewalls and bottom surface of the region in the source / drain region 505 that is not filled by the first epitaxial layer 510.

[0126] One or more epitaxial layers 510, 515 of the source / drain region 505 are not merged at the bottom of the source / drain recess 305, such that the hollow core 1005 extends completely from the top of the source / drain region 505 to the bottom of the source / drain region 505. For example... Figure 10A As shown, in some implementations, a bottom isolation layer 1010 (sometimes referred to as a flexible bottom insulator) may be formed at the bottom of the source / drain recess 305. The bottom isolation layer 1010 may include one or more materials that inhibit the epitaxial growth of one or more epitaxial layers 510, 515 of the source / drain region 505 on the bottom of the source / drain recess 305, which facilitates the formation of the hollow core 1005. For example, the bottom isolation layer 1010 may include silicon nitride (Si). x N y Examples include Si3N4, silicon oxycarbonate (SiOC), silicon oxycarbonate (SiOCN), and / or silicon carbonitride (SiCN).

[0127] Because the bottom isolation layer 1010 inhibits the epitaxial growth of one or more epitaxial layers 510, 515 of the source / drain region 505 on the bottom of the source / drain recess 305, the epitaxial growth of one or more epitaxial layers 510, 515 can be primarily on the sidewalls of the source / drain region 505. For example, a deposition tool can be used to perform this epitaxial deposition operation, wherein the material of the first epitaxial layer 510 is grown on the exposed ends of the nanostructured channel 315 and the mesa region 310 in the source / drain recess 305. The exposed ends of the nanostructured channel 315 and the mesa region 310 serve as the growth substrate for the first epitaxial layer 510. The deposition tool can be used to perform another epitaxial deposition operation in which the material of the second epitaxial layer 515 is grown on the first epitaxial layer 510, such that the epitaxial material of the second epitaxial layer 515 is merged together to form a continuous epitaxial material layer on the sidewall of the source / drain recess 305.

[0128] Deposition tools can be used to deposit the bottom isolation layer 1010 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, the bottom isolation layer 1010 can be formed to include a thickness ranging from about 1 nanometer to about 5 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0129] In some implementations, a buffer region 1015 is first formed in the source / drain recess 305, and a bottom isolation layer 1010 is formed on the buffer region 1015. In some implementations, the semiconductor device 105 omits the buffer region 1015 and / or the bottom isolation layer 1010. The buffer region 1015 may include a semiconductor material layer epitaxially grown at the bottom of the source / drain recess 305.

[0130] like Figure 10AAs further shown, a capping layer 1020 may be formed on the second epitaxial layer 515. The capping layer 1020 may include undoped semiconductor material, such as undoped silicon (Si). In some implementations, the capping layer 1020 includes amorphous undoped silicon (Si) and is formed such that the capping layer 1020 can be consumed to form a metal silicide layer 825 on the second epitaxial layer 515 (e.g., instead of consuming material of the second epitaxial layer 515 to form the metalicide layer 825, or otherwise). A deposition tool may be used to perform an epitaxial deposition operation in which the material of the capping layer 1020 is grown on the second epitaxial layer 515.

[0131] like Figure 10A As further shown, the hollow core 1005 of the source / drain region 505 may have a tapered cross-sectional profile, wherein the bottom width of the hollow core 1005 (e.g., along the y-direction) is (in Figure 10A The width of the top of the hollow core 1005 (represented as dimension D6) is smaller than the top width of the hollow core 1005 (e.g., along the y-direction). Figure 10A (Represented as dimension D7). The width of the hollow core 1005 can decrease from the top to the bottom of the hollow core 1005. In some implementations, the tapered cross-sectional profile of the hollow core 1005 is generated by a source / drain recess 305 having a similar tapered cross-sectional shape. In some implementations, the tapered cross-sectional profile of the hollow core 1005 is caused by the epitaxial growth of one or more epitaxial layers 510, 515 of the source / drain region 505, which is larger at the bottom of the source / drain region 505 than at the top.

[0132] like Figure 10B As shown, the hollow core 1005 in the source / drain region 505 is filled with a sacrificial material to form a sacrificial plug 1025 in the hollow core 1005. The sacrificial plug 1025 may be a temporary structure that is subsequently removed and replaced with a metal core 830 (or a portion of the source / drain contact 850 extending into the source / drain region 505). The sacrificial plug 1025 allows subsequent processes to be performed prior to the formation of the source / drain contacts, such as a replacement gate process that replaces the dummy gate structure 205 with a metal gate structure.

[0133] In some implementations, the material of the sacrificial plug 1025 differs from the material of one or more epitaxial layers 510, 515 of the source / drain region 505, and / or differs from the material of the internal spacer 410. This allows the etchant to be used to selectively remove the sacrificial plug 1025 with minimal or no material removed from the one or more epitaxial layers 510, 515 of the source / drain region 505 and from the internal spacer 410.

[0134] In some implementations, the sacrificial plug 1025 is made of a semiconductor material different from the semiconductor material of one or more epitaxial layers 510, 515. For example, one or more epitaxial layers 510, 515 may include doped silicon and / or silicon-germanium, and the sacrificial plug 1025 may include germanium (Ge). The germanium concentration in the sacrificial plug 1025 may be greater than the germanium content in one or more epitaxial layers 510, 515. In some implementations, the sacrificial plug 1025 is made of a metal oxide material, such as aluminum oxide (AlxOy, e.g., Al2O3) or hafnium oxide (HfO). x For example, HfO2) and / or zirconium oxide (ZrO2) x For example, ZrO2, etc.

[0135] like Figure 10C As shown, the dielectric layer 605 can be bonded with Figure 6 Formed in a similar manner, the gate structure 710 can be combined with... Figure 7A and Figure 7B Formed in a similar manner, and the ESL 805 and dielectric layer 810 can be bonded together. Figure 8A Formed in a similar manner as described above.

[0136] like Figure 10D As shown, in the formation Figure 7A and Figure 7B Following the gate replacement process, a first etching operation can be performed to penetrate dielectric layer 810, ESL 805, dielectric layer 605, and reach sacrificial plug 1025 to form contact recess 815 (e.g., front-side contact recess). Contact recess 815 can be coupled with... Figure 8B Formed in a similar manner as described above.

[0137] like Figure 10E As shown, a second etching operation is performed (e.g., in the bonding process). Figure 10C Following the first etching operation, the sacrificial plug 1025 is removed from the hollow core 1005 of the source / drain region 505. Removing the sacrificial plug 1025 exposes the hollow core 1005. The second etching operation may differ from the first etching operation because the first etching operation is performed using a first etchant, and the second etching operation is performed using a second etchant different from the first etchant. For example, the first etching operation may be performed using a plasma-based etchant, and the second etching operation may be performed using a gas-based etchant or a wet etchant.

[0138] Different etchants can be used in the first and second etching operations to achieve different etch selectivity for the first and second etching operations. For example, the first etchant used in the first etching operation can be selected to achieve low etch selectivity between the materials of the dielectric layer (e.g., dielectric layer 605, ESL 805, dielectric layer 810) above the source / drain region 505 and the sacrificial plug 1025. This allows the contact recess 815 to be formed through the dielectric layer 605, ESL 805, dielectric layer 810 and into the sacrificial plug 1025 in the first etching operation.

[0139] For the second etching operation, a second etchant can be selected to achieve high etch selectivity between the materials of the dielectric layer (e.g., dielectric layer 605, ESL 805, dielectric layer 810) above the source / drain region 505 and the sacrificial plug 1025, and between the material of the sacrificial plug 1025 and one or more epitaxial layers 510, 515 of the source / drain region 505 (e.g., semiconductor materials of one or more epitaxial layers 510 and 515). For example, one or more epitaxial layers 510, 515 of the source / drain region 505 may include doped silicon, the material of the sacrificial plug 1025 may include germanium, and the sacrificial plug 1025 may be etched using a wet etchant (e.g., a mixed solution including hydrogen peroxide (H2O2), acetic acid (CH3COOH), and / or hydrogen fluoride (HF)). As another example, one or more epitaxial layers 510, 515 of the source / drain region 505 may include doped silicon, the material of the sacrificial plug 1025 may include a metal oxide material, and the sacrificial plug 1025 may be etched using an etchant such as hydrogen fluoride (HF), phosphoric acid (H3PO4) and / or hydrochloric acid (HCl).

[0140] In some implementations, some mixing occurs between the sacrificial plug 1025 and the second epitaxial layer 515 of the source / drain region 505. In these implementations, some material of the second epitaxial layer 515 can be removed during the second etch operation.

[0141] like Figure 10F As shown, the sidewall liner 820 can be combined with Figure 8C A similar arrangement is formed on the sidewall of the contact recess 815 above the hollow core 1005.

[0142] like Figure 10F As further shown, a metal silicide layer 825 can be formed in the hollow core 1005. The metal silicide layer 825 can be bonded to... Figure 8EThe formation is similar, except that the capping layer 1020 is consumed to form the metal silicide layer 825, while the material of the first epitaxial layer 510 and the second epitaxial layer 515 is consumed minimally or not at all. Since one or more epitaxial layers 510, 515 of the source / drain regions 505 are not merged at the bottom of the hollow core 1005, the metal silicide layer 825 can extend from the top of the hollow core 1005 to the bottom of the hollow core 1005, and then to the underlying bottom isolation layer 1010.

[0143] like Figure 10F As further shown, the metal core 830 of the source / drain region 505 is formed on the metal silicide layer 825 in the hollow core 1005, and the remaining area in the contact recess 815 is filled with the material of the source / drain contact 835. The metal core 830 and the source / drain contact 835 can be coupled with Figure 8F A similar manner is used. However, in example implementation 1000, since one or more epitaxial layers 510, 515 of the source / drain regions 505 are not merged at the bottom of the hollow core 1005, the metal core 830 extends from the top of the hollow core 1005 to the bottom of the hollow core 1005, and then to the underlying bottom isolation layer 1010. In other words, the metal core 830 can extend completely from the top of the source / drain regions 505 to the bottom of the source / drain regions 505. Therefore, the bottom of the metal core 830 can be located in a vertical (z-direction) position, which is lower than the bottommost nanostructure channel 315 (e.g., nanostructure channel 315c) in the semiconductor device 105, and lower than the bottommost internal spacer 410 (e.g., internal spacer 410c) in the semiconductor device 104. In some implementations, the bottom of the metal core 830 may be located in a vertical (z-direction) position corresponding to the mesa region 310 (or the bottom of the mesa region 310).

[0144] Thus, before the gate replacement process, the sacrificial plug 1025 is formed in the hollow core 1005 of the source / drain region 505, and after the gate replacement process, the sacrificial plug 1025 is removed from the hollow core 1005, thereby forming a metal core 830 in the hollow core 1005.

[0145] like Figure 10G As shown, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. During the planarization operation, excess material is removed from the source / drain contacts 835, and the dielectric layer 810 can also be removed. The planarization operation can be stopped once ESL 805 is reached.

[0146] like Figure 10GAs further shown, the metal core 830 of the source / drain region 505 may have a tapered cross-sectional profile, wherein the bottom width (dimension D6) of the metal core 830 (e.g., along the y-direction) is smaller than the top width (dimension D7) of the metal core 830 (e.g., along the y-direction). The width of the metal core 830 may decrease from the top to the bottom of the source / drain region 505 because the metal core 830 can conform to the profile of the hollow core 1005.

[0147] like Figure 10H As shown, semiconductor device 105 can be flipped so that a back-side processing is performed on the back side of semiconductor device 105 (e.g., after a front-side processing of semiconductor device 104). The back-side processing may include forming a contact recess 840 (e.g., a back-side contact recess) in the back side of semiconductor device 105. In example implementation 1000, the contact recess 840 may extend through semiconductor substrate 110, fin portion 160, bottom isolation layer 1010, and / or buffer region 1015 to the metal core 830 of source / drain region 505. The contact recess 840 may be coupled with… Figure 8H Formed in a similar manner as described above.

[0148] like Figure 10H As further shown, the sidewall liner 845 can be formed on the portion of the sidewall of the contact recess 840 corresponding to the fin portion 160, the portion of the sidewall of the contact recess 840 corresponding to the bottom isolation layer 1010, and / or the portion of the sidewall of the contact recess 840 corresponding to the buffer region 1015. The sidewall liner 845 can be bonded to... Figure 8H Formed in a similar manner as described above.

[0149] like Figure 10I As shown, the contact recess 840 can be filled with the material of the source / drain contact 850 (e.g., the rear source / drain contact), such that the source / drain contact 850 extends through the fin portion 160, the bottom isolation layer 1010, and / or the buffer region 1015. The source / drain contact 850 can be formed such that the source / drain contact 850 rests on and contacts a portion of the metal silicide layer 825 and / or contacts a portion of the metal core 830. In other words, at least a portion of the bottom surface of the source / drain contact 850 can be in solid contact with the metal core 830. Therefore, a first side (e.g., the top side) of the metal core 830 can be in solid contact with the bottom of the source / drain contact 835, and a second side (e.g., the bottom side) of the metal core 830, vertically opposite to the first side, can be in solid contact with the bottom of the source / drain contact 850. As described above, Figure 10A-10I Provided as an example. Other examples may be related to... Figure 10A-10I The descriptions differ.

[0150] Figure 11A-11G This is a schematic diagram illustrating an example implementation 1100 of the semiconductor device 105 described herein. Example implementation 1100 is similar to... Figure 10A-10I The example implementation method 1000 is described above. However, as... Figure 11A As shown, in example implementation 1100, the bottom isolation layer 1010 may be formed of the same material as the sacrificial plug 1025 (or a material with minimal etch selectivity relative to the sacrificial plug 1025). Furthermore, the cap layer 1020 may be omitted in example implementation 1100.

[0151] like Figure 11B As shown, the dielectric layer 605 can be bonded with Figure 6 Formed in a similar manner as described above. The gate structure 710 can be combined with... Figure 7A and Figure 7B Formed in a similar manner as described above. ESL 805 and dielectric layer 810 can be bonded together. Figure 8A Formed in a similar manner. The contact recess 815 (e.g., front contact recess) and the sidewall liner 820 can be joined with... Figure 8B and Figure 8C Formed in a similar manner as described above.

[0152] like Figure 11C As shown, it can be used with Figure 10E The sacrificial plug 1025 is removed through the contact recess 815 in a similar manner. However, in example implementation 1100, the bottom insulating layer 1010 can also be removed together with the sacrificial plug 1025 through the contact recess 815. The bottom insulating layer 1010, formed of the same material as the sacrificial plug 1025 (or of a material with minimal etch selectivity relative to the sacrificial plug 1025), can be removed in the same etching operation as the sacrificial plug 1025. In some implementations, etching tools are used to perform a wet etching operation to remove the bottom insulating layer 1010 and the sacrificial plug 1025, thereby exposing the hollow core 1005.

[0153] like Figure 11C As further shown, removing the bottom isolation layer 1010 creates a gap between the fin portion 160 and one or more epitaxial layers 510, 515 in the source / drain region 505 of the hollow core 1005. At the bottom of the hollow core 1005, some portions of the second epitaxial layer 515 may extend below the bottommost portion of the first epitaxial layer 510.

[0154] like Figure 11C As further shown, in example implementation 1000, the cross-sectional profile of the hollow core 1005 of the source / drain region 505 can be compared with... Figure 10AThe cross-sectional profiles shown are different. Specifically, the hollow core 1005 of the source / drain region 505 in example implementation 1100 can have a tapered cross-sectional profile, wherein the bottom width of the hollow core 1005 (e.g., along the y-direction) is (in Figure 11C The dimension D8 is greater than the top width of the hollow core 1005 (e.g., along the y-direction). Figure 11C (This is represented as dimension D9). The width of the hollow core 1005 is not uniform from the top to the bottom of the hollow core 1005.

[0155] like Figure 11D As shown, by consuming the surface material of the second epitaxial layer 515 of the source / drain region 505, a metal silicide layer 825 can be formed in the hollow core 1005. The metal silicide layer 825 can be bonded to... Figure 8E It is formed in a similar manner as described above. However, as mentioned above, at the bottom of the hollow core 1005, some portions of the second epitaxial layer 515 may extend below the bottommost portion of the first epitaxial layer 510. Therefore, in some implementations, at the bottom of the hollow core 1005, the metal silicide layer 825 may extend below the bottommost portion of the first epitaxial layer 510.

[0156] like Figure 11D As further shown, a metal core 830 can be formed in the hollow core 1005 of the source / drain region 505, and a source / drain contact 835 can be formed in the remaining area of ​​the contact recess 815. The metal core 830 and the source / drain contact 835 can be coupled with... Figure 8F It is formed in a similar manner as described above. However, since the bottom isolation layer 1010 is removed (leaving a gap between one or more epitaxial layers 510, 515 and the fin portion 160), the bottom portion 1105 of the metal core 830 extends below one or more epitaxial layers 510, 515 and fills the gap between one or more epitaxial layers 510, 515 and the fin portion 160.

[0157] Thus, before the gate replacement process, the sacrificial plug 1025 is formed in the hollow core 1005 of the source / drain region 505, and after the gate replacement process, the sacrificial plug 1025 is removed from the hollow core 1005, thereby forming a metal core 830 in the hollow core 1005.

[0158] like Figure 11E As shown, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. During the planarization operation, excess material is removed from the source / drain contacts 835, and the dielectric layer 810 can also be removed. The planarization operation can be stopped once ESL 805 is reached.

[0159] like Figure 11F As shown, semiconductor device 105 can be flipped so that a back-side processing is performed on the back side of semiconductor device 105 (e.g., after a front-side processing of semiconductor device 104). The back-side processing may include forming a contact recess 840 (e.g., a back-side contact recess) in the back side of semiconductor device 105. In example implementation 1000, the contact recess 840 may extend through semiconductor substrate 110, fin portion 160, bottom isolation layer 1010, and / or buffer region 1015 to the metal core 830 of source / drain region 505. The contact recess 840 may be coupled with… Figure 8H Formed in a similar manner as described above.

[0160] like Figure 11F As further shown, the sidewall liner 845 can be formed on the portion of the sidewall of the contact recess 840 corresponding to the fin portion 160, the portion of the sidewall of the contact recess 840 corresponding to the bottom isolation layer 1010, and / or the portion of the sidewall of the contact recess 840 corresponding to the buffer region 1015. The sidewall liner 845 can be bonded to... Figure 8H Formed in a similar manner as described above.

[0161] like Figure 11G As shown, the contact recess 840 can be filled with the material of the source / drain contact 850 (e.g., the rear source / drain contact), such that the source / drain contact 850 extends through the fin portion 160, the bottom isolation layer 1010, and / or the buffer region 1015. The source / drain contact 850 can be formed such that the source / drain contact 850 rests on and contacts a portion of the metal silicide layer 825 and / or contacts a portion of the metal core 830. In other words, at least a portion of the bottom surface of the source / drain contact 850 can be in solid contact with the metal core 830. Therefore, a first side (e.g., the top side) of the metal core 830 can be in solid contact with the bottom of the source / drain contact 835, and a second side (e.g., the bottom side) of the metal core 830, vertically opposite to the first side, can be in solid contact with the bottom of the source / drain contact 850. As described above, Figure 11A-11G Provided as an example. Other examples may be related to... Figure 11A-11G The descriptions differ.

[0162] Figure 12A-12F This is a schematic diagram illustrating an example implementation 1200 of the semiconductor device 105 described herein. Example implementation 1200 is similar to... Figure 10A-10IThe example implementation 1000 is described in that, in example implementation 1200, the hollow core 1005 extends completely through the source / drain region 505 in the vertical direction. Furthermore, in example implementation 1200, a metal core 830 is formed in the hollow core 1005 such that the metal core 830 extends completely through the source / drain region 505 in the vertical direction.

[0163] However, example implementation 1200 and combination Figure 10A-10I The difference in example implementation 1000 is that, in example implementation 1200, before forming the dielectric layer 605 and... Figure 7A and Figure 7B Prior to the gate replacement process shown, the metal core 830 is formed in the hollow core 1005 passing through the source / drain recess 305; while in example implementation 1000, after the dielectric layer 605 is formed and Figure 7A and Figure 7B Following the replacement gate process shown, a metal core 830 is formed in a hollow core 1005 that passes through a contact recess 815.

[0164] In example implementation 1200, the sacrificial plug 1025 is omitted, and the metal core 830 is formed in the hollow core 1005 and covered by the dielectric layer 605 (e.g., Figures 12A-12C (As shown). The metal core 830 can be formed on the capping layer 1020 using deposition techniques such as thermal CVD or plasma-enhanced CVD. The precursor concentration and temperature of the material used to deposit the metal core 830 can be selected to achieve metal growth of the metal core 830 on the capping layer 1020 (e.g., undoped semiconductor material) at a higher growth rate than on the dielectric layer, thereby achieving selective deposition of the metal core 830.

[0165] The metal core 830 may have a tapered cross-sectional profile, wherein the bottom width of the metal core 830 is ( Figure 12B The dimension D6 in the middle is smaller than the top width of the metal core 830 ( Figure 12B (Dimension D7 in the middle). However, other cross-sectional profiles of the metal core 830 are within the scope of this disclosure.

[0166] like Figure 12C-12D As shown, ESL 805 and dielectric layer 810 can be formed above dielectric layer 605, and contact recess 815 can be formed on top of dielectric layer 605. Figure 7A and Figure 7B The replacement gate process shown is followed by the top of the metal core 830 being exposed through the contact recess 815. In some implementations, the contact recess 815 is formed such that the bottom of the contact recess 815 is recessed within the metal core 830.

[0167] like Figure 12E As shown, the sidewall liner 820 and the source / drain contact 835 are formed in the contact recess 815, such that the contact recess 815 rests on top of the metal core 830. In some implementations, the metal core 830 and the source / drain contact 835 are formed of the same conductive material. In some implementations, the metal core 830 and the source / drain contact 835 are formed of different conductive materials. For example, the metal core 830 may be formed of a high-melting-point material such as ruthenium (Ru), and the source / drain contact 835 may be formed of a relatively low-melting-point material such as cobalt (Co). However, other combinations of materials used for the metal core 830 and the source / drain contact 835 are within the scope of this disclosure.

[0168] As described above, the contact recess 815 can be formed such that the bottom of the contact recess 815 is recessed within the metal core 830. Therefore, the bottom of the source / drain contact 835 can be recessed below the top surface of the metal core 830. Consequently, the interface 1205 between the metal core 830 and the source / drain contact 835 can have a curved or arcuate cross-sectional profile, wherein the curve or arcuate shape faces downwards in the semiconductor device 105. However, other cross-sectional profiles of the interface 1205 between the metal core 830 and the source / drain contact 835 are within the scope of this disclosure.

[0169] exist Figure 12A-12F In the illustrated example implementation 1200, the metal core 830 is shown formed on the capping layer 1020 of the source / drain region 505, and the metal silicide layer 825 is omitted. However, in other implementations, the capping layer 1020 may be omitted, and the metal silicide layer 825 may be formed on the second epitaxial layer 515 in the source / drain recess 305. In these implementations, the metal core 830 may be formed on the metal silicide layer 825 in the source / drain recess 305.

[0170] like Figure 12F As shown, in example implementation 1200, it is possible to perform and combine... Figure 10H and Figure 10I Similar back-side processing operations, as shown and described, are used to form a contact recess 840 (e.g., a rear-side contact recess), to form a sidewall liner 845 on the sidewall of the contact recess 840, and / or to form a source / drain contact 850 (e.g., a rear-side source / drain contact). In some implementations, a portion of the bottom of the source / drain contact 850 is in solid contact with the cap layer 1020.

[0171] As mentioned above, Figure 12A-12F Provided as an example. Other examples may be related to... Figure 12A-12F The descriptions differ.

[0172] Figure 13 This is a schematic diagram of an example implementation 1300 of the semiconductor device 105 described herein. For example... Figure 13 As shown, the example implementation 1300 of the semiconductor device 105 is similar to the example implementation shown in Figures 1-12F because the source / drain region 505 of the nanostructure transistor of the semiconductor device 105 has a metal core 830 electrically coupled to a source / drain contact 835 (e.g., a front source / drain contact) on a first side of the metal core 830 and a source / drain contact 850 (e.g., a rear source / drain contact) on a second side of the metal core 830 opposite to the first side. However, in example implementation 1300, the metal core 830 and the source / drain contact 835 of the source / drain region 505 are partially laterally offset by a distance (in... Figure 13 The metal core 830 and source / drain contact 850 of the source / drain region 505 are partially offset laterally by a certain distance (represented by dimension D8), and / or the source / drain region 505 is partially offset laterally by a certain distance. Figure 13 (represented as dimension D9).

[0173] The partial lateral offset between the metal core 830 and the source / drain contact 835 may be due to overlay shift during the formation of the contact recess 815. This partial lateral offset may cause a portion of the bottom surface of the source / drain contact 835 to contact the cap layer 1020 and / or the second epitaxial layer 515. Additionally and / or alternatively, the partial lateral offset may cause a portion of the top surface of the metal core 830 to contact the sidewall liner 820 and / or the dielectric layer 605.

[0174] The partial lateral offset between the metal core 830 and the source / drain contact 850 may be due to overlay misalignment during the formation of the contact recess 840. This partial lateral offset may cause a portion of the bottom surface of the source / drain contact 850 to contact the cap layer 1020 and / or the second epitaxial layer 515. Additionally and / or alternatively, the partial lateral offset may cause a portion of the bottom surface of the metal core 830 to contact the bottom isolation layer 1010.

[0175] As mentioned above, Figure 13 Provided as an example. Other examples may be related to... Figure 13 The descriptions differ.

[0176] Figure 14A-14F This is a schematic diagram illustrating an example implementation 1400 of the semiconductor device 105 described herein. Example implementation 1400 is similar to... Figure 11A-11GThe example implementation 1100 differs in that, in example implementation 1400, the hollow core 1005 extends vertically completely through the source / drain region 505. Furthermore, in example implementation 1400, a metal core 830 is formed in the hollow core 1005 such that the metal core 830 extends vertically completely through the source / drain region 505.

[0177] However, example implementation 1400 and combination Figure 11A-11G The difference in example implementation 1100 is that, in example implementation 1400, the bottom isolation layer 1010 can extend below the countertop area 310, such as... Figure 14A As shown. In some implementations, a bottom isolation layer 1010 is formed over the semiconductor substrate 110 before forming the layer stack 115.

[0178] Hollow core 1005 may have a tapered cross-sectional profile, wherein the bottom width of hollow core 1005 ( Figure 14A The dimension D10 in the middle is greater than the top width of the hollow core 1005. Figure 14A (Dimension D11 in the hollow core). However, other cross-sectional profiles of the hollow core 1005 are within the scope of this disclosure.

[0179] like Figure 14B As shown, the sacrificial plug 1025 is omitted. In example implementation 1400, it is placed before the formation of the dielectric layer 605 and Figure 7A and Figure 7B Prior to the gate replacement process shown, a metal core 830 is formed in the hollow core 1005 passing through the source / drain recess 305, while in example implementation 1100, a metal core 830 is formed after the dielectric layer 605 is formed and Figure 7A and Figure 7B Following the replacement gate process shown, a metal core 830 is formed in the hollow core 1005 passing through the contact recess 815. The metal core 830 may rest on the bottom isolation layer 1010 exposed in the hollow core 1005.

[0180] A metal core 830 may be formed in the hollow core 1005, such that the metal core 830 is in contact with the cap layer 1020. Alternatively, a metal silicide layer 825 may be formed in the hollow core 1005, and the metal core 830 may be formed within the hollow core 1005, such that the metal core 830 is in contact with the metal silicide layer 825.

[0181] like Figure 14C As shown, the metal core 830 is covered by dielectric layer 605, ESL 805, and dielectric layer 810. Figure 14D As shown, in Figure 7A and Figure 7BThe replacement gate process shown forms a contact recess 815 (e.g., a front contact recess), through which the top of the metal core 830 is exposed. In some implementations, the contact recess 815 is formed such that the bottom of the contact recess 815 is recessed within the metal core 830.

[0182] like Figure 14E As shown, the sidewall liner 820 and source / drain contacts 835 (e.g., front source / drain contacts) are formed in the contact recess 815 such that the source / drain contacts 835 rest on top of the metal core 830. The sidewall liner 820, source / drain contacts 835, and / or dielectric layer 810 can then be planarized.

[0183] In some implementations, the metal core 830 and the source / drain contact 835 are formed of the same conductive material. In other implementations, the metal core 830 and the source / drain contact 835 are formed of different conductive materials. For example, the metal core 830 may be formed of a high-melting-point material such as ruthenium (Ru), and the source / drain contact 835 may be formed of a relatively low-melting-point material such as cobalt (Co). However, other combinations of materials used for the metal core 830 and the source / drain contact 835 are within the scope of this disclosure.

[0184] like Figure 14F As shown, in example implementation 1400, it is possible to perform and combine... Figure 11F and Figure 10G Similar back-side processing operations are shown and described to form a contact recess 840 (e.g., a rear-side contact recess), to form a sidewall liner 845 on the sidewall of the contact recess 840, and / or to form a source / drain contact 850 (e.g., a rear-side source / drain contact). However, in example implementation 1400, the contact recess 840 is formed through the bottom insulating layer 1010, and the source / drain contact 850 extends through the bottom insulating layer 1010 to the metal core 830 of the source / drain region 505. In some implementations, a portion of the bottom of the source / drain contact 850 is in solid contact with the cap layer 1020.

[0185] As mentioned above, Figure 14A-14F Provided as an example. Other examples may be related to... Figure 14A-14F The descriptions differ.

[0186] Figure 15This is a flowchart of an example process 1500 associated with the formation of the semiconductor device described herein. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform the process. Figure 15 One or more process boxes.

[0187] like Figure 15 As shown, process 1500 may include forming a plurality of nanostructured channels arranged in a direction generally perpendicular to the semiconductor layer of the semiconductor device (box 1510). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructured channels (e.g., nanostructured channels 315, 315a-315c) arranged in a direction (e.g., z-direction) generally perpendicular to the semiconductor layer (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0188] like Figure 15 As further shown, process 1500 may include forming source / drain regions adjacent to the plurality of nanostructure channels (box 1520). For example, as described herein, one or more semiconductor processing tools may be used to form source / drain recesses (e.g., source / drain recess 305) adjacent to the plurality of nanostructure channels.

[0189] like Figure 15 As further shown, process 1500 may include partially filling the source / drain recess with epitaxial material to form a source / drain region in the recess (block 1530). For example, one or more semiconductor processing tools may be used to partially fill the source / drain recess with epitaxial material (e.g., a first epitaxial layer 510, a second epitaxial layer 515, a merged region 520, a plurality of discontinuous second epitaxial regions 525) to form a source / drain region (e.g., a source / drain region 505) in the recess, as described herein. In some implementations, the source / drain region includes a hollow core.

[0190] like Figure 15 As further shown, process 1500 may include forming a gate structure (block 1540) surrounding at least three sides of the plurality of nanostructure channels. For example, one or more semiconductor processing tools may be used to form a gate structure (e.g., gate structure 710) surrounding at least three sides of the plurality of nanostructure channels, as described herein.

[0191] like Figure 15As further shown, process 1500 may include filling the hollow core of the source / drain region with a material of a metal core (box 1550). For example, one or more semiconductor processing tools may be used to fill the hollow core of the source / drain region with a material of a metal core (e.g., metal core 830), as described herein.

[0192] like Figure 15 As further shown, process 1500 may include forming a first source / drain contact on a first side of the metal core (block 1560). For example, as described herein, one or more semiconductor processing tools may be used to form the first source / drain contact (e.g., source / drain contact 835) on the first side of the metal core. In some implementations, the metal core 830 corresponds to a bottom portion of the source / drain contact 835, which is recessed in the source / drain region 505 and laterally surrounded by one or more epitaxial layers of the source / drain region 505.

[0193] like Figure 15 As further shown, process 1500 may include forming a second source / drain contact (block 1570) on a second side of the metal core opposite to the first side. For example, one or more semiconductor processing tools may be used to form the second source / drain contact (e.g., source / drain contact 850) on a second side of the metal core opposite to the first side, as described herein.

[0194] Process 1500 may include additional implementations, such as any single implementation or any combination of implementations described below and / or related to one or more other processes described elsewhere in this document.

[0195] In the first implementation, filling the hollow core of the source / drain region with the material of the metal core includes: after forming the gate structure, forming a first source / drain contact such that the first source / drain contact extends into the hollow core of the source / drain region.

[0196] In the second implementation, either alone or in combination with the first implementation, process 1500 includes: forming a dielectric layer (e.g., dielectric layer 605) over the source / drain region, and after forming the gate structure, forming a contact recess (e.g., contact recess 815) through the dielectric layer and reaching the hollow core of the source / drain region, wherein forming the first source / drain contact includes: forming the first source / drain contact in the contact recess such that the first source / drain contact extends into the hollow core of the source / drain region.

[0197] In the third implementation, either alone or in combination with one or more of the first and second implementations, process 1500 includes: filling the hollow core with material of a sacrificial plug (e.g., sacrificial plug 1025) before forming the gate structure, and removing the sacrificial plug from the hollow core of the source / drain region through a contact recess.

[0198] In the fourth implementation, either alone or in combination with one or more of the first to third implementations, the material of the sacrificial plug is different from the epitaxial material of the source / drain region.

[0199] In the fifth implementation, the material of the sacrificial plug may be, alone or in combination with one or more of the first to fourth implementations, include at least one of metal oxide materials or semiconductor materials.

[0200] In the sixth implementation, either alone or in combination with one or more of the first to fifth implementations, the first source / drain contact makes physical contact with the first side of the metal core, and the second source / drain contact makes physical contact with the second side of the metal core.

[0201] In the seventh implementation, the hollow core of the source / drain region filled with the material of the metal core, either alone or in combination with one or more of the first to sixth implementations, includes forming the metal core in the hollow core before forming the gate structure.

[0202] In the eighth implementation, either alone or in combination with one or more of the first to seventh implementations, process 1500 includes forming a dielectric layer (e.g., dielectric layer 605) over the source / drain region after forming the metal core, and forming a contact recess (e.g., contact recess 815) of the metal core through the dielectric layer and reaching the source / drain region after forming the gate structure, wherein forming the first source / drain contact includes forming a first source / drain region contact in the contact recess such that the first source / drain contact rests on the metal core.

[0203] In the ninth implementation, either alone or in combination with one or more of the first to eighth implementations, process 1500 includes forming a bottom isolation layer (e.g., bottom isolation layer 1010) in the source / drain recess, wherein filling the hollow core of the source / drain region with the material of the metal core includes filling the hollow core of the source / drain region with the material of the metal core such that the material of the metal core falls onto the bottom isolation layer.

[0204] although Figure 15 The example box for process 1500 is shown, but in some implementations, process 1500 includes a comparison with... Figure 15The boxes shown may include additional boxes, fewer boxes, different boxes, or boxes arranged differently. Alternatively, two or more boxes in process 1500 may be executed in parallel.

[0205] Figure 16 This is a flowchart of an example process 1600 associated with the formation of the semiconductor device described herein. In some implementations, this process is performed using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool). Figure 16 One or more process boxes.

[0206] like Figure 16 As shown, process 1600 may include forming a plurality of nanostructured channels arranged in a first direction in a semiconductor device and extending in a second direction generally perpendicular to the first direction in the semiconductor device (box 1610). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructured channels (e.g., nanostructured channels 315, 315a-315c) arranged in a first direction (e.g., the z-direction) in a semiconductor device (e.g., semiconductor device 105) and extending in a second direction (e.g., the y-direction) generally perpendicular to the first direction in the semiconductor device, as described herein.

[0207] like Figure 16 As further shown, process 1600 may include forming a source / drain region adjacent to a plurality of nanostructure channels in a second direction (box 1620). For example, one or more semiconductor processing tools may be used to form a source / drain region (e.g., source / drain region 505) adjacent to a plurality of nanostructure channels in a second direction, as described herein.

[0208] like Figure 16 As further shown, process 1600 may include forming a dielectric layer over the source / drain regions (box 1630). For example, one or more semiconductor processing tools may be used to form a dielectric layer (e.g., dielectric layer 605) over the source / drain regions, as described herein.

[0209] like Figure 16 As further shown, process 1600 may include forming a gate structure (block 1640) surrounding at least three sides of the plurality of nanostructure channels. For example, one or more semiconductor processing tools may be used to form a gate structure (e.g., gate structure 710) surrounding at least three sides of the plurality of nanostructure channels, as described herein.

[0210] like Figure 16As further shown, process 1600 may include: forming a first contact recess from a first side of the semiconductor device, penetrating the dielectric layer and entering the source / drain region, such that the bottom of the first contact recess is at a depth in the semiconductor device lower than the bottommost nanostructure channel among a plurality of nanostructure channels (box 1650). For example, one or more semiconductor processing tools may be used to form the first contact recess (e.g., contact recess 815) from a first side of the semiconductor device, penetrating the dielectric layer and entering the source / drain region, such that the bottom of the first contact recess is at a depth (e.g., dimension D2) in the semiconductor device lower than the bottommost nanostructure channel among a plurality of nanostructure channels (e.g., nanostructure channel 315c), as described herein.

[0211] like Figure 16 As further shown, process 1600 may include: forming a first source / drain contact in a first contact recess such that the first source / drain contact extends into a source / drain region (block 1660). For example, one or more semiconductor processing tools may be used to form the first source / drain contact (e.g., source / drain contact 835) in the first contact recess such that the source / drain contact extends into a source / drain region, as described herein.

[0212] like Figure 16 As further shown, process 1600 may include forming a second contact recess (block 1670) extending into the source / drain region from a second side of the semiconductor device opposite to the first side. For example, one or more semiconductor processing tools may be used to form the second contact recess (e.g., contact recess 840) extending into the source / drain region from a second side of the semiconductor device opposite to the first side, as described herein.

[0213] like Figure 16 As further shown, process 1600 may include: forming a second source / drain contact in the second contact recess such that the second source / drain region is coupled to the second source / drain region (block 1680). For example, one or more semiconductor processing tools may be used to form the second source / drain contact (e.g., source / drain contact 850) in the second contact recess such that the second source / drain region is coupled to the second source / drain region, as described herein.

[0214] Process 1600 may include additional implementations, such as any single implementation or any combination of implementations described below and / or related to one or more other processes described elsewhere herein.

[0215] In a first implementation, forming the first contact recess includes: performing a first etching operation to form the first contact recess such that the bottom of the first contact recess is at a first depth (e.g., dimension D1) in the source / drain region, and performing a second etching operation to extend the first contact recess from the first depth to a depth below the bottommost nanostructure channel.

[0216] In the second implementation, either alone or in combination with the first implementation, process 1600 includes: forming a protective liner (e.g., sidewall liner 820) on the sidewall of the first contact recess and on top of the source / drain regions in the first contact recess after the first etching operation and before the second etching operation, and performing a third etching operation after the first etching operation and before the second etching operation to etch through the protective liner, thereby exposing the top of the source / drain regions through the first contact recess.

[0217] In the third implementation, performing the second etching operation, either alone or in combination with one or more of the first and second implementations, includes performing the second etching operation while the protective liner is located on the sidewall of the first contact recess.

[0218] In the fourth implementation, forming the first source / drain contact, either alone or in combination with one or more of the first to third implementations, includes: forming a metal silicide layer (e.g., metal silicide layer 825) in the first contact recess, and forming the first source / drain contact on the metal silicide layer.

[0219] In the fifth implementation, forming a second source / drain contact in the second contact recess, either alone or in combination with one or more of the first to fourth implementations, includes forming a second source / drain region in the second contact recess such that the second source / drain contact contacts the metal silicide layer.

[0220] although Figure 16 The example box for process 1600 is shown, but in some implementations, process 1600 includes a comparison with... Figure 16 The boxes shown may include additional boxes, fewer boxes, different boxes, or boxes arranged differently. Alternatively, two or more boxes in process 1600 may be executed in parallel.

[0221] This forms the source / drain regions of a nanostructured transistor for semiconductor devices, such that the source / drain regions include a metal core. Compared to the case where the source / drain regions are completely filled with epitaxially grown semiconductor material, the metal core provides a larger surface area for the front and rear source / drain contacts to be coupled to the source / drain regions. Since the current flow path between the source / drain regions and the front and rear source / drain contacts is less restricted, the increased contact surface area provides a reduced contact resistance between the source / drain regions and the front and rear source / drain contacts. This reduced contact resistance between the source / drain regions and the front and rear source / drain contacts enables the nanostructured transistor to achieve higher power efficiency and / or improve its switching speed.

[0222] As described in more detail above, some implementations of this document provide a method. The method includes forming a plurality of nanostructured channels arranged in a direction generally perpendicular to a semiconductor layer of a semiconductor device. The method includes forming source / drain recesses adjacent to the plurality of nanostructured channels. The method includes partially filling the source / drain recesses with an epitaxial material to form source / drain regions within the source / drain recesses, wherein the source / drain regions include hollow cores. The method includes forming gate structures surrounding at least three sides of the plurality of nanostructured channels. The method includes filling the hollow cores of the source / drain regions with a material from a metal core. The method includes forming a first source / drain contact on a first side of the metal core. The method includes forming a second source / drain contact on a second side of the metal core opposite to the first side.

[0223] As described in more detail above, some implementations of this document provide a method. The method includes forming a plurality of nanostructured channels arranged in a first direction within a semiconductor device and extending in the semiconductor device in a second direction substantially perpendicular to the first direction. The method includes forming source / drain regions adjacent to the plurality of nanostructured channels in the second direction. The method includes forming a dielectric layer over the source / drain regions. The method includes forming gate structures surrounding at least three sides of the plurality of nanostructured channels. The method includes forming a first contact recess from a first side of the semiconductor device, penetrating the dielectric layer and entering the source / drain regions, such that the bottom of the first contact recess is at a depth in the semiconductor device lower than that of the bottommost nanostructured channel among the plurality of nanostructured channels. The method includes forming a first source / drain contact in the first contact recess, such that the first source / drain contact extends into the source / drain regions; and forming a second contact recess from a second side of the semiconductor device opposite to the first side, extending into the source / drain regions. The method includes forming a second source / drain contact in a second contact recess, such that the second source / drain contact is coupled to the source / drain region.

[0224] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructured channels arranged along a first direction and extending along a second direction substantially perpendicular to the first direction. The semiconductor device includes a gate structure surrounding the plurality of nanostructured channels. The semiconductor device includes source / drain regions adjacent to the sides of the gate structure and to the ends of the plurality of nanostructured channels, the source / drain regions including: a metal core; and one or more epitaxial layers laterally surrounding the metal core. The semiconductor device includes front-side source / drain contacts located on the front side of the semiconductor device and electrically connected to a first side of the metal core of the source / drain regions; and rear-side source / drain contacts located on the rear side of the semiconductor device and electrically connected to a second side of the metal core of the source / drain regions opposite to the first side.

[0225] Here are some examples.

[0226] Example 1. A method comprising: forming a plurality of nanostructured channels arranged in a direction substantially perpendicular to a semiconductor layer of a semiconductor device; forming source / drain recesses adjacent to the plurality of nanostructured channels; partially filling the source / drain recesses with an epitaxial material to form source / drain regions in the source / drain recesses, wherein the source / drain regions include a hollow core; forming a gate structure surrounding at least three sides of the plurality of nanostructured channels; filling the hollow core of the source / drain regions with a material of a metal core; forming a first source / drain contact on a first side of the metal core; and forming a second source / drain contact on a second side of the metal core opposite to the first side.

[0227] Example 2. According to the method of Example 1, wherein filling the hollow core of the source / drain region with the material of the metal core includes: after forming the gate structure, forming a first source / drain contact such that the first source / drain contact extends into the hollow core of the source / drain region.

[0228] Example 3. The method according to Example 2 further includes: forming a dielectric layer over the source / drain region; and after forming the gate structure, forming a contact recess that extends through the dielectric layer and reaches the hollow core of the source / drain region, wherein forming the first source / drain contact includes: forming the first source / drain contact in the contact recess such that the first source / drain contact extends into the hollow core of the source / drain region.

[0229] Example 4. The method according to Example 3 further includes: filling the hollow core with the material of the sacrificial plug before forming the gate structure; and removing the sacrificial plug from the hollow core of the source / drain region through a contact recess.

[0230] Example 5. Following the method of Example 4, wherein the material of the sacrificial plug is different from the epitaxial material of the source / drain region.

[0231] Example 6. According to the method of Example 4, wherein the material of the sacrificial plug includes at least one of the following: a metal oxide material or a semiconductor material.

[0232] Example 7. According to the method of Example 2, wherein the first source / drain contact is in solid contact with a first side of the metal core; and wherein the second source / drain contact is in solid contact with a second side of the metal core.

[0233] Example 8. According to the method of Example 1, wherein filling the hollow core of the source / drain region with the material of the metal core includes: forming a metal core in the hollow core before forming the gate structure.

[0234] Example 9. The method according to Example 8 further includes: after forming the metal core, forming a dielectric layer over the source / drain region; and after forming the gate structure, forming a contact recess of the metal core that passes through the dielectric layer and reaches the source / drain region, wherein forming the first source / drain contact includes: forming the first source / drain contact in the contact recess such that the first source / drain contact rests on the metal core.

[0235] Example 10. The method according to Example 1 further includes: forming a bottom isolation layer in the source / drain recess, wherein filling the hollow core of the source / drain region with the material of the metal core includes: filling the hollow core of the source / drain region with the material of the metal core such that the material of the metal core falls on the bottom isolation layer.

[0236] Example 11. A method comprising: forming a plurality of nanostructured channels arranged in a semiconductor device along a first direction and extending in the semiconductor device along a second direction substantially perpendicular to the first direction; forming source / drain regions adjacent to the plurality of nanostructured channels in the second direction; forming a dielectric layer over the source / drain regions; forming a gate structure surrounding at least three sides of the plurality of nanostructured channels; forming a first contact recess from a first side of the semiconductor device, penetrating the dielectric layer and entering the source / drain regions, such that the bottom of the first contact recess is at a depth in the semiconductor device lower than that of the bottommost nanostructured channel of the plurality of nanostructured channels; forming a first source / drain contact in the first contact recess, such that the first source / drain contact extends into the source / drain regions; forming a second contact recess from a second side of the semiconductor device opposite to the first side, extending into the source / drain regions; and forming a second source / drain contact in the second contact recess, such that the second source / drain contact is coupled to the source / drain regions.

[0237] Example 12. According to the method of Example 11, forming the first contact recess includes: performing a first etching operation to form the first contact recess such that the bottom of the first contact recess is at a first depth in the source / drain region; and performing a second etching operation to extend the first contact recess from the first depth to a depth below the bottommost nanostructure channel.

[0238] Example 13. The method according to Example 12 further includes: forming a protective liner on the sidewall of the first contact recess and on top of the source / drain regions in the first contact recess after the first etching operation and before the second etching operation; and performing a third etching operation after the first etching operation and before the second etching operation to etch through the protective liner, thereby exposing the top of the source / drain regions through the first contact recess.

[0239] Example 14. According to the method of Example 13, wherein performing the second etching operation includes performing the second etching operation while the protective liner is located on the sidewall of the first contact recess.

[0240] Example 15. According to the method of Example 11, forming the first source / drain contact includes: forming a metal silicide layer in a first contact recess; and forming the first source / drain contact on the metal silicide layer.

[0241] Example 16. According to the method of Example 15, wherein forming a second source / drain contact in a second contact recess includes: forming a second source / drain contact in a second contact recess such that the second source / drain contact contacts a metal silicide layer.

[0242] Example 17. A semiconductor device comprising: a plurality of nanostructured channels arranged along a first direction and extending along a second direction substantially perpendicular to the first direction; a gate structure surrounding the plurality of nanostructured channels; a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructured channels, the source / drain region comprising: a metal core; and one or more epitaxial layers laterally surrounding the metal core; a front source / drain contact located on the front side of the semiconductor device and electrically connected to a first side of the metal core of the source / drain region; and a rear source / drain contact located on the rear side of the semiconductor device and electrically connected to a second side of the metal core of the source / drain region opposite to the first side.

[0243] Example 18. The semiconductor device according to Example 17 further includes: a bottom isolation layer adjacent to a second side of the metal core, wherein a rear-side source / drain contact extends through the bottom isolation layer.

[0244] Example 19. The semiconductor device according to Example 17 further includes: a semiconductor buffer region adjacent to a second side of the metal core, wherein a rear-side source / drain contact extends through the semiconductor buffer region.

[0245] Example 20. The semiconductor device according to Example 17 further includes: a semiconductor cap layer located between a metal core and one or more epitaxial layers.

[0246] The terms “approximate” and “basic” can mean that the value of a given quantity varies within 5% of its value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “approximate” and “basic” can refer to a percentage of the value of a given quantity.

[0247] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method comprising: Multiple nanostructured channels are formed, and the multiple nanostructured channels are arranged in a direction that is substantially perpendicular to the semiconductor layer of the semiconductor device; Source / drain recesses are formed adjacent to the plurality of nanostructured channels; The source / drain recess is partially filled with epitaxial material to form a source / drain region in the source / drain recess, wherein the source / drain region includes a hollow core; A gate structure is formed around at least three sides of the plurality of nanostructure channels; The hollow core of the source / drain region is filled with a material containing a metal core. A first source / drain contact is formed on a first side of the metal core; and A second source / drain contact is formed on the second side of the metal core opposite to the first side.

2. The method according to claim 1, wherein, Filling the hollow core of the source / drain region with the material of the metal core includes: After the gate structure is formed, the first source / drain contact is formed such that the first source / drain contact extends into the hollow core of the source / drain region.

3. The method according to claim 2, further comprising: A dielectric layer is formed above the source / drain region; as well as After the gate structure is formed, a contact recess is formed through the dielectric layer and to the source / drain region of the hollow core. The first source / drain contact includes: The first source / drain contact is formed in the contact recess such that the first source / drain contact extends into the hollow core of the source / drain region.

4. The method according to claim 3, further comprising: Prior to forming the gate structure, the hollow core is filled with the material of the sacrificial plug; as well as The sacrificial plug is removed from the hollow core of the source / drain region through the contact recess.

5. The method according to claim 4, wherein, The material of the sacrificial plug is different from the epitaxial material of the source / drain region.

6. The method according to claim 4, wherein, The material of the sacrificial plug includes at least one of the following: Metal oxide materials, or Semiconductor materials.

7. The method according to claim 2, wherein, The first source / drain contact makes solid contact with the first side of the metal core; and The second source / drain contact is in contact with the second side of the metal core.

8. The method according to claim 1, wherein, Filling the hollow core of the source / drain region with the material of the metal core includes: The metal core is formed in the hollow core before the gate structure is formed.

9. A method comprising: Multiple nanostructured channels are formed, the multiple nanostructured channels are arranged in a first direction in the semiconductor device, and extend in the semiconductor device in a second direction, the second direction being substantially perpendicular to the first direction; A source / drain region is formed in the second direction adjacent to the plurality of nanostructure channels; A dielectric layer is formed above the source / drain region; A gate structure is formed around at least three sides of the plurality of nanostructure channels; A first contact recess is formed from a first side of the semiconductor device, passing through the dielectric layer and entering the source / drain region, such that the bottom of the first contact recess is at a depth in the semiconductor device that is lower than the bottommost nanostructure channel among the plurality of nanostructure channels; A first source / drain contact is formed in the first contact recess such that the first source / drain contact extends into the source / drain region; A second contact recess is formed from a second side of the semiconductor device opposite to the first side, extending into the source / drain region; as well as A second source / drain contact is formed in the second contact recess, such that the second source / drain contact is coupled to the source / drain region.

10. A semiconductor device, comprising: Multiple nanostructured channels are arranged along a first direction and extend along a second direction, the second direction being approximately perpendicular to the first direction; A gate structure surrounds the plurality of nanostructured channels; A source / drain region, adjacent to the side of the gate structure and to the ends of the plurality of nanostructure channels, the source / drain region comprising: Metal core; and One or more epitaxial layers are laterally surrounding the metal core; A front-side source / drain contact is located on the front side of the semiconductor device and is electrically connected to the first side of the metal core of the source / drain region; and The rear source / drain contact is located on the rear side of the semiconductor device and is electrically connected to the second side of the metal core of the source / drain region opposite to the first side.

Images