Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. A source / drain region of a nanostructured transistor of a semiconductor device is formed such that a cavity extends from a top of the source / drain region into the source / drain region. In some implementations, the cavity extends completely through a depth of the source / drain region. The cavity is created by a partial epitaxial growth of one or more epitaxial layers of the source / drain region. A metal core of a source / drain region is formed in the cavity, and the metal core is electrically coupled to a source / drain contact of the nanostructured transistor such that the conductive material is recessed within the source / drain region. This provides a greater amount of surface area for the source / drain contact to contact the source / drain region than if the source / drain region is completely filled with an epitaxially grown semiconductor material.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of forming the same. BACKGROUND

[0002] As semiconductor device fabrication advances and technology process node sizes decrease, transistors can be affected by short channel effects (SCE) such as hot carrier degradation, barrier lowering, and quantum confinement. Additionally, for smaller technology nodes, as the gate length of a transistor decreases, source / drain (S / D) electron tunneling increases, which increases the off-state current of the transistor (current flowing through the channel of the transistor when the transistor is in an off configuration). Silicon (Si) / silicon germanium (SiGe) nanostructure transistors (such as nanowires, nanosheets, and gate-all-around (GAA) devices) are potential candidates to overcome short channel effects at smaller technology nodes. Relative to other types of transistors, nanostructure transistors are effective structures that can experience reduced SCE and enhanced carrier mobility. SUMMARY

[0003] According to a first aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a semiconductor layer of the semiconductor device; forming source / drain recesses adjacent to the plurality of nanostructure channels; partially filling the source / drain recesses with an epitaxial material to form source / drain regions in the recesses, wherein the source / drain regions have cavities; filling the cavities with a material of a sacrificial plug; forming a dielectric layer over the source / drain regions; forming a gate structure wrapping at least three sides of the plurality of nanostructure channels; removing the sacrificial plug to expose the cavities of the source / drain regions; and filling the cavities of the source / drain regions with a metal material layer.

[0004] According to a second aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a plurality of nanostructure channels arranged in a first direction in a semiconductor device; forming source / drain recesses adjacent to the plurality of nanostructure channels in a second direction substantially perpendicular to the first direction; partially filling the source / drain recesses with an epitaxial material to form source / drain regions in the recesses, wherein the source / drain regions have cavities; filling the cavities with a material of a metal core; forming a dielectric layer over the source / drain regions; forming a gate structure wrapping at least three sides of the plurality of nanostructure channels; forming a recess through the dielectric layer and into the metal core; and forming a source / drain contact in the recess on the metal core.

[0005] According to a third aspect of the disclosure, there is provided a semiconductor device comprising: a plurality of nanostructure channels arranged in a first direction and extending in a second direction substantially perpendicular to the first direction; a gate structure encircling the plurality of nanostructure channels; a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructure channels in the second direction, the source / drain region comprising: a metal core; and one or more epitaxial layers laterally surrounding the metal core; and a source / drain contact on and in contact with the metal core. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. Skilled artisans appreciate that the functions explained herein below can be implemented using different circuitry, software, firmware, or combinations thereof. It should be noted that functions explained herein below can be implemented on various system architectures.

[0007] Figures 1A to 1C is an illustration of an example implementation of the fin defining process described herein.

[0008] Figure 2 is an illustration of an example dummy gate structure forming process described herein.

[0009] Figure 3 is an illustration of an example implementation of the source / drain recess forming process described herein.

[0010] Figure 4A and Figure 4B is an illustration of an example implementation of the internal spacer forming process described herein.

[0011] Figures 5A to 5C is an illustration of an example implementation of the source / drain region forming process described herein.

[0012] Figure 6 is an illustration of an example implementation of the interlayer dielectric forming process described herein.

[0013] Figure 7A and Figure 7B is an illustration of an example implementation of the replacement gate process described herein.

[0014] Figures 8A-8F is an illustration of an example implementation of the source / drain contact forming process described herein.

[0015] Figures 9A-9D is an illustration of an example implementation of the source / drain contact forming process described herein.

[0016] Figures 10A-10Fis a depiction of an example implementation of the source / drain contact formation process described herein.

[0017] Figure 11A-11D is a depiction of an example implementation of the source / drain contact formation process described herein.

[0018] Figures 12A-12E is a depiction of an example implementation of the source / drain contact formation process described herein.

[0019] Figure 13 is a depiction of an example implementation of the semiconductor device described herein.

[0020] Figures 14A-14E is a depiction of an example implementation of the source / drain contact formation process described herein.

[0021] Figure 15 is a flowchart of an example process associated with forming the semiconductor device described herein.

[0022] Figure 16 is a flowchart of an example process associated with forming the semiconductor device described herein. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. For simplicity, in the following description, a particular embodiment or example can be described solely in terms of its components or steps. Moreover, these embodiments or examples should not be construed as limiting and should be understood not to exclude the presence or addition of one or more other components or steps. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Furthermore, the present disclosure can repeat certain previously described

[0024] Furthermore, spatially relative terms (for example, “beneath,” “below,” “lower,” “above,” “upper,” and the like) can be used herein for ease of describing one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0025] Nanowire transistors, nanosheet transistors, GAA transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanowire transistors can overcome one or more of the above-mentioned shortcomings of some types of transistors. However, nanowire transistors face manufacturing challenges that can lead to performance issues, manufacturing yield issues, and / or device failures.

[0026] For example, as feature sizes are reduced, various portions of nanowire transistors can be susceptible to increased resistance. One such portion of a nanowire transistor that can be susceptible to increased resistance is the connection between a source / drain region of the nanowire transistor and a source / drain contact formed on the source / drain region. As the size (e.g., lateral width) of the source / drain region and the source / drain contact are reduced, the contact surface area between the source / drain region and the source / drain contact is reduced. The reduced contact surface area between the source / drain region and the source / drain contact limits the flow of electrons between the source / drain region and the source / drain contact, which increases current crowding around the source / drain region and the source / drain contact. The increased current crowding leads to increased contact resistance between the source / drain region and the source / drain contact. This can lead to reduced power efficiency of the nanowire transistor and / or reduced switching speed of the nanowire transistor, among other things.

[0027] In some implementations described herein, a source / drain region of a nanowire transistor forming a semiconductor device is formed such that a hollow cavity extends from a top of the source / drain region into the source / drain region. In some implementations, the cavity extends completely through a depth of the source / drain region. The cavity results from partial epitaxial growth of one or more epitaxial layers of the source / drain region. A metal core of the source / drain region is formed in the cavity and is electrically coupled to a source / drain contact of the nanowire transistor such that the conductive material is recessed within the source / drain region. This provides a greater amount of surface area for the source / drain contact to contact the source / drain region than if the source / drain region were completely filled with epitaxially grown semiconductor material. The increased contact surface area provides reduced contact resistance between the source / drain region and the source / drain contact due to less restriction of current flow paths between the source / drain region and the source / drain contact. In this way, the reduced contact resistance between the source / drain region and the source / drain contact enables greater power efficiency to be achieved for the nanowire transistor and / or increased switching speed to be achieved for the nanowire transistor, among other things.

[0028] Figures 1A to 1Cis an illustration of an example implementation 100 of the fin defining process described herein. The example implementation 100 includes an example of forming a fin structure and associated shallow trench isolation (STI) regions of a semiconductor device 105 described herein. The semiconductor device 105 can be fabricated to include one or more transistors. The one or more transistors can include nanos tructure transistor(s), such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge-channel transistors, nanoribbon transistors, and / or other types of nanos tructure transistors. The example implementation 100 includes an example of forming a fin structure and associated STI regions of a transistor of the semiconductor device 105.

[0029] Figures 1A to 1C Each illustrates a perspective view and a cross-sectional view along line A-A in the perspective view of the semiconductor device 105. As shown, processing of the semiconductor device 105 is performed in conjunction with a semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a group III-V compound semiconductor material (e.g., gallium arsenide (GaAs)) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. Figure 1A

[0030] A layer stack 115 is formed on the semiconductor substrate 110. The layer stack 115 can be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction substantially perpendicular to the semiconductor substrate 110 (e.g., a z-direction). For example, the layer stack 115 includes vertically alternating layers of a sacrificial nanos tructure layer 120 and a nanos tructure channel layer 125 above the semiconductor substrate 110. Figure 1A The number of sacrificial nanos tructure layers 120 and the number of nanos tructure channel layers 125 shown are examples, and other numbers of sacrificial nanos tructure layers 120 and nanos tructure channel layers 125 are within the scope of the present disclosure.

[0031] ​The sacrificial nanostructure layer 120 enables defining a vertical distance between adjacent nanostructure channels formed from the nanostructure channel layer 125 and serves as a placeholder layer for a subsequently formed gate structure of transistors of the semiconductor device 105 formed around the nanostructure channels. The sacrificial nanostructure layer 120 includes a first material composition and the nanostructure channel layer 125 includes a second material composition. In some implementations, the first material composition and the second material composition are the same material composition. In some implementations, the first material composition and the second material composition are different material compositions. As an example, the sacrificial nanostructure layer 120 can include silicon germanium (SiGe) and the nanostructure channel layer 125 can include silicon (Si). This enables the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 to be selectively etched depending on the type of etchant used (e.g., such that the sacrificial nanostructure layer 120 can be etched while the nanostructure channel layer 125 is not etched, such that the nanostructure channel layer 125 can be etched while the sacrificial nanostructure layer 120 is not etched).

[0032] One or more types of deposition tools can be used to deposit and / or grow the alternating layers of the layer stack 115 on the semiconductor substrate 110 to include nanostructures (e.g., nanosheets). For example, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be grown using a deposition tool by epitaxial growth, which can include an epitaxial technique such as molecular beam epitaxy (MBE), a metal-organic chemical vapor deposition (MOCVD) process, and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0033] One or more mask layers can be formed on the layer stack 115 (e.g., using one or more deposition tools). The mask layer(s) can include a hard mask (HM) layer 130, a cap layer 135, an oxide layer 140, and / or a nitride layer 145. The mask layer(s) can be used to perform a fin patterning operation to form fin structures in the semiconductor substrate 110.

[0034] As Figure 1BAs shown, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This results in the formation of a fin structure 150 extending over the semiconductor substrate 110. The fin structure 150 may extend in the y-direction within the semiconductor device 105 and may be arranged in the x-direction within the semiconductor device 105. The fin structure 150 includes portions 155 of the layer stack 115 above and / or on the fin portions 160 above the semiconductor substrate 110. The fin structure 150 can be formed by patterning one or more mask layers and etching the semiconductor substrate 110 based on the pattern formed in the one or more mask layers. The one or more mask layers can be patterned using photolithography techniques, including dual-patterning or multi-patterning techniques. Etching tools can be used to etch the semiconductor substrate 110 based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0035] like Figure 1B As further shown, some fin structures 150 can be formed with different widths for different types of nanostructure transistors. As an example, a first subgroup fin structure 150a can be formed for a p-type nanostructure transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor), and a second subgroup fin structure 150b can be formed for an n-type nanostructure transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) nanostructure transistor). As another example, the first subgroup fin structure 150a can be formed for a nanostructure transistor configured to operate at a lower voltage, and the second subgroup fin structure 150b can be formed for a nanostructure transistor configured to operate at a higher voltage.

[0036] like Figure 1C As shown, a liner 165 and an STI region 170 are formed between adjacent fin portions 160 of the fin structure 150. The liner 165 and the STI region 170 may each comprise a dielectric material, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), low-k dielectric materials and / or another suitable insulating material.

[0037] The deposition tool can be used to deposit the liner conformally (e.g., using ALD or other conformal deposition techniques), and a dielectric layer can be deposited on the liner 165 (e.g., using CVD, PVD, ALD, and / or other suitable deposition techniques) such that the dielectric layer completely fills the spaces between the fin structures 150 and extends over the top of the fin structures 150. A planarization tool can then be used to perform a planarization or polishing operation (e.g., a chemical mechanical planarization (CMP) operation) to planarize the dielectric layer such that the top surface of the dielectric layer is approximately coplanar with the top of the nitride layer 145. The nitride layer 145 serves as a CMP stop layer in the planarization operation. An etch tool can then be used to etch the dielectric layer to form the STI region 170 such that the top surface of the STI region 170 is approximately coplanar with or below the bottommost sacrificial nanomesh layer 120.

[0038] As noted above, Figures 1A to 1C are provided by way of example. Other examples can differ Figures 1A to 1C from the examples described.

[0039] Figure 2 is an illustration of an example implementation 200 of the dummy gate formation process described herein. The example implementation 200 includes an example of forming a dummy gate structure 205 of a nanomesh transistor of a semiconductor device 105. In some implementations, the operations described in connection with the example implementation 700 are performed after the processes described in connection with Figures 1A to 1C

[0040] Figure 2 A perspective view of the semiconductor device 105 on which the dummy gate structure 205 is formed is shown. The dummy gate structure 205 (also referred to as a dummy gate stack or a temporary gate structure) is formed over portions of the fin structures 150 and portions of the STI region 170. The dummy gate structure 205 extends in the x-direction and is arranged in the y-direction such that the dummy gate structure 205 is approximately perpendicular to the fin structures 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack at a later process stage of the semiconductor device 105. The dummy gate structure 205 can also be used to define source / drain (S / D) recesses in the fin structures 150 in which source / drain regions of the nanomesh transistor are formed.

[0041] ​Dummy gate structure 205 can include gate electrode layer 210, hard mask layer 215 over and / or on gate electrode layer 210, spacer layer 220 on opposite sides of gate electrode layer 210, and gate dielectric layer 225 under gate electrode layer 210. Gate electrode layer 210 includes polysilicon (PO) or other material. Hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a liner oxide layer, which can include silicon dioxide (Si02) or another material) and a nitride layer (e.g., a liner nitride layer, which can include silicon nitride (e.g., Si3N4) or another material) formed over the oxide layer. Spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or another suitable material. Gate dielectric layer 225 can include silicon oxide (e.g., Si02), silicon nitride (e.g., Si3N4), high dielectric constant (high-k) dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9), and / or another suitable material. x As noted above, x As noted above, y As noted above,

[0042] Various semiconductor processing techniques (e.g., depositing layers of dummy gate structure 205, patterning layers of dummy gate structure 205 to define dummy gate structure 205, and / or other semiconductor processing techniques) can be used to form the layers of dummy gate structure 205.

[0043] Figure 2 Reference cross-sections used in subsequent figures described herein are also shown. Cross-section A-A is in the x-z plane (referred to as a y-cut), across fin structure 150, in a source / drain region of semiconductor device 105. Cross-section B-B is in the y-z plane (referred to as an x-cut), perpendicular to cross-section A-A, and across dummy gate structure 205 and along the underlying fin structure 150. Cross-section C-C is in the x-z plane, parallel to cross-section A-A and perpendicular to cross-section B-B, and along dummy gate structure 205. For clarity, subsequent figures refer to these reference cross-sections. In some figures, some reference numbers for components or features shown therein can be omitted to avoid obscuring other components or features, for ease of drawing the figures.

[0044] As noted above, Figure 2 are provided by way of example. Other examples can differ Figure 2 from the examples described.

[0045] Figure 3is an illustration of an example implementation 300 of the source / drain recess formation process described herein. The example implementation 300 includes an example of forming source / drain recesses 305 for source / drain regions of a nanostructure transistor for the semiconductor device 105. Figure 3 is an illustration of an example implementation 300 of the source / drain recess formation process described herein. The example implementation 300 includes an example of forming source / drain recesses 305 for source / drain regions of a nanostructure transistor for the semiconductor device 105. Figure 2 is shown from multiple perspectives (including Figure 2 a perspective of a cross-sectional plane A-A in Figure 2 a perspective of a cross-sectional plane B-B in Figure 2 a perspective of a cross-sectional plane C-C in Figures 1A to 2 The operations described in connection with the example implementation 300 are performed after the process described in connection with

[0046] As shown in the perspective of the cross-sectional plane A-A and the cross-sectional plane B-B in Figure 3 the source / drain recesses 305 are formed in an etching operation through the portions 155 of the fin structures 150. The source / drain recesses 305 are formed on opposite sides of the dummy gate structures 205. The etching operation can be performed using an etching tool, and can be referred to as a strained source / drain (SSD) etching operation. In some implementations, the etching operation includes using a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique.

[0047] The source / drain recesses 305 also extend into portions of the fin portions 160 of the fin structures 150. This results in formation of a mesa region 310 in the fin structures 150. The sidewalls of each source / drain recess 305 that are below the portions of the layer stack 115 correspond to the sidewalls of the mesa region 310. The mesa region 310 (also referred to as a pedestal) refers to a region of the fin portions 160 of the fin structures 150 on which a nanostructure channel is defined from the nanostructure channel layer 125. The nanostructure channel 315 extends between and under the dummy gate structures 205 between adjacent source / drain recesses 305.

[0048] The nanostructure channel 315 includes a silicon-based nanostructure (e.g., a nanosheet or a nanowire, etc.) that serves as a semiconductor channel for the nanostructure transistor of the semiconductor device 105. In some implementations, the nanostructure channel 315 can include silicon germanium (SiGe) or another silicon-based material. The nanostructure channel 315 is arranged in a direction (e.g., a z-direction) that is substantially perpendicular to the semiconductor substrate 110. In other words, the nanostructure channel 315 is vertically arranged or stacked above the semiconductor substrate 110.

[0049] In some implementations, the sidewalls of the source / drain recess 305 can be substantially vertical and can extend primarily in the z-direction. In some implementations, the sidewalls of the source / drain recess 305 can be tapered and can extend at an opposite angle relative to the bottom surface of the source / drain recess 305. In these implementations, the y-direction width at the top of the source / drain recess 305 can be greater than the y-direction width at the bottom of the source / drain recess 305.

[0050] As noted above, Figure 3 are provided by way of example. Other examples can differ Figure 3 from the one described.

[0051] Figure 4A and Figure 4B is an illustration of an example implementation 400 of the internal spacer formation process described herein. The example implementation 400 includes an example of forming an internal spacer between the ends of the nanostructure channel 315 exposed in the source / drain recess 305. Figure 4A and Figure 4B is shown from multiple perspectives, including Figure 2 the perspective of cross-sectional plane A-A in Figure 2 the perspective of cross-sectional plane B-B in Figure 2 the perspective of cross-sectional plane C-C in Figure 2 In some implementations, the operations described in connection with the example implementation 400 are performed after the process described in connection with Figures 1A to 3

[0052] As shown in cross-section A-A and cross-section B-B in Figure 4A the ends of the sacrificial nanostructure layer 120 can be etched laterally (e.g., in the x-direction generally parallel to the length of the sacrificial nanostructure layer 120) in an etching operation, thereby forming a cavity 405 between the ends of the nanostructure channel 315 exposed in the source / drain recess 305. An etching tool can be used to perform a wet etching operation to selectively etch the ends of the sacrificial nanostructure layer 120 relative to the nanostructure channel 315, thereby forming the cavity 405. Additionally and / or alternatively, another etching technique, such as a dry etching (e.g., a gas-based etching), can be used.

[0053] As shown in cross-section A-A and cross-section B-B in Figure 4B ​In cross-sectional plane A-A and cross-sectional plane B-B in FIG. 4B, an internal spacer (InSP) 410 is formed in the cavities 405 in the ends of the sacrificial nanostructure layer 120 exposed in the source / drain recesses 305. The internal spacer 410 can be included to reduce parasitic capacitance in the nanostructure transistors and to prevent the source / drain regions (subsequently formed in the source / drain recesses 305) from being etched in a nanosheet release operation to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. The internal spacer 410 includes silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or another dielectric material.

[0054] To form the internal spacer 410, a deposition tool can be used to deposit a layer of dielectric material in the cavities 405 and along the sidewalls and bottom surfaces of the source / drain recesses 305. The layer of dielectric material can be deposited using CVD techniques, PVD techniques, and ALD techniques, and / or another deposition technique. Subsequently, an etch tool is used to remove excess material of the layer of dielectric material from the source / drain recesses such that the remaining portions correspond to the internal spacer 410. Alternatively, a precursor that selectively bonds to the material of the sacrificial nanostructure layer 120 without bonding to the material of the fin portions 160 and the nanostructure channels 315 can be used to selectively form the internal spacer 410 on the ends of the sacrificial nanostructure layer 120.

[0055] As indicated above, Figure 4A and Figure 4B are provided by way of example. Other examples can differ from what is described with respect to Figure 4A and Figure 4B .

[0056] Figures 5A to 5C is an illustration of an example implementation of the source / drain region formation process described herein. The example implementation 500 includes an example of forming source / drain regions of a nanostructure transistor of a semiconductor device 105. Figures 5A-5C is an illustration of the example implementation 500 from a plurality of perspectives, including a perspective of cross-sectional plane A-A in Figure 2 , Figure 2 a perspective of cross-sectional plane B-B in Figure 2 , and a perspective of cross-sectional plane C-C in Figure 2 . In some implementations, the operations described in connection with the example implementation 500 are performed after the processes described in connection with Figures 1A to 4B .

[0057] As Figure 5AAs shown in cross-sectional plane A-A and cross-sectional plane B-B in FIG. 5B, the end portions of the nanowire channel 315 can be laterally etched (e.g., in an x-direction generally parallel to the length of the sacrificial nanowire layer 120) in an etching operation to form cavities 505 between vertically adjacent inner spacers 410. An etching tool can be used to perform a wet etching operation to selectively etch the end portions of the nanowire channel 315 relative to the sacrificial nanowire layer to form the cavities 505. Additionally and / or alternatively, another etching technique, such as a dry etching (e.g., a gas-based etching), can be used.

[0058] As shown in cross-sectional plane A-A and cross-sectional plane B-B in FIG. 5B, the end portions of the nanowire channel 315 can be laterally etched (e.g., in an x-direction generally parallel to the length of the sacrificial nanowire layer 120) in an etching operation to form cavities 505 between vertically adjacent inner spacers 410. An etching tool can be used to perform a wet etching operation to selectively etch the end portions of the nanowire channel 315 relative to the sacrificial nanowire layer to form the cavities 505. Additionally and / or alternatively, another etching technique, such as a dry etching (e.g., a gas-based etching), can be used. Figure 5B As shown in cross-sectional plane A-A and cross-sectional plane B-B in FIG. 5B, the end portions of the nanowire channel 315 can be laterally etched (e.g., in an x-direction generally parallel to the length of the sacrificial nanowire layer 120) in an etching operation to form cavities 505 between vertically adjacent inner spacers 410. An etching tool can be used to perform a wet etching operation to selectively etch the end portions of the nanowire channel 315 relative to the sacrificial nanowire layer to form the cavities 505. Additionally and / or alternatively, another etching technique, such as a dry etching (e.g., a gas-based etching), can be used.

[0059] The source / drain regions can individually or collectively refer to a source or a drain, depending on the context. The source / drain regions 510 can be included on opposite sides of the dummy gate structure 205, such that the nanowire channel 315 under the dummy gate structure 205 extends between and is electrically coupled to the source / drain regions 510.

[0060] The first epitaxial layer 515 and the second epitaxial layer 520 of the source / drain regions 510 can each include a semiconductor material, such as silicon (Si), silicon germanium (SiGe), silicon arsenide (SiAs), silicon phosphorus (SiP), and / or another semiconductor material. The first epitaxial layer 515 and the second epitaxial layer 520 can each be doped with one or more types of dopants, such as arsenic (As), phosphorus (P), and / or boron (B), among others.

[0061] For a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor, the first and second epitaxial layers 515, 520 of the source / drain region 510 can each include silicon germanium (SiGe) doped with boron (B). The germanium (Ge) concentration of the second epitaxial layer 520 can be greater than the germanium (Ge) concentration of the first epitaxial layer 515. For example, the germanium (Ge) concentration of the second epitaxial layer 520 can be included in a range of about 40% to about 60%, while the germanium (Ge) concentration of the first epitaxial layer 515 can be included in a range of about 10% to about 20%. However, other values and ranges are within the scope of the present disclosure. The boron (B) dopant concentration of the second epitaxial layer 520 and the boron (B) dopant concentration of the first epitaxial layer 515 can each be included in a range of about 5 x 1019cm-3to about 5 x 1020cm-3. However, other values and ranges are within the scope of the present disclosure. 20 21 21 21 20 21

[0062] For an n-type metal-oxide-semiconductor (NMOS) nanostructure transistor, the first and second epitaxial layers 515, 520 of the source / drain region 510 can each include silicon (Si) or the like doped with arsenic (As) and / or phosphorus (P). The dopant concentration of the second epitaxial layer 520 can be greater than the dopant concentration of the first epitaxial layer 515. For example, the dopant concentration of the second epitaxial layer 520 can be included in a range of about 2 x 1019cm-3to about 9 x 1020cm-3, while the dopant concentration of the first epitaxial layer 515 can be included in a range of about 1 x 1019cm-3to about 1 x 1020cm-3. However, other values and ranges are within the scope of the present disclosure. 21 21 20 21

[0063] The first and second epitaxial layers 515, 520 of the source / drain region 510 can each be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques. For example, a deposition tool can epitaxially grow the coalesced region 525 of the first epitaxial layer 515 at the bottom of the source / drain recess 305. The coalesced region 525 can include a continuous layer of epitaxially grown material that spans upward from the mesa region 310 to the end of the bottommost nanostructure channel 315.

[0064] ​​As another example, the deposition tool can epitaxially grow a plurality of non-contiguous second epitaxial regions 530 of the first epitaxial layer 515 on the recessed end portions of the nanostructure channels 315 in the cavities 505 such that the non-contiguous second epitaxial regions 530 are located above the merged regions 525. The non-contiguous second epitaxial regions 530 are regions of epitaxially grown material that are not in contact with each other (e.g., due to being separated by the interior spacers 410) and are not in contact with the merged regions 525. The second epitaxial layer 520 can grow on portions of the interior spacers 410 that are exposed between the non-contiguous second epitaxial regions 530 and between the merged regions 525 and the non-contiguous second epitaxial regions 530.

[0065] As Figure 5B As further shown, the one or more epitaxial layers 515, 520 of the source / drain regions 510 partially fill the source / drain recesses 305, resulting in cavities 535 in the source / drain regions 510 that extend from the top of the source / drain regions 510 into the source / drain regions 510. The cavities 535 are hollow regions within the source / drain regions 510 that are not filled with epitaxial material and are filled with air. The cavities 535 result from the second epitaxial layer 520 not fully merging, but instead forming along the sidewalls and bottom surfaces of the regions in the source / drain regions 510 that are not filled by the first epitaxial layer 515.

[0066] In some implementations, the bottom of the cavities 535 is at a vertical (z-direction) location that corresponds to the vertical (z-direction) location of the bottommost interior spacer 410. In some implementations, the bottom of the cavities 535 is at a vertical (z-direction) location that corresponds to the vertical (z-direction) location of the bottommost sacrificial nanostructure layer 120. In some implementations, the bottom of the cavities 535 is at a vertical (z-direction) location that corresponds to the vertical (z-direction) location of the bottommost nanostructure channel 315.

[0067] As Figure 5C As shown, the cavities 535 in the source / drain regions 510 are filled to form sacrificial plugs 540 in the cavities 535. The sacrificial plugs 540 can be temporary structures that are later removed and replaced with portions of the source / drain contacts that extend into the source / drain regions 510. The sacrificial plugs 540 enable subsequent processes (e.g., a replacement gate process that replaces the dummy gate structures 205 with metal gate structures) to be performed prior to forming the source / drain contacts.

[0068] In some implementations, the material of the sacrificial plug 540 differs from the material of one or more epitaxial layers 515, 520 of the source / drain region 510, and / or differs from the material of the internal spacer 410. This allows the etchant to be used to selectively remove the sacrificial plug 540, with minimal or no material removed from the one or more epitaxial layers 515, 520 of the source / drain region 510 and from the internal spacer 410.

[0069] In some implementations, the sacrificial plug 540 is made of a semiconductor material different from the semiconductor material of one or more epitaxial layers 515, 520. For example, one or more epitaxial layers 515, 520 may include doped silicon and / or silicon germanium, and the sacrificial plug 540 may include germanium (Ge). The germanium concentration in the sacrificial plug 540 may be greater than the germanium concentration in one or more epitaxial layers 515, 520. In some implementations, the sacrificial plug 540 is made of a metal oxide material, such as aluminum oxide (Al₂O₃). x O y Such as Al2O3), hafnium oxide (HfO) x (e.g., HfO2) and / or zirconium oxide (ZrO) x (e.g., ZrO2).

[0070] As pointed out above, Figures 5A to 5C Provided as an example. Other examples may be provided in relation to... Figures 5A to 5C The descriptions are different.

[0071] Figure 6 This is a diagram illustrating an example implementation 600 of the interlayer dielectric (ILD) formation process described in this paper. Figure 6 From Figure 2 The multiple perspectives shown include Figure 2 The perspective of the cross-sectional plane AA in the middle Figure 2 The viewpoint of the cross-sectional plane BB in the middle, and Figure 2 The view is shown from the perspective of the cross-sectional plane CC. In some implementations, in combination Figures 1A to 5B The described process is followed by the operation described in conjunction with example implementation 600.

[0072] like Figure 6 As shown in cross-sectional planes AA and BB, a dielectric layer 605 is formed over the source / drain region 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of damage to the source / drain region 510 during a replacement gate process for replacing the dummy gate structures 205 and / or to prevent such damage. The dielectric layer 605 may be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0073] In some implementations, a contact etch stop layer (CESL) 610 is conformally deposited (e.g., by a deposition tool) over the source / drain regions 510 prior to forming the dielectric layer 605. The dielectric layer 605 is then formed over the CESL 610. The CESL 610 can provide a mechanism to stop the etch process when forming contacts or vias to the source / drain regions 510.

[0074] The dielectric layer 605 can include an oxide (e.g., silicon oxide (SiO x ) and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric material. In some implementations, the dielectric layer 605 includes an extremely low-k (ELK) dielectric material having a dielectric constant less than about 2.5. Examples of ELK dielectric materials include: carbon-doped silicon oxide (C-SiO x ), amorphous carbon-fluoride (a-C x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbide (SiOC) polymer, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiO x ) and the like. The dielectric layer 605 can be deposited using a deposition process such as ALD, CVD, or another deposition technique.

[0075] The CESL 610 can be formed of a dielectric material having a different etch selectivity than adjacent layers or components. The CESL 610 can include or be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Further, the CESL 610 can include or be silicon nitride (Si x N y ), silicon carbon nitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or a combination thereof, and the like. The CESL 610 can be deposited using a deposition process such as ALD, CVD, or other deposition technique.

[0076] As indicated above, Figure 6 are provided by way of example. Other examples can differ Figure 6 from those described.

[0077] Figure 7A and Figure 7Bis an illustration of an example implementation 700 of a replacement gate (RPG) process described herein. The example implementation 700 includes an example of a replacement gate process that replaces dummy gate structures 205 with high-k / metal gate structures (e.g., replacement gate structures) of nanowire transistors of a semiconductor device 105. Figure 7A and Figure 7B each is shown from a plurality of perspectives including a perspective of a cross-sectional plane A-A in Figure 2 a perspective of a cross-sectional plane B-B in Figure 2 a perspective of a cross-sectional plane C-C in Figure 2 In some implementations, the operations described in connection with the example implementation 700 are performed after the operations described in connection with the example implementation 600. Figure 2 Figures 1A to 6 As shown in the perspective of the cross-sectional plane B-B and the cross-sectional plane C-C in the replacement gate process includes a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structures 205 from the semiconductor device 105. The removal of the dummy gate structures 205 leaves an opening (or recess) in the dielectric layer 605 and provides access to the underlying sacrificial nanowire layer 120. The dummy gate structures 205 can be removed in one or more etching operations. Such etching operations can include plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0078] Figure 7A As further shown in the replacement gate process includes a nanowire release operation (e.g., a SiGe release operation). The nanowire release operation is performed to remove the sacrificial nanowire layer 120 (e.g., a silicon germanium layer). This creates openings 705 between the nanowire channels 315 (e.g., regions around the nanowire channels 315). The sacrificial nanowire layer 120 can be removed through the space previously occupied by the dummy gate structures 205. The nanowire release operation can include performing an etching operation using an etching tool to remove the sacrificial nanowire layer 120 based on a difference in etching selectivity between the material of the sacrificial nanowire layer 120 and the material of the nanowire channels 315 and between the material of the sacrificial nanowire layer 120 and the material of the inner spacers 410. The inner spacers 410 can act as an etch stop layer in the etching operation to prevent the source / drain regions 510 from being etched.

[0079] Figure 7A As further shown in

[0080] As further shown in Figure 7B ​As shown in cross-sectional planes BB and CC, the gate replacement operation includes forming a gate structure (e.g., a replacement gate structure) 710 in an opening 705 between the source / drain regions 510 and between the internal spacers 410. Specifically, the gate structure 710 fills the regions previously occupied by the sacrificial nanostructure layer 120 between and around the nanostructure channels 315, such that the gate structure 710 completely surrounds and encloses the nanostructure channels 315. This increases control over the nanostructure channels 315, increases the drive current of the nanostructure transistor(s) of the semiconductor device 105, and / or reduces the short-channel effect (SCE) of the nanostructure transistor(s) of the semiconductor device 105, etc. The gate structure 710 may also fill the space previously occupied by the dummy gate structure 205. Partial gate structures 710 are formed in an alternating vertical arrangement between pairs of nanostructure channels 315. In other words, as Figure 7B As shown, the semiconductor device 105 includes one or more vertically stacked alternating nanostructured channels 315 and partial gate structures 710.

[0081] Gate structures 710 may each include a gate dielectric layer 715 and a metal gate electrode 720. The metal gate electrode 720 may include one or more metallic materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), and / or titanium (Ti). Additionally and / or alternatively, gate structures 710 may each include one or more work function metal layers for tuning the work function of the metal gate electrode 720.

[0082] The gate dielectric layer 715 may be a conformal high-k dielectric liner deposited on the nanostructured channel 315 and on the sidewalls of the internal spacer 410 prior to the formation of the gate electrode 720. The gate structures 710 may each include additional layers, such as interface layers, adhesive layers, and / or capping layers. The gate dielectric layer 715 may include one or more high-k dielectric materials, such as silicon nitride (Si). x N y ), hafnium oxide (HfO) x ), Lanthanum oxide (LaO) x ), and / or another suitable high-k dielectric material.

[0083] Some source / drain regions 510 and gate structures 710 can be shared among two or more nanoscale transistors in semiconductor device 105. In these implementations, one or more source / drain regions 510 and gate structures 710 can be connected or coupled to multiple nanostructured channels 315, such as... Figure 7B As shown in the example. This allows multiple nanostructured channels 315 to be controlled by a single gate structure 710 and a pair of source / drain regions 510.

[0084] As noted above, Figure 7A and Figure 7B are provided by way of example. Other examples can differ Figure 7A and Figure 7B from those described.

[0085] Figures 8A to 8F is a diagram of an example implementation 800 of the source / drain contact formation process described herein. Specifically, example implementation 800 includes the example of forming a source / drain contact such that the source / drain contact is recessed within a source / drain region 510 of a nanostructure transistor of a semiconductor device 105 to achieve lower contact resistance and lower current crowding between the source / drain contact and the source / drain region 510. Figures 8A to 8F Each is shown from the perspective of a cross-sectional plane B-B in Figure 2 In some implementations, the operations described in connection with example implementation 800 are performed after the operations described in connection with Figures 1A to 7B

[0086] As shown in Figure 8A , an etch stop layer (ESL) 805 can be formed over and / or on the dielectric layer 605, and over and / or on top of the gate structure 710. Another dielectric layer 810 can be formed over and / or on the ESL 805.

[0087] The ESL 805 can include one or more dielectric materials, such as silicon nitride (Si x N y ), silicon carbon nitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or a combination thereof, etc. The dielectric layer 810 can be referred to as an ILD layer (e.g., an ILD1 layer), and can include one or more dielectric materials, such as an oxide (e.g., silicon oxide (SiO x )(and / or another oxide material), an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric material. In some implementations, the dielectric layer 810 includes an ELK dielectric material.

[0088] ​The deposition tool can be used to deposit the ESL 805 and / or the dielectric layer 810 using a PVD technique, an ALD technique, a CVD technique, and / or other suitable deposition techniques. The ESL 805 and / or the dielectric layer 810 can be deposited in one or more deposition operations. In some implementations, after the ESL 805 and / or the dielectric layer 810 is deposited, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the ESL 805 and / or the dielectric layer 810.

[0089] As shown, a contact recess 815 is formed in the sacrificial plug 540 in the cavity 535 through the dielectric layer 810, through the ESL 805, through the dielectric layer 605, and to the source / drain region 510. Figure 8B

[0090] A first etching operation using an etching tool is performed to form the contact recess 815. In some implementations, a pattern in a photoresist layer is used to form the contact recess 815. In these implementations, a deposition tool can be used to form a photoresist layer on the dielectric layer 810 (e.g., using a spin-on technique and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool can be used to etch the dielectric layer 810, the ESL 805, the dielectric layer 605, and / or the sacrificial plug 540 based on the pattern to form the contact recess 815. In some implementations, the etching operation includes a dry etching operation (e.g., a plasma-based etching operation, a gas-based etching operation), a wet chemical etching operation, and / or other types of etching operations. In some implementations, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some implementations, a hardmask layer is used as an alternative technique for forming the contact recess 815 based on the pattern.

[0091] As shown, a second etching operation is performed (e.g., after the first etching operation described in connection with Figure 8C Figure 8B The second etching operation can differ from the first etching operation in that the first etching operation is performed using a first etchant and the second etching operation is performed using a second etchant that is different from the first etchant. For example, the first etching operation can be performed using a plasma-based etchant and the second etching operation can be performed using a gas-based etchant or a wet etchant.

[0092] ​​Different etchants can be used in the first and second etching operations to achieve different etch selectivity. For example, the first etchant used in the first etching operation can be selected to achieve low etch selectivity between the materials of the dielectric layer (e.g., dielectric layer 605, ESL 805, dielectric layer 810) above the source / drain region 510 and the sacrificial plug 540. This allows the contact recess 815 to be formed in the sacrificial plug 540 through the dielectric layer 605, ESL 805, dielectric layer 810 in the first etching operation.

[0093] For the second etching operation, the second etchant can be selected to achieve high etch selectivity between the dielectric layer (e.g., dielectric layer 605, ESL 805, dielectric layer 810) above the source / drain region 510 and the material of the sacrificial plug 540, and between the material of the sacrificial plug 540 and one or more epitaxial layers 515, 520 of the source / drain region 510 (e.g., the semiconductor material of one or more epitaxial layers 515, 520). For example, one or more epitaxial layers 515, 520 of the source / drain region 510 may include doped silicon, the material of the sacrificial plug 540 may include germanium, and a wet etchant (e.g., a mixed solution including hydrogen peroxide (H2O2), acetic acid (CH3COOH), and / or hydrogen fluoride (HF)) may be used to etch the sacrificial plug 540. As another example, one or more epitaxial layers 515, 520 of the source / drain region 510 may include doped silicon, the material of the sacrificial plug 540 may include a metal oxide material, and etchants such as hydrogen fluoride (HF), phosphoric acid (H3PO4) and / or hydrochloric acid (HCl) may be used to etch the sacrificial plug 540.

[0094] In some implementations, some mixing occurs between the sacrificial plug 540 and the second epitaxial layer 520 of the source / drain region 510. In these implementations, some material of the second epitaxial layer 520 can be removed during the second etching operation.

[0095] like Figure 8C As shown, the bottom of cavity 535 may be located at a vertical (z-direction) position corresponding to the vertical (z-direction) position of the top of the bottommost inner spacer 410 (e.g., inner spacer 410c among vertically arranged inner spacers 410a to 410c). In some implementations, the bottom of cavity 535 is located at a vertical (z-direction) position corresponding to the vertical (z-direction) position of the bottom of the bottommost nanostructure channel 315 (e.g., nanostructure channel 315c among vertically arranged nanostructure channels 315a to 315c).

[0096] like Figure 8DAs shown, a sidewall liner 820 can be formed on portions of the sidewalls of the contact recess 815 over the cavity 535 in the source / drain region 510. The sidewall liner 820 can be formed as a protective liner that prevents the sidewalls of the contact recess 815 from being etched (and thus, prevents the lateral width of the contact recess 815 from being widened) during a second etch operation that is to be subsequently performed to increase the depth of the contact recess 815. Additionally and / or alternatively, the sidewall liner 820 can include a barrier liner that is included to reduce and / or prevent diffusion of material from the source / drain contact (e.g., the source / drain contact to be formed in the contact recess 815) into the surrounding dielectric layers.

[0097] The sidewall liner 820 can include one or more dielectric materials. For example, the sidewall liner 820 can include silicon nitride (Si x N y such as Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and / or another suitable dielectric material.

[0098] To form the sidewall liner 820, a layer of conformal dielectric material can be deposited on the sidewalls of the contact recess 815 (e.g., corresponding to the exposed surfaces of the dielectric layer 605, the exposed surfaces of the ESL 805, and the exposed surfaces of the dielectric layer 810) and on the bottom surface of the contact recess 815 (e.g., corresponding to the exposed surfaces of the second epitaxial layer 520 of the source / drain region 510). A deposition tool can be used to deposit the layer of conformal dielectric material using a deposition technique (e.g., ALD and / or CVD, etc.).

[0099] An etch tool can be used to trim the portions of the layer of conformal dielectric material that are on the bottom surface of the contact recess 815 such that the layer of conformal dielectric material is removed from the surface of the second epitaxial layer 520 of the source / drain region 510. In this way, the surface of the second epitaxial layer 520 of the source / drain region 510 is again exposed through the contact recess 815, and the remaining portions of the layer of conformal dielectric material that are on the sidewalls of the contact recess 815 correspond to the sidewall liner 820.

[0100] An anisotropic etch technique can be used to trim the portions of the layer of conformal dielectric material that are on the bottom surface of the contact recess 815 such that the portions of the layer of conformal dielectric material that are on the sidewalls of the contact recess 815 remain as the sidewall liner 820. For example, a plasma-based etch technique (e.g., a reactive ion etch (RIE) technique) can be used to perform a primarily vertical (e.g., z-directional) etch to trim the layer of conformal dielectric material. However, other etch techniques are within the scope of the present disclosure.

[0101] As Figure 8DAs further shown, a metal silicide layer 825 is formed at the bottom of the cavity 535 in the source / drain region 510. Specifically, the metal silicide layer 825 can be formed from the surface of the source / drain region 510 exposed in the cavity 535 (e.g., the surface of the second epitaxial layer 520 of the source / drain region 510). To form the metal silicide layer 825, a salicidation process can be performed. The salicidation process involves depositing a metal material layer on the surface of the second epitaxial layer 520 of the source / drain region 510 exposed in the cavity 535 using a deposition tool (e.g., by CVD, ALD, PVD, and / or electroplating). An annealing operation can be performed to increase the temperature of the metal material layer and the surface of the second epitaxial layer 520 of the source / drain region 510 exposed in the cavity 535, so that the metal material diffuses into the surface of the second epitaxial layer 520 of the source / drain region 510 exposed in the cavity 535. This allows the formation of the metal silicide layer 825. In other words, the surface of the second epitaxial layer 520 of the source / drain region 510 exposed in the cavity 535 can be transformed from a semiconductor surface to a metal silicide surface.

[0102] In some implementations, the metal material layer includes titanium (Ti), and the metal silicide layer 825 includes titanium silicide (TiSi). In some implementations, the metal material layer includes ruthenium (Ru), and the metal silicide layer 825 includes ruthenium silicide (RuSi). In some implementations, the metal material layer includes cobalt (Co), and the metal silicide layer 825 includes cobalt silicide (CoSi).

[0103] The metal silicide layer 825 can be formed to a thickness ranging from about 3.5 nanometers to about 7 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0104] In some implementation methods, in combination Figure 8C The material remaining in the second epitaxial layer 520 after the second etching operation is completely consumed during the metal silicide deposition process to form the metal silicide layer 825. In other words, the remaining material in the second epitaxial layer 520 can be completely converted into the metal silicide layer 825 during the metal silicide deposition process, so that the second epitaxial layer 520 is no longer retained in the source / drain region 510.

[0105] like Figure 8E As shown, the remaining area in cavity 535 and contact recess 815 are filled with conductive material. The conductive material deposited in cavity 535 of source / drain region 510 corresponds to metal core 830 of source / drain region 510. Therefore, source / drain region 510 may include metal core 830 laterally surrounded by one or more epitaxial layers 515, 520 and metal silicide layer 825.

[0106] Alternatively, the conductive material deposited in the cavity 535 of the source / drain region 510 can correspond to a bottom portion of a source / drain contact 835 recessed within the source / drain region 510. The source / drain contact 835 extends through the dielectric layer 810, through the ESL 805, and through the dielectric layer 605. The sidewall liner 820 can be located between the source / drain contact 835 and the dielectric layer 605, between the source / drain contact 835 and the etch stop layer 805, and / or between the source / drain contact 835 and the dielectric layer 810.

[0107] The metal core 830 and / or the source / drain contact 835 can include a contact plug, a via, a conductive bump, a conductive pillar, and / or another type of conductive structure elongated in the z-direction in the semiconductor device 105. The metal core 830 and / or the source / drain contact 835 can include one or more conductive materials, such as tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), molybdenum (Mo), copper (Cu), and / or aluminum (Al), among others. A deposition tool can be used to deposit the material of the metal core 830 and / or the source / drain contact 835 in the cavity 535 and in the contact recess 815 using a CVD technique, an ALD technique, a PVD technique, an electroplating technique, and / or another suitable deposition technique.

[0108] In this manner, the metal core 830 (or the bottom of the source / drain contact 835) and the metal silicide layer 825 extend to a depth in the source / drain region 510 that is lower than the intermediate nanosheet channel 315 (e.g., the nanosheet channel 315b). The increased depth of the metal core 830 and / or the source / drain contact 835 recessed within the source / drain region 510 in the semiconductor device 105 can decrease the contact resistance between the source / drain contact 835 and the source / drain region 510 due to the increased contact area between the source / drain contact 835 and the source / drain region 510. As the metal core 830 and / or the source / drain contact 835 is recessed within the source / drain region 510, such that in addition to the bottom surface of the metal core 830 and / or the source / drain contact 835 being in contact with the source / drain region 510, portions of the sidewalls of the metal core 830 and / or the source / drain contact 835 are also in contact with the source / drain region 510, an increased contact area is achieved.

[0109] Additionally and / or alternatively, the increased depth of the recess in the source / drain region 510 of the metal core 830 and / or the source / drain contact 835 within the semiconductor device 105 can reduce current congestion in the source / drain region 510 because the metal core 830 and / or the source / drain contact 835 extend alongside the topmost nanostructured channel (e.g., nanostructured channel 315a), alongside the middle nanostructured channel (e.g., nanostructured channel 315b), and in some implementations alongside the bottommost nanostructured channel (e.g., nanostructured channel 315c). This provides a more direct lateral travel path for charge carriers to traverse the source / drain region 510 between the source / drain contact 835 and the nanostructured channel 315 (e.g., conversely, if the source / drain contact 835 terminates at the top of the source / drain region 510, the charge carriers would have to travel vertically in addition to horizontally to reach the nanostructured channels 315a, 315b and / or 315c).

[0110] like Figure 8F As shown, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. During the planarization operation, excess material is removed from the source / drain contacts 835, and the dielectric layer 810 can also be removed. The planarization operation can be stopped once ESL 805 is reached.

[0111] In this way, the semiconductor device 105 can include multiple nanostructure channels 315 arranged in a first direction (e.g., nanostructure channels 315a-c arranged in the z-direction) in the semiconductor device 105. The semiconductor device 105 can include a gate structure 710 that wraps around the multiple nanostructure channels 315. The semiconductor device 105 can include a source / drain region 510 that is adjacent (e.g., laterally adjacent) to a side of the gate structure 710 and laterally adjacent to ends of the multiple nanostructure channels 315 in a second direction that is substantially perpendicular to the first direction (e.g., in the y-direction). The semiconductor device 105 can include multiple internal spacers 410 (e.g., internal spacers 410a-c arranged in the z-direction) between the source / drain region 510 and the gate structure 710. The semiconductor device 105 can include a source / drain contact 835 that extends (e.g., in the z-direction) to a depth in the source / drain region 510 that is below a topmost internal spacer (e.g., internal spacer 410a) and below a topmost nanostructure channel (e.g., nanostructure channel 315a). A bottom portion of the source / drain contact 835 can correspond to the metal core 830 of the source / drain region 510, and the metal core 830 can be laterally surrounded by one or more epitaxial layers 515, 520 and a metal silicide layer 825 of the source / drain region 510.

[0112] The source / drain contact 835 can electrically connect the source / drain region 510 to an interconnect layer (e.g., a back-end-of-line or back-end-of-line (BEOL) region) of the semiconductor device 105. This enables routing of electrical signals and / or power between one or more conductive structures (not shown) in the interconnect layer and the source / drain region 510 through the source / drain contact 835.

[0113] As noted above, Figures 8A to 8F are provided by way of example. Other examples can differ Figures 8A to 8F from the examples described.

[0114] Figures 9A to 9D is an illustration of an example implementation 900 of the semiconductor device 105 described herein. The example implementation 900 is similar to the process described in connection with Figures 1A to 8F but can omit the second epitaxial layer 520.

[0115] As Figure 9AAs shown, a sacrificial plug 540 can be formed in the cavity 535, such that the sacrificial plug 540 contacts the first epitaxial layer 515. The first epitaxial layer 515 can be formed such that the first epitaxial layer 515 is merged along the sidewalls and bottom surface of the source / drain region 510, but is not merged in the central region of the source / drain region 510, thereby forming the cavity 535.

[0116] like Figure 9B As shown, during execution Figure 7A and 7B Following the gate replacement process, the sacrificial plug 540 can then be removed via the contact recess 815. This exposes the cavity 535 in the source / drain region 510. It can then be combined with... Figure 8C A similar method is described for removing the sacrificial plug 540. It can be combined with... Figure 8D A similar manner to that described is used to form a sidewall liner 820 on the sidewall of the contact recess 815 above the cavity 535.

[0117] like Figure 9C As shown, a metal silicide layer 825 can be formed in the cavity 535. It can be bonded with... Figure 8D A similar method is described to form the metal silicide layer 825, but a portion of the material of the first epitaxial layer 515 is consumed to form the metal silicide layer 825. Therefore, in example implementation 900, the metal silicide layer 825 can be formed from the material of the first epitaxial layer 515.

[0118] like Figure 9C As further shown, a metal core 830 of the source / drain region 510 is formed on the metal silicide layer 825 in the cavity 535, and the remaining area in the contact recess 815 is filled with the material of the source / drain contact 835. This can be combined with... Figure 8E The metal core 830 and source / drain contacts 835 are formed in a similar manner as described.

[0119] like Figure 9D As shown, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. During the planarization operation, excess material is removed from the source / drain contacts 835, and the dielectric layer 810 can also be removed. The planarization operation can be stopped once ESL 805 is reached.

[0120] As pointed out above, Figures 9A to 9D Provided as an example. Other examples may be provided in relation to... Figures 9A to 9D The descriptions are different.

[0121] Figures 10A to 10FThis is a diagram illustrating an example implementation 1000 of the semiconductor device 105 described herein. Example implementation 1000 is similar to... Figures 1A to 8F The described process. However, as... Figure 10A As shown, in example implementation 1000, the cavity 535 extends vertically and completely passes through the source / drain region 510. In other words, one or more epitaxial layers 515, 520 of the source / drain region 510 do not merge at the bottom of the source / drain recess 305, so that the source / drain region 510 has a hollow core.

[0122] like Figure 10A As shown, in some implementations, a bottom isolation layer 1005 (sometimes referred to as a flexible bottom insulator) can be formed at the bottom of the source / drain recess 305. The bottom isolation layer 1005 can prevent, minimize, and / or reduce bottom parasitic transistor leakage current, while also reducing parasitic capacitance (e.g., effective capacitance Ceff) in the semiconductor device.

[0123] Furthermore, the bottom isolation layer 1005 may include one or more materials that suppress the epitaxial growth of one or more epitaxial layers 515, 520 of the source / drain region 510 on the bottom of the source / drain recess 305. For example, the bottom isolation layer 1005 may include silicon nitride (Si). x N y Materials such as Si3N4, silicon oxycarbonate (SiOC), silicon oxycarbonitride (SiOCN), and / or silicon carbonitride (SiCN) are used. Because the bottom isolation layer 1005 inhibits the epitaxial growth of one or more epitaxial layers 515, 520 of the source / drain region 510 on the bottom of the source / drain recess 305, the epitaxial growth of one or more epitaxial layers 515, 520 can primarily occur on the sidewalls of the source / drain region 510. For example, a deposition tool can be used to perform an epitaxial deposition operation, wherein the material of the first epitaxial layer 515 is grown on the exposed ends of the nanostructured channel 315 in the source / drain recess 305 and on the exposed ends of the mesa region 310. The exposed ends of the nanostructured channel 315 and the exposed ends of the mesa region 310 serve as the growth substrate for the first epitaxial layer 515. The deposition tool can be used to perform another epitaxial deposition operation, wherein the material of the second epitaxial layer 520 is grown on the first epitaxial layer 515 such that the epitaxial material of the second epitaxial layer 520 is merged together to form a continuous layer of epitaxial material on the sidewall of the source / drain recess 305.

[0124] The deposition tool can be used to deposit the bottom isolation layer 1005 using a PVD technique, an ALD technique, a CVD technique, an oxidation technique, and / or another suitable deposition technique. In some embodiments, the bottom isolation layer 1005 can be formed to include a thickness in a range from about 1 nanometer to about 5 nanometers. However, other values and ranges are within the scope of the present disclosure.

[0125] As shown in Figure 10A Further shown, a cap layer 1010 can be formed on the second epitaxial layer 520. The cap layer 1010 can include an undoped semiconductor material, such as undoped silicon (Si). In some implementations, the cap layer 1010 includes amorphous undoped silicon (Si) and is formed such that the cap layer 1010 can be consumed to form a metal silicide layer 825 on the second epitaxial layer 520 (e.g., in addition to or in addition to consuming material of the second epitaxial layer 520 to form the metal silicide layer 825). The deposition tool can be used to perform an epitaxial deposition operation in which material of the cap layer 1010 is grown on the second epitaxial layer 520.

[0126] As shown in Figure 10A Further shown, the cavity 535 (e.g., the hollow core) of the source / drain region 510 can have a tapered cross-sectional profile in which a bottom width (e.g., in the y-direction) of the cavity 535 (indicated as dimension Dl in Figure 10A ) is less than a top width (e.g., in the y-direction) of the cavity 535 (indicated as dimension D2 in Figure 10A ). The width of the cavity 535 can decrease from the top of the cavity 535 to the bottom of the cavity 535. In some implementations, the tapered cross-sectional profile of the cavity 535 is produced by the source / drain recess 305 having a similar tapered cross-sectional profile. In some implementations, the tapered cross-sectional profile of the cavity 535 is produced due to epitaxial growth of one or more epitaxial layers 515, 520 of the source / drain region 510 being greater at the bottom of the source / drain region 510 than at the top of the source / drain region 510.

[0127] As shown in Figure 10B Further shown, a sacrificial plug 540 can be formed in the cavity 535 such that the sacrificial plug 540 is in contact with the cap layer 1010. In addition, a dielectric layer 605, an etch stop layer 805, and a dielectric layer 810 can be formed over the source / drain region 510. In addition, a replacement gate process can be performed to replace the dummy gate structure 205 and the sacrificial nanostmcture layer 120 with the metal gate structure 710 in a similar manner as described in connection with Figure 7A and Figure 7B

[0128] As shown in Figure 10C Further shown, a dielectric layer 605 can be formed on the cap layer 1010. The dielectric layer 605 can include an oxide material, such as silicon dioxide (SiO2). In some implementations, the dielectric layer 605 includes a conformal oxide material that is formed to conform to the tapered cross-sectional profile of the cavity 535. The deposition tool can be used to perform a conformal deposition operation in which the dielectric layer 605 is formed on the cap layer 1010. Figure 7A and​ Figure 7B After the replacement gate process of FIG. 8, a contact recess 815 can be formed through the dielectric layer 810, through the ESL 805, through the dielectric layer 605, and into the sacrificial plug 540. The contact recess 815 can be formed in a similar manner as described in connection with the contact recess 315 of FIG. 3. Figure 8B

[0129] As shown in FIG. 9, the sacrificial plug 540 can then be removed through the contact recess 815. This exposes the cavity 535 (e.g., hollow core) in the source / drain region 510. The sacrificial plug 540 can be removed in a similar manner as described in connection with the removal of the sacrificial plug 340 of FIG. 3. Figure 10D Figure 8C

[0130] As shown in FIG. 10, a sidewall liner 820 can be formed on the sidewalls of the contact recess 815 over the cavity 535 in a similar manner as described in connection with the sidewall liner 320 of FIG. 3. Figure 10E Figure 8D

[0131] As further shown in FIG. 11, a metal silicide layer 825 can be formed in the cavity 535. The metal silicide layer 825 can be formed in a similar manner as described in connection with the metal silicide layer 325 of FIG. 3, but the cap layer 1010 is consumed to form the metal silicide layer 825 with minimal or no consumption of material of the second epitaxial layer 520 to form the metal silicide layer 825. Since the one or more epitaxial layers 515, 520 of the source / drain region 510 do not merge at the bottom of the cavity 535, the metal silicide layer 825 can extend from the top of the cavity 535 to the bottom of the cavity 535, and to the underlying bottom isolation layer 1005. Figure 10E Figure 8D

[0132] As further shown in FIG. 12, a metal core 830 of the source / drain region 510 is formed on the metal silicide layer 825 in the cavity 535, and the remaining area in the contact recess 815 is filled with material of a source / drain contact 835. The metal core 830 and the source / drain contact 835 can be formed in a similar manner as described in connection with the metal core 330 and the source / drain contact 335 of FIG. 3. Figure 10E Figure 8E

[0133] ​​​​​​​​​However, because the one or more epitaxial layers 515, 520 of the source / drain region 510 do not merge at the bottom of the cavity 535, in the example implementation 1000, the metal core 830 extends from the top of the cavity 535 to the bottom of the cavity 535, and to the underlying bottom isolation layer 1005. In other words, the metal core 830 can extend completely through the source / drain region 510 from the top of the source / drain region 510 to the bottom of the source / drain region 510. Thus, the bottom of the metal core 830 can be located at a vertical (z-direction) location in the semiconductor device 105 that is lower than the lowest nanowire channel 315 (e.g., nanowire channel 315c) and lower than the lowest internal spacer 410 (e.g., internal spacer 410c). In some implementations, the bottom of the metal core 830 can be located at a vertical (z-direction) location that corresponds to the mesa region 310 (or the bottom of the mesa region 310).

[0134] As Figure 10F illustrated, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. In the planarization operation, excess material of the source / drain contact 835 is removed, and the dielectric layer 810 can be removed. Once the ESL 805 is reached, the planarization operation can be stopped.

[0135] As Figure 10F further illustrated, the metal core 830 of the source / drain region 510 can have a tapered cross-sectional profile, where a bottom width (e.g., in the y-direction) of the metal core 830 (dimension Dl) is less than a top width (e.g., in the y-direction) of the metal core 830 (dimension D2). The width of the metal core 830 can decrease from the top of the source / drain region 510 to the bottom of the source / drain region 510 because the metal core 830 can conform to the profile of the cavity 535.

[0136] As noted above, Figures 10A to 10F are provided by way of example. Other examples can differ Figures 10A to 10F from the examples described.

[0137] Figures 11A to 11D is an illustration of an example implementation 1100 of the semiconductor device 105 described herein. The example implementation 1100 is similar to the example implementation 1000 described in connection with Figures 10A to 10F However, in the example implementation 1100, the bottom isolation layer 1005 can extend below the mesa region 310. In some implementations, the bottom isolation layer 1005 is formed over the semiconductor substrate 110 prior to forming the layer stack 115.

[0138] Additionally and / or alternatively, as Figure 11BAs shown, the cavity 535 (e.g., hollow core) of the source / drain region 510 can have the same characteristics as in example implementation 1000. Figure 10A The cross-sectional profiles shown are different. Specifically, the cavity 535 (e.g., a hollow core) of the source / drain region 510 can have a tapered cross-sectional profile, wherein the bottom width of the cavity 535 (e.g., in the y-direction) (in Figure 11B The dimension D3 is greater than the top width of the cavity 535 (e.g., in the y direction). Figure 11B (represented as dimension D4). The width of cavity 535 may be non-uniform from the top to the bottom of cavity 535.

[0139] like Figure 11C and Figure 11D As further shown, the metal core 830 of the source / drain region 510 may have a tapered cross-sectional profile, wherein the bottom width (e.g., in the y-direction) (dimension D3) of the metal core 830 is greater than the top width (e.g., in the y-direction) (dimension D4) of the metal core 830. The width of the metal core 830 from the top to the bottom of the source / drain region 510 may be non-uniform because the metal core 830 may conform to the profile of the cavity 535.

[0140] As pointed out above, Figures 11A to 11D Provided as an example. Other examples may be provided in relation to... Figures 11A to 11D The descriptions are different.

[0141] Figures 12A to 12E This is a diagram illustrating an example implementation 1200 of the semiconductor device 105 described herein. Example implementation 1200 and its combination... Figures 10A to 10F The similarity to the described example implementation 1000 is that, in example implementation 1200, the cavity 535 (e.g., a hollow core) extends vertically, completely passing through the source / drain region 510. Furthermore, in example implementation 1200, a metal core 830 is formed in the cavity 535 such that the metal core 830 extends vertically, completely passing through the source / drain region 510.

[0142] However, example implementation 1200 and combination Figures 10A to 10F The difference in the described example implementation 1000 is that, before forming the dielectric layer 605 and... Figure 7A and Figure 7B Prior to the gate replacement process shown, a metal core 830 is formed in cavity 535 through source / drain recess 305, and after the dielectric layer 605 is formed and Figure 7A and Figure 7BAfter the replacement gate process shown, a metal core 830 is formed in the cavity 535 through the contact recess 815.

[0143] In the example implementation 1200, the sacrificial plug 540 is omitted, and the metal core 830 is formed in the cavity 535 and covered by the dielectric layer 605 (as shown in Figure 12B and Figure 12C The metal core 830 can have a tapered cross-sectional profile, in which a bottom width (dimension Dl in Figure 12B ) of the metal core 830 is less than a top width (dimension D2 in Figure 12B ) of the metal core 830. However, other cross-sectional profiles of the metal core 830 are within the scope of the present disclosure.

[0144] As shown in Figure 12D , the contact recess 815 is formed after the replacement gate process shown in Figure 7A and Figure 7B The top of the metal core 830 is exposed through the contact recess 815. In some implementations, the contact recess 815 is formed such that a bottom of the contact recess 815 is recessed within the metal core 830.

[0145] As shown in Figure 12E , the sidewall liner 820 and the source / drain contact 835 are formed in the contact recess 815 such that the contact recess 815 lands on the top of the metal core 830. In some implementations, the metal core 830 and the source / drain contact 835 are formed of the same conductive material. In some implementations, the metal core 830 and the source / drain contact 835 are formed of different conductive materials. For example, the metal core 830 can be formed of a high melting point material such as ruthenium (Ru), and the source / drain contact 835 can be formed of a relatively lower melting point material such as cobalt (Co). However, other combinations of materials for the metal core 830 and the source / drain contact 835 are within the scope of the present disclosure.

[0146] As noted above, the contact recess 815 can be formed such that a bottom of the contact recess 815 is recessed within the metal core 830. Thus, a bottom of the source / drain contact 835 can be recessed below a top surface of the metal core 830. Accordingly, an interface 1205 between the metal core 830 and the source / drain contact 835 can have a curved or arcuate cross-sectional profile, in which the curve or arc faces downward in the semiconductor device 105. However, other cross-sectional profiles of the interface 1205 between the metal core 830 and the source / drain contact 835 are within the scope of the present disclosure.

[0147] In Figures 12A to 12EIn the illustrated example implementation 1200, the metal core 830 is shown as being formed on the cap layer 1010 of the source / drain region 510, and the metal silicide layer 825 is omitted. However, in other implementations, the cap layer 1010 can be omitted, and the metal silicide layer 825 can be formed on the second epitaxial layer 520 in the source / drain recess 305. In these implementations, the metal core 830 can be formed on the metal silicide layer 825 in the source / drain recess 305.

[0148] As indicated above, Figures 12A to 12E are provided by way of example. Other examples can vary Figures 12A to 12E differently from what is described without departing from the scope of the application.

[0149] Figure 13 is an illustration of an example implementation 1300 of the semiconductor device 105 described herein. As Figure 13 illustrated, the example implementation 1300 of the semiconductor device 105 is similar to the example Figure 12E implementations illustrated in FIGS. 1-12 in that the source / drain region 510 of the nanostructure transistor of the semiconductor device 105 has a metal core 830 that is electrically coupled to a source / drain contact 835. However, in the example implementation 1300, the metal core 830 and the source / drain contact 835 of the source / drain region 510 are partially laterally offset by a distance (denoted as dimension D5 in Figure 13 the example implementation 1300). The partial lateral offset between the metal core 830 and the source / drain contact 835 of the source / drain region 510 can result from an overlay shift during formation of the contact recess 815. The partial lateral offset can cause a portion of the bottom surface of the source / drain contact 835 to be in contact with the cap layer 1010 and / or with the second epitaxial layer 520. Additionally and / or alternatively, the partial lateral offset can cause a portion of the top surface of the metal core 830 to be in contact with the sidewall liner 820 and / or with the dielectric layer 605.

[0150] As indicated above, Figure 13 are provided by way of example. Other examples can vary Figure 13 differently from what is described without departing from the scope of the application.

[0151] Figures 14A to 14E is an illustration of an example implementation 1400 of the semiconductor device 105 described herein. The example implementation 1400 is similar to the example Figures 11A to 11DSimilar to the described example implementation 1100, in the example implementation 1400, the cavity 535 (e.g., hollow core) extends vertically, completely through the source / drain region 510. Further, in the example implementation 1400, the metal core 830 is formed in the cavity 535 such that the metal core 830 extends vertically, completely through the source / drain region 510.

[0152] However, the example implementation 1400 differs from the example implementation 1300 in that the metal core 830 is formed in the cavity 535 through the source / drain recess 305 prior to the replacement gate process shown in Figures 11A to 11D The example implementation 1100 described differs in that the metal core 830 is formed in the cavity 535 through the contact recess 815 after the replacement gate process shown in Figure 7A and Figure 7B The example implementation 1100 described differs in that the metal core 830 is formed in the cavity 535 through the source / drain recess 305 prior to the replacement gate process shown in Figure 7A and Figure 7B The example implementation 1100 described differs in that the metal core 830 is formed in the cavity 535 through the contact recess 815 after the replacement gate process shown in

[0153] In the example implementation 1400, the sacrificial plug 540 is omitted and the metal core 830 is formed in the cavity 535 and covered by the dielectric layer 605 (as shown in Figure 14B and Figure 14C The metal core 830 can have a tapered cross-sectional profile, where a bottom width (dimension D3 in Figure 14B ) of the metal core 830 is greater than a top width (dimension D4 in Figure 14B ) of the metal core 830. However, other cross-sectional profiles of the metal core 830 are within the scope of the present disclosure.

[0154] As shown in Figure 14D , the contact recess 815 is formed after the replacement gate process shown in Figure 7A and Figure 7B The top of the metal core 830 is exposed by the contact recess 815. In some implementations, the contact recess 815 is formed such that a bottom of the contact recess 815 is recessed within the metal core 830.

[0155] As shown in Figure 14EAs shown, the sidewall liner 820 and the source / drain contact 835 are formed in the contact recess 815 such that the contact recess 815 lands on top of the metal core 830. In some implementations, the metal core 830 and the source / drain contact 835 are formed of the same conductive material. In some implementations, the metal core 830 and the source / drain contact 835 are formed of different conductive materials. For example, the metal core 830 can be formed of a high melting point material such as ruthenium (Ru), and the source / drain contact 835 can be formed of a relatively lower melting point material such as cobalt (Co). However, other combinations of materials for the metal core 830 and the source / drain contact 835 are within the scope of the present disclosure.

[0156] As noted above, the contact recess 815 can be formed such that the bottom of the contact recess 815 is recessed within the metal core 830. Thus, the bottom of the source / drain contact 835 can be recessed below the top surface of the metal core 830. Accordingly, the interface between the metal core 830 and the source / drain contact 835 can have a curved or arcuate cross-sectional profile, with the curve or arc facing downward in the semiconductor device 105. However, other cross-sectional profiles for the interface between the metal core 830 and the source / drain contact 835 are within the scope of the present disclosure.

[0157] In Figures 14A to 14E In the example implementation 1400 shown, the metal core 830 is shown as being formed on the cap layer 1010 of the source / drain region 510, and the metal silicide layer 825 is omitted. However, in other implementations, the cap layer 1010 can be omitted, and the metal silicide layer 825 can be formed on the second epitaxial layer 520 in the source / drain recess 305. In these implementations, the metal core 830 can be formed on the metal silicide layer 825 in the source / drain recess 305.

[0158] As noted above, Figures 14A to 14E are provided by way of example. Other examples can differ Figures 14A to 14E from the examples described.

[0159] Figure 15 is a flow diagram of an example process 1500 associated with forming the semiconductor devices described herein. In some implementations, one or more of the process blocks of the process 1500 are performed using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools). Figure 15

[0160] As Figure 15 ​As shown, process 1500 can include forming a plurality of nanostructure channels arranged in a direction generally perpendicular to a semiconductor layer of a semiconductor device (block 1510). For example, one or more semiconductor processing tools can be used to form a plurality of nanostructure channels (e.g., nanostructure channels 315, 315a-c) arranged in a direction (e.g., z-direction) generally perpendicular to a semiconductor layer (e.g., semiconductor substrate 110) of a semiconductor device (e.g., semiconductor device 105), as described herein.

[0161] As shown, process 1500 can include forming a plurality of nanostructure channels arranged in a direction generally perpendicular to a semiconductor layer of a semiconductor device (block 1510). For example, one or more semiconductor processing tools can be used to form a plurality of nanostructure channels (e.g., nanostructure channels 315, 315a-c) arranged in a direction (e.g., z-direction) generally perpendicular to a semiconductor layer (e.g., semiconductor substrate 110) of a semiconductor device (e.g., semiconductor device 105), as described herein. Figure 15 Further shown, process 1500 can include forming a source / drain recess adjacent to the plurality of nanostructure channels (block 1520). For example, one or more semiconductor processing tools can be used to form a source / drain recess (e.g., source / drain recess 305) adjacent to the plurality of nanostructure channels, as described herein.

[0162] As shown, process 1500 can include forming a plurality of nanostructure channels arranged in a direction generally perpendicular to a semiconductor layer of a semiconductor device (block 1510). For example, one or more semiconductor processing tools can be used to form a plurality of nanostructure channels (e.g., nanostructure channels 315, 315a-c) arranged in a direction (e.g., z-direction) generally perpendicular to a semiconductor layer (e.g., semiconductor substrate 110) of a semiconductor device (e.g., semiconductor device 105), as described herein. Figure 15 Further shown, process 1500 can include forming a source / drain recess adjacent to the plurality of nanostructure channels (block 1520). For example, one or more semiconductor processing tools can be used to form a source / drain recess (e.g., source / drain recess 305) adjacent to the plurality of nanostructure channels, as described herein.

[0163] As shown, process 1500 can include forming a plurality of nanostructure channels arranged in a direction generally perpendicular to a semiconductor layer of a semiconductor device (block 1510). For example, one or more semiconductor processing tools can be used to form a plurality of nanostructure channels (e.g., nanostructure channels 315, 315a-c) arranged in a direction (e.g., z-direction) generally perpendicular to a semiconductor layer (e.g., semiconductor substrate 110) of a semiconductor device (e.g., semiconductor device 105), as described herein. Figure 15 Further shown, process 1500 can include forming a source / drain recess adjacent to the plurality of nanostructure channels (block 1520). For example, one or more semiconductor processing tools can be used to form a source / drain recess (e.g., source / drain recess 305) adjacent to the plurality of nanostructure channels, as described herein.

[0164] As shown, process 1500 can include forming a plurality of nanostructure channels arranged in a direction generally perpendicular to a semiconductor layer of a semiconductor device (block 1510). For example, one or more semiconductor processing tools can be used to form a plurality of nanostructure channels (e.g., nanostructure channels 315, 315a-c) arranged in a direction (e.g., z-direction) generally perpendicular to a semiconductor layer (e.g., semiconductor substrate 110) of a semiconductor device (e.g., semiconductor device 105), as described herein. Figure 15 Further shown, process 1500 can include forming a source / drain recess adjacent to the plurality of nanostructure channels (block 1520). For example, one or more semiconductor processing tools can be used to form a source / drain recess (e.g., source / drain recess 305) adjacent to the plurality of nanostructure channels, as described herein.

[0165] As shown, process 1500 can include forming a plurality of nanostructure channels arranged in a direction generally perpendicular to a semiconductor layer of a semiconductor device (block 1510). For example, one or more semiconductor processing tools can be used to form a plurality of nanostructure channels (e.g., nanostructure channels 315, 315a-c) arranged in a direction (e.g., z-direction) generally perpendicular to a semiconductor layer (e.g., semiconductor substrate 110) of a semiconductor device (e.g., semiconductor device 105), as described herein. Figure 15Further, process 1500 can include forming a gate structure wrapping at least three sides of the plurality of nanostructure channels (block 1560). For example, one or more semiconductor processing tools can be used to form a gate structure (e.g., gate structure 710) wrapping at least three sides of the plurality of nanostructure channels, as described herein.

[0166] As Figure 15 Further, process 1500 can include removing the sacrificial plug to expose the cavity of the source / drain region (block 1570). For example, one or more semiconductor processing tools can be used to remove the sacrificial plug to expose the cavity of the source / drain region, as described herein.

[0167] As Figure 15 Further, process 1500 can include filling the cavity of the source / drain region with a layer of metallic material (block 1580). For example, one or more semiconductor processing tools can be used to fill the cavity of the source / drain region with a layer of metallic material (e.g., metallic core 830), as described herein.

[0168] Process 1500 can include additional implementations, such as any single implementation or any combination of combinations of the implementations described below and / or in connection with one or more other processes described elsewhere herein.

[0169] In a first implementation, filling the cavity of the source / drain region with a layer of metallic material includes, after removing the sacrificial plug, forming a source / drain contact (e.g., source / drain contact 835) such that the source / drain contact extends into the cavity of the source / drain region.

[0170] In a second implementation, alone or in combination with the first implementation, process 1500 includes, after forming the gate structure, forming a recess (e.g., contact recess 815) through the dielectric layer and into the source / drain region, wherein forming the source / drain contact includes depositing the layer of metallic material of the source / drain contact in the cavity through the recess.

[0171] In a third implementation, alone or in combination with one or more of the first and second implementations, process 1500 includes removing the sacrificial plug from the cavity of the source / drain region through the recess.

[0172] In a fourth implementation, alone or in combination with one or more of the first through third implementations, the epitaxial material of the source / drain region includes a first semiconductor material, the sacrificial plug includes a second semiconductor material, and the first and second semiconductor materials are different semiconductor materials.

[0173] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, the process 1500 includes forming a metal silicide layer (e.g., the metal silicide layer 825) on the sidewalls of the cavity, wherein filling the cavity with the material of the metal material layer includes depositing the metal material layer on the metal silicide layer.

[0174] In a sixth embodiment, alone or in combination with one or more of the first through fifth implementations, the cavity extends completely through the source / drain region from a top of the source / drain region to a bottom of the source / drain region, and the metal material layer extends completely through the source / drain region from the top of the source / drain region to the bottom of the source / drain region.

[0175] In a seventh implementation, alone or in combination with one or more of the first through sixth implementations, the process 1500 includes forming a silicon (Si) cap layer (e.g., the cap layer 1010) on the sidewalls of the cavity, wherein filling the cavity with the material of the sacrificial plug includes depositing the sacrificial plug on the silicon cap layer.

[0176] In an eighth implementation, alone or in combination with one or more of the first through seventh implementations, the process 1500 includes performing a silicidation metal deposition process to form a metal silicide layer (e.g., the metal silicide layer 825) from the silicon cap layer from the sidewalls of the cavity after the sacrificial plug is removed.

[0177] In a ninth implementation, alone or in combination with one or more of the first through eighth implementations, the cavity extends partially into the source / drain region, and the metal material layer extends into and lands on a bottom portion of the source / drain region.

[0178] Although Figure 15 Example blocks of the process 1500 are shown, but in some implementations, the process 1500 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 16. Additionally, or alternatively, two or more of the blocks of the process 1500 can be performed in parallel. Figure 15

[0179] Figure 16 is a flow diagram of an example process 1600 associated with forming a semiconductor device described herein. In some implementations, one or more process blocks of the process 1600 are performed using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools). Figure 16 ​​

[0180] As shown in Figure 16 Process 1600 can include forming a plurality of nanostructure channels arranged in a first direction in a semiconductor device (block 1610). For example, one or more semiconductor processing tools can be used to form a plurality of nanostructure channels (e.g., nanostructure channels 315, 315a-c) arranged in a first direction (e.g., z-direction) in a semiconductor device (e.g., semiconductor device 105), as described herein.

[0181] As shown in Figure 16 Process 1600 can include forming a source / drain recess adjacent to the plurality of nanostructure channels in a second direction substantially perpendicular to the first direction (block 1620). For example, one or more semiconductor processing tools can be used to form a source / drain recess (e.g., source / drain recess 305) adjacent to the plurality of nanostructure channels in a second direction (e.g., y-direction) substantially perpendicular to the first direction, as described herein.

[0182] As shown in Figure 16 Process 1600 can include partially filling the source / drain recess with an epitaxial material to form a source / drain region in the recess (block 1630). For example, one or more semiconductor processing tools can be used to partially fill the source / drain recess with an epitaxial material (e.g., first epitaxial layer 515, second epitaxial layer 520, merged region 525, discontinuous second epitaxial region 530) to form a source / drain region (e.g., source / drain region 510) in the recess, as described herein. In some implementations, the source / drain region has a cavity (e.g., cavity 535 extending from a top of the source / drain region 510 into the source / drain region 510).

[0183] As shown in Figure 16 Process 1600 can include filling the cavity with a material of a metallic core (block 1640). For example, one or more semiconductor processing tools can be used to fill the cavity with a material of a metallic core (e.g., metallic core 830), as described herein.

[0184] As shown in Figure 16 Process 1600 can include forming a dielectric layer over the source / drain region (block 1650). For example, one or more semiconductor processing tools can be used to form a dielectric layer (e.g., dielectric layer 605) over the source / drain region, as described herein.

[0185] As shown in Figure 16Further, process 1600 can include forming a gate structure wrapping at least three sides of the plurality of nanostructure channels (block 1660). For example, one or more semiconductor processing tools can be used to form a gate structure (e.g., gate structure 710) wrapping at least three sides of the plurality of nanostructure channels, as described herein.

[0186] As Figure 16 Further, process 1600 can include forming a recess through the dielectric layer and into the metal core (block 1670). For example, one or more semiconductor processing tools can be used to form a recess (e.g., contact recess 815) through the dielectric layer and into the metal core, as described herein.

[0187] As Figure 16 Further, process 1600 can include forming a source / drain contact on the metal core in the recess (block 1680). For example, one or more semiconductor processing tools can be used to form a source / drain contact (e.g., source / drain contact 835) on the metal core in the recess, as described herein.

[0188] Process 1600 can include additional implementations, such as any single implementation or any combination of combinations of the implementations described below and / or in connection with one or more other processes described elsewhere herein.

[0189] In a first implementation, forming the recess includes forming the recess such that the recess extends into a portion of the metal core.

[0190] In a second implementation, alone or in combination with the first implementation, forming the source / drain contact includes forming the source / drain contact such that a bottom of the source / drain contact extends into a portion of the metal core.

[0191] In a third implementation, alone or in combination with one or more of the first and second implementations, process 1600 includes forming a silicon (Si) cap layer (e.g., cap layer 1010) on sidewalls of the cavity, wherein filling the cavity with the material of the metal core includes forming the material of the metal core on the silicon cap layer.

[0192] In a fourth implementation, alone or in combination with one or more of the first through third implementations, a top width (e.g., dimension D2) of the cavity at a top of the cavity is greater than a bottom width (e.g., dimension Dl) of the cavity at a bottom of the cavity.

[0193] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, the metal core comprises a first metal, the source / drain contact comprises a second metal, and the first metal and the second metal are different metals.

[0194] Although Figure 16 Example blocks of the process 1600 are shown, but in some implementations, the process 1600 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than pictured. Additionally or alternatively, two or more of the blocks of the process 1600 can be performed in parallel. Figure 16

[0195] In this way, a source / drain region of a nanowire transistor of a semiconductor device is formed such that a hollow cavity extends from a top of the source / drain region into the source / drain region. In some implementations, the cavity extends completely through a depth of the source / drain region. The cavity results from partial epitaxial growth of one or more epitaxial layers of the source / drain region. A metal core of the source / drain region is formed in the cavity, and the metal core is electrically coupled to a source / drain contact of the nanowire transistor such that the conductive material is recessed within the source / drain region. This provides a greater amount of surface area for the source / drain contact to contact the source / drain region than if the source / drain region were completely filled with epitaxially grown semiconductor material. The increased contact surface area provides a reduced contact resistance between the source / drain region and the source / drain contact due to a less restricted current flow path between the source / drain region and the source / drain contact. In this way, the reduced contact resistance between the source / drain region and the source / drain contact enables greater power efficiency to be achieved for the nanowire transistor, and / or enables increased switching speed to be achieved for the nanowire transistor, etc.

[0196] As described in greater detail above, some implementations described herein provide a method. The method includes forming a plurality of nanowire channels arranged in a direction substantially perpendicular to a semiconductor layer of a semiconductor device. The method includes forming a source / drain recess adjacent to the plurality of nanowire channels. The method includes partially filling the source / drain recess with an epitaxial material to form a source / drain region in the recess, wherein the source / drain region has a cavity. The method includes filling the cavity with a material of a sacrificial plug. The method includes forming a dielectric layer over the source / drain region. The method includes forming a gate structure wrapping at least three sides of the plurality of nanowire channels. The method includes removing the sacrificial plug to expose the cavity of the source / drain region. The method includes filling the cavity of the source / drain region with a layer of a metal material.

[0197] ​As described in more detail above, some implementations described herein provide a method. The method includes forming a plurality of nanostructure channels arranged in a first direction in a semiconductor device. The method includes forming a source / drain recess adjacent to the plurality of nanostructure channels in a second direction substantially perpendicular to the first direction. The method includes partially filling the source / drain recess with an epitaxial material to form a source / drain region in the recess, wherein the source / drain region has a cavity. The method includes filling the cavity with a material of a metal core. The method includes forming a dielectric layer over the source / drain region. The method includes forming a gate structure wrapping at least three sides of the plurality of nanostructure channels. The method includes forming a recess through the dielectric layer and into the metal core. The method includes forming a source / drain contact in the recess on the metal core.

[0198] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructure channels arranged in a first direction and extending in a second direction substantially perpendicular to the first direction. The semiconductor device includes a gate structure wrapping the plurality of nanostructure channels. The semiconductor device includes a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructure channels in the second direction, the source / drain region including a metal core, one or more epitaxial layers laterally wrapping the metal core. The semiconductor device includes a source / drain contact on and in contact with the metal core.

[0199] The terms “about” and “substantially” can mean a value of a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are examples only and are not intended to limit. It will be understood that, in light of the present disclosure, the terms “about” and “substantially” can refer to a percentage of a value of a given quantity.

[0200] The features of the embodiments described above are provided to enable a person skilled in the art to better understand the aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for the design or modification of other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

[0201] Example

[0202] Example 1. A method for forming a semiconductor device, comprising: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a semiconductor layer of the semiconductor device; forming source / drain recesses adjacent to the plurality of nanostructure channels; partially filling the source / drain recesses with an epitaxial material to form source / drain regions in the recesses, wherein the source / drain regions have cavities; filling the cavities with a material of a sacrificial plug; forming a dielectric layer over the source / drain regions; forming a gate structure that wraps at least three sides of the plurality of nanostructure channels; removing the sacrificial plug to expose the cavities of the source / drain regions; and filling the cavities of the source / drain regions with a metal material layer.

[0203] Example 2. The method of example 1, wherein filling the cavities of the source / drain regions with the metal material layer comprises, after removing the sacrificial plug, forming a source / drain contact such that the source / drain contact extends into the cavities of the source / drain regions.

[0204] Example 3. The method of example 2, further comprising, after forming the gate structure, forming a recess through the dielectric layer and into the source / drain regions, wherein forming the source / drain contact comprises depositing the metal material layer of the source / drain contact in the cavities through the recess.

[0205] Example 4. The method of example 3, further comprising removing the sacrificial plug from the cavities of the source / drain regions through the recess.

[0206] Example 5. The method of example 4, wherein the epitaxial material of the source / drain regions comprises a first semiconductor material; wherein the sacrificial plug comprises a second semiconductor material; and wherein the first semiconductor material and the second semiconductor material are different semiconductor materials.

[0207] Example 6. The method of example 1, further comprising forming a metal silicide layer on sidewalls of the cavities, wherein filling the cavities with the metal material layer comprises depositing the metal material layer on the metal silicide layer.

[0208] Example 7. The method of example 1, wherein the cavities extend completely through the source / drain regions from a top of the source / drain regions to a bottom of the source / drain regions; and wherein the metal material layer extends completely through the source / drain regions from the top of the source / drain regions to the bottom of the source / drain regions.

[0209] Example 8. The method of example 1, further comprising forming a silicon (Si) cap layer on sidewalls of the cavity, wherein filling the cavity with material of the sacrificial plug comprises depositing the sacrificial plug on the silicon cap layer.

[0210] Example 9. The method of example 8, further comprising, after removing the sacrificial plug, performing a silicidation metal deposition process to form a metal silicide layer from the silicon cap layer from sidewalls of the cavity.

[0211] Example 10. The method of example 1, wherein the cavity extends partially into the source / drain region; and wherein the metal material layer extends into and lands on a bottom portion of the source / drain region.

[0212] Example 11. A method for forming a semiconductor device, comprising: forming a plurality of nanostructure channels arranged in a first direction in a semiconductor device; forming a source / drain recess adjacent to the plurality of nanostructure channels in a second direction substantially perpendicular to the first direction; partially filling the source / drain recess with an epitaxial material to form a source / drain region in the recess, wherein the source / drain region has a cavity; filling the cavity with material of a metal core; forming a dielectric layer over the source / drain region; forming a gate structure that wraps at least three sides of the plurality of nanostructure channels; forming a recess through the dielectric layer and into the metal core; and forming a source / drain contact in the recess on the metal core.

[0213] Example 12. The method of example 11, wherein forming the recess comprises forming the recess such that the recess extends into a portion of the metal core.

[0214] Example 13. The method of example 12, wherein forming the source / drain contact comprises forming the source / drain contact such that a bottom of the source / drain contact extends into the portion of the metal core.

[0215] Example 14. The method of example 11, further comprising forming a silicon (Si) cap layer on sidewalls of the cavity, wherein filling the cavity with material of the metal core comprises depositing the metal core on the silicon cap layer.

[0216] Example 15. The method of example 11, wherein a top width of the cavity at a top of the cavity is greater than a bottom width of the cavity at a bottom of the cavity.

[0217] Example 16. The method of example 11, wherein the metal core comprises a first metal; wherein the source / drain contact comprises a second metal; and wherein the first metal and the second metal are different metals.

[0218] Example 17. A semiconductor device comprising: a plurality of nanostructure channels arranged in a first direction and extending in a second direction substantially perpendicular to the first direction; a gate structure surrounding the plurality of nanostructure channels; a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructure channels in the second direction, the source / drain region comprising: a metal core; and one or more epitaxial layers laterally surrounding the metal core; and a source / drain contact on and in contact with the metal core.

[0219] Example 18. The semiconductor device of example 17, further comprising: a metal silicide layer between the metal core and the one or more epitaxial layers.

[0220] Example 19. The semiconductor device of example 18, wherein the metal core extends vertically between a topmost nanostructure channel of the plurality of nanostructure channels and a bottommost nanostructure channel of the plurality of nanostructure channels.

[0221] Example 20. The semiconductor device of example 19, wherein a portion of the one or more epitaxial layers is below a bottom of the metal core.

Claims

1. A method for forming a semiconductor device, comprising: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a semiconductor layer of the semiconductor device; forming a source / drain recess adjacent to the plurality of nanostructure channels; partially filling the source / drain recess with an epitaxial material to form a source / drain region in the recess, wherein the source / drain region has a cavity; filling the cavity with a material of a sacrificial plug; forming a dielectric layer over the source / drain region; forming a gate structure wrapping at least three sides of the plurality of nanostructure channels; removing the sacrificial plug to expose the cavity of the source / drain region; and filling the cavity of the source / drain region with a layer of a metallic material.

2. The method of claim 1, wherein, filling the cavity of the source / drain region with the layer of the metallic material comprises: after removing the sacrificial plug, forming a source / drain contact such that the source / drain contact extends into the cavity of the source / drain region.

3. The method of claim 2, further comprising: after forming the gate structure, forming a recess through the dielectric layer and into the source / drain region, wherein forming the source / drain contact comprises: depositing the layer of the metallic material of the source / drain contact in the cavity through the recess.

4. The method of claim 3, further comprising: removing the sacrificial plug from the cavity of the source / drain region through the recess.

5. The method of claim 4, wherein, the epitaxial material of the source / drain region comprises a first semiconductor material; wherein the sacrificial plug comprises a second semiconductor material; and wherein the first semiconductor material and the second semiconductor material are different semiconductor materials.

6. The method of claim 1, further comprising: forming a layer of metal silicide on sidewalls of the cavity, wherein filling the cavity with the layer of the metallic material comprises: depositing the layer of the metallic material on the layer of metal silicide.

7. The method of claim 1, wherein, the cavity extends completely through the source / drain region from a top of the source / drain region to a bottom of the source / drain region; and wherein the layer of the metallic material extends completely through the source / drain region from a top of the source / drain region to a bottom of the source / drain region.

8. The method of claim 1, further comprising: forming a silicon (Si) cap layer on sidewalls of the cavity, wherein filling the cavity with the material of the sacrificial plug comprises: depositing the sacrificial plug on the silicon cap layer.

9. A method for forming a semiconductor device, comprising: forming a plurality of nanostructure channels arranged in a first direction in a semiconductor device; forming a source / drain recess adjacent to the plurality of nanostructure channels in a second direction substantially perpendicular to the first direction; partially filling the source / drain recess with an epitaxial material to form a source / drain region in the recess, wherein the source / drain region has a cavity; filling the cavity with a material of a metallic core; forming a dielectric layer over the source / drain region; forming a gate structure that wraps at least three sides of the plurality of nanostructure channels; forming a recess through the dielectric layer and into the metal core; and forming a source / drain contact on the metal core in the recess.

10. A semiconductor device, comprising: a plurality of nanostructure channels arranged in a first direction and extending in a second direction substantially perpendicular to the first direction; a gate structure wrapping the plurality of nanostructure channels; a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructure channels in the second direction, the source / drain region comprising: a metal core; and one or more epitaxial layers laterally surrounding the metal core; and a source / drain contact on and in contact with the metal core.

10. A semiconductor device, comprising: a plurality of nanostructure channels arranged in a first direction and extending in a second direction substantially perpendicular to the first direction; a gate structure wrapping the plurality of nanostructure channels; a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructure channels in the second direction, the source / drain region comprising: a metal core; and one or more epitaxial layers laterally surrounding the metal core; and a source / drain contact on and in contact with the metal core.

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