Vertical groove type gallium nitride super-junction MOSFET device integrated with double Schottky diodes and preparation method of vertical groove type gallium nitride super-junction MOSFET device

Abstract

The invention relates to a vertical groove type gallium nitride super-junction MOSFET device integrated with double Schottky diodes and a preparation method of the vertical groove type gallium nitride super-junction MOSFET device, and belongs to the technical field of semiconductors. The super junction structure is applied to the vertical trench MOSFET, the p / n-columns which are arranged alternately form a transverse electric field in a drift region, the trench is etched to be filled with Schottky metal, meanwhile, the trench and the n-columns form an N-type SBD, and the trench and the p-columns form a P-type SBD. And the P-type SBD and the p +-GaN / p-column / n-column diode are connected in series. During reverse conduction, the N-type SBD serves as a main fly-wheel diode, low starting voltage is achieved, meanwhile, the reverse biased P-type SBD restrains the minority carrier injection phenomenon of a PN junction, reverse recovery charges are reduced, and the design that the reverse voltage resistance of the device is greatly improved under the condition that the forward characteristic of the device is slightly improved is achieved.

Description

TECHNICAL FIELD

[0001] The application relates to an integrated vertical trench-type gallium nitride super-junction MOSFET device with double Schottky diodes and a preparation method thereof, and belongs to the technical field of semiconductors. BACKGROUND

[0002] GaN, as a representative of the third-generation semiconductor material, has shown significant advantages in the power electronics field due to its excellent physical and chemical properties. Compared with traditional silicon (Si) and silicon carbide (SiC) materials, GaN has a wider bandgap (3.4 eV), a higher critical breakdown electric field (3.3 MV / cm), and a higher electron saturation drift velocity (2.5×10 7 cm / s). These characteristics enable GaN power transistors to achieve higher operating voltages, faster switching frequencies, and lower on-state losses. Based on these advantages, GaN power transistors have shown broad application prospects in high-frequency and high-power scenarios such as consumer electronics fast charging, new energy vehicle electric drive systems, and photovoltaic inverters, and have gradually become key devices for improving the performance of power electronic systems.

[0003] GaN-based lateral high electron mobility transistors (HEMTs) have a high mobility two-dimensional electron gas (2DEG) channel formed by AlGaN / GaN heterojunctions, which exhibit excellent switching performance and low on-state losses in medium and low voltage applications below 650 V. However, its lateral structure faces significant challenges in high voltage (>1 kV) and large current applications: to achieve high voltage resistance, the gate-drain spacing needs to be increased, resulting in increased chip area and cost; the large gate-drain capacitance limits high-frequency performance; surface state effects easily cause threshold voltage drift; and low threshold voltage is easily disturbed by noise, affecting system reliability. In contrast, vertical GaN power transistors can effectively overcome the inherent defects of lateral HEMTs by optimizing the device structure. Vertical devices increase the thickness of the epitaxial layer to improve the voltage resistance without sacrificing device area; and the conduction channel is located inside the device, avoiding the current collapse effect caused by surface traps; in addition, vertical devices have excellent thermal management capabilities. The current mainstream vertical structures include current aperture vertical electron transistors (CAVETs), fin field effect transistors (FinFETs), and trench-type metal-oxide-semiconductor field effect transistors (T-MOSFETs). Among them, T-MOSFETs have a simple and mature manufacturing process, are easy to be compatible with existing semiconductor production lines, have good industrialization prospects, and have a threshold voltage greater than 3 V, avoiding false opening. Therefore, T-MOSFETs are widely studied.

[0004] Although T-MOSFETs show great potential in high-power applications, their breakdown voltage still faces significant limitations. On one hand, devices in high-voltage states are prone to current crowding at the isolation mesa edges and trench gate corners, leading to premature breakdown and reducing the voltage withstanding capability of the device. On the other hand, conventional MOSFETs follow the typical trade-off relationship between breakdown voltage and on-resistance (BV 2 ∝R on,sp ), which means that increasing the breakdown voltage requires increasing the drift layer thickness or reducing the doping concentration, but this will increase the on-resistance and affect the power conversion efficiency. To overcome these challenges, researchers have proposed the introduction of a super junction (SJ) structure. The lateral PN junction introduced by it suppresses the crowding electric field near the gate trench, while the super junction structure modulates the electric field distribution of the drift region from the traditional triangle to a trapezoidal distribution, breaking the BV 2 ∝R on,sp limitation, and the device can increase the doping concentration of the drift region while maintaining a high breakdown voltage, thereby achieving a lower on-resistance and a significantly improved static bariga figure of merit (BFOM).

[0005] However, the introduction of a super junction structure can improve the electric field distribution, but it will form a large area of PN junction, leading to an increase in the stored minority carriers of the PN diode in the freewheeling mode, and the reverse recovery performance of the device is severely degraded. Excessive reverse recovery charge (Q rr ) will increase the switching loss, high-frequency oscillation current will radiate electromagnetic interference, and affect the stability of the system, and serious voltage spikes may damage the device. These problems seriously restrict the performance improvement of super junction devices, and it is urgent to balance the contradiction between electric field regulation and parasitic effects through structural optimization. Using electron irradiation, heavy metal doping, and other carrier lifetime control methods can accelerate carrier recombination and reduce Q rr , but this will increase the on-resistance and the leakage current. Connecting a super junction MOSFET with a junction field effect transistor (JFET) in series can completely avoid the reverse recovery problem of the super junction body diode by using the characteristics of the latter without a body diode, but the driving circuit of this scheme is particularly complex and costly. Therefore, developing a new device structure that applies super junction while avoiding the deterioration of the reverse recovery characteristics of the device is of great significance for optimizing the performance of super junction MOSFET devices and improving the overall efficiency and reliability of the power conversion system. SUMMARY

[0006] In view of the deficiencies of the prior art, the application provides a vertical trench type gallium nitride super-junction MOSFET device integrated with double Schottky diodes and a preparation method thereof. The application applies a super-junction structure to a vertical trench MOSFET by a deep trench etching and then epitaxial filling method, and the alternately arranged p-columns and n-columns form a lateral electric field in a drift region, so that a more uniform electric field distribution in the device is realized, thereby improving the withstand voltage capability of the device. In order to avoid the problem of poor reverse recovery performance caused by the super-junction embedding, the application etches a trench above the p-column by a process fully compatible with gate trench etching, and fills a Schottky metal, at the same time, forms an N-type Schottky diode (SBD) with the n-column and a P-type SBD with the p-column. The P-type SBD and the p + The diode formed by the GaN / p-column / n-column is connected in series. When reverse conduction, the N-type SBD serves as a main freewheeling diode, and a low turn-on voltage is realized, and at the same time, the reverse-biased P-type SBD suppresses the minority carrier injection phenomenon of a large-area PN junction, so that the reverse recovery charge is reduced.

[0007] The technical scheme of the application is as follows: The vertical trench type gallium nitride super-junction MOSFET device integrated with double Schottky diodes, an epitaxial structure includes, from bottom to top, a substrate, n-GaN epitaxial layers (n-columns) and p-GaN epitaxial layers (p-columns) of the same thickness, and an NPN structure, the NPN structure includes, from bottom to top, an n-GaN layer, a p + -GaN body region layer, an n + -GaN source layer; the NPN structure above the n + -GaN source layer and the p + -GaN body region layer has a thickness, and extends to the n-GaN layer; a surface of the NPN structure and a bottom and a sidewall of the gate trench are deposited with a dielectric layer, and a gate metal is evaporated on the dielectric layer of an inner surface of the gate trench; the NPN structure beside the Schottky metal groove has an n + -GaN source layer is etched with a body electrode metal groove, and the body electrode metal groove has a depth exceeding that of the n + -GaN source layer has a thickness, and extends to the p + -GaN body region layer, the body electrode metal groove is provided with a body electrode metal, and a surface of the body electrode metal and the Schottky metal is provided with a source metal; a drain metal layer is arranged below the substrate.

[0008] The application realizes the super-junction by the deep trench etching and epitaxial filling method, forms a drift region lateral electric field, and breaks through the BV and R on,spThe trade-off relationship between breakdown voltage and on-state resistance is improved. In order to avoid the poor reverse recovery performance of the traditional super-junction MOSFET, an N / P dual-type SBD is integrated in the GaN super-junction MOSFET. Compared with the body PN diode (about 3 V), the integrated N-type SBD is turned on at about 0.7 V, which can effectively reduce the on-state loss of the device. Compared with the bipolar current of the body PN diode, the N-type SBD only relies on electron conduction, which suppresses the bipolar degradation effect and makes the device have better stability, so that the performance degradation of the device is avoided. When the device is working in the third quadrant, the reverse-biased P-type SBD can effectively suppress the opening of the large-area PN diode introduced by the super-junction, further reducing the minority carrier injection phenomenon, and greatly reducing the reverse recovery charge.

[0009] Due to the material properties of GaN, N-type and P-type GaN SBDs can be formed at the same time without the need for two Schottky junction preparations. After forming a p / n-pillar super-junction epitaxial layer, a second epitaxial growth of n-GaN / p + -GaN / n + -GaN structure, the n-GaN layer not only serves as part of the MOSFET drift region, but also as the N-type region forming the Schottky junction. A trench is formed above the p-pillar by ICP etching, and the bottom of the trench is in contact with the p-pillar and the sidewall is in contact with the n-GaN. Then, a Schottky metal is filled in the trench, forming a P-type SBD with the p-pillar and an N-type SBD with the n-GaN. The ICP etching process of the Schottky metal trench is fully compatible with the gate trench etching process, and after etching the trench, TMAH treatment can be used to repair the etching damage, thereby reducing the defect state density at the etching interface, reducing the leakage current, and improving the electron mobility in the channel. The synergistic effect of the super-junction and the dual-type SBD makes the proposed device have higher breakdown voltage, lower on-state resistance, lower reverse on-voltage, and lower reverse recovery charge compared to the traditional GaN T-MOSFET. The main technical means and the advantages of each improvement point are as follows: 1. Deep trench etching + epitaxial filling to realize super-junction.

[0010] Advantages: By one-time deep trench etching, a high aspect ratio trench structure can be formed, which can reduce the number of masks and etching steps compared to traditional multiple epitaxial growth, and reduce the process complexity and manufacturing cost. The trench filling uses metal organic chemical vapor deposition (MOCVD), which can accurately control the doping concentration and size of the P-type pillar, achieve charge balance with the N-type region, and avoid the problem of interface defect accumulation caused by multiple epitaxial growth.

[0011] 2. P-type and N-type SBDs improve the reverse recovery and third quadrant conduction performance of the device.

[0012] Advantages: Ni, as a Schottky metal, can simultaneously form Schottky contacts with both N-type and P-type GaN. This means that both N-type and P-type SBDs can be integrated simultaneously in the source region of the superjunction MOSFET, eliminating the need for two separate SBD fabrications and reducing process complexity. The N-type SBD handles the main freewheeling current, while the P-type SBD and the PN diode introduced by the superjunction are connected in series. When the device is reverse-biased, the P-type SBD blocks the current, suppressing the turn-on of the large-area PN diode. The combined effect of the two SBDs significantly improves the reverse recovery characteristics.

[0013] 3. Schottky metal trench process is compatible with gate trench process. Advantages: It is fully compatible with ICP etching process, requiring no additional process development and reducing process difficulty; after etching, wet etching of GaN with TMAH solution can reduce etching damage, optimize etching morphology, reduce interface states, and thus reduce leakage current.

[0014] A method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes includes the following steps: (a) An n-GaN epitaxial layer is grown on the substrate as an n-pillar, preferably with a thickness of 5-15 μm, and more preferably with a thickness of 11.9 μm.

[0015] (b) ICP (Cl2 / BCl3 / Ar) trench etching is performed on the epitaxial wafer. The etching depth is the thickness of the epitaxial layer grown in step (a), and the etching width is 3-6 μm, preferably 3 μm.

[0016] (c) A p-GaN epitaxial layer is grown in the trench of step (b) using MOCVD selective epitaxy as a p-pillar, and the thickness of the p-GaN epitaxial layer is equal to the thickness of the n-GaN epitaxial layer (n-pillar) grown in step (a).

[0017] (d) Secondary epitaxial growth of NPN structure, with the material type and thickness of each layer from bottom to top as follows: n-GaN layer, p + -GaN bulk layer, n + -GaN source layer, n + - The doping concentration of the GaN source layer is higher than that of the n-GaN layer; preferably, the thickness of the n-GaN layer is 1.1 μm, p + The thickness of the GaN channel layer is 0.7 μm, n + The thickness of the GaN source layer is 0.2 μm.

[0018] (e) ICP (Cl2 / BCl3 / Ar) trench etching is performed on the epitaxial structure using SiO2 as a hard mask to form gate trenches; the etching location is the NPN structure above the n-pillars, and the etching depth is > n. +- GaN source layer and p + - The sum of the thicknesses of the GaN body region layers, i.e. extending into the n-GaN layer of the NPN structure. The etching width is in the range of 2-4 μm, preferably the gate trench is a trench shaped with an etching depth of 2 μm and a width of 2 μm.

[0019] (f) After TMAH wet etching and annealing, ALD or PEALD growth of a gate dielectric layer, preferably SiO2, or Al2O3, or HfO2, further preferably 100 nm of SiO2.

[0020] (g) ICP etching of a Schottky metal slot on top of the NPN structure above the p-pillar, with an etching depth ≥ the sum of the thicknesses of the NPN grown in step (d) of the second epitaxy, i.e. the etched trench bottom is in contact with the p-pillar.

[0021] (h) E-beam evaporation of Ni metal in the Schottky metal slot to form a Schottky contact.

[0022] (i) Etching of a dielectric layer on top of the NPN structure in the source region to complete the source region opening. Then ICP etching of a body electrode metal slot, etched to the p + - GaN body region upper surface, the body electrode metal slot can be adjacent to the Schottky metal slot, then evaporation of Pd metal in the trench to form an ohmic contact to the p + - GaN.

[0023] (j) E-beam evaporation of metal to form source on the body electrode metal and Schottky metal upper surface, drain under the substrate and gate in the gate trench. Preferably, the source, gate, drain metals are Cr / Au.

[0024] The application proposes introducing a super junction structure in a GaN T-MOSFET, and using the advantage that Ni metal can form SBDs with N-type / P-type GaN at the same time, integrating N-type and P-type SBDs in a monolithic device, namely a double SBD structure. On the one hand, the super junction structure effectively regulates the internal electric field distribution of the device, thereby significantly improving the breakdown voltage while maintaining a high current density. On the other hand, during the third quadrant conduction phase of the device, the N-type SBD assumes the role of reverse freewheeling, compared with the body diode, further reducing the opening voltage of the reverse channel and reducing the conduction loss. The P-type SBD is reverse biased when the MOSFET device is in reverse conduction, suppressing the opening of the large-area PN diode introduced by the super junction, thereby suppressing the minority carrier injection and reducing the reverse recovery charge. Under the joint action of both N-type and P-type SBDs, the reverse recovery performance of the device is greatly improved. Unlike other monolithic GaN MOSFET device structures integrated with SBDs, the SBDs integrated in the application are located in the source region, and N / P double-type SBDs are formed at the same time by relying on a one-time Schottky junction process.

[0025] Through a large number of simulation and analysis, we know that the structure design greatly improves the breakdown performance of the device while maintaining a low forward conduction resistance, successfully breaking the breakdown voltage bottleneck of T-MOSFET. At the same time, the application of double SBDs brings lower reverse opening voltage and excellent reverse recovery performance, showing the great potential of GaN power devices as a new generation of high-power, large-current, low-loss power devices.

[0026] The application effectively solves the problems of T-MOSFET reverse freewheeling and limited breakdown voltage. The introduction of a super junction in the drift region solves the problem of low breakdown voltage; the integration of N-type and P-type SBDs solves the problems of poor reverse freewheeling capability and degraded reverse recovery performance.

[0027] The beneficial effects of the application are as follows: The application embeds a super junction in a traditional GaN-based T-MOSFET, solves the problem of premature breakdown of the device caused by current crowding in the traditional structure, and changes the drift region electric field distribution from a triangle to an approximate trapezoid, overcoming the BV 2 ∝R on,sp limitation, thereby achieving a design that slightly improves the forward characteristics of the device while greatly improving the reverse voltage withstand characteristics of the device. In addition, by using a process fully compatible with the gate trench, a Schottky metal trench is etched, and N-type and P-type SBDs are simultaneously realized. Both of them have an inhibitory effect on the body diode of the MOSFET, reducing the minority carrier injection and achieving excellent reverse recovery performance. The N-type SBD acts as the main freewheeling channel in reverse conduction, achieving a lower conduction voltage. The breakthrough design of the device not only significantly improves the performance limit of GaN power devices, but also opens up a new path for future efficient and compact power electronic systems. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A specific process flow chart is prepared for the proposed GaN super-junction MOSFET integrated with double Schottky diodes (DSSJ-MOSFET); Figure 2 The BV, R on,sp and BFOM of the DSSJ-MOSFET vary with the p / n-column doping concentration; Figure 3 The forward conduction performance of the proposed DSSJ-MOSFET is compared with that of the conventional T-MOSFET; Figure 4 The voltage resistance performance of the proposed DSSJ-MOSFET is compared with that of the conventional T-MOSFET; Figure 5 The reverse conduction performance of the proposed DSSJ-MOSFET is compared with that of the conventional T-MOSFET; Figure 6 The reverse recovery performance of the proposed DSSJ-MOSFET is compared with that of the conventional T-MOSFET, and the reverse recovery charge Q rr is determined. DETAILED DESCRIPTION

[0029] The present application is further described below by way of examples and with reference to the accompanying drawings, but is not limited thereto.

[0030] Example 1

[0031] A vertical trench type GaN super-junction MOSFET device integrated with double Schottky diodes, the epitaxial structure of which comprises, from bottom to top, a substrate, n-GaN epitaxial layers (n-columns) and p-GaN epitaxial layers (p-columns) of the same thickness, and an NPN structure, the NPN structure comprising, from bottom to top, an n-GaN layer, a p + -GaN body region layer, and an n + -GaN source layer. The NPN structure above the n-column is provided with a gate trench, the depth of which exceeds the thickness of the n + -GaN source layer and the p + -GaN body region layer, and extends to the n-GaN layer. A dielectric layer is deposited on the upper surface of the NPN structure and the bottom and sidewall of the gate trench, and a gate metal is evaporated on the dielectric layer of the inner surface of the gate trench; the NPN structure above the p-column is provided with a Schottky metal trench, which is provided with a Schottky metal; a body electrode metal trench is etched in the uppermost n + -GaN source layer of the NPN structure beside the Schottky metal trench, the depth of which exceeds the thickness of the n + -GaN source layer, and extends to the p +-GaN body region layer, body electrode metal groove, body electrode metal, source electrode metal on the upper surface of the body electrode metal and Schottky metal; drain metal layer under the substrate.

[0032] Example 2

[0033] A preparation method of an integrated vertical trench type gallium nitride super junction MOSFET device with double Schottky diodes, as shown in Figure 1 , includes the following steps: (a) growing an n-GaN epitaxial layer as an n-column on a substrate, and the thickness of the epitaxial layer is 11.9 μm.

[0034] (b) performing ICP (Cl2 / BCl3 / Ar) trench etching on the epitaxial wafer, the etching depth is the thickness of the epitaxial layer grown in step (a), and the etching width is 3 μm.

[0035] (c) growing a p-GaN epitaxial layer (p-column) by using MOCVD selective epitaxy at the trench of step (b), and the thickness of the p-GaN epitaxial layer is equal to the thickness of the n-GaN epitaxial layer (n-column) grown in step (a).

[0036] (d) growing a NPN structure by secondary epitaxy, and the material type and thickness of each layer from bottom to top are as follows: n-GaN layer, p + -GaN body region layer, n + -GaN source layer, n + The doping concentration of the n-GaN layer is higher than that of the GaN source layer; the thickness of the n-GaN layer is 1.1 μm, and the thickness of the p + The thickness of the n-GaN channel layer is 0.7 μm. + The thickness of the n-GaN source layer is 0.2 μm.

[0037] (e) performing ICP (Cl2 / BCl3 / Ar) etching of the gate trench on the epitaxial structure using SiO2 as a hard mask, and the etching position is the NPN structure above the n-column, and the etching depth is > n + -GaN source layer and p + The sum of the thicknesses of the n-GaN body region layer and the p

[0038] (f) wet etching using a 25% TMAH solution, water bath heating at 75℃, then, N2 atmosphere, 850℃ annealing for 20-30 min to activate the holes in the p-GaN. After that, ALD or PEALD is used to grow a gate dielectric layer, 100nm of SiO2.

[0039] (g) On the NPN structure above the p-pillar, ICP etching of Schottky metal trenches, with an etching depth ≥ the sum of the NPN thicknesses grown in the second epitaxial growth in step (d), i.e., the bottom of the etching trench is in contact with the p-pillar.

[0040] (h) Ni metal is deposited in a Schottky metal bath by electron beam evaporation to form a Schottky contact.

[0041] (i) Etch the dielectric layer above the NPN structure in the source region to complete the source region opening. Then etch the bulk electrode metal trench down to the p-type. + On the upper surface of the GaN bulk layer, the bulk electrode metal trench can be adjacent to the Schottky metal trench, and then Pd metal is deposited in the trench, along with p + -GaN forms ohmic contacts.

[0042] (j) A source electrode is formed on the upper surface of the bulk electrode metal and the Schottky metal by electron beam evaporation, a drain electrode is formed below the substrate, and a gate electrode is formed in the gate trench. Preferably, the source, gate, and drain metals are all Cr / Au.

[0043] Depend on Figure 2 It can be seen that as the doping concentration in the pillar region increases, the R of the proposed device (DSSJ-MOSFET) decreases. on,sp The trend shows a decrease, which is due to the reduction in the resistance of the drift region. At the same time, due to the weakening depletion effect between p-pillars and n-pillars, BV is negatively correlated with the doping concentration in the pillar region.

[0044] Depend on Figure 3 It can be seen that the proposed device (DSSJ-MOSFET) exhibits a lower Ri compared to the traditional T-MOSFET device. on,sp And higher saturation current density, because the JFET region of the device has a higher doping concentration and lower JFET resistance.

[0045] Depend on Figure 4 It can be seen that the electric field modulation effect of the superjunction structure significantly increases the BV of the DSSJ-MOSFET, reaching over 1900 V, which is better than the 1250 V of the traditional T-MOSFET.

[0046] Depend on Figure 5 It can be seen that, in the third quadrant operating state, the turn-on voltage (0.69V) of the proposed DSSJ-MOSFET is significantly lower than that of the T-MOSFET (2.93V). This is because when the device is operating in the reverse conduction phase, the N-type SBD serves as the main freewheeling path, and the Schottky barrier height is lower than that of the PN junction barrier height of the body diode.

[0047] Depend on Figure 6It can be seen that the reverse peak current (I rr ), reverse recovery time (t rr ) and reverse recovery charge (Q rr ) of the proposed DSSJ-MOSFET are significantly reduced compared to the T-MOSFET during the reverse recovery process. This is because the SBD works as a unipolar device, and its current conduction is completely dominated by majority carriers, thus eliminating the minority carrier storage effect. Moreover, the P-type SBD suppresses the opening of the large-area PN diode introduced by the super junction, and suppresses the minority carrier injection phenomenon. Therefore, by replacing the body PN diode with an SBD as a freewheeling diode, the reverse recovery performance of the MOSFET can be significantly improved. In addition, due to the introduction of the double SBD structure, the DSSJ-MOSFET can also effectively suppress the reverse recovery oscillation phenomenon compared to the T-MOSFET.

[0048] Example 3

[0049] A method for preparing a vertical trench type gallium nitride super junction MOSFET device integrated with double Schottky diodes, the steps of which are as described in Example 2, except that in step (a), the thickness of the n-GaN epitaxial layer is 5 μm; in step (b), the etching width is 3 μm; and in step (e), the width of the gate trench is 2 μm.

[0050] Example 4

[0051] A method for preparing a vertical trench type gallium nitride super junction MOSFET device integrated with double Schottky diodes, the steps of which are as described in Example 2, except that in step (a), the thickness of the n-GaN epitaxial layer is 15 μm; in step (b), the etching width is 6 μm; and in step (e), the width of the gate trench is 4 μm.

Claims

1. A vertical trench gallium nitride superjunction MOSFET device integrating dual Schottky diodes, characterized in that, The epitaxial structure, from bottom to top, includes a substrate, n-pillars and p-pillars of the same thickness, and an NPN structure. The NPN structure, from bottom to top, includes an n-GaN layer, a p-pillar, and a π-GaN layer. + -GaN bulk layer, n + -GaN source layer; the NPN structure above the n-pillar has a gate trench with a depth exceeding n + -GaN source layer and p + The thickness of the GaN bulk layer extends to the n-GaN layer; a dielectric layer is deposited on the upper surface of the NPN structure, as well as the bottom and sidewalls of the gate trench; gate metal is deposited on the dielectric layer on the inner surface of the gate trench; a Schottky metal trench is formed in the NPN structure above the p-pillar, and Schottky metal is placed inside it; the uppermost n-GaN layer of the NPN structure next to the Schottky metal trench... + - The GaN source layer is etched with a bulk electrode metal trench, and the depth of the bulk electrode metal trench exceeds n. + -GaN source layer thickness, extending to p + -GaN bulk layer, with bulk electrode metal in the bulk electrode metal groove, and source metal on the upper surface of the bulk electrode metal and Schottky metal; A drain metal layer is provided beneath the substrate.

2. A method for fabricating a vertical trench gallium nitride superjunction MOSFET device integrating dual Schottky diodes, characterized in that, The steps include the following: (a) An n-GaN epitaxial layer is grown on the substrate as an n-pillar; (b) ICP trench etching is performed on the epitaxial wafer, with an etching depth equal to the thickness of the epitaxial layer grown in step (a); (c) A p-GaN epitaxial layer is grown in the trench of step (b) using MOCVD selective epitaxy to form a p-pillar, the thickness of which is equal to the thickness of the n-pillar grown in step (a). (d) Secondary epitaxial growth of NPN structure, with the material type and thickness of each layer from bottom to top as follows: n-GaN layer, p + -GaN bulk layer, n + -GaN source layer, n + - The doping concentration of the GaN source layer is higher than that of the n-GaN layer; (e) ICP (Cl2 / BCl3 / Ar) trench etching to form gate trenches. The etching location is the NPN structure above the n-pillars, and the etching depth is > n. + -GaN source layer and p + -The sum of the thicknesses of the GaN bulk layers; (f) After TMAH wet etching and annealing, a gate dielectric layer is grown; (g) On the NPN structure above the p-pillar, ICP etching of Schottky metal trenches, with an etching depth ≥ the sum of the NPN thicknesses grown in the second epitaxial growth in step (d), i.e., the bottom of the etching trench contacts the p-pillar; (h) Ni metal is deposited by electron beam evaporation in a Schottky metal bath to form a Schottky contact; (i) Etch the dielectric layer above the NPN structure in the source region to complete the opening of the source region; Then, the bulk electrode metal trench is etched, with a depth exceeding n. + -GaN source layer thickness, then Pd metal is deposited in the trench, and p + -GaN bulk layers form ohmic contacts; (j) Using electron beam evaporation, a source electrode is formed on the upper surface of the bulk electrode metal and the Schottky metal, a drain electrode is formed below the substrate, and a gate electrode is formed in the gate trench.

3. The method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes according to claim 2, characterized in that, In step (a), the thickness of the n-GaN epitaxial layer is 5-15 μm.

4. The method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes according to claim 3, characterized in that, In step (a), the thickness of the n-GaN epitaxial layer is 11.9 μm.

5. The method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes according to claim 2, characterized in that, In step (b), the etching width is 3-6 μm.

6. The method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes according to claim 2, characterized in that, In step (d), n - The GaN layer has a thickness of 1.1 μm, p + The thickness of the GaN channel layer is 0.7 μm, n + The thickness of the GaN source layer is 0.2 μm.

7. The method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes according to claim 2, characterized in that, In step (e), the etching width ranges from 2 to 4 μm.

8. The method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes according to claim 7, characterized in that, In step (e), the gate trench is a trench with an etching depth of 2 μm and a width of 2 μm.

9. The method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes according to claim 2, characterized in that, In step (f), the dielectric layer is silicon dioxide.

10. The method for fabricating a vertical trench gallium nitride superjunction MOSFET device with integrated dual Schottky diodes according to claim 2, characterized in that, In step (j), the source, gate, and drain metals are all Cr / Au.

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