SLED chip structure and manufacturing method
By using a single-crystal substrate with a specific crystal orientation tilt and a ridge waveguide structure in the SLED chip, the tilt of the emitted light from the cavity surface is controlled, solving the problem of unstable spectral ripple coefficient and achieving more stable spectral output and higher photoelectric performance.
Patent Information
- Application Number
- CN202511390420.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-26
- Publication Date
- 2026-02-03
AI Technical Summary
Existing SLED chips exhibit unstable spectral ripple coefficients in high-end applications, affecting the signal-to-noise ratio and measurement accuracy. Traditional methods struggle to effectively suppress this ripple across an ultra-wide spectral range.
By using a single-crystal substrate with a specific crystal orientation and defining the outgoing light tilt angle with microscopic crystal plane angles, a ridge waveguide structure is designed to control the angle of the outgoing light from the cavity surface, thereby disrupting the laser oscillation feedback loop and reducing the spectral ripple coefficient.
It improves the stability of spectral ripple coefficient and chip batch consistency, enhances optical mode control, ensures the smoothness and stability of output spectrum, and improves maximum output power and slope efficiency.
Smart Images
Figure CN121463597A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor optoelectronic device technology, and in particular to an SLED chip structure and manufacturing method. Background Technology
[0002] A Superluminescent Light Emitting Diode (SLED) is a semiconductor optoelectronic device based on the principle of electroluminescence, falling between a laser diode (LD) and a conventional light-emitting diode (LED). Its working principle is as follows: when current is injected, charge carriers in the active region undergo stimulated emission, generating optical gain. Simultaneously, through carefully designed device structures (such as tilted waveguides and anti-reflective films), feedback from the internal resonant cavity of the chip is significantly suppressed, thereby preventing laser oscillation. Therefore, SLEDs possess both the high output power and high brightness of LDs and the wide spectral characteristics of LEDs. This unique low coherence and wide spectral output gives them irreplaceable advantages in fiber optic sensing, especially fiber optic gyroscopes, optical coherence tomography (OCT), and optical testing and measurement. In OCT applications, the wide spectrum determines the system's axial resolution, while low coherence effectively suppresses coherent noise and improves image quality.
[0003] However, in the aforementioned high-end application areas, especially in long-distance, high-resolution OCT systems where signal-to-noise ratio and measurement accuracy are extremely critical, the output spectral stability of SLEDs faces severe challenges. A key performance parameter is the spectral ripple coefficient. High spectral ripple translates into coherent noise in the time domain, severely reducing the system's signal-to-noise ratio and dynamic range, and introducing artifacts in OCT images, misleading diagnosis. To reduce the ripple coefficient, the core technical approach commonly adopted in the industry is to suppress reflection feedback within the chip and at the chip's end face to the greatest extent possible. Traditional methods mainly include: 1. Tilted waveguide structures, where the active waveguide is angled (e.g., 7°) to the chip's cleaved cavity surface, preventing front-reflected light from returning to the gain region along its original path, thus disrupting the formation conditions of the FP resonant cavity; 2. Depositing an anti-reflection (AR) film on the cavity surface to further reduce the residual reflectivity of the end face (R < 0.1%). While these methods are effective, they still have limitations when pursuing ultimate performance: tilted waveguide designs slightly reduce effective gain, and angle control relies on the alignment accuracy of the photolithographic pattern relative to the wafer's flat edge; furthermore, subsequent packaging requires introducing a macroscopic tilt angle within the plane to ensure coupling collimation. The performance of AR films is extremely sensitive to the coating process; their wavelength dependence and environmental stability can cause the ripple coefficient to drift in practical applications, making it difficult to achieve consistently high suppression across an ultra-wide spectral range. Therefore, there is an urgent need for a more stable and controllable structural design that is compatible with existing technologies to further stabilize and reduce the process complexity and consistency of spectral ripple control in SLEDs, in order to meet the demands of next-generation high-performance applications. Summary of the Invention
[0004] In view of this, the purpose of this invention is to provide an SLED chip structure and manufacturing method, which defines the outgoing light tilt by the microscopic crystal plane angle, thereby not only improving the stability of the spectral ripple coefficient, but also enhancing the batch consistency of the chip.
[0005] The present invention solves the above-mentioned technical problems through the following technical means:
[0006] In a first aspect, this application provides an SLED chip structure, including a single crystal substrate, an epitaxial layer disposed on the single crystal substrate, and a ridge waveguide and a P-ohm contact layer disposed on the epitaxial layer. The epitaxial layer includes, in sequence from the single crystal substrate to the P-ohm contact layer, a buffer layer, a lower cladding layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper cladding layer, and a contact Cap layer. The ridge waveguide is above the active layer and is formed by etching the upper waveguide layer. The crystal orientation of the single crystal substrate surface is tilted along the waveguide direction, and the tilt angle of the cavity surface emitted light is defined by the microscopic crystal orientation tilt angle.
[0007] This single-crystal substrate uses a single-crystal substrate with a specific crystal orientation tilt as a growth template. After epitaxial growth on this substrate, all epitaxial layers (including buffer layers, cladding layers, waveguide layers, active layers, etc.) and the ridge waveguide structure finally etched will inherit the tilt angle of the substrate at their end faces (cavity faces). According to the law of optical refraction, when light propagates from a high-refractive-index semiconductor material to low-refractive-index air, it will be refracted at this tilted cavity face. The angle of the outgoing light is strictly defined by the tilt degree of the cavity face (i.e., the tilt angle of the microscopic crystal orientation). This design ensures that most of the light emitted from the cavity face cannot be reflected back into the waveguide along the same path, thus fundamentally destroying the optical feedback loop required for laser oscillation from a physical structure perspective. This helps to optimize the optical waveguide characteristics, enhance the light guiding effect by adjusting light reflection, and reduce the spectral ripple coefficient.
[0008] Preferably, the tilt angle of the single crystal substrate is α, wherein the value of α is in the range of 0° < α < 30°.
[0009] Preferably, the P-ohmic contact layer is provided with a P-Pad electrode layer, and the side of the single crystal substrate away from the buffer layer is provided with an N-Pad electrode layer, and the P-Pad electrode layer is provided with an opening.
[0010] Preferably, the single-crystal substrate material is GaAs or InP.
[0011] Preferably, the ridge waveguide is a locally circular arc ridge, and the tilt angle of the extension line of the locally circular arc ridge is β, wherein the value of β is in the range of 0°<β≤90°.
[0012] Preferably, the buffer layer is a heavily doped N-type or P-type semiconductor material with a doping concentration of 1*10⁻⁶. 17 -1*10 21 cm -3 .
[0013] Preferably, both the lower cladding layer and the upper cladding layer are N-type or P-type semiconductor materials, and the doping types of the lower cladding layer and the upper cladding layer are opposite.
[0014] Preferably, the P-ohmic contact layer is electrically connected to the contact Cap layer.
[0015] Secondly, this application provides a method for manufacturing an SLED chip structure, comprising the following steps:
[0016] S1. Fabrication of epitaxial wafer: Select a single crystal substrate and grow a buffer layer, a lower cladding layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper cladding layer, and a contact Cap layer sequentially on the single crystal substrate;
[0017] S2. Fabrication of chip ridges: SiN is deposited sequentially on the epitaxial wafer. XAlternatively, a SiO2 mask is used, retaining the middle of the active layer as the mask above the active gain region. The masks on both sides of the active gain region are etched away to form a ridge waveguide. Then, the contact Cap layer and the upper cladding on both sides of the epitaxial wafer are etched, and a P-ohmic contact layer is grown on the contact Cap layer.
[0018] Preferably, the manufacturing method of the SLED chip structure further includes the following steps:
[0019] S3. Remove the first mask and clean the epitaxial wafer;
[0020] S4. Fabrication of chip isolation: SiN plating on the epitaxial wafer. X Alternatively, use a SiO2 mask to etch the mask corresponding to the two edges of the etching area in step S2, and etch the upper waveguide layer, active layer, and lower waveguide layer to expose the doped material of the same type as the substrate.
[0021] S5. Remove the second mask and clean the epitaxial wafer;
[0022] S6. Metal contact layer: SiN plated on the epitaxial wafer. X Alternatively, a SiO2 mask is used, and photoresist is applied. The mask and photoresist above the active gain region are etched to remove the mask and photoresist above the active gain region. Metal is deposited on the chip surface using evaporation or sputtering processes, and then the photoresist is removed.
[0023] S7. P-Pad electrode layer fabrication: A secondary metal coating is performed on the chip surface to thicken the P-Pad electrode layer area by electroplating, and then the entire surface is etched with metal.
[0024] S8. Etch away the areas where the secondary metal coating is not thickened, and use the height difference generated by the vapor deposition or electroplating area to cleanly etch away the secondary metal.
[0025] S9. After thinning and polishing the epitaxial wafer, an N-Pad electrode layer is prepared on the back side, and an AR antireflection film is deposited on both ends of the cleaved chip.
[0026] The beneficial effects of this invention are:
[0027] (1) By controlling the microscopic crystal orientation, this invention effectively suppresses parasitic laser oscillations caused by cavity surface reflection in the SLED chip, thereby ensuring that the device can still operate stably in superradiative mode under high injection current. This not only significantly improves the maximum output power and slope efficiency of the SLED, but also ensures that its output spectrum maintains the required width, avoiding spectral narrowing.
[0028] (2) The structure of the present invention does not depend on the alignment accuracy of the photolithography relative to the flat edge of the wafer. The packaging process does not require in-plane angle compensation, which reduces the manufacturing difficulty from chip to module and improves the stability of ripple control. It helps to achieve better optical mode control, ensures the smoothness and stability of spectral output, and significantly improves the overall optoelectronic performance of the chip. Attached Figure Description
[0029] Figure 1 This is a perspective view of the SLED chip structure of the present invention;
[0030] Figure 2 This is a front view of the SLED chip structure of the present invention;
[0031] Figure 3 yes Figure 1 Left side view;
[0032] Figure 4 This is a schematic diagram of the tilt angle of a single-crystal substrate;
[0033] Figure 5 This is a schematic diagram of the tilt angle of a ridge waveguide;
[0034] Figure 6 This is the spectrum of Embodiment 2 of the present invention;
[0035] Figure 7 This is the spectrum of Comparative Example 1 of the present invention.
[0036] Among them, 10 is a single crystal substrate;
[0037] 20 is the epitaxial layer;
[0038] 21 is the buffer layer, 22 is the lower cladding layer, 23 is the lower waveguide layer, 24 is the active layer, 25 is the upper waveguide layer, 26 is the upper cladding layer, 27 is the AR antireflection coating, 28 is the contact cap layer, and 29 is the P-ohmic contact layer.
[0039] 30 is the P-Pad electrode layer;
[0040] 40 is the N-Pad electrode layer. Detailed Implementation
[0041] The technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0042] Example 1
[0043] like Figure 1-3As shown: This embodiment is an SLED chip structure.
[0044] This embodiment provides an SLED chip, which includes:
[0045] Single-crystal substrate 10: The single-crystal substrate material is GaAs or InP, which can be selected as needed. The crystal orientation of the substrate surface is tilted along the waveguide direction, and the tilt angle is defined by the microscopic crystal orientation tilt angle, which is used to control the tilt angle of the emitted light from the cavity surface. That is, the substrate surface deviates from the crystal principal axis direction (such as
[100] or
[110] or
[011] ) by a certain angle. This microscopic crystal orientation tilt angle can be obtained by crystal orientation adjustment before single-crystal substrate cutting or epitaxial growth. By adjusting this tilt angle, the tilt direction and angle of the emitted light from the SLED cavity surface can be controlled, realizing optical control of the predetermined direction of the emitted light, thereby improving the optical coupling efficiency and reducing the reflection loss in the optical system.
[0046] like Figure 4 As shown, the tilt angle α of the single-crystal substrate 10 is controlled within 0° < α < 30° to optimize the optical waveguide characteristics. By adjusting the light reflection, the light guiding effect is enhanced, and the spectral ripple coefficient is reduced. In this embodiment, 10° is specifically selected.
[0047] Epitaxial layer 20: disposed on the single crystal substrate, comprising, from substrate 10 to P-ohmic contact layer 29, the following:
[0048] Buffer layer 21: Used to improve substrate epitaxial matching and reduce lattice defects; it is made of heavily doped N-type or heavily doped P-type semiconductor material with a doping concentration ranging from 1*10⁻⁶. 17 -1*10 21 cm -3 This is used to buffer lattice mismatch and improve the quality of the epitaxial layer. Specifically, a 1*10⁻⁶ layer is selected in this embodiment. 20 cm -3 .
[0049] Lower cladding 22: Composed of doped semiconductor material, used to form waveguide optical confinement;
[0050] Lower waveguide layer 23: Used to support the optical field mode of the active layer;
[0051] Active layer 24: includes a multiple quantum well (MQW) structure or a quantum dot structure for light emission;
[0052] Upper waveguide layer 25: Together with the lower waveguide layer, it forms the waveguide core;
[0053] Upper cladding 26: Used for optical confinement and to form a complete waveguide structure;
[0054] Contact Cap layer 28: A P-type doped semiconductor layer used for electrical contact and reducing contact resistance.
[0055] Ridge waveguide: Located above the active layer, formed by etching the upper waveguide layer, used to define the optical field mode. The ridge waveguide is a locally circular arc ridge, and the tilt angle of the extension line of the locally circular arc ridge is β, where the value of β ranges from 0° to 90°. In this embodiment, 90° is specifically chosen.
[0056] P-ohmic contact layer: Located above the ridge waveguide, used to form a low-impedance electrical contact.
[0057] Traditional SLED chips have their front and rear light-emitting surfaces perpendicular to the ground, forming a standard rectangle when viewed from the left and right sides. The SLED in this application has an angled light-emitting surface, making the chip a parallelogram when viewed from the side. Figure 4 As shown, in this embodiment, the crystal orientation of the single crystal substrate surface is tilted along the waveguide direction, and the tilt angle of the microscopic crystal orientation is adjustable to control the tilt angle of the emitted light from the cavity surface, thereby achieving the control of the emitted light direction and improving the beam coupling efficiency of the SLED chip.
[0058] In this embodiment, the lower cladding layer 22 is an N-type semiconductor material and the upper cladding layer 26 is a P-type semiconductor material, forming an effective optical confinement structure and providing optical field confinement.
[0059] The P-ohmic contact layer 29 and the contact Cap layer 28 are electrically connected to achieve conductivity. Simultaneously, a P-Pad electrode layer 30 is disposed on the P-ohmic contact layer 29, and an N-Pad electrode layer 40 is disposed on the back side of the single-crystal substrate 10 to ensure current input and output channels. For ease of subsequent processing, openings are designed on the P-Pad electrode layer 30 for optical detection or testing of the contact area.
[0060] Example 2
[0061] This embodiment describes the manufacturing method of the SLED chip structure in Embodiment 1.
[0062] S1. Fabrication of epitaxial wafer: Select a single crystal substrate 10 with a tilt angle of 10°, and grow a buffer layer 21, a lower cladding layer 22, a lower waveguide layer 23, an active layer 24, an upper waveguide layer 25, an upper cladding layer 26 and a contact Cap layer 28 on the single crystal substrate 10 in sequence.
[0063] S2. Fabrication of chip ridges: SiN is deposited sequentially on the epitaxial wafer. XAlternatively, a SiO2 mask is used, with the middle of the active layer 24 retained as the mask above the active gain region. The masks on both sides of the active gain region are etched away by a combination of dry etching (RIE) and wet etching to form a ridge waveguide. Here, a Br2:HBr:H2O = 1:50:200 solution is generally selected. The contact Cap layer 28 and the upper cladding layer 26 on both sides of the epitaxial wafer are etched using ICP etching, and a P-ohmic contact layer 29 is grown on the contact Cap layer 28.
[0064] S3. Remove the first mask and clean the epitaxial wafer;
[0065] S4. Fabrication of chip isolation: SiN plating on the epitaxial wafer. X Alternatively, a SiO2 mask is used to etch the mask corresponding to the two edges of the etching area in step S2, and the upper waveguide layer 25, active layer 24, and lower waveguide layer 23 are etched to expose the doped material of the same type as the substrate.
[0066] S5. Remove the second mask and clean the epitaxial wafer;
[0067] S6. Metal contact layer: SiN plated on the epitaxial wafer. X Alternatively, a SiO2 mask is used, and photoresist is applied. The mask and photoresist above the active gain region are etched to remove the mask and photoresist above the active gain region. Metal is deposited on the chip surface using evaporation or sputtering processes, and then the photoresist is removed.
[0068] S7. P-Pad electrode layer 30 fabrication: A secondary metal coating is performed on the chip surface using evaporation or sputtering processes to thicken the P-Pad electrode layer 30 area by electroplating, and then the entire surface is etched with metal.
[0069] S8. Use RIE or wet etching to remove the areas where the secondary metal coating is not thickened, and use the height difference generated by the vapor deposition or electroplating area to clean the secondary metal.
[0070] S9. After thinning and polishing the epitaxial wafer, an N-Pad electrode layer 40 is prepared on the back side, and an AR antireflection film 27 is deposited on both ends of the cleaved chip.
[0071] Comparative Example 1
[0072] Unlike Example 2, the single crystal substrate of S1 is not tilted, and the front and rear light-emitting surfaces of the chip are perpendicular to the ground. When viewed from the left and right sides, it should be a standard rectangle.
[0073] The experimental results of the spectrum are as follows Figure 6 and Figure 7 As shown, where Figure 6 The spectral fluctuations are smooth. Figure 7The spectral fluctuations are relatively large, and the comparative example has a RIP of about 0.4 dB, while the example has a RIP of about 0.1 dB. This shows that Example 2 achieves a smaller ripple coefficient and a smoother spectrum, thereby significantly improving the smoothness and stability of the output spectrum.
[0074] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications and substitutions should be covered within the scope of the claims of the present invention. Technical aspects, shapes, and structures not described in detail in this invention are all well-known technologies.
Claims
1. An SLED chip structure, comprising a single-crystal substrate, an epitaxial layer disposed on the single-crystal substrate, and a ridge waveguide and a P-ohm contact layer disposed on the epitaxial layer, wherein the epitaxial layer comprises, sequentially from the single-crystal substrate to the P-ohm contact layer, a buffer layer, a lower cladding layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper cladding layer, and a contact cap layer, wherein the ridge waveguide is above the active layer and is formed by etching the upper waveguide layer, characterized in that: The crystal orientation of the single crystal substrate surface is tilted along the waveguide direction, and the tilt angle of the emitted light from the cavity surface is defined by the tilt angle of the microscopic crystal orientation.
2. The SLED chip structure according to claim 1, characterized in that, The tilt angle of the single crystal substrate is α, where the value of α ranges from 0° to 30°.
3. The SLED chip structure according to claim 1, characterized in that, The P-ohmic contact layer is provided with a P-Pad electrode layer, and the side of the single crystal substrate away from the buffer layer is provided with an N-Pad electrode layer. An opening is provided on the P-Pad electrode layer.
4. An SLED chip structure according to any one of claims 1-3, characterized in that, The ridge waveguide is a locally circular arc ridge, and the tilt angle of the extension line of the locally circular arc ridge relative to the edge of the light-emitting surface is β, where the value of β ranges from 0° to 90°.
5. An SLED chip structure according to claim 4, characterized in that, The single-crystal substrate material is GaAs or InP.
6. An SLED chip structure according to any one of claims 1-3, characterized in that, The buffer layer is a heavily doped N-type or P-type semiconductor material with a doping concentration of 1*10⁻⁶. 17 -1*10 21 cm -3 .
7. An SLED chip structure according to any one of claims 1-3, characterized in that, Both the lower cladding layer and the upper cladding layer are N-type or P-type semiconductor materials, and the doping types of the lower cladding layer and the upper cladding layer are opposite.
8. An SLED chip structure according to any one of claims 1-3, characterized in that, The P-ohm contact layer is electrically connected to the contact Cap layer.
9. A method for manufacturing an SLED chip structure as described in any one of claims 1-8, characterized in that, Includes the following steps: S1. Fabrication of epitaxial wafer: Select a single crystal substrate and grow a buffer layer, a lower cladding layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper cladding layer, and a contact Cap layer sequentially on the single crystal substrate; S2. Fabrication of chip ridges: SiN is deposited sequentially on the epitaxial wafer. X Alternatively, a SiO2 mask is used, retaining the middle of the active layer as the mask above the active gain region. The masks on both sides of the active gain region are etched away to form a ridge waveguide. Then, the contact Cap layer and the upper cladding on both sides of the epitaxial wafer are etched, and a P-ohmic contact layer is grown on the contact Cap layer.
10. A method for manufacturing an SLED chip structure according to claim 9, characterized in that, It also includes the following steps: S3. Remove the first mask and clean the epitaxial wafer; S4. Fabrication of chip isolation: SiN plating on the epitaxial wafer. X Alternatively, use a SiO2 mask to etch the mask corresponding to the two edges of the etching area in step S2, and etch the upper waveguide layer, active layer, and lower waveguide layer to expose the doped material of the same type as the substrate. S5. Remove the second mask and clean the epitaxial wafer; S6. Metal contact layer: SiN plated on the epitaxial wafer. X Alternatively, a SiO2 mask is used, and photoresist is applied. The mask and photoresist above the active gain region are etched to remove the mask and photoresist above the active gain region. Metal is deposited on the chip surface using evaporation or sputtering processes, and then the photoresist is removed. S7. P-Pad electrode layer fabrication: A secondary metal coating is performed on the chip surface to thicken the P-Pad electrode layer area by electroplating, and then the entire surface is etched with metal. S8. Etch away the areas where the secondary metal coating is not thickened, and use the height difference generated by the vapor deposition or electroplating area to cleanly etch away the secondary metal. S9. After thinning and polishing the epitaxial wafer, an N-Pad electrode layer is prepared on the back side, and an AR antireflection film is deposited on both ends of the cleaved chip.