Partial row refresh in memory device

Abstract

This disclosure provides systems, methods, and devices for a memory system that support partial row refresh operations of the memory system. In a first aspect, a method of refreshing a memory array includes obtaining, by a memory controller from a host device over a channel, partial row refresh information associated with a first row in the memory array; and refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 351,909, filed July 13, 2023, entitled “PARTIAL ROW REFRESH IN A MEMORY DEVICE,” which is expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] Aspects of the present disclosure relate generally to computer information systems and more specifically to memory systems for storing data. Some features can be implemented and provide improved memory capabilities for lower power operation through the use of partial row refresh of memory cells in a memory system. BACKGROUND

[0004] Computing devices (e.g., laptops, mobile phones, etc.) can include one or several processors to perform various computing functions, such as telephony, wireless data access, and camera / video functions, among others. Memory systems are important components of computing devices. Processors can be coupled to memory systems to perform the aforementioned computing functions. For example, processors can fetch instructions from memory systems to perform computing functions and / or store temporary data involved in performing these computing functions within memory systems.

[0005] Memory systems can utilize memory cells that are intrinsically volatile. Volatile memory cells hold information for a short period of time, such as fractions of a second. A refresh operation can be performed by a volatile memory cell to maintain information for a longer period of time. In example volatile memory cells that store information as an electrical charge, the electrical charge decays within fractions of a second. The memory cell can be refreshed to extend the period of time that the memory cell holds information before the electrical charge decays beyond the point of losing information. In some cases, the refresh can be performed repeatedly to extend the storage period of information indefinitely, or as long as power is supplied to the circuit. This refresh operation consumes power, which impacts the operation of devices operating from a limited power source, such as mobile devices operating from battery power.

[0006] One conventional technique to reduce power consumption is partial array self refresh (PASR), which is a lower power refresh mode in which some banks of a memory system are refreshed while other banks are powered down to conserve power. The un-refreshed banks will lose information stored therein. SUMMARY

[0007] The following presents a summary of some aspects of the disclosure to provide a basic understanding of the discussed technology. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a general framework so as to provide a starting point for the more detailed description presented later.

[0008] In some aspects, partial row refresh techniques are described for a memory system to allow refresh operations to maintain information stored in a particular portion of a row of memory cells of the memory system. The partial row refresh techniques can be performed by refreshing a portion of a row based on partial row refresh information. As one example, the partial row refresh information for a row can indicate that a particular portion of the row should be refreshed, such as twenty-five percent of the row, fifty percent of the row, seventy-five percent of the row, or one hundred percent of the row. The partial row refresh information can be determined based on an amount of data stored in the row and can be included in address information for the row. Thus, a portion of a memory row can be refreshed based on an amount of data stored in the memory row.

[0009] In some embodiments, the partial row refresh operations based on the partial row refresh information can be performed during a sleep mode of a processor or other logic device of a host device. When a user presses a power button or when a user does not interact with the device for a predefined period of time, the processor can enter a sleep mode. Prior to entering the sleep mode, the processor can save data, such as context data, to one or more rows of memory and can generate partial row refresh information based on storing the data to the one or more rows of memory. Such generation can include generating address information for the respective rows that includes respective partial row refresh information indicating an amount of data stored in each row. The processor can output the partial row refresh information, such as the address information including the partial row refresh information, to the memory system, which can store the partial row refresh information in registers and / or memory cells of the memory array. The processor can then command the memory system to enter a self-refresh mode, such as a PASR mode, during which the memory system performs refresh operations without input from the processor. The processor can then enter a sleep state or mode during which power consumption of the processor is reduced. Example sleep states or modes can include C0 (active), CI (auto-stop), C2 (stop clock), C3 (deep sleep), and C4 (deeper sleep). Different sleep states or modes can correspond to states or modes in which different portions or combinations of portions of the processor are turned off or reduced in power.

[0010] Partial refresh of a row of memory while in self-refresh mode can reduce power consumption of a memory system, such as up to seventy-five percent while in self-refresh mode. In automotive applications, for example, up to and over 2 mAh of battery power can be saved during a fifteen minute period while the memory is in self-refresh mode compared to per-bank memory refresh in situations where the memory system can encounter extreme temperatures. In applications where a system including a host device and a memory device frequently enters a sleep state or low power mode, up to and over 1 mAh can be saved during a fifteen minute period while the memory is in self-refresh mode compared to per-bank memory refresh. The life of a memory system, such as a double data rate (DDR) memory system, can be extended by using partial row refresh because sense amplifiers used to perform refresh can be activated less frequently. In addition, the application of partial row refresh techniques can be compatible with existing DDR dynamic random access memory (DRAM) chips.

[0011] These aspects can be implemented as a sequence of commands sent from a host to a memory system. The commands sent by the host can include commands to read capabilities from the memory system, set configurations in the memory system, read data at one or more specified addresses from the memory system, and / or write data at one or more specified addresses to the memory system. For example, a host device can include a processor and can be coupled to a memory system. Based on instructions from the processor, the host device can issue a command to set partial row refresh information in the memory system and can subsequently issue a command to initiate a self-refresh mode of operation of the memory system during which the memory system refreshes portions of rows based on the partial row refresh information without further instructions from the processor. The processor can wake up from a sleep state at a later time and issue a command to exit the self-refresh mode of operation.

[0012] An apparatus according to at least one embodiment includes a memory system configured to communicate with a host. The memory system includes a memory array configured to store data. The memory system can include a memory controller configured to provide data stored in the memory array to the host for further processing by a processor or other component of the host. The memory controller can also be configured to receive data from the host for storage in the memory array. In some embodiments, the memory array can be a plurality of volatile memory cells organized in rows and columns, such as in a DRAM or static random access memory (SRAM). In other embodiments, the memory array can be a plurality of non-volatile memory cells or a mix of volatile and non-volatile memory cells.

[0013] An apparatus according to at least one other embodiment includes a host device having a memory controller configured to communicate with a memory system to receive data stored in a memory array and / or store data in the memory array. The host device can be, for example, a user equipment (UE) device such as a cellular phone, a tablet computing device, a personal computer, a server, a smart watch, or an Internet of Things (IoT) device.

[0014] In one aspect of the disclosure, a method for partial row refresh in a memory device includes obtaining, by a memory controller from a host device over a channel, partial row refresh information associated with a first row in a memory array, and refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information.

[0015] In an additional aspect of the disclosure, an apparatus includes a memory controller coupled to a memory array by a data bus and configured to access data stored in the memory array over the data bus, the memory controller configured to be coupled to a host device over a channel. The memory controller is configured to perform operations including obtaining, from the host device over the data channel, partial row refresh information associated with a first row in the memory array, and refreshing a portion of the first row in the memory array based on the partial row refresh information. For example, the memory controller can be a processor, controller, or other logic circuitry in the host. The processor can alternatively be a controller embedded in the memory device.

[0016] In an additional aspect of the disclosure, an apparatus includes means for obtaining, by a memory controller from a host device over a channel, partial row refresh information associated with a first row in a memory array, and means for refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information.

[0017] In one aspect of the disclosure, a method for partial row refresh in a memory device includes saving, by at least one processor of a memory controller of a host device coupled to a memory system over a channel, data to a first portion of a first row in a memory array of the memory system by the memory controller, determining, by the at least one processor, partial row refresh information for the first row based on the saving of data to the first portion of the first row, and copying, by the at least one processor, the partial row refresh information to the memory system by the memory controller.

[0018] In an additional aspect of the disclosure, an apparatus includes at least one processor; and a memory controller coupled to the at least one processor and a memory system by a channel and configured to communicate with the memory system over the channel. The at least one processor is configured to perform operations including saving, by the memory controller, data to a first portion of a first row in a memory array of the memory system; determining, based on the saving of data to the first portion of the first row, partial row refresh information for the first row; and copying, by the memory controller, the partial row refresh information to the memory system. For example, the memory controller can be a processor, controller, or other logic circuit in a host. The processor can alternatively be a controller embedded in a memory device.

[0019] In an additional aspect of the disclosure, an apparatus includes means for saving, by at least one processor of a memory controller of a host device coupled to a memory system by a channel, data to a first portion of a first row in a memory array of the memory system by the memory controller; means for determining, by the at least one processor, based on the saving of data to the first portion of the first row, partial row refresh information for the first row; and means for copying, by the at least one processor, the partial row refresh information to the memory system by the memory controller.

[0020] In an additional aspect of the disclosure, an apparatus, such as a wireless device, includes at least one processor and memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory system through a memory controller coupled to a channel that couples the processor to the memory system. The processor can be a processor, controller, or other logic circuit in a host.

[0021] In an additional aspect of the disclosure, a non-transitory computer- readable medium stores instructions that, when executed by a processor, cause the processor to perform operations described herein with respect to aspects of the disclosure.

[0022] The memory system in the present disclosure can be embedded within a processor on a semiconductor die or be part of a different semiconductor die. The memory system can be of various types. For example, the memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash or NOR flash, etc.

[0023] The methods and apparatus are presented in this disclosure as non-limiting examples of low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, LPDDR memory operates according to an LPDDR specification promulgated by the Joint Electron Device Engineering Council (JEDEC). One such LPDDR specification can be LPDDR5. Another such LPDDR specification can be LPDDR6.

[0024] Other aspects, features, and details will become apparent to those of ordinary skill in the art, upon reviewing the following description in conjunction with the accompanying drawings. While features can be discussed relative to certain aspects and figures below, various aspects can include one or more of the advantageous features discussed herein. In other words, while one or more aspects can be discussed with respect to certain features, one or more of those features can be utilized with any other aspect. Similarly, while aspects can be discussed below as devices, systems, or methods, aspects can be implemented in various devices, systems, or methods.

[0025] The method can be embedded in a computer readable medium as computer program code including instructions for causing a processor to perform the steps of the method. In some embodiments, the processor can be part of a mobile device that includes a first network adapter configured to transmit data, such as recorded images or video or streaming data, over a first network connection of a plurality of network connections. The processor can be coupled to the first network adapter and a memory for storing data to support processing and communication operations performed by the processor. The network adapter can support communication over a wireless communication network, such as a 5G NR communication network. The processor can cause transmission of data stored in the memory over the wireless communication network.

[0026] The foregoing has outlined rather broadly the features and technical advantages of examples according to the disclosure in order that the detailed description that follows can be better understood. Additional features and advantages will be described hereinafter. The disclosed concepts and specific examples can be readily utilized as bases upon which the other structures can be designed and constructed for performing the same purposes of the disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The particular implementations shown and described herein are shown as examples of the structures being pointed out but are not limiting as to the scope of the disclosure. The characteristics of the concepts disclosed herein, both their organization and their method of operation, together with associated advantages will be better understood from the following description when considered in connection with the accompanying drawings. Each of the figures is provided for the purpose of illustration and description, and is not intended as a definition of the limits of the claims.

[0027] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, aspects and / or implementations may be via integrated chip implementations and other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically point to use cases or applications, applicability to various types of the described innovations is possible. The scope of implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily involve multiple components (e.g., hardware components, including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.) for analog and digital purposes. The innovations described herein are intended to be implemented in a variety of devices, chip-level components, systems, distributed arrangements, end-user equipment, etc., with different sizes, shapes, and constructions. Attached Figure Description

[0028] A further understanding of the nature and advantages of this disclosure can be achieved by referring to the following figures. In the figures, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numerals and a second reference numeral for differentiation between similar components. If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0029] Figure 1 A block diagram of an example computing system comprising a host, a memory system, and a channel coupling the host and the memory system, according to one or more aspects of this disclosure, is shown.

[0030] Figure 2 A block diagram of an example computing system comprising a host, a memory system, and a channel coupling the host and the memory system, according to one or more aspects of this disclosure, is shown.

[0031] Figure 3A and Figure 3BWaveforms illustrating data transfer through an example channel in a read operation in accordance with certain aspects of the present disclosure are shown.

[0032] Figure 4A and Figure 4B Waveforms illustrating data transfer through an example channel in a read operation in accordance with certain aspects of the present disclosure are shown.

[0033] Figure 5A is a block diagram illustrating aspects of a system supporting partial row refresh in accordance with some embodiments of the present disclosure.

[0034] Figure 5B is a block diagram of a sleep manager supporting partial row refresh in accordance with some embodiments of the present disclosure.

[0035] Figure 5C is a chart of example values of partial row refresh information in accordance with some embodiments of the present disclosure.

[0036] Figure 5D is a block diagram of a refresh unit supporting partial row refresh in accordance with some embodiments of the present disclosure.

[0037] Figure 5E is a block diagram of a partial row refresh operation on a memory bank in accordance with some embodiments of the present disclosure.

[0038] Figure 6 is an example flow diagram illustrating performance of partial row refresh in accordance with some embodiments of the present disclosure.

[0039] Figure 7 is a flow diagram illustrating a memory system operating to perform a partial row refresh operation in accordance with some embodiments of the present disclosure.

[0040] Figure 8 is a flow diagram illustrating a host device operating a memory system to perform a partial row refresh operation in accordance with some embodiments of the present disclosure.

[0041] The same reference numbers and designations in different drawings represent the same elements. DETAILED DESCRIPTION

[0042] The detailed description set forth below, in connection with the appended drawings and embodiments described herinin, is intended as a description of various configurations and is not intended to limit the scope of the disclosure. Rather, the detailed description includes specific details for the purpose of providing a thorough understanding of the inventive subject matter. It will be apparent to those skilled in the art, from this detailed description, that numerous

[0043] The present disclosure provides systems, apparatuses, methods, and computer-readable media that support data processing, including techniques for partial row refresh techniques that allow refresh operations to maintain information stored in portions of rows of memory cells of a memory system. The partial row refresh techniques can be performed by activating only portions of a row that include stored data to reduce power consumption and increase the lifetime of the memory system through refresh operations. In different embodiments, the portions of a row to be refreshed can be determined based on partial row refresh information. For example, such information can be determined based on the amount of data stored in each respective row.

[0044] Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages or benefits. In some aspects, the present disclosure provides reduced power consumption by refreshing portions of a row based on the amount of data stored in the row. As less than an entire row can be refreshed when the entire row is not used for storage of information, power consumption can be reduced by up to and over 2 mAh per 15 minute sleep period depending on environmental factors such as temperature. Further, activating a sense amplifier less frequently to refresh blocks of rows of a memory array can increase the lifetime of the memory array.

[0045] Figure 1 An example memory device that can incorporate aspects of the present disclosure, including partial row refresh based on partial row refresh information, is shown in FIG. 1. Figure 1 An apparatus 100 incorporating a host 110, a memory 150, and a channel 190 coupling the host 110 and the memory 150 is illustrated. The apparatus 100 can be, for example, a device in a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop computer, a cellular phone, a vehicle, etc.), an Internet of Things device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a standalone digital camera or digital video camera, a camera-equipped wireless communication device handset such as a mobile telephone, a cellular or satellite radio telephone, a personal digital assistant (PDA), a panel or tablet computer, a gaming device, a computing device such as a webcam, a video surveillance camera, or other device with digital imaging or video capability), and / or a multimedia system (e.g., a television, a compact disc player, a streaming device).

[0046] The host 110 can include at least one processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a multimedia engine, and / or a neural processing unit (NPU). The host 110 can be configured to couple and communicate with the memories 150 (e.g., memories 150-1 to 150-4) via channels 190 (e.g., channels 190-1 to 190-4) to perform a computing function, such as one of data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, and / or the like. For example, the memories 150-1 to 150-4 can store instructions or data for the host to perform the computing function.

[0047] The host 110 can include a memory controller 130, which can include controller PHY modules 134-1 to 134-4. Each of the controller PHY modules 134-1 to 134-4 can be coupled to a respective one of the memories 150-1 to 150-4 via a respective one of the channels 190-1 to 190-4. For ease of reference, read and write are referenced from the perspective of the host 110. For example, in a read operation, the host 110 can receive stored data from one or more of the memories 150-1 to 150-4 via one or more of the channels 190-1 to 190-4. In a write operation, the host 110 can provide data to be written into one or more of the memories 150-1 to 150-4 for storage via one or more of the channels 190-1 to 190-4. The memory controller 130 can be configured to control various aspects of the communication to and from the memories 150-1 to 150-4, such as a logical layer. The controller PHY modules 134-1 to 134-4 can be configured to control electrical properties (e.g., voltage levels, phases, delays, frequencies, and / or the like) of signals provided or received on the channels 190-1 to 190-4, respectively.

[0048] In some examples, the memories 150-1 to 150-4 can be LPDDR DRAMs (e.g., LPDDR5, LPDDR6). In some examples, the memories 150-1 to 150-4 can be different kinds of memories, such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM, respectively. The host 110, the memories 150-1 to 150-4, and / or the channels 190-1 to 190-4 can operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of the channels 190-1 to 190-4 can include 16 data bits (e.g., 16 DQs). In some examples, each of the channels 190-1 to 190-4 can operate on 32 data bits (e.g., 32 DQs). In some examples, the channels 190-1 to 190-4 can operate according to a JEDEC standard (e.g., a DDR standard, such as DDR4, DDR5, LPDDR4, LPDDR5, LPDDR6, and / or the like). Figure 1In particular embodiments, four channels are shown, however, the device 100 can include more or fewer channels, such as 8 or 16 channels.

[0049] In Figure 2 Additional details are shown in FIG. 1 illustrating an aspect of an embodiment of the device 100 for providing access to a memory system, such as one of the memories 150-1 to 150-4 including logic and control circuitry. Figure 2 A configuration of the host 110, memory system 250, and channel 190 in accordance with some aspects of the present disclosure is illustrated. The channel 190 between the host 110 and the memory system 250 can include a plurality of connections, some of which carry data (e.g., user data or application data) and some of which carry non-data (e.g., address and other signaling information). For example, the non-data connections in the channel 190 can include a data clock (e.g., WCK) used when providing data on a per-byte basis to the respective memory system 250 and a read data strobe (e.g., RDQS) used when receiving data from the respective memory system 250. The channel 190 can also include data mask (e.g., DM, sometimes referred to as data mask inversion DMI) signaling for masking certain portions of data in write operations. The channel 190 can also include command and address (e.g., CA[0:n]) and associated CA clock to provide commands (e.g., read or write commands) to the memory system 250.

[0050] The host 110 can include at least one processor 120, which can include a CPU 122, a GPU 123, and / or a NPU 124. The host 110 can also include a memory controller 130 having a controller PHY module 134. The memory controller 130 can be coupled to the at least one processor 120 via a bus system 115 to perform various computing functions. The term “bus system” can provide that elements coupled to the “bus system” can exchange information among them, directly or indirectly. In different embodiments, the “bus system” can encompass a plurality of physical connections and intermediate stages such as buffers, latches, registers, etc. Modules can be implemented in hardware, software, or a combination of hardware and software.

[0051] Memory controller 130 can transmit and / or receive data blocks to other modules, such as at least one processor 120 and / or memory system 250. Memory system 250 can include a memory controller 180 with a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, delays, frequencies, etc.) to provide or receive signals on connections of channel 190. For example, memory I / O module 160 can be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. In Figure 3A , Figure 3B , Figure 4A and Figure 4B Example techniques for communicating on channel 190 between memory I / O module 160 and memory controller 130 are shown in the examples. Memory controller 180 can also include data registers 182A-182K configured to store data transmitted between host 110 and memory array 175 and / or store configuration settings or other data.

[0052] Memory system 250 can also include memory array 175, which can include a plurality of memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, flash memory cells) that store values. Host 110 can read data stored in memory array 175 and write data into memory array 175 via channel 190 and memory I / O module 160. Memory array 175 can be divided into a plurality of memory banks, where each memory bank is organized into a plurality of pages.

[0053] Application or user data can be processed by processor 120 and instruct memory controller 130 to store such data and / or retrieve such data from memory system 250. For example, data can be generated during execution of an application, such as a spreadsheet program that computes values based on other data. As another example, data can be generated during execution of an application by receiving user input to, for example, a spreadsheet program. As another example, data can be generated during execution of a game application that generates information about a representation of a scene rendered by a three-dimensional (3-D) application.

[0054] The host 110 is coupled to the memory system 250 via a channel 190, which is illustrated for data bytes, DQ[0:7]. The channel 190 and signaling between the host 110 and the memory system 250 can be implemented in accordance with JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As illustrated, the channel 190 includes signal connections for DQ, read data strobe (RDQS), data mask (DM), data clock (WCK), command and address (CA[0:n]), and command and address clock (CK). The host 110 can use the read data strobe RDQS to strobe (e.g., clock) data in a read operation to receive data on DQ. The memory system 250 can use the data mask DM to mask certain portions of data from being written in a write operation. The memory system 250 can use the data clock WCK to sample data on DQ for a write operation. The memory system 250 can use the command and address clock CK to clock (e.g., receive) CA. The signal connections for each of the signaling can include pins at the host 110, pins at the memory system 250, and one or more conductive traces that electrically connect the pins. The one or more conductive traces can be part of a single integrated circuit (IC) on a silicon chip that includes the processor 120 and the memory system 250, can be part of a package-on-package (PoP) that includes the processor 120 and the memory system 250, or can be part of a printed circuit board (PCB) that is coupled to both the processor 120 and the memory system 250.

[0055] The memory system 250 can include a memory I / O module 160 (e.g., a PHY layer) that is configured to control electrical properties (e.g., voltage levels, phases, delays, frequencies, etc.) to provide or receive signals on the channel 190. For example, the memory I / O module 160 can be configured to capture (e.g., sample) data, commands, and addresses from the host 110 via the channel 190 and output data to the host 110 via the channel 190. Information sent across the channel 190 can be stored in registers in the memory I / O module 160 of the memory system 250 as a temporary or short-term storage location prior to longer-term storage in the memory array 175.

[0056] The memory system 250 can also include a memory array 175 that can include a plurality of memory cells (e.g., DRAM memory cells) that store information. The host 110 can read data stored in the memory array 175 and write data into the memory array 175 via the channel 190. In addition, the memory array 175 can be configured to store metadata associated with stored data, such as ECC (e.g., system or array ECC).

[0057] Operations for storing information and retrieving information from the memory array 175 according to some embodiments of the disclosure can be performed by signals on separate lines of the control channel 190. Reference is made to Figure 3A and Figure 3B Example embodiments of signaling for a write operation are shown and described. Reference is made to Figure 4A and Figure 4B Example embodiments of signaling for a read operation are shown and described.

[0058] Figure 3A and Figure 3B Waveforms illustrating data transfer through example channels in a write operation according to certain aspects of the disclosure are illustrated. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At TO (rising edge of CK_t and falling edge of CK_c), a CAS command for a write operation to the memory system 250 can be provided by the host 110. At Tl, the host 110 can provide a write command to the memory system 250.

[0059] After a period of write latency (WL), the host 110 can toggle the data clock WCK0_t and WCK0_c to provide a clock for receiving data for a write on the DQ signal connections to the memory system 250. At Tc0 to Tc2, the memory system 250 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections and clocked by the data clock WCK0_t and WCK0_c. The memory system 250 can serially receive a 16-bit data mask DM0 (e.g., based on the data clock WCK0_t and WCK0_c) to mask certain portions of the received data from the write operation. In some examples, the 16 bytes of data and the 16-bit data mask DM0 can be received by the memory system 250, where each bit of the data mask DM0 masks a corresponding byte of the received data. At Tc0 to Tc2, the RDQS_t signal connection can be in a Hi-Z condition. In a read operation, the RDQS_t signal connection can be configured to provide a read data strobe (RDQS) from the memory system 250 to the host 110.

[0060] Figure 4A and Figure 4BWaveforms illustrating data transfer through example channels in a read operation according to certain aspects of this disclosure are illustrated. Command and address clock CK can be a differential signal with CK_t and CK_c signal connections. Data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. Read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. Data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At TO (rising edge of CK_t and falling edge of CK_c), a CAS command for a read operation to memory system 250 can be provided by host 110. At Tl, host 110 can provide a read command to memory system 250.

[0061] After a period of read latency (RL), memory system 250 can toggle read data strobe RDQS to provide a clock for host 110 to receive data for the read operation on DQ signal connections. At TcO to Tc2, host 110 can serially receive 16 bytes of data on each of DQ[0:7] signal connections and clocked by read data strobe RDQS_t and RDQS_c. Thus, in this example, 16 bytes of data are received by host 110.

[0062] At TcO to Tc2, data mask DM0 signal connection can be in a Hi-Z condition. In a write operation, DM signal connection can be configured to provide data mask from host 110 to memory system 250, which can be clocked by WCK0_t and WCK0_c.

[0063] Figure 5A An example system supporting partial row refresh operations for memory array 175 of memory system 250 is shown in FIG. 7. Figure 5Ais a block diagram illustrating aspects of a system that supports partial row refresh operations for a memory array in accordance with some embodiments of the present disclosure. The memory array 175 of the memory system 250 can be organized with a plurality of rows, where each row has a corresponding address. Each of the rows can have a plurality of memory cells or blocks, where each memory cell is assigned to a separate column. The memory controller 180 can be configured to perform refresh operations on the memory array 175 on a row-by-row basis. Conventionally, this includes cycling through each of the plurality of rows and refreshing the information stored in that row. As one particular example, in a partial array self-refresh mode, when the host 110 enters a sleep state, the memory controller 180 can be configured to refresh an entire bank and / or an entire row of the memory array 175. Such a refresh can be performed by activating the sense amplifiers connected to each column of the row of the memory array 175 to refresh the blocks corresponding to that row and that column. For example, the sense amplifiers corresponding to each column of the row of the memory array 175 can be activated to sense and / or read the blocks of the row that are in the columns corresponding to the sense amplifiers. The memory array 175 can not be completely filled with data. In some cases, each row of the memory array 175 can not be completely filled with data. For example, one or more rows of the memory array 175 can include one or more blocks that are not filled with data. Thus, refreshing the entirety of each row in a partial array self-refresh mode can result in unnecessarily refreshing portions of the row that do not store data, wasting power. In particular, activating the sense amplifiers corresponding to blocks of the row of the memory array 175 that do not store data can waste power.

[0064] The memory controller 180 can include a refresh unit 502 configured to perform at least some refresh operations on the memory array 175. For example, the refresh unit 502 can be configured to perform a partial row refresh within the memory array 175 based on partial row refresh information. The partial row refresh information can be stored in the refresh unit 502. For example, address information including the partial row refresh information can be stored by the refresh unit 502 and can be used to determine a portion of a row to refresh, such as twenty-five percent, fifty percent, seventy-five percent, one hundred percent, or another amount of a particular row indicated by the address information. For example, such a refresh operation can be performed from left to right, such that if the partial row refresh information indicates that twenty-five percent of a row should be refreshed, the first twenty-five percent of the row from left to right can be refreshed. Other patterns of refreshing a row based on the partial row refresh information can be used. In some embodiments, the partial row refresh information can be stored elsewhere by the memory controller 180, such as in a cache of the memory controller 180 or in the memory array 175, and can be accessed by the refresh unit 502. The partial row refresh information can be populated by obtaining such information from the host 110 and / or accessing a memory location corresponding to the partial row refresh information.

[0065] CPU 122 of host 110 can execute a sleep manager that tracks partial row refresh information and row address information, such as Figure 5B sleep manager 510. Figure 5B is a block diagram illustrating an example sleep manager 510 executed by a processor of a host device to support partial row refresh operations, in accordance with some embodiments. In some embodiments, sleep manager 510 can be executed as a kernel-level process in an operating system executing on CPU 122. In some embodiments, sleep manager 510 can be executed in firmware on hardware circuitry within host 110.

[0066] Row address information 514, including metadata for one or more rows of memory array 175, can be stored by sleep manager 510. For example, address information 514 can include partial row refresh information 512 for each row. Thus, address information 514 stored by sleep manager 510 for each row of memory array 175 can include, for each respective row, an address and respective partial row refresh information 512 indicating an amount of each row used to store data.

[0067] In some embodiments, partial row refresh information 512 can include two bits of row address information 514. In Figure 5CAn example table is shown in Table 520, which shows example values for the portion row information 512 for the example portion of the row to be refreshed corresponding to the row. Example values for the first bit are shown in the first column 522, and example values for the second bit are shown in the second column 524. An example percentage of the row that is filled with data to be refreshed is shown in the third column 526. For example, if the value of the first bit of the portion row refresh information 512 for a row is 0 and the value of the second bit of the portion row refresh information 512 for the row is 0, then the percentage of the row that is filled with data can be less than or equal to twenty-five percent. As another example, if the value of the first bit of the portion row refresh information 512 for a row is 0 and the value of the second bit of the portion row refresh information 512 for the row is 1, then the percentage of the row that is filled with data can be greater than twenty-five percent and less than or equal to fifty percent. As another example, if the value of the first bit of the portion row refresh information 512 for a row is 1 and the value of the second bit of the portion row refresh information 512 for the row is 0, then the percentage of the row that is filled with data can be greater than fifty percent but less than seventy-five percent. As another example, if the value of the first bit of the portion row refresh information 512 for a row is 1 and the value of the second bit of the portion row refresh information 512 for the row is 1, then the percentage of the row that is filled with data can be greater than seventy-five percent and less than or equal to one hundred percent. In some embodiments, the portion row refresh information 512 can include less than or more than two bits corresponding to less than or more than four row usage percentages. In some embodiments, other indications of row usage, such as values corresponding to each block of the row used to store data, can be included in the portion row information 512.

[0068] The sleep manager 510 can generate the portion row refresh information 512 and / or the row address information 514 when storing data in the memory array 175. For example, as data is stored in a row, the sleep manager 510 can generate the address information 514 and / or the portion row information 512 for the row based on the amount of data stored in the row.

[0069] For example, the CPU 122 can be configured to detect a trigger event for activating the partial row refresh memory mode. The trigger event can be based on a counter determining that the host 110 has been in a low power mode (e.g., sleep mode) for a predetermined amount of time. The trigger event can be based on the host 110 being in a location that indicates that the host 110 can be in a sleep mode for an extended period of time. For example, when the host 110 is an automobile, such a location can be a parking lot at an airport. The trigger event can be a user input in which a user indicates that the host 110 should enter a sleep mode, such as by pressing a power button.

[0070] As an example, if host 110 is integrated into a vehicle, CPU 122 can determine from location data that host 110 is located in a parking lot or car rental area, indicating that host 110 will not be used for an extended period of time. Therefore, once CPU 122 determines that host 110 is in a parking lot or car rental area, CPU 122 can store data in memory array 175, generate partial row refresh information 512 and / or row address information 514, send partial row refresh information 512 and / or row address information 514 to memory system 250, and put memory system 250 into partial row refresh memory mode.

[0071] Figure 5D An example refresh unit 540 (such as...) is shown in the figure. Figure 5A A block diagram of refresh unit 502 is provided. Refresh unit 540 may include partial row self-refresh circuitry 542. Partial row self-refresh circuitry 542 may be configured to receive partial row refresh information (such as address information including partial row refresh information 544) and decode the partial row refresh information to activate a refresh for a portion of the row indicated by the partial row refresh information. In some embodiments, the partial row refresh information may be received directly from CPU 122 by refresh unit 540, or it may be stored by memory controller 180 and accessed by partial row refresh circuitry 542. Partial row refresh circuitry 542 may activate one or more sense amplifiers 546 corresponding to a row of memory array 175 based on the partial row refresh information decoded by partial row refresh circuitry 542. For example, if the partial row refresh information of a particular row indicates that up to 25 percent of the row is storing data, partial row refresh circuitry 542 may activate sense amplifiers 546 corresponding to the first 25 percent of the row (such as the first 25 percent of the row's blocks or columns) to refresh the corresponding block of the row.

[0072] For example, such as Figure 5E As shown, the refresh unit 502 can perform partial row refresh operations on the rows of the memory array 175. Figure 5EAn example block diagram 560 of a partial row refresh operation performed on memory array 175 is shown. Memory array 175 can include a first array including eight memory banks. The eight memory banks can include a first bank 562A, a second bank 562B, and an eighth bank 562C. First bank 562A can include a first section 564. First section 564 can include a plurality of rows. Each row of the plurality of rows can include a respective plurality of blocks. Different rows can have different numbers of empty blocks and different numbers of blocks storing data, such as different numbers of valid blocks. The shaded blocks of each row shown in first section 564 can be blocks storing data or valid blocks. In some embodiments, data can be stored in the blocks of a row from left to right. Thus, if twenty-five percent of the blocks of a row store data, the twenty-five percent of the blocks of the row storing data can be the first twenty-five percent of the blocks of the row storing data from left to right.

[0073] An example row 566 of first section 564 can include two blocks storing data and six blocks not storing data. Thus, for example, Figure 5B The sleep manager 510 shown executed by CPU 122 can generate address information including partial row refresh information for example row 566 indicating that twenty-five percent of example row 566 is storing data after data is stored in the row. Sleep manager 510 can send the address information including the partial row refresh information to memory controller 180. In some embodiments, memory controller 180 can store and / or provide the address information including the partial row refresh information to refresh unit 502. Refresh unit 502 of memory controller 180, which can correspond to refresh unit 540 of FIG. 5, Figure 5D may decode the address information to determine that twenty-five percent of row 566 is storing data. Refresh unit 502 can activate sense amplifiers (shown as SAs in Figure 5E ) corresponding to the first twenty-five percent of blocks of example row 566, such as two sense amplifiers corresponding to the first two blocks of example row 566, to refresh the blocks storing data based on the partial row refresh information. The remaining six sense amplifiers corresponding to the next six blocks of example row 566 can remain deactivated using less power than if all of the sense amplifiers for example row 566 were activated. Similar refresh operations can be performed on other rows, sections, and / or banks of memory array 175 based on partial row refresh information corresponding to the rows. In some embodiments, refresh unit 502 can refresh banks and / or rows of banks in a circular sequence.

[0074] Memory system 250 can be configured for partial row refresh operations by CPU 122 based on a power state of host device 110. Figure 6is an example flowchart illustrating the execution of a partial row refresh according to some embodiments of the present disclosure. The method 600 begins at block 602 with receiving a request by a sleep manager of a CPU. At block 604, the sleep manager determines whether the request is a sleep entry request or another request. If the request is not a sleep entry request, the CPU can remain in an active state at block 606 and can continue processing the request at block 602.

[0075] If it is determined at block 604 that the request is a sleep entry request, the sleep manager can notify one or more subsystems of the sleep entry request at block 608 and can save one or more contexts to memory. For example, the sleep manager can save data, such as context data for one or more applications or system processes, to one or more blocks of one or more rows of a memory array of a memory system.

[0076] At block 610, the sleep manager can calculate optimized row addresses based on a density of valid data in each row. For example, such a calculation can include determining an amount of data stored in each row and generating partial row refresh information based on the amount of data stored in each row. The partial row refresh information for each respective row can be appended to the address of each respective row, such as by adding one or more bits of the partial row refresh information to the beginning or end of the address of each respective row. Thus, in addition to the address of the row, the calculated row address can include the partial row refresh information corresponding to the row address.

[0077] At block 612, the sleep manager can copy address information, such as optimized row address information including partial row refresh information, to a refresh unit of the memory system. The memory system can be a DDR memory system and the refresh unit can be a DDR refresh unit. In some embodiments, the address information can be sent to and stored by a memory controller of the memory system for access by the refresh unit.

[0078] At block 614, the host device can enter a sleep state. For example, the CPU of the host device can enter a sleep state. When entering the sleep state, an instruction can be communicated to the memory controller of the memory system to enter a refresh mode applicable during the sleep mode, such as a partial array self-refresh mode including a partial row refresh operation. For example, a self-refresh command can be communicated to the memory system. In some embodiments, the instruction can include an indication that a partial row refresh should be performed based on the partial row refresh information in the address information copied at block 612. In some embodiments, the instruction can be specific to a partial row self-refresh mode. When in the partial row self-refresh mode, the memory controller issues a refresh command to the memory array of the memory system at block 616 to maintain the context of the memory (e.g., context data). The refresh command can be from the memory controller on the host device or the memory controller on the memory system. The refresh command causes the refresh unit to decode the address information including the partial row refresh information at block 618. At block 620, the portion of the row is refreshed based on the decoded address information, such as based on the partial row refresh information. As discussed herein, a portion or partial row of a row can be less than or equal to an entire row.

[0079] Figure 7is a flowchart illustrating a partial refresh operation performed by a memory system according to some embodiments of the present disclosure. For example, the method 700 can be performed by a memory controller of a memory system. The memory controller can be coupled to a memory array by a data bus and configured to access data stored in the memory array through the data bus. The memory array can be a low power double data rate (LPDDR) memory array. The memory controller can be configured to be coupled to a host device through a channel and perform the operations of the method 700. The method 700 begins at block 702 with obtaining, by a memory controller of a memory system, from a host device (e.g., by receiving) partial row refresh information associated with a first row of a memory array. The partial row refresh information can be received by the memory controller 180 of the memory system 250 from the memory controller 130 of the host 110 through the channel 190. The partial row refresh information can be received as part of a command sent on a command and address CA bus of the channel 190. The partial row refresh information can alternatively be received as part of data sent on a DQ bus of the channel 190. For example, the partial row refresh information can include an indication of a percentage of the first row to be refreshed. In some embodiments, the partial row refresh information can include a two-bit value. In some embodiments, the partial row refresh information can include an indication to refresh twenty-five percent of the first row, an indication to refresh fifty percent of the first row, an indication to refresh seventy-five percent of the first row, or an indication to refresh one hundred percent of the first row. For example, the partial row refresh information can be included in address information associated with the first row. For example, the address information for the first row can include the partial row refresh information for the first row and an address for the first row. In some embodiments, at block 702, the partial row refresh information (such as the partial row refresh information included in the address information) can be received for multiple rows of the memory array.

[0080] At block 704, the memory controller receives an indication to enter a self-refresh mode. For example, the indication to enter the self-refresh mode can be an indication that the host device is entering a sleep mode. The indication can cause the memory controller 180 to assume responsibility for refreshing the memory array 175 without further input from the host 110 until a new instruction to change the refresh mode is received. The indication to enter the self-refresh mode can be in the format of an instruction for the memory system 250 to enter a particular sleep mode that allows the host 110 to enter the sleep mode.

[0081] In some embodiments, the operations of block 702 and block 704 can be performed by a single operation. For example, a command for an initiated partial row self-refresh operation can include the partial row refresh information. As another example, the indication to enter the self-refresh mode can include the partial row refresh information.

[0082] At block 706, the memory controller refreshes a portion of the first row in the memory array based on the partial row refresh information. For example, the memory controller can determine a portion of the first row to be refreshed based on the partial row refresh information. For example, determining a portion of the first row to be refreshed based on the partial row refresh information can include decoding the partial row refresh information. Then, based on the partial row refresh information, such as based on the determined portion of the first row to be refreshed, the memory controller can activate one or more sense amplifiers corresponding to one or more blocks of the first row. For example, sense amplifiers corresponding to a particular percentage of blocks of a row indicated by the partial row refresh information can be activated to refresh those blocks. The refresh can be performed by a refresh unit 502 (e.g., refresh unit 502 that generates control signals (e.g., row select and enable signals)) of the logic circuit 162 in the memory controller 180. In some embodiments, portions of multiple respective rows of the memory array can be refreshed based on receiving respective partial row refresh information for the respective rows. Figure 5A

[0083] The host device can configure the memory system for performing self-refresh operations. Figure 7 Figure 8 is a flow diagram illustrating a host device operating a memory system to perform a partial row refresh operation in accordance with one or more aspects of the present disclosure. The method 800 begins at block 802 with receiving, by a host processor, an indication to enter a sleep mode. The indication can be triggered by information such as a location of the host device, a processing queue of the host device, a user input specifying a low power mode of the host device, and / or no user input to the host device for a predetermined period of time. Although some examples of a sleep mode are described, the sleep mode can refer to any lower power operating state during which the memory system will not be accessed by the host device for a period of time.

[0084] At block 804, the host processor can save data to a first portion of a first row in a memory array of the memory system. The first portion of the first row can be the entire first row, less than the entire first row. In some embodiments, the data can be context data. The context data can include application data, user data, register values from a processor core, etc. that indicate a current state of processing by the host device.

[0085] ​​At block 806, the host processor determines partial row refresh information for the first row. In some embodiments, partial row refresh information can be determined for multiple rows. For example, such a determination can be performed in response to saving of data to a first portion of the first row. For example, after saving data to the first portion of the first row, the host processor can determine an address of the first row and an amount of stored data of the first row, such as a percentage of stored data of the first row. The processor can generate the partial row refresh information based on the determination of the amount of the first row used to store data. The partial row refresh information can be included in the address information of the first row. For example, one or more bits of partial row refresh data can be added at the beginning or end of the address of the row. Thus, determining the partial row refresh information can include determining address information of the first row based on a number of blocks in the first portion of the first row for which data is saved.

[0086] At block 808, the host processor can copy the partial row refresh information to the memory system. For example, the address information including the partial row refresh information for the first row can be copied to the memory system. The copying can include storing the partial row refresh information at a particular location in the memory or appending the partial row refresh information as a data value to a command transmitted to the memory system, such as a command to update a configuration register or change a mode of the memory system.

[0087] At block 810, the host processor can enter a sleep mode. While in the sleep mode, the host processor can rely on the memory system to perform self-refresh operations without input from the host processor. While in the sleep mode, power consumed by the host device is reduced by lowering the operating system of the host processor to a lower voltage, lower frequency, a deeper sleep state, and / or power gating portions or all of the host processor. The host processor can later receive a trigger to exit the sleep mode. When exiting the sleep mode, the host processor can send a command to the memory system to exit the partial row self-refresh mode of operation for the host processor to resume handling refresh operations.

[0088] A wireless communication device can include as at least Figure 1 and Figure 2A memory system is illustrated and configured to receive and output data from a memory array and refresh portions of rows of the memory array based on partial row refresh information. A memory system according to any of the aspects disclosed herein can be provided or integrated into any processor-based device. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computer (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a transportation component, or an avionics system.

[0089] In one or more aspects, techniques for memory storage and retrieval can include additional aspects, such as any single aspect or any combination of aspects described in the following or in connection with one or more other processes or devices described elsewhere herein. In a first aspect, supporting data operations can include an apparatus configured to perform operations comprising: obtaining, by a first channel, partial row refresh information associated with a first row in a memory array from a host device; and refreshing a portion of the first row in the memory array based on the partial row refresh information.

[0090] Additionally, the apparatus can perform or operate according to one or more aspects as described below. In some implementations, the apparatus includes a wireless device, such as a UE. In some implementations, the apparatus includes a remote server, such as a cloud-based computing solution, that receives image data for processing to determine output image frames. In some implementations, the apparatus can include at least one processor and a memory coupled to the processor. The processor can be configured to perform the operations described herein with respect to the apparatus. In some other implementations, the apparatus can include a non-transitory computer-readable medium having program code recorded thereon and the program code can be capable of being executed by a computer to cause the computer to perform the operations described herein with reference to the apparatus. In some implementations, the apparatus can include one or more means configured to perform the operations described herein. In some implementations, a method of wireless communication can include one or more operations described herein with reference to the apparatus.

[0091] In a second aspect, in combination with the first aspect, the partial row refresh information includes an indication of a percentage of the first row to be refreshed.

[0092] In a third aspect, in combination with one or more of the first aspect or the second aspect, the indication of the percentage of the first row to be refreshed includes a two-bit value.

[0093] In a fourth aspect, in combination with one or more of the first through third aspects, the indication of the percentage of the first row to be refreshed includes one of an indication to refresh twenty-five percent of the first row, an indication to refresh fifty percent of the first row, an indication to refresh seventy-five percent of the first row, or an indication to refresh one hundred percent of the first row.

[0094] In a fifth aspect, in combination with one or more of the first through fourth aspects, the apparatus is further configured to perform operations comprising receiving an indication from the host device to enter a self-refresh mode, wherein after receiving the indication to enter the self-refresh mode, the memory controller performs the refresh of the portion of the first row in the memory array based on the partial row refresh information.

[0095] In a sixth aspect, in combination with one or more of the first through fifth aspects, receiving the indication to enter the self-refresh mode includes receiving an indication that the host device is entering a sleep mode.

[0096] In a seventh aspect, in combination with one or more of the first through sixth aspects, the partial row refresh information is included in address information associated with the first row.

[0097] In an eighth aspect, in combination with one or more of the first through seventh aspects, refreshing, by the memory controller, the portion of the first row in the memory array based on the partial row refresh information includes determining a portion of the first row to be refreshed based on the partial row refresh information, and activating one or more sense amplifiers corresponding to one or more blocks of the first row based on the portion of the first row to be refreshed.

[0098] In a ninth aspect, in combination with one or more of the first through eighth aspects, determining the portion of the first row to be refreshed includes decoding the partial row refresh information.

[0099] In a tenth aspect, in combination with one or more of the first through ninth aspects, the memory array includes a low power double data rate (LPDDR) memory array.

[0100] In an eleventh aspect, the apparatus can be configured to perform operations including saving, by a memory controller, data to a first portion of a first row in a memory array of a memory system, determining, based on the saving of the data to the first portion of the first row, partial row refresh information for the first row, and copying, by the memory controller, the partial row refresh information to the memory system.

[0101] In a twelfth aspect, in combination with the eleventh aspect, the apparatus can be further configured to perform operations including receiving an indication to enter a sleep mode, wherein saving the data is performed after receiving the indication to enter the sleep mode, sending, by the memory controller to the memory system, an indication to enter a self-refresh mode after receiving the indication to enter the sleep mode, and entering the sleep mode after copying the partial row refresh information to the memory system.

[0102] In a thirteenth aspect, in combination with one or more of the eleventh aspect through the twelfth aspect, determining the partial row refresh information includes determining address information for the first row based on a number of blocks in the first portion of the first row.

[0103] In a fourteenth aspect, in combination with one or more of the eleventh aspect through the thirteenth aspect, the partial row refresh information includes an indication of a percentage of the first row to be refreshed.

[0104] In a fifteenth aspect, in combination with one or more of the eleventh aspect through the fourteenth aspect, the memory controller is configured to communicate with a double data rate (DDR) memory system.

[0105] In the description of the embodiments of the present document, numerous specific details are set forth in order to provide a thorough understanding of the present document. As used herein, the term "coupled" means connected, either directly or indirectly, through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature is set forth in order to provide a thorough understanding of the present document. It will be apparent, however, to one skilled in the art, that these specific details can not be required to practice the teachings presented herein. In other instances, well-known circuits and devices are shown in block diagram form in order to avoid obscuring the present document.

[0106] Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing and other symbolic representations of operations on data bits within computer memories. In the present disclosure, procedures, logic blocks, processes and the like are conceived to be self-consistent sequences of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.

[0107] In the drawings, a single block can be described as performing one or more functions. The one or more functions performed by a block can be performed in a single component or across multiple components, and / or can be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Additionally, the example devices can include components other than those shown, including well-known components such as processors, memory, etc.

[0108] Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the present disclosure, discussions utilizing terms such as "accessing," "receiving," "transmitting," "using," "selecting," "determining," "normalizing," "multiplying," "averaging," "monitoring," "comparing," "applying," "updating," "measuring," "deriving," "setting," "generating," or the like, refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories, registers or other such information storage, transmission or display devices.

[0109] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (such as one smartphone, one camera controller, one processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some portions of the present disclosure. While the description and examples herein use the term "device" to describe various aspects of the present disclosure, the term "device" is not limited to a specific configuration, type, or number of objects. As used herein, an apparatus can include a device or a portion of a device for performing the described operations.

[0110] Certain components described as "means for accessing," "means for receiving," "means for transmitting," "means for using," "means for selecting," "means for determining," "means for normalizing," "means for multiplying," or other similar terminology referring to one or more operations on data (such as image data) can refer to processing circuitry (e.g., an application specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a central processing unit (CPU)) configured to perform the described function by hardware only, software only, or a combination of software and hardware configured by software.

[0111] Those skilled in the art will understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0112] The terms "coupled" and "connected," along with their derivatives, can be used. Figures 1-2 The described components, blocks, and modules include processors, electronic devices, hardware devices, electronic components, logical circuits, memories, software codes, firmware codes, etc., or any combination thereof. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, and / or functions, among other examples, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Furthermore, features discussed herein can be implemented via special-purpose processor circuitry, via executable instructions, or a combination thereof.

[0113] Those skilled in the art will appreciate that one or more blocks (or operations) described with reference to one or more of the drawings included with this specification can be combined with one or more blocks (or operations) described with reference to another drawing included with this specification. For example, one or more blocks (or operations) of FIG. 3 can be combined with one or more blocks (or operations) of Figure 1 or Figure 2 FIG. 1.

[0114] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Skilled artisans will also readily recognize the equality of a variety of means for performing the nubricative functions described herein with the nubricative elements as described above and set forth in the following claims. The application is thus to be understood in a manner that

[0115] The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, above. The described functionality can be implemented in a variety of different manners depending on the particular application and design constraints imposed on the overall system. The various components, blocks, modules, circuits, and processes described herein can be implemented in electronic hardware, computer software, or combinations of both.

[0116] The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein can be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor can be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of a

[0117] In one or more aspects, the functions described can be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by, or to control the operation of, data processing apparatus.

[0118] If implemented in software, the functions can be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of methods or algorithms can reside as one or any combination of sets of codes and instructions on a machine-readable medium and computer-readable medium, which can be incorporated in a computer program product.

[0119] Various modifications to the specific implementations described herein will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to some other implementations without departing from the spirit or scope of the disclosure. Thus, the claims are not intended to be limited to the specific implementations shown herein, but instead are to be accorded the full scope consistent with the language of the claims, the principles disclosed herein and the patentable concept preserved by the disclosure.

[0120] Additionally, those of ordinary skill in the art will readily recognize that the principles disclosed herein can be applied to any platform and that the description of specific implementations is merely for illustrative purposes. Accordingly, the claims are not intended to be limited to the specific implementations disclosed herein, but are to be accorded the full scope consistent with the language of the claims, the principles disclosed herein and the patentable concept preserved by the disclosure.

[0121] As used herein, the term "coupled to" in various forms thereof, as used herein, can mean that an element A is directly connected to element B, or that other elements can be connected in between element A and B (i.e., element A is indirectly connected to element B) to operate certain intended functions. In the context of electrical components, the term "coupled to" can also be used herein to mean that a wire, trace, or other conductive material is used to electrically connect element A and B (and any components electrically connected in between them). In some examples, the term "coupled to" means that electrical energy is transferred between element A and B to operate certain intended functions.

[0122] In some examples, the term "electrically connected" means having a current or being able to be configured to have a current flow between element A and B. For example, in addition to wires, traces, or other conductive materials and components, element A and B can be connected via resistors, transistors, or inductors. Further, for radio frequency functions, element A and B can be "electrically connected" via capacitors.

[0123] Some features described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Furthermore, while features can have been described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a subcombination or variation of a subcombination.

[0124] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such an order, nor that all illustrated operations be performed, to achieve desirable results. Further, the drawings can schematically depict one more example processes in the form of a flowchart. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously with, or between any illustrated operation. Under certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.

[0125] As used herein, including the claims, the term “or” as used in the listing of two or more items pertains to the inclusion of at least one of the listed items and is intended to be interpreted in the inclusive manner, such that, for example, a composition comprising components A, B, or C includes at least one of A, or B, or C, individually, or any combination thereof. Additionally, as used herein, including the claims, the term “or” as used in the listing of items in an “at least one of’ list means an “and / or,” such that, for example, “at least one of A or B” means A or B or both A and B.

[0126] The term “substantially” is defined as largely but not necessarily wholly that which is specified (and includes what is specified; e.g., substantially 90 degrees includes 90 degrees and substantially parallel includes parallel), as understood by one of ordinary skill in the art. In any of the disclosed implementations, the term “substantially” can be replaced with “[percentage] within” of what is specified, where the percentage includes 0.1%, 1%, 5%, or 10%.

[0127] The preceding description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: A memory controller, coupled to the memory array via a data bus and configured to access data stored in the memory array via the data bus, and configured to be coupled to a host device via a channel and configured to perform operations including: Partial row refresh information associated with the first row in the memory array is obtained from the host device via the channel; as well as A portion of the first row in the memory array is refreshed based on the partial row refresh information.

2. The apparatus of claim 1, wherein the partial row refresh information includes an indication of the percentage of the first row to be refreshed.

3. The apparatus of claim 2, wherein the indication of the percentage of the first row to be refreshed comprises a two-digit value.

4. The apparatus of claim 3, wherein the indication of the percentage of the first row to be refreshed includes one of the following: Refresh the 25% indicator in the first line; Refresh the 50% indicator in the first line; Refresh the 75% instruction in the first line; or Refresh the 100% instruction in the first line.

5. The apparatus of claim 1, wherein the memory controller is configured to perform operations further comprising: Receive an instruction to enter self-refresh mode from the host device. Upon receiving the instruction to enter the self-refresh mode, the memory controller performs a refresh of a portion of the first row in the memory array based on the partial row refresh information.

6. The apparatus of claim 5, wherein receiving the instruction to enter the self-refresh mode includes receiving an instruction to the host device to enter a sleep mode.

7. The apparatus of claim 1, wherein the partial row refresh information is included in address information associated with the first row.

8. The apparatus of claim 1, wherein refreshing a portion of the first row in the memory array based on the partial row refresh information comprises: Based on the partial row refresh information, determine the portion of the first row that needs to be refreshed; as well as One or more sensing amplifiers corresponding to one or more blocks of the first row are activated based on the portion of the first row to be refreshed.

9. The apparatus of claim 8, wherein determining the portion of the first row to be refreshed comprises decoding refresh information for the portion of the row.

10. The apparatus of claim 1, wherein the memory array comprises a low-power double data rate (LPDDR) memory array.

11. A method, the method comprising: The memory controller obtains partial row refresh information associated with the first row in the memory array from the host device via a channel; as well as The memory controller refreshes a portion of the first row in the memory array based on the partial row refresh information.

12. The method of claim 11, wherein the partial row refresh information includes an indication of the percentage of the first row to be refreshed.

13. The method of claim 12, wherein the indication of the percentage of the first row to be refreshed comprises a two-digit value.

14. The method of claim 13, wherein the indication of the percentage of the first row to be refreshed comprises one of the following: Refresh the 25% indicator in the first line; Refresh the 50% indicator in the first line; Refresh the 75% instruction in the first line; or Refresh the 100% instruction in the first line.

15. The method according to claim 11, further comprising: Receive an instruction to enter self-refresh mode from the host device. Upon receiving the instruction to enter the self-refresh mode, the memory controller performs a refresh of a portion of the first row in the memory array based on the partial row refresh information.

16. The method of claim 15, wherein receiving the instruction to enter the self-refresh mode includes receiving an instruction to the host device to enter a sleep mode.

17. The method of claim 11, wherein the partial row refresh information is included in address information associated with the first row.

18. The method of claim 11, wherein refreshing a portion of the first row in the memory array by the memory controller based on the partial row refresh information comprises: Based on the partial row refresh information, determine the portion of the first row that needs to be refreshed; as well as One or more sensing amplifiers corresponding to one or more blocks of the first row are activated based on the portion of the first row to be refreshed.

19. The method of claim 18, wherein determining a portion of the first row to be refreshed comprises decoding refresh information for the portion of the row.

20. The method of claim 11, wherein the memory array comprises a low-power double data rate (LPDDR) memory array.

21. An apparatus comprising: At least one processor; and A memory controller, coupled to the at least one processor and the memory system via a channel and configured to communicate with the memory system via the channel. The at least one processor is configured to perform operations including the following: The memory controller saves the data to the first part of the first row of the memory array of the memory system; Based on the saving of the first portion of the data to the first row, partial row refresh information of the first row is determined; as well as The memory controller copies the partial row refresh information to the memory system.

22. The apparatus of claim 21, wherein the at least one processor is configured to perform operations further comprising: Receive an instruction to enter sleep mode, wherein saving the data is performed after receiving the instruction to enter sleep mode; After receiving the instruction to enter the sleep mode, the memory controller sends an instruction to the memory system to enter the self-refresh mode; as well as After copying the partial row refresh information to the memory system, the system enters the sleep mode.

23. The apparatus of claim 21, wherein determining the partial row refresh information includes determining the address information of the first row based on the number of blocks in the first portion of the first row.

24. The apparatus of claim 21, wherein the partial row refresh information includes an indication of the percentage of the first row to be refreshed.

25. The apparatus of claim 22, wherein the memory controller is configured to communicate with a double data rate (DDR) memory system.

26. A method, the method comprising: At least one processor of a host device, connected via a channel to a memory controller of the memory system, saves data to a first portion of a first row in the memory array of the memory system through the memory controller; The at least one processor determines partial row refresh information for the first row based on the saving of data to the first portion of the first row; as well as The at least one processor copies the partial row refresh information to the memory system via the memory controller.

27. The method according to claim 26, further comprising: The at least one processor receives an instruction to enter a sleep mode, wherein saving the data is performed after receiving the instruction to enter the sleep mode; Upon receiving the instruction to enter the sleep mode, the at least one processor sends an instruction to enter the self-refresh mode to the memory system via the memory controller; as well as After the partial row refresh information is copied to the memory system, the at least one processor enters the sleep mode.

28. The method of claim 26, wherein determining the partial row refresh information includes determining the address information of the first row based on the number of blocks in the first portion of the first row.

29. The method of claim 26, wherein the partial row refresh information includes an indication of the percentage of the first row to be refreshed.

30. The method of claim 26, wherein the memory controller is configured to communicate with a double data rate (DDR) memory system.

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