Signal channel delay compensation method and test system

Abstract

This application discloses a signal channel delay compensation method and testing system, relating to the field of semiconductor technology. The signal channel delay compensation method includes: for each signal channel in a multi-channel test device, updating the programmable compensation delay required by the signal channel according to a preset clock cycle to obtain a coarse adjustment compensation amount, wherein the clock cycle includes a parallel clock cycle and a serial clock cycle; determining the parallel clock cycle of the first cycle compensation coefficient and the serial clock cycle of the second cycle compensation coefficient based on the coarse adjustment compensation amount; performing a first cycle macroscopic delay compensation on the signal channel based on the parallel clock cycle of the first cycle compensation coefficient; and performing a second cycle microscopic delay compensation on the signal channel based on the serial clock cycle of the second cycle compensation coefficient. This application can achieve effective delay compensation for multiple signal channels to achieve timing synchronization between multiple signal channels.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and in particular to a signal channel delay compensation method and testing system. Background Technology

[0002] With the rapid development of semiconductor technology, the design of integrated circuits (ICs) is becoming increasingly complex, posing stringent challenges to the testing requirements of automatic test equipment (ATEs), especially in scenarios of large-scale parallel testing and high-frequency timing testing.

[0003] While current ATE systems can perform multi-channel testing, differences in physical trace length and external cable lengths during signal transmission cause inconsistent signal delays from the FPGA (Field-Programmable Gate Array) output to the device under test (DUT) pins. This signal asynchrony leads to deviations in the signal sequence that should arrive at the DUT pins simultaneously, resulting in unreliable test results and potentially failing to accurately determine the chip's performance or functionality.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a signal channel delay compensation method and testing system, which aims to solve the technical problem of how to effectively compensate for the delay of multiple signal channels in order to achieve timing synchronization between multiple signal channels.

[0006] To achieve the above objectives, this application proposes a signal channel delay compensation method applied to FPGA. The signal channel delay compensation method includes:

[0007] For each signal channel in the multi-channel test equipment, the programmable compensation delay required by the signal channel is updated according to the preset clock cycle to obtain the coarse adjustment compensation amount. The clock cycle includes the parallel clock cycle and the serial clock cycle.

[0008] The parallel clock period for the first cycle compensation coefficient and the serial clock period for the second cycle compensation coefficient are determined based on the coarse adjustment compensation amount.

[0009] The signal channel is subjected to macroscopic delay compensation for the first cycle based on the parallel clock cycle of the first cycle compensation coefficient;

[0010] The signal channel is subjected to second-cycle micro-delay compensation based on the serial clock cycle of the second-cycle compensation coefficient.

[0011] In one embodiment, the step of performing first-cycle macroscopic delay compensation on the signal channel based on the parallel clock cycle of the first-cycle compensation coefficient includes:

[0012] Determine the compensation coefficient range that includes the first cycle compensation coefficient, determine the third cycle compensation coefficient that is greater than the maximum value in the compensation coefficient range, and determine the fourth cycle compensation coefficient that is located in the compensation coefficient range.

[0013] In the historical parallel data with a data length of the third cycle compensation coefficient, the first parallel data after the parallel clock cycle delay of the fourth cycle compensation coefficient is determined, and the first parallel data is output as the current cycle parallel data.

[0014] In one embodiment, the FPGA includes an interconnected chain of shift registers and multiplexers.

[0015] The steps for determining the first parallel data after a parallel clock cycle delay of the fourth cycle compensation coefficient from historical parallel data with a data length of the third cycle compensation coefficient include:

[0016] Determine the shift register chain containing historical parallel data with a data length equal to the third-cycle compensation coefficient;

[0017] Based on the historical parallel data in the shift register chain selected by the multiplexer after a delay of the parallel clock cycle with the fourth cycle compensation coefficient, the historical parallel data is selected as the first parallel data.

[0018] In one embodiment, the step of performing second-cycle micro-delay compensation on the signal channel based on the serial clock cycle of the second-cycle compensation coefficient includes:

[0019] Determine a data window containing a second parallel data of two cycle lengths, wherein the second parallel data includes the current cycle parallel data and the previous cycle parallel data;

[0020] Based on the serial clock period of the second period compensation coefficient, a parallel data of a period length is selected out of the data window as the third parallel data output.

[0021] In one embodiment, the step of selecting a parallel data of a period length with a misalignment in the data window as the third parallel data output, based on the serial clock period of the second period compensation coefficient, includes:

[0022] In the second parallel data contained in the data window, starting from the position of the parallel data after the serial clock cycle delay of the second cycle compensation coefficient, and ending at the position of the parallel data after one cycle length, the second parallel data is sliced ​​to obtain parallel data of one cycle length, and the parallel data of one cycle length is output as the third parallel data.

[0023] In one embodiment, the step of updating the programmable compensation delay required for the signal channel according to a preset clock cycle to obtain the coarse adjustment compensation amount includes:

[0024] The quantization step size is determined based on a preset clock cycle;

[0025] The programmable compensation delay is updated based on the quantization step size to obtain the coarse adjustment compensation amount.

[0026] In one embodiment, the step of determining the quantization step size based on a preset clock cycle includes:

[0027] Determine the minimum adjustable resolution for the parallel clock cycle;

[0028] The minimum adjustable resolution is converted into the minimum coarse adjustment resolution of the serial clock cycle according to the preset serialization ratio, and the minimum coarse adjustment resolution is used as the quantization step size.

[0029] In one embodiment, the step of updating the programmable compensation delay based on the quantization step size to obtain the coarse adjustment compensation amount includes:

[0030] The comparison results of programmable compensation delay and quantization step size are rounded and quantized to obtain the integer number of serial clock cycles.

[0031] The number of integer cycles is updated based on the quantization step size to obtain the coarse adjustment compensation amount.

[0032] In one embodiment, after updating the programmable compensation delay required for the signal channel according to a preset clock period to obtain the coarse adjustment compensation amount, the method includes:

[0033] Determine the delay remainder between the programmable compensation delay and the coarse adjustment compensation amount;

[0034] In response to the absolute value of the delay remainder being less than or equal to half a serial clock cycle, the steps of determining the parallel clock cycle of the first cycle compensation coefficient and the serial clock cycle of the second cycle compensation coefficient based on the coarse adjustment compensation amount are performed.

[0035] In one embodiment, the step of determining the parallel clock period of the first cycle compensation coefficient and the serial clock period of the second cycle compensation coefficient based on the coarse adjustment compensation amount includes:

[0036] Determine the integer number of serial clock cycles;

[0037] The compensation coefficient for the first cycle is determined based on the comparison between the integer number of cycles and the preset serialization ratio.

[0038] The second cycle compensation coefficient is obtained by performing a modulo operation on the serialization ratio and the integer number of cycles.

[0039] The coarse adjustment compensation amount is decomposed based on the first cycle compensation coefficient and the second cycle compensation coefficient to obtain the parallel clock period of the first cycle compensation coefficient and the serial clock period of the second cycle compensation coefficient.

[0040] In one embodiment, the signal channel delay compensation method further includes:

[0041] Determine the required programmable compensated delay for each signal channel in the multi-channel test equipment;

[0042] Determine the inherent FPGA delay and external hardware delay for each signal channel;

[0043] For each signal channel, the first total delay of the signal channel is determined using a model that characterizes the total delay of the signal channel, based on the programmable compensated delay, the inherent delay of the FPGA, and the external hardware delay.

[0044] In response to a first total delay mismatch corresponding to at least two signal channels, the step of updating the programmable compensation delay required for each of the multiple signal channels of the test equipment according to a preset clock cycle is performed to obtain the coarse adjustment compensation amount.

[0045] In one embodiment, the step of determining the programmable compensated delay required for each signal channel in the multiple signal channels of the test equipment includes:

[0046] Determine the first total delay difference of each signal channel relative to a preset reference channel;

[0047] The signal channel with the smallest delay is determined based on the first total delay difference corresponding to each signal channel, and the first total delay difference corresponding to the signal channel with the smallest delay is used as the second total delay difference;

[0048] For each signal channel, the first total delay difference of the signal channel is updated based on the absolute value of the second total delay difference to obtain a programmable compensated delay.

[0049] In one embodiment, the step of determining a first total delay difference for each signal channel relative to a preset reference channel includes:

[0050] When the programmable compensation delay of each signal channel is set to zero, the first total delay difference corresponding to each signal channel is determined based on the second total delay of each signal channel and the third total delay of the reference channel.

[0051] In one embodiment, the signal channel delay compensation method further includes at least one of the following:

[0052] FPGA inherent delays include logic processing delay, serialization delay, and internal routing delay;

[0053] External hardware delays include PCB trace delays, cable delays, and load board delays.

[0054] In addition, to achieve the above objectives, this application also proposes a testing system, which includes a controller and a memory. The memory stores a computer program, and the controller can execute the computer program to implement the steps of the signal channel delay compensation method described above.

[0055] One or more technical solutions proposed in this application have at least the following technical effects:

[0056] In this embodiment, for each signal channel in the multi-channel test equipment, the programmable compensation delay required for the signal channel is updated according to a preset clock cycle (such as parallel clock cycle and serial clock cycle) to obtain the coarse adjustment compensation amount. This allows the coarse adjustment compensation amount to be determined solely through the general logic resources within the FPGA, enabling subsequent delay compensation for each signal channel without relying on the scarce and limited ODELAY hard core resources within the FPGA resource area. This avoids the resource constraints and insufficient delay range encountered in multi-channel synchronous scenarios. Furthermore, the coarse adjustment compensation amount is decomposed into the parallel clock cycle of the first-cycle compensation coefficient and the serial clock cycle of the second-cycle compensation coefficient. This transforms the complex delay compensation problem into an integer configuration problem (i.e., configuring the first-cycle compensation coefficient and the second-cycle compensation coefficient). All logic control can operate in the low-speed clock domain. This purely digital implementation significantly reduces the timing convergence difficulty and simplifies the design and verification steps. Furthermore, it performs first-cycle macroscopic delay compensation on the signal channel based on the parallel clock cycle of the first-cycle compensation coefficient. This allows for a wide range of first-cycle macroscopic delay compensation based on the first-cycle compensation coefficient. The compensation range corresponding to the first-cycle compensation coefficient is only limited by the data length of the FPGA's internal logic and can be easily extended to tens or even hundreds of parallel clock cycles, effectively addressing the ultra-large delay differences caused by long-distance cables. It also performs second-cycle microscopic delay compensation on the signal channel based on the serial clock cycle of the second-cycle compensation coefficient. This allows for high-precision second-cycle microscopic delay compensation based on the second-cycle compensation coefficient. Therefore, by performing first-cycle macroscopic delay compensation and second-cycle microscopic delay compensation separately on the same signal channel, hierarchical high-precision control of the signal channel can be achieved. For example, it allows for a wide range of first-cycle macroscopic delay compensation and high-precision second-cycle microscopic delay compensation. This enables effective delay compensation for multiple signal channels at both macroscopic and microscopic levels, achieving timing synchronization between multiple signal channels. Attached Figure Description

[0057] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0058] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1This is a schematic diagram of the first process of an embodiment of the signal channel delay compensation method of this application;

[0060] Figure 2 This is a schematic diagram of the second process in an embodiment of the signal channel delay compensation method of this application;

[0061] Figure 3 This is a schematic diagram of the third process in an embodiment of the signal channel delay compensation method of this application;

[0062] Figure 4 This is a schematic diagram of a scenario in the signal channel delay compensation method of this application;

[0063] Figure 5 This is a schematic diagram of the memory structure involved in the signal channel delay compensation method in the embodiments of this application.

[0064] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0065] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0066] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0067] To address the issue of timing discrepancies and time deviations among multiple signal channels in testing equipment, two methods are provided.

[0068] Method 1, cable length matching: Timing matching of multiple signal channels is achieved by precisely controlling the length of PCB traces and external cables. However, this method is costly, inflexible, and cannot compensate for delays caused by internal FPGA routing.

[0069] Method 2, Hard-core Delay Unit Compensation: Within the FPGA, variable-delay hard-core resources provided by the resource area, such as the ODELAY module (output delay module), are used to finely adjust the output signal. However, this method has limitations. For example, the number of hard-core resources like the ODELAY module is usually limited on the FPGA chip. In large-scale, multi-channel parallel testing applications, hard-core resources often become the main bottleneck for the scalability of large-scale high-speed synchronous systems. Furthermore, hard-core delay compensation also suffers from a limited compensation range. The design purpose of hard-core delay unit compensation is to perform fine-tuning of timing, and its total delay compensation range is relatively small (usually only a few nanoseconds). Faced with huge delay differences (such as tens or even hundreds of nanoseconds) introduced by long-distance external cables, it cannot provide sufficient compensation.

[0070] Therefore, this application provides a signal channel delay compensation method to achieve high precision, wide-range compensation, and multi-channel signal synchronization without being limited by FPGA hard core resources. Furthermore, by employing an OSERDES module (parallel-to-serial converter module) in conjunction with pure digital logic for hierarchical compensation, the shortcomings of methods 1 and 2 are effectively avoided. The delay compensation for the signal channel is divided into a first-cycle macroscopic delay compensation and a second-cycle microscopic delay compensation, achieving efficient and flexible digital compensation in the low-speed clock domain, thus providing a feasible synchronization solution for next-generation high-speed, high-density ATE systems.

[0071] Furthermore, in this embodiment, the general-purpose logic resources of the FPGA can be used to replace the traditional hard-core delay unit, avoiding the resource constraints and insufficient delay range defects faced in multi-channel synchronous scenarios. Compared with methods 1 and 2, it has the following advantages:

[0072] Advantage 1: Overcoming the limitation of hard core resources: Method 2 relies on hard core resources such as the scarce and limited number of ODELAY modules in the FPGA resource area. In the embodiment of this application, delay compensation can be achieved by using general logic resources (such as multiplexers MUX), which completely gets rid of the dependence on specific hard core primitives. This makes the number of channels in the multi-channel synchronization scheme no longer limited by the scarcity of hard core resources, and greatly improves the channel density and scalability of the system.

[0073] Advantage 2: Flexible and vast compensation range, enabling hierarchical high-precision control: For example, the compensation range of the ODELAY module is usually limited (e.g., within 10ns). In this embodiment, the first-cycle macroscopic delay compensation can be achieved through a shift register chain, and its compensation range... Limited only by the data length of the FPGA's internal logic, it can be easily scaled to tens or even hundreds of parallel clock cycles (e.g., 100 × 5ns = 500ns), effectively addressing the significant latency differences caused by long-distance cables. Furthermore, the total latency can be decomposed into... The first cycle of the cycle macroeconomic delay compensation and The second cycle of the micro-delay compensation utilizes the high-frequency characteristics of the OSERDES module to improve the delay accuracy to the serial clock cycle. This achieves a wide range of ( (Level) and high precision ( Delay-level control (level 1).

[0074] Advantage 3: Delay control is easy to implement, improving design reliability: The complex delay compensation problem is transformed into an integer configuration problem (configuring two integer coefficients, M and K), and all control logic runs in a low-speed parallel clock domain. This purely digital implementation reduces the difficulty of timing convergence and simplifies the design and verification process.

[0075] Advantage 4: Improved system portability: Since the embodiments of this application only rely on the general logic resources of the FPGA (flip-flops, lookup tables and multiplexers MUX), the synchronization technology can be easily ported to FPGA platforms of different models and manufacturers, enhancing the versatility and economy of the solution.

[0076] Optionally, embodiments of this application can be applied to the field of semiconductor testing (ATE) to avoid the defects of timing inconsistencies caused by differences in external paths for multi-channel high-speed signals. It abandons the reliance on hardware delay primitives such as ODELAY that are scarce inside the FPGA, and instead utilizes the general logic resources of the FPGA (flip-flops, lookup tables and multiplexers) to build a high-precision, wide-range, fully digital hierarchical delay compensation mechanism.

[0077] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a memory, computer, mobile phone, FPGA, etc., or an electronic device capable of implementing the above functions. This embodiment uses an FPGA as an example only.

[0078] Reference Figure 1 , Figure 1 This illustration shows a first flowchart of a signal channel delay compensation method provided in an embodiment of this application. In this embodiment, the signal channel delay compensation method is applied to an FPGA, and the signal channel delay compensation method includes steps S10-S40:

[0079] Step S10: For each signal channel in the multi-channel signal channel of the test equipment, update the programmable compensation delay required by the signal channel according to the preset clock cycle to obtain the coarse adjustment compensation amount. The clock cycle includes the parallel clock cycle and the serial clock cycle.

[0080] Optionally, the testing equipment can be ATE (Automatic Test Equipment), such as an integrated circuit automatic test machine, used to test the integrity of integrated circuit functions. This is the final step in integrated circuit manufacturing to ensure the quality of integrated circuit production. ATE is specialized equipment used to test chip functions and performance; chip yield monitoring, process improvement, and reliability verification all require the use of this type of equipment.

[0081] Optionally, the test equipment can generate various test signals for different chips under test and different test items. During the test operation, the multiple signal channels in the test equipment can be electrically connected to multiple pins in the chip under test, and the test equipment generates test signals with corresponding delay amounts. The test signals are transmitted to the corresponding multiple pins through each signal channel for testing.

[0082] Optionally, the delay of each signal channel of the test equipment can be adjusted by FPGA. For example, the signal channel delay adjustment device for the test equipment can be set on the FPGA chip, and steps S10-S40 can be executed by the signal channel delay adjustment device to realize the delay adjustment of multiple signal channels of the test equipment.

[0083] Optionally, the parallel clock cycle can be the master clock cycle followed by the internal logic modules of the FPGA. For example, it could be 5ns (200MHz). In this clock domain, test signal data exists in parallel, and one data word (e.g., an 8-bit number) can be transmitted per parallel clock cycle. The parallel clock cycle can be a low-speed parallel clock cycle, ranging from 100MHz to 250MHz.

[0084] Optionally, the serial clock cycle can be the clock cycle used by the FPGA's high-performance serial interface module to drive the final output pins. For example, it could be 625 ps. In this clock domain, parallel test signal data is broken down into individual bits and output serially at extremely high speed. The serial clock cycle can be a high-speed serial clock cycle, ranging from 500 MHz to 2 GHz.

[0085] Optionally, the same operating steps are applied to each of the multiple signal channels (e.g., 10 signal channels) of the test equipment. The following example illustrates the procedure for a single signal channel.

[0086] Optionally, the programmable compensation delay can be updated based on the serial clock cycle to obtain the coarse adjustment compensation amount; alternatively, the programmable compensation delay can be updated based on the parallel clock cycle, for example, by converting the parallel clock cycle into a serial clock cycle and then updating the programmable compensation delay based on the serial clock cycle to obtain the coarse adjustment compensation amount.

[0087] Optionally, the total number of serial clock cycles included in the programmable compensation delay can be determined, and the coarse adjustment compensation amount can be determined based on the total number of cycles. For example, the total number of cycles can be directly used as the coarse adjustment compensation amount, or the total number of cycles can be amplified to obtain the coarse adjustment compensation amount.

[0088] Step S20: Determine the parallel clock period of the first cycle compensation coefficient and the serial clock period of the second cycle compensation coefficient based on the coarse adjustment compensation amount.

[0089] Optionally, the first cycle compensation coefficient can be a large cycle compensation coefficient, and can be an integer multiple of the parallel clock cycle.

[0090] Optionally, the second cycle compensation coefficient can be a small cycle compensation coefficient, and can be an integer multiple of the serial clock cycle.

[0091] Optionally, the coarse adjustment compensation amount can be the sum of the first cycle compensation coefficient and the second cycle compensation coefficient, as shown in Formula (I) below.

[0092] Formula (1);

[0093] in, This is for coarse adjustment compensation. For parallel clock cycles, such as 5ns; The serial clock period is 625ps; M is the compensation coefficient for the first period; and K is the compensation coefficient for the second period.

[0094] Optionally, the coarse adjustment compensation amount can be an integer multiple of the serial clock cycle. Therefore, the coarse adjustment compensation amount can be decomposed into two configurable hardware operations (i.e., the first cycle compensation coefficient of parallel clock cycles and the second cycle compensation coefficient of serial clock cycles) to achieve macroscopic delay compensation in the first cycle and microscopic delay compensation in the second cycle.

[0095] Alternatively, the compensation logic for M and K can be instantiated as a programmable delay control circuit embodied in a shift register chain and multiplexers using a hardware description language (such as Verilog HDL). This circuit operates at low speeds. Parallel clock domain operation.

[0096] Step S30: Perform first-cycle macroscopic delay compensation on the signal channel based on the parallel clock cycle of the first-cycle compensation coefficient;

[0097] Optionally, the macroscopic delay compensation in the first cycle can be achieved by adjusting the parallel clock cycle. The periodicity is achieved. The first periodic macroscopic delay compensation can be a large-cycle macroscopic delay compensation, and its compensation range can be less than or equal to 200ns.

[0098] Alternatively, macroscopic delay compensation for the signal channel can be performed using general logic resources in the FPGA, such as multiplexers (MUX) and shift register chains, combined with the parallel clock cycle of the first-cycle compensation coefficient.

[0099] Optionally, for each signal channel, the first period compensation coefficient corresponding to that signal channel can be determined, or a compensation coefficient range can be constructed based on the first period compensation coefficient, wherein the maximum value of the compensation coefficient range is the first period compensation coefficient, and the minimum value is 0.

[0100] Optionally, any data in the compensation coefficient range can be determined as the number of parallel clock cycles, and the signal channel can be subjected to the first cycle macroscopic delay compensation based on the number of parallel clock cycles.

[0101] Optionally, in step S30, the step of performing first-cycle macroscopic delay compensation on the signal channel based on the parallel clock cycle of the first-cycle compensation coefficient includes steps a10-a20.

[0102] Step a10: Determine the compensation coefficient range that includes the first cycle compensation coefficient, determine the third cycle compensation coefficient that is greater than the maximum value in the compensation coefficient range, and determine the fourth cycle compensation coefficient that is located in the compensation coefficient range.

[0103] Optionally, a compensation coefficient range can be set for each signal channel, and the maximum value of the compensation coefficient range can be set. It can be the compensation coefficient for the first cycle, and the minimum value can be 0, for example, [0, ].

[0104] Optionally, a periodic compensation coefficient greater than the maximum value in the compensation coefficient range can be set and used as the third periodic compensation coefficient, for example... Alternatively, a periodic compensation coefficient can be selected within this compensation coefficient range as the fourth periodic compensation coefficient. This fourth periodic compensation coefficient can be 0 or... For example, 10.

[0105] Step a20: In the historical parallel data with a data length equal to the third cycle compensation coefficient, determine the first parallel data after a delay of the parallel clock cycle with the fourth cycle compensation coefficient, and output the first parallel data as the current cycle parallel data.

[0106] Optionally, when the first cycle of macroscopic delay compensation is required, it can be performed during the parallel clock cycle. Driven by a clock, a historical parallel dataset with a length equal to the compensation coefficient of the third cycle is constructed, for example, a dataset with a length of... +1 is the history of the parallel data stream.

[0107] Optionally, the first parallel data after the parallel clock cycle delay by the fourth cycle compensation coefficient can be selected from the historical parallel data and output as the current cycle parallel data.

[0108] In this embodiment, the current period parallel data, delayed by the parallel clock cycle of the fourth period compensation coefficient, is output from the historical parallel data with a data length greater than the first period compensation coefficient and a third period compensation coefficient. Since the fourth period compensation coefficient is a compensation coefficient within the compensation coefficient range, it can be flexibly set and changed. Thus, the output can be selected from the parallel data delayed by the parallel clock cycle of the fourth period compensation coefficient, thereby achieving macroscopic delay compensation of the first period and ensuring the effectiveness of delay compensation for the signal channel.

[0109] Optionally, the FPGA connected to the test equipment includes an interconnected chain of shift registers and multiplexers.

[0110] Optionally, in step a20, the step of determining the first parallel data after a parallel clock cycle delay by a fourth cycle compensation coefficient from the historical parallel data with a data length of the third cycle compensation coefficient includes steps a21-a22.

[0111] Step a21: Determine the shift register chain containing historical parallel data with a data length equal to the compensation coefficient of the third cycle;

[0112] Step a22: Based on the historical parallel data in the shift register chain, the multiplexer selects the historical parallel data after the parallel clock cycle delay with the fourth cycle compensation coefficient as the first parallel data.

[0113] Optionally, when macroscopic delay compensation for the first cycle is required, it can be performed using a macroscopic delay circuit in the FPGA. The macroscopic delay circuit may include an interconnected chain of shift registers and a multiplexer (MUX), where the shift register chain contains historical parallel data with a data length equal to the compensation coefficient for the third cycle.

[0114] Optionally, the configuration value of the multiplexer can be set to the fourth cycle compensation coefficient, and m parallel clock cycles can be selected and output in the shift register chain based on this configuration value. The delayed historical parallel data (i.e., the first parallel data) is used as the current cycle's parallel data. m can be the fourth cycle compensation coefficient, such as 1 or... .

[0115] Optionally, in the shift register chain, each parallel clock cycle At the rising edge of the clock cycle, new parallel data is written to the head of the shift register chain, and all other parallel data in the chain are shifted one bit to the right. Therefore, when selecting parallel data from the shift register chain for output using a multiplexer, when the configuration value m is 0, the parallel data at the head of the shift register chain is selected as the first parallel data for output; when the configuration value m is 1, the parallel data in the shift register chain delayed by one clock cycle is selected. The parallel data of the clock cycle is output as the first parallel data, with the configured value... At that time, select the delay in the shift register chain. one parallel clock cycle The parallel data of the clock cycle is output as the first parallel data.

[0116] In this embodiment, by selecting historical parallel data with a fourth-cycle compensation coefficient after a delay in the parallel clock cycle from the historical parallel data of the shift register chain based on the multiplexer, and outputting it as the current cycle parallel data, it is possible to achieve macroscopic delay compensation for the first cycle by relying solely on the general logic resources of the multiplexer and shift register chain within the FPGA, thus eliminating the dependence on the scarce and limited number of ODELAY module hard core resources within the FPGA resource area.

[0117] Step S40: Perform second-cycle micro-delay compensation on the signal channel based on the serial clock cycle of the second-cycle compensation coefficient.

[0118] Optionally, the micro delay compensation in the second cycle can be adjusted The phase is realized. The second-cycle micro-delay compensation can be a small-cycle micro-delay compensation, and its compensation range can be less than or equal to 2.8 ns.

[0119] Alternatively, the first-cycle macroscopic delay compensation of the signal channel can be performed using general-purpose logic resources in the FPGA, such as multiplexers (MUX), in conjunction with the serial clock cycle of the second-cycle compensation coefficient.

[0120] Optionally, for each signal channel, a second-cycle compensation coefficient can be determined for that signal channel, or another compensation coefficient range can be constructed based on the second-cycle compensation coefficient. The maximum value of this other compensation coefficient range is the second-cycle compensation coefficient, and the minimum value is 0. Second-cycle micro-delay compensation can be performed on the signal channel based on the second-cycle compensation coefficient or any cycle compensation coefficient in this other compensation coefficient range.

[0121] Optionally, in this embodiment, the execution order of performing the first cycle macroscopic delay compensation and the second cycle microscopic delay compensation on the same signal channel can be either performing the first cycle macroscopic delay compensation first and then performing the second cycle microscopic delay compensation, or performing the first cycle macroscopic delay compensation and the second cycle microscopic delay compensation in parallel.

[0122] Optionally, in step S40, the step of performing second-cycle micro-delay compensation on the signal channel based on the serial clock cycle of the second-cycle compensation coefficient includes steps b10-b20.

[0123] Step b10: Determine a data window containing a second parallel data of two cycle lengths, wherein the second parallel data includes the current cycle parallel data and the previous cycle parallel data;

[0124] Step b20: Based on the serial clock period of the second period compensation coefficient, select a parallel data of a period length in the data window as the third parallel data output.

[0125] Optionally, when it is determined that a second-cycle micro-delay compensation is needed for the signal channel, this compensation can be performed using a micro-delay circuit within the FPGA. The micro-delay circuit may include a data splicing unit and a second multiplexer (MUX).

[0126] Optionally, the parallel data of the current cycle and the parallel data of the previous cycle can be concatenated into a 2N-bit data window using a data concatenation unit. The cycle length of a parallel data can be N bits, such as 8 bits.

[0127] Optionally, the second parallel data included in the data window can be obtained by concatenating the current cycle parallel data (output based on the first cycle macroscopic delay compensation for the same signal channel) and the previous cycle parallel data. Alternatively, the current cycle parallel data and the previous cycle parallel data can be directly obtained and concatenated to obtain the second parallel data.

[0128] Optionally, when performing micro-delay compensation in the second cycle, a configuration value, such as a second configuration value, can be set. The second cycle compensation coefficient of the serial clock cycle can be used as the second configuration value. Based on the second configuration value, the second multiplexer (MUX) can be driven to select a data slice with an N-bit offset (i.e., parallel data of one cycle length) in the data window as the third parallel data for output. Thus, this selection operation can be logically equivalent to timing-wise implementation. Sub-period delay of (the serial clock period of the second period compensation coefficient).

[0129] In this embodiment, by selecting a parallel data of a period length in the data window as the third parallel data output based on the serial clock period of the second period compensation coefficient, and since the data window includes the current period parallel data and the previous period parallel data, this staggered selection operation is logically equivalent to realizing the second period micro delay compensation in timing, thereby ensuring the effectiveness of the signal channel delay compensation.

[0130] Optionally, step b20, which involves selecting a parallel data of a certain period length in the data window as the third parallel data output based on the serial clock period of the second period compensation coefficient, includes step b21.

[0131] Step b21: In the second parallel data contained in the data window, starting from the position of the parallel data after the serial clock cycle delay of the second cycle compensation coefficient, and ending at the position of the parallel data after one cycle length, the second parallel data is sliced ​​to obtain parallel data of one cycle length, and the parallel data of one cycle length is output as the third parallel data.

[0132] Optionally, when selecting a data window, the second parallel data contained in the data window can be determined, and the second parallel data can be sliced ​​starting from the position of the parallel data after the serial clock cycle delay of the second cycle compensation coefficient and ending at the position of the parallel data after one cycle length to obtain parallel data of one cycle length, i.e., the third parallel data, and the third parallel data can be output.

[0133] Optionally, in the micro-delay circuit, the data splicing unit splices the current cycle parallel data and the previous cycle parallel data to obtain a data window. After obtaining the data window, the data window can be input to the second multiplexer MUX, and the second cycle compensation coefficient K can be used as the selection control signal of the second multiplexer MUX to select an N-bit data slice from the data window as the third parallel data for output. The Kth bit of the spliced ​​data is in the data window of the starting bit of the N-bit data slice.

[0134] Optionally, the parallel data after two levels of digital compensation (first-cycle compensation coefficient M and second-cycle compensation coefficient K) can be sent to the OSERDES module for high-speed serialization output. By configuring independent first-cycle compensation coefficient M and second-cycle compensation coefficient K for each signal channel, precise, wide-range, and highly scalable synchronous control of multi-channel signals can be achieved.

[0135] In this embodiment, by taking the position of the parallel data after the serial clock cycle delay of the second period compensation coefficient as the starting point and the position of the parallel data after one period as the ending point in the second parallel data contained in the data window, data slicing is performed on the second parallel data to obtain the third parallel data and output it. In this way, the micro-delay compensation of the second period of the signal channel can be indirectly achieved by selecting the parallel data after the serial clock cycle delay of the second period compensation coefficient in a staggered manner, thus ensuring the effectiveness of the delay compensation of the signal channel.

[0136] In this embodiment, for each signal channel in the multi-channel test equipment, the programmable compensation delay required for the signal channel is updated according to a preset clock cycle (such as parallel clock cycle and serial clock cycle), resulting in a coarse adjustment compensation amount. This allows the coarse adjustment compensation amount to be determined solely through the general logic resources within the FPGA, enabling subsequent delay compensation for each signal channel without relying on the scarce and limited ODELAY hard core resources within the FPGA resource area. This avoids the resource constraints and insufficient delay range encountered in multi-channel synchronous scenarios. Furthermore, the coarse adjustment compensation amount is decomposed into the parallel clock cycle of the first-cycle compensation coefficient and the serial clock cycle of the second-cycle compensation coefficient. This transforms the complex delay compensation problem into an integer configuration problem (i.e., configuring the first-cycle compensation coefficient and the second-cycle compensation coefficient). All logic control can operate in the low-speed clock domain. This purely digital implementation significantly reduces the timing convergence difficulty and simplifies the design and verification steps. Furthermore, it performs first-cycle macroscopic delay compensation on the signal channel based on the parallel clock cycle of the first-cycle compensation coefficient. This allows for a wide range of first-cycle macroscopic delay compensation based on the first-cycle compensation coefficient. The compensation range corresponding to the first-cycle compensation coefficient is only limited by the data length of the FPGA's internal logic and can be easily extended to tens or even hundreds of parallel clock cycles, effectively addressing the ultra-large delay differences caused by long-distance cables. It also performs second-cycle microscopic delay compensation on the signal channel based on the serial clock cycle of the second-cycle compensation coefficient. This allows for high-precision second-cycle microscopic delay compensation based on the second-cycle compensation coefficient. Therefore, by performing first-cycle macroscopic delay compensation and second-cycle microscopic delay compensation separately on the same signal channel, hierarchical high-precision control of the signal channel can be achieved. For example, it allows for a wide range of first-cycle macroscopic delay compensation and high-precision second-cycle microscopic delay compensation. This enables effective delay compensation for multiple signal channels at both macroscopic and microscopic levels, achieving timing synchronization between multiple signal channels.

[0137] Reference Figure 2 , Figure 2This illustration shows a second flowchart of the signal channel delay compensation method provided in an embodiment of this application. Contents in this embodiment that are the same as or similar to those in the above embodiments can be referred to the above description and will not be repeated hereafter.

[0138] Optionally, in step S10, the step of updating the programmable compensation delay required for the signal channel according to a preset clock cycle to obtain the coarse adjustment compensation amount includes steps S11-S12.

[0139] Step S11: Determine the quantization step size based on the preset clock cycle;

[0140] Optionally, the quantization step size can be determined based on the clock cycle according to the N:1 OSERDES module (parallel-to-serial converter module). N can be the serialization ratio of the OSERDES module, i.e., the parallel data width, and can be equal to the cycle length N bits.

[0141] Optionally, in step S11, the step of determining the quantization step size according to the preset clock cycle includes steps c10-c20.

[0142] Step c10: Determine the minimum adjustable resolution of the parallel clock cycle;

[0143] Step c20: Based on the preset serialization ratio, the minimum adjustable resolution is converted into the minimum coarse adjustment resolution of the serial clock cycle, and the minimum coarse adjustment resolution is used as the quantization step size.

[0144] Alternatively, the minimum adjustable resolution can be converted from the parallel clock cycle to the minimum coarse adjustment resolution within the serial clock cycle via the OSERDES module.

[0145] Optionally, the minimum adjustable resolution within the parallel clock cycle can be obtained first, and the minimum adjustable resolution within the parallel clock cycle can be converted into the minimum coarse adjustment resolution within the serial clock cycle according to the following formula (II).

[0146] Formula (II);

[0147] in, For parallel clock cycles, such as 5ns; Where N is the serial clock period, for example, 625ps; and N is the serialization ratio, for example, 8, satisfying the following conditions: Requirements.

[0148] Optionally, in response to obtaining the serial clock period corresponding to the minimum adjustable resolution, the serial clock period can be used as the quantization step size.

[0149] Alternatively, after determining the minimum coarse adjustment resolution within the serial clock cycle, the minimum coarse adjustment resolution within the serial clock cycle can be directly used as the quantization step size, such as 625ps. Alternatively, the minimum coarse adjustment resolution within the serial clock cycle can be processed (such as increased or decreased) to obtain the quantization step size.

[0150] For example, with For example, with a resolution of 5ns (200MHz) and N=8, the minimum coarse adjustment resolution is... At this point, the minimum coarse adjustment resolution can be set to 625 ps as the quantization step size.

[0151] In this embodiment, the minimum adjustable resolution within the parallel clock cycle is converted into the minimum coarse adjustment resolution within the serial clock cycle according to a preset serialization ratio, and this is used as the quantization step size. This enables the conversion of the minimum adjustable resolution from the parallel clock cycle to the serial clock cycle, facilitating efficient delay compensation processing of the signal channel in the future.

[0152] Step S12: Update the programmable compensation delay according to the quantization step size to obtain the coarse adjustment compensation amount.

[0153] Optionally, after determining the quantization step size, the programmable compensation delay can be coarsely adjusted and updated based on the quantization step size to obtain the coarse adjustment compensation amount. For example, the programmable compensation delay can be increased or decreased based on the quantization compensation to obtain the coarse adjustment compensation amount.

[0154] Optionally, step S12, which updates the programmable compensation delay based on the quantization step size to obtain the coarse adjustment compensation amount, includes steps d10-d20.

[0155] Step d10: The comparison result of programmable compensation delay and quantization step size is rounded and quantized to obtain the integer number of serial clock cycles.

[0156] Optionally, you can first determine Included Total number of cycles, and for Perform rounding quantization, such as rounding to the nearest integer, to obtain the integer number of periods. For example, the number of integer cycles can be calculated using the following formula (iii).

[0157] Formula (3).

[0158] Step d20: Update the integer number of cycles based on the quantization step size to obtain the coarse adjustment compensation amount.

[0159] Optionally, the same operation can be performed for each signal channel to obtain the coarse adjustment compensation amount corresponding to each signal channel. For example, the coarse adjustment compensation amount can be obtained by multiplying the quantization step size and the integer number of cycles. For example, the coarse adjustment compensation amount can be calculated according to the following formula (iv).

[0160] Formula (IV).

[0161] Optionally, the coarse adjustment compensation amount can be Integer multiples of.

[0162] Optionally, a coarse adjustment compensation model can be constructed, and the programmable compensation delay and quantization step size can be input into the coarse adjustment compensation model to output the coarse adjustment compensation amount. The operations of steps d10-d20 can be performed in the coarse adjustment compensation model.

[0163] Optionally, the function corresponding to the coarse adjustment compensation model can be as shown in Formula (V).

[0164] Formula (5);

[0165] in, This is the coarse adjustment compensation amount; round() is for rounding to the nearest integer. For serial clock cycles; Programmable delay compensation; The number of cycles is an integer.

[0166] Optionally, the programmable compensation delay can be quantized by rounding (e.g., rounding to the nearest integer) to obtain the closest... Integer multiples of .

[0167] In this embodiment, the comparison results of the programmable delay and the quantization step size are rounded to obtain an integer number of cycles. Then, the integer number of cycles is updated according to the quantization step size to obtain the coarse adjustment compensation amount, thereby ensuring the effectiveness of the obtained coarse adjustment compensation amount.

[0168] Optionally, the programmable compensation delay can be updated according to steps d10-d20 to obtain the coarse adjustment compensation amount.

[0169] In this embodiment, by determining the quantization step size based on the clock cycle and updating the programmable compensation delay based on the quantization step size, the coarse adjustment compensation amount is obtained. This ensures that the coarse adjustment compensation amount of each signal channel is closely related to the specific clock cycle, thus guaranteeing the effectiveness of the final coarse adjustment compensation amount.

[0170] Optionally, after step S10, which updates the programmable compensation delay required for the signal channel according to a preset clock cycle to obtain the coarse adjustment compensation amount, steps e10-e20 are included.

[0171] Step e10: Determine the delay remainder between the programmable compensation delay and the coarse adjustment compensation amount;

[0172] Step e20, in response to the absolute value of the delay remainder being less than or equal to half a serial clock cycle, execute the step of determining the parallel clock cycle of the first cycle compensation coefficient and the serial clock cycle of the second cycle compensation coefficient based on the coarse adjustment compensation amount.

[0173] Optionally, after determining the coarse adjustment compensation amount for each signal channel, the delay remainder corresponding to each signal channel can be calculated. For example, the delay remainder can be calculated using the following formula (vi).

[0174] Formula (VI);

[0175] Where R is the delay remainder.

[0176] Optionally, after obtaining the delay remainder, the absolute value of the delay remainder can be judged. When the absolute value of the delay remainder is less than or equal to the serial clock period, subsequent signal channel delay compensation processing can be performed.

[0177] Optionally, the delay remainder can be input into the following formula (VII) for judgment.

[0178] Formula (VII);

[0179] Alternatively, the delay remainder represents the residual error that cannot be completely eliminated. Due to the rounding principle, the absolute value of this delay remainder R is strictly limited to half a digit. Within the period.

[0180] In this embodiment, the delay remainder between the programmable compensation delay and the coarse adjustment compensation amount is determined, and the signal channel delay compensation operation is continued when the absolute value of the delay remainder is less than or equal to half a serial clock cycle, so as to avoid the phenomenon that the delay compensation fails due to the delay remainder being too large.

[0181] Optionally, step S20, which involves determining the parallel clock period of the first period compensation coefficient and the serial clock period of the second period compensation coefficient based on the coarse adjustment compensation amount, includes steps f10-f40.

[0182] Step f10: Determine the integer number of serial clock cycles;

[0183] Step f20: Determine the first cycle compensation coefficient based on the comparison result between the integer number of cycles and the preset serialization ratio;

[0184] Step f30: Perform a modulo operation on the serialization ratio and the integer number of cycles to obtain the second cycle compensation coefficient;

[0185] Step f40: Decompose the coarse adjustment compensation amount according to the first cycle compensation coefficient and the second cycle compensation coefficient to obtain the parallel clock period of the first cycle compensation coefficient and the serial clock period of the second cycle compensation coefficient.

[0186] Optionally, the coarse adjustment compensation amount can be adjusted. The compensation is converted into two configurable integer parameters: the first-cycle compensation coefficient M and the second-cycle compensation coefficient K, and the compensation is performed in the low-speed parallel clock domain. The first-cycle compensation coefficient M can represent the large-cycle compensation coefficient, representing... Number of cycles; the second cycle compensation coefficient K can represent the small cycle compensation coefficient, representing Number of cycles.

[0187] Alternatively, the serial clock period can be determined first. Integer number of periods The specific value can be determined by referring to formula (III) above.

[0188] Optionally, the number of integer periods can be calculated. The result of comparing with the serialization ratio N is used as the first cycle compensation coefficient M. For example, the first cycle compensation coefficient M is calculated according to the following formula (8).

[0189] Formula M=Q / N (8);

[0190] Optionally, the first cycle compensation coefficient M corresponds to the switching or adjustment of the parallel clock. The first cycle of macroscopic delay compensation is achieved cyclically. And M can be... Integer multiples of.

[0191] Optionally, a modulo operation can be performed on the serialization ratio and the integer number of cycles to obtain... The remainder is used as the second-cycle compensation coefficient K. For example, the second-cycle compensation coefficient K is calculated according to the following formula (IX).

[0192] Formula (IX);

[0193] Optionally, the second-cycle compensation coefficient K corresponds to the second-cycle micro-delay compensation achieved through the phase adjustment function within the OSERDES module. Furthermore, K can be... The integer multiples of K, and 0 ≤ K < N (e.g., 0 ≤ K < 8).

[0194] In this embodiment, the first cycle compensation coefficient is determined by comparing the integer number of cycles and the serialization ratio, and the second cycle compensation coefficient is determined by performing a modulo operation on the serialization ratio and the integer number of cycles. Then, the coarse adjustment compensation amount is decomposed based on the first and second cycle compensation coefficients so that the signal channels can be compensated in stages. This includes a wide range of macroscopic delay compensation in the first cycle and high-precision microscopic delay compensation in the second cycle. This allows for effective delay compensation for multiple signal channels at both macroscopic and microscopic levels, achieving timing synchronization between multiple signal channels.

[0195] Reference Figure 3 , Figure 3 This diagram illustrates the third step of the signal channel delay compensation method provided in this application. Contents identical or similar to those in the above embodiments can be referred to the above description and will not be repeated hereafter. Optionally, the signal channel delay compensation method further includes steps S100-S400.

[0196] Step S100: Determine the programmable compensation delay required for each signal channel in the multi-channel signal channel of the test equipment;

[0197] Optionally, the total transmission path of a signal (such as test signal data) from inside the FPGA to the device under test (such as a test device) can be accurately modeled. The total delay of any signal channel (such as the first total delay) can be composed of programmable compensated delay, FPGA inherent delay, and external hardware delay.

[0198] Alternatively, the same operation can be performed on each of the multiple signal channels (e.g., 8 signal channels) of the test equipment, such as determining the programmable compensation delay required for each signal channel.

[0199] Optionally, step S100, which involves determining the programmable compensation delay required for each signal channel in the multiple signal channels of the test equipment, includes steps g10-g30.

[0200] Step g10: Determine the first total delay difference of each signal channel relative to a preset reference channel;

[0201] Optionally, the preset reference channel can be a pre-set signal channel or a signal channel selected from multiple signal channels, such as the first selected signal channel.

[0202] Optionally, the first total delay difference can be the total delay difference between the signal channel and the reference channel.

[0203] Optionally, step g10, which involves determining the first total delay difference of each signal channel relative to a preset reference channel, includes step g11.

[0204] Step g11: In response to the programmable compensation delay of each signal channel being set to zero, the first total delay difference corresponding to each signal channel is determined based on the second total delay of each signal channel and the third total delay of the reference channel.

[0205] Optionally, the second total delay can be the total delay of the signal channel; the third total delay can be the total delay of the reference channel.

[0206] Optionally, when determining the first total delay difference of each signal channel relative to the reference channel, the programmable compensation delay of all channels (i.e., signal channels and reference channels) can be configured to 0 first, and then the total delay difference of all signal channels i relative to the reference channel j can be initialized using a high-precision oscilloscope and used as the first total delay difference.

[0207] For example, the first total delay difference corresponding to the signal channel can be calculated according to the following formula (x).

[0208] Formula (10);

[0209] in, This is the first total delay difference; This is the second total delay of the signal channel; This is the third total delay for the reference channel.

[0210] In this embodiment, when the programmable compensation delay is zero, the first total delay difference of each signal channel relative to the reference channel is determined based on the second total delay of each signal channel and the third total delay of the reference channel, thereby ensuring the accuracy of the determined first total delay difference.

[0211] Step g20: Determine the signal channel with the smallest delay based on the first total delay difference corresponding to each signal channel, and use the first total delay difference corresponding to the signal channel with the smallest delay as the second total delay difference;

[0212] Optionally, since the programmable delay compensation method implemented by FPGA can only increase the delay and cannot achieve negative delay (i.e., make the signal arrive earlier), the first total delay difference corresponding to each signal channel can be normalized, and the minimum delay difference can be found, that is, the signal channel with the minimum delay is determined, and the first total delay difference corresponding to the signal channel with the minimum delay is used as the second total delay difference.

[0213] Optionally, a minimum value can be determined from the first total delay difference corresponding to each signal channel, and the signal channel corresponding to the minimum value is the signal channel with the fastest physical path and the smallest delay.

[0214] For example, the minimum value among the various first total delay differences can be determined by the following formula (XI), that is, if there exists One signal channel (e.g., 6 signal channels) can determine The first total delay difference corresponding to each signal channel in each signal channel is then processed. The cross-comparison operation between each signal channel is used to determine The smallest total delay difference among the first total delay differences corresponding to each signal channel is taken as the minimum value among all the first total delay differences (i.e., the second total delay difference).

[0215] Formula (XI);

[0216] in, This represents the minimum value among the various first total delay differences (i.e., the second total delay difference), such as a negative number or 0; Indicates the number of signal channels.

[0217] Step g30: For each signal channel, update the first total delay difference of the signal channel based on the absolute value of the second total delay difference to obtain the programmable compensated delay.

[0218] Optionally, after determining the second total delay difference corresponding to the signal channel with the smallest delay, this can be used as a reference zero point to determine the value of the programmable compensation delay required for each signal channel (in this embodiment, programmable compensation delay is used for brief explanation).

[0219] Optionally, for each signal channel, the absolute value of the second total delay difference can be determined, and the absolute value of the second total delay difference can be added to the first total delay difference of the signal channel to update the first total delay difference of the signal channel, thereby obtaining the programmable compensated delay of the signal channel.

[0220] Optionally, the absolute value of the second total delay difference As a base delay offset that needs to be added to all signal channels, the programmable compensated delay of each signal channel is obtained.

[0221] Optionally, the programmable compensation delay of the signal channel can be calculated and determined according to the following formula (xii).

[0222] Formula (12).

[0223] In this embodiment, the signal channel with the smallest delay among the multiple signal channels is determined based on each first total delay difference, and its corresponding first total delay difference is used as the second total delay difference. Then, the first total delay difference of each signal channel is updated based on the absolute value of the second total delay difference to obtain the programmable compensated delay, thereby ensuring the accuracy and effectiveness of the obtained programmable compensated delay.

[0224] Step S200: Determine the FPGA inherent delay and external hardware delay for each signal channel;

[0225] Optionally, the inherent delay of the FPGA includes logic processing delay, serialization delay, and internal routing delay.

[0226] Optionally, referring to formula (xiii), it can be determined that the inherent delay of the FPGA consists of logic processing delay, serialization delay, and internal routing delay.

[0227] Formula (XIII);

[0228] in, Indicates the inherent delay of the FPGA; This represents the logic processing delay, which is the processing time for the FPGA core logic to generate data. This represents the serialization delay of the OSERDES module, which is the inherent delay of the OSERDES module in converting parallel data into serial data. This indicates the internal wiring delay, which is the delay caused by the wiring between the output of the FPGA's internal logic unit and the input of the OSERDES module.

[0229] Optionally, external hardware delays include PCB trace delays, cable delays, and load board delays.

[0230] Optionally, referring to formula (xiv), the external hardware delay can be determined to consist of PCB trace delay, cable delay, and load board delay.

[0231] Formula (XIV);

[0232] in, This indicates external hardware delay, which is the main source of delay differences between signal channels; This indicates the PCB trace delay, which is the delay of the signal traveling from the FPGA pin to the connector on the PCB trace. This indicates cable delay, such as the cable delay of signal channel i (e.g., 1). It represents the delay of connector and cable transmission and is the main source of delay differences between multiple channels. This indicates the load board delay, such as the load board delay of signal channel i, which is the signal routing delay on the DUT interface board.

[0233] Step S300: For each signal channel, the first total delay of the signal channel is determined using a model characterizing the total delay of the signal channel, based on the programmable compensated delay, the inherent delay of the FPGA, and the external hardware delay.

[0234] Optionally, the function corresponding to the model characterizing the total delay of the signal channel can be as shown in the following formula (XV).

[0235] Formula (XV);

[0236] in, This refers to the total delay of the signal channel, such as the first total delay. The programmable compensation delay for channel i is provided by a programmable digital delay unit implemented with general logic resources (e.g., a programmable digital delay method implemented with Verilog HDL code). The inherent delay of channel i in the FPGA; External hardware delay for channel i.

[0237] Step S400: In response to a first total delay mismatch corresponding to at least two signal channels, perform the following step for each of the multiple signal channels of the test equipment to update the programmable compensation delay required for the signal channel according to a preset clock cycle, thereby obtaining the coarse adjustment compensation amount.

[0238] Optionally, in this embodiment, the programmable compensation delay of each signal channel is precisely configured. So that The first total delay of each signal channel Equal, for example The first total delay of the first signal channel is... The first total delay of the second signal channel is , No. The first total delay of each signal channel is .

[0239] Optionally, after determining the first total delay of each signal channel, the first total delays can be matched to determine whether the first total delays are equal or whether the absolute difference between two first total delays is less than a preset threshold (e.g., 1 ps).

[0240] Optionally, if there is a mismatch in the first total delay corresponding to at least two signal channels (e.g., the first total delays corresponding to the at least two signal channels are not equal, or the absolute difference between them is greater than or equal to a preset threshold), then it can be determined that programmable delay compensation needs to be applied to the at least two signal channels. The adjustment involves executing steps S10-S40 in the above embodiment, and then continuing to execute steps S100-S400 in the next cycle. For example, it involves continuing to determine whether the first total delay of each signal channel is equal. If they are not equal, signal channel delay compensation adjustment is performed until the first total delay of each signal channel is equal.

[0241] In this embodiment, for each signal channel, based on the model characterizing the total delay of the signal channel, and based on the inherent delay of the FPGA and the external hardware delay of each signal channel, the first total delay of each signal channel is determined. When the first total delays of at least two signal channels do not match, steps S10-S40 in the above embodiment can be executed to achieve delay compensation for multiple signal channels. When performing delay compensation, for each signal channel in the test equipment, the programmable compensation delay required by the signal channel is updated according to a preset clock cycle (such as parallel clock cycle and serial clock cycle) to obtain the coarse adjustment compensation amount. Thus, the coarse adjustment compensation amount can be determined solely through the general logic resources inside the FPGA, so that delay compensation for each signal channel can be performed subsequently. This eliminates the need to rely on the scarce and limited ODELAY hard core resources in the FPGA resource area, avoiding the resource constraints and insufficient delay range faced in multi-channel synchronous scenarios. Furthermore, the coarse adjustment compensation amount is decomposed into the parallel clock cycle of the first-cycle compensation coefficient and the serial clock cycle of the second-cycle compensation coefficient. This transforms the complex delay compensation problem into an integer configuration problem (i.e., configuring the two integer coefficients, the first-cycle compensation coefficient and the second-cycle compensation coefficient). All logic control can operate in the low-speed clock domain. This purely digital implementation significantly reduces the timing convergence difficulty and simplifies the design and verification steps. Moreover, the first-cycle macroscopic delay compensation is performed on the signal channel based on the parallel clock cycle of the first-cycle compensation coefficient. This enables large-scale first-cycle macroscopic delay compensation based on the first-cycle compensation coefficient. The compensation range corresponding to the first-cycle compensation coefficient is only limited by the data length of the FPGA's internal logic and can be easily extended to tens or even hundreds of parallel clock cycles, effectively addressing the ultra-large delay differences caused by long-distance cables. Furthermore, based on the serial clock cycle of the second-cycle compensation coefficient, the signal channel will undergo second-cycle micro-delay compensation. This enables high-precision second-cycle micro-delay compensation based on the second-cycle compensation coefficient. Therefore, by performing first-cycle macro-delay compensation and second-cycle micro-delay compensation on the same signal channel, hierarchical high-precision control of the signal channel can be achieved. For example, a wide range of first-cycle macro-delay compensation and high-precision second-cycle micro-delay compensation can be achieved. This allows for effective delay compensation of multiple signal channels at both macro and micro levels, thus achieving timing synchronization between multiple signal channels.

[0242] In addition, to aid in understanding the principle of signal channel delay compensation in the embodiments of this application, examples are provided below.

[0243] For example, such as Figure 4 As shown, when signal channel delay compensation begins, the initial configuration of the model is performed first, such as determining the programmable compensation delay, FPGA inherent delay, and external hardware delay for each signal channel. The programmable compensation delay can be precisely configured to achieve the goal of synchronizing all signal channels. Delay difference measurement can be performed. For example, the first total delay difference of all signal channels relative to the reference channel can be measured using an oscilloscope, and the minimum delay difference can be determined. For example, the second total delay difference corresponding to the signal channel with the smallest delay can be determined. Then, normalization processing can be performed. For example, for each signal channel, the first total delay difference of the signal channel can be updated based on the absolute value of the second total delay difference to obtain the programmable compensation delay. Then, the programmable compensation delay can be subjected to hierarchical quantization processing. For example, the programmable compensation delay required by the signal channel can be updated based on a preset clock cycle to obtain the coarse adjustment compensation amount. Then, the parameters can be decomposed. For example, based on the coarse adjustment compensation amount, the parallel clock cycle of the first cycle compensation coefficient and the serial clock cycle of the second cycle compensation coefficient can be determined. Then, hardware configuration can be performed. That is, the first cycle macroscopic delay compensation can be performed by combining the first multiplexer and the shift register chain, as well as the parallel clock cycle of the first cycle compensation coefficient. Alternatively, the second cycle microscopic delay compensation can be performed by combining the second multiplexer and the serial clock cycle of the second cycle compensation coefficient, until all signal channels have completed delay compensation, and then the end / synchronization completion can be determined.

[0244] The following is for reference. Figure 5 This is a schematic diagram of a test system 400 provided in an embodiment of this application. The test system 400 includes a controller 410 and a memory 420. The controller 410 and the memory 420 are electrically connected directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0245] The memory 420 stores a computer program that can be executed by the controller 410. The controller reads / writes the data or computer program stored in the memory 420 and performs corresponding functions. For example, when the computer program stored in the memory 420 is executed by the controller 410, the signal channel delay compensation method disclosed in the above embodiments can be implemented.

[0246] It should be understood that, Figure 5 The structure shown is only a schematic diagram of the test system 400. The test system 400 may also include a ratio Figure 5The more or fewer components shown, or having the same Figure 5 The different configurations shown. Figure 5 The components shown can be implemented using hardware, software, or a combination thereof.

[0247] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the signal channel delay compensation method in the above embodiments.

[0248] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0249] The aforementioned computer-readable storage medium may be contained within a memory or may exist independently without being assembled into a memory.

[0250] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the memory, cause the memory to:

[0251] For each signal channel in the multi-channel test equipment, the programmable compensation delay required by the signal channel is updated according to the preset clock cycle to obtain the coarse adjustment compensation amount. The clock cycle includes the parallel clock cycle and the serial clock cycle.

[0252] The parallel clock period for the first cycle compensation coefficient and the serial clock period for the second cycle compensation coefficient are determined based on the coarse adjustment compensation amount.

[0253] The signal channel is subjected to macroscopic delay compensation for the first cycle based on the parallel clock cycle of the first cycle compensation coefficient;

[0254] The signal channel is subjected to second-cycle micro-delay compensation based on the serial clock cycle of the second-cycle compensation coefficient.

[0255] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0256] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0257] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0258] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described signal channel delay compensation method. This solves the technical problem of how to effectively compensate for the delay of multiple signal channels to achieve timing synchronization between them. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the signal channel delay compensation method provided in the above embodiments, and will not be repeated here.

[0259] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the signal channel delay compensation method described above.

[0260] The computer program product provided in this application can solve the technical problem of how to effectively compensate for the delay of multiple signal channels in order to achieve timing synchronization between multiple signal channels. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the signal channel delay compensation method provided in the above embodiments, and will not be repeated here.

[0261] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A signal channel delay compensation method, characterized in that, The signal channel delay compensation method is applied to FPGA and includes: For each signal channel in the multi-channel test equipment, the programmable compensation delay required by the signal channel is updated according to a preset clock cycle to obtain the coarse adjustment compensation amount. The clock cycle includes a parallel clock cycle and a serial clock cycle. The parallel clock period of the first cycle compensation coefficient and the serial clock period of the second cycle compensation coefficient are determined based on the coarse adjustment compensation amount. The signal channel is subjected to first-cycle macroscopic delay compensation based on the parallel clock cycle of the first-cycle compensation coefficient. The signal channel is subjected to second-cycle micro-delay compensation based on the serial clock cycle of the second-cycle compensation coefficient. The step of performing first-cycle macroscopic delay compensation on the signal channel based on the parallel clock cycle of the first-cycle compensation coefficient includes: Determine the compensation coefficient range that includes the first period compensation coefficient, determine the third period compensation coefficient that is greater than the maximum value in the compensation coefficient range, and determine the fourth period compensation coefficient that is located in the compensation coefficient range. In the historical parallel data with a data length equal to the third cycle compensation coefficient, the first parallel data after the parallel clock cycle delay by the fourth cycle compensation coefficient is determined, and the first parallel data is output as the current cycle parallel data. The FPGA includes an interconnected chain of shift registers and multiplexers. The step of determining the first parallel data after a parallel clock cycle delay of the fourth cycle compensation coefficient from historical parallel data with a data length equal to the third cycle compensation coefficient includes: Determine the shift register chain containing historical parallel data with a data length equal to the third cycle compensation coefficient; Based on the multiplexer, the historical parallel data after the parallel clock cycle delay by the fourth cycle compensation coefficient is selected from the historical parallel data of the shift register chain as the first parallel data; The step of performing second-cycle micro-delay compensation on the signal channel based on the serial clock cycle of the second-cycle compensation coefficient includes: Determine a data window containing a second parallel data of two cycle lengths, wherein the second parallel data includes the current cycle parallel data and the previous cycle parallel data; Based on the serial clock period of the second period compensation coefficient, a parallel data of a period length is selected out of the data window as the third parallel data output. The step of selecting a parallel data of a certain period length in the data window as the third parallel data output based on the serial clock period of the second period compensation coefficient includes: In the second parallel data contained in the data window, starting from the position of the parallel data after the serial clock cycle delay of the second cycle compensation coefficient, and ending at the position of the parallel data after one cycle length, the second parallel data is sliced ​​to obtain parallel data of one cycle length, and the parallel data of one cycle length is output as the third parallel data.

2. The signal channel delay compensation method as described in claim 1, characterized in that, The step of updating the programmable compensation delay required for the signal channel according to a preset clock cycle to obtain the coarse adjustment compensation amount includes: The quantization step size is determined based on the preset clock cycle; The programmable compensation delay is updated based on the quantization step size to obtain the coarse adjustment compensation amount.

3. The signal channel delay compensation method as described in claim 2, characterized in that, The step of determining the quantization step size based on a preset clock period includes: Determine the minimum adjustable resolution of the parallel clock cycle; The minimum adjustable resolution is converted into the minimum coarse adjustment resolution of the serial clock cycle according to the preset serialization ratio, and the minimum coarse adjustment resolution is used as the quantization step size.

4. The signal channel delay compensation method as described in claim 2, characterized in that, The step of updating the programmable compensation delay based on the quantization step size to obtain the coarse adjustment compensation amount includes: The comparison result of the programmable compensation delay and the quantization step size is rounded and quantized to obtain the integer number of serial clock cycles. The integer number of cycles is updated based on the quantization step size to obtain the coarse adjustment compensation amount.

5. The signal channel delay compensation method as described in claim 1, characterized in that, After the step of updating the programmable compensation delay required for the signal channel according to a preset clock cycle to obtain the coarse adjustment compensation amount, the following steps are included: Determine the delay remainder between the programmable compensation delay and the coarse adjustment compensation amount; In response to the absolute value of the delay remainder being less than or equal to half of the serial clock cycle, the step of determining the parallel clock cycle of the first cycle compensation coefficient and the serial clock cycle of the second cycle compensation coefficient based on the coarse adjustment compensation amount is performed.

6. The signal channel delay compensation method as described in claim 1, characterized in that, The step of determining the parallel clock period of the first cycle compensation coefficient and the serial clock period of the second cycle compensation coefficient based on the coarse adjustment compensation amount includes: Determine the integer number of the serial clock cycles; The first cycle compensation coefficient is determined based on the comparison between the integer number of cycles and the preset serialization ratio; The second cycle compensation coefficient is obtained by performing a modulo operation on the serialization ratio and the integer number of cycles. The coarse adjustment compensation amount is decomposed based on the first period compensation coefficient and the second period compensation coefficient to obtain the parallel clock period of the first period compensation coefficient and the serial clock period of the second period compensation coefficient.

7. The signal channel delay compensation method according to any one of claims 1-6, characterized in that, The signal channel delay compensation method further includes: Determine the required programmable compensated delay for each signal channel in the multi-channel test equipment; Determine the FPGA's inherent delay and external hardware delay for each signal channel; For each signal channel, the first total delay of the signal channel is determined using a model characterizing the total delay of the signal channel, based on the programmable compensated delay, the inherent delay of the FPGA, and the external hardware delay. In response to a first total delay mismatch corresponding to at least two signal channels, the step of updating the programmable compensation delay required for each of the multiple signal channels for the test equipment according to a preset clock cycle to obtain the coarse adjustment compensation amount is performed.

8. The signal channel delay compensation method as described in claim 7, characterized in that, The step of determining the programmable compensation delay required for each signal channel in the multiple signal channels of the test equipment includes: Determine the first total delay difference of each signal channel relative to a preset reference channel; The signal channel with the smallest delay is determined based on the first total delay difference corresponding to each signal channel, and the first total delay difference corresponding to the signal channel with the smallest delay is used as the second total delay difference; For each of the signal channels, the first total delay difference of the signal channel is updated based on the absolute value of the second total delay difference to obtain a programmable compensated delay.

9. The signal channel delay compensation method as described in claim 8, characterized in that, The step of determining the first total delay difference of each signal channel relative to a preset reference channel includes: In response to the programmable compensation delay of each signal channel being set to zero, a first total delay difference corresponding to each signal channel is determined based on the second total delay of each signal channel and the third total delay of the reference channel.

10. The signal channel delay compensation method as described in claim 7, characterized in that, The signal channel delay compensation method further includes at least one of the following: The inherent delay of the FPGA includes logic processing delay, serialization delay, and internal routing delay; The external hardware delays include PCB trace delays, cable delays, and load board delays.

11. A testing system, characterized in that, The test system includes a controller and a memory, the memory storing a computer program, and the controller executing the computer program to implement the signal channel delay compensation method according to any one of claims 1-10.

Images