Exposure head and image forming apparatus

Abstract

The invention discloses an exposure head and an image forming apparatus. The exposure head for exposing a photosensitive drum includes: a substrate; a plurality of strip-shaped semiconductor chips provided with a plurality of light emitting elements for emitting light and a driving circuit for driving the light emitting elements, the plurality of strip-shaped semiconductor chips being arranged on the substrate; and a lens array that converges light from the light emitting element onto the photosensitive drum. The driving circuit operates between a first potential and a second potential, the light emitting element operates between a third potential and a fourth potential, and a potential difference between the third potential and the fourth potential is equal to or greater than a potential difference between the first potential and the second potential.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202180083734.9, filed on August 25, 2021, entitled "Exposure Head and Image Forming Apparatus". Technical Field

[0002] The present invention relates to an exposure head for an exposure photosensitive drum and an image forming apparatus including the exposure head. Background Technology

[0003] To date, printers used in electrophotographic systems are generally known to form latent images by exposing a photosensitive drum using an exposure head made of LEDs, organic ELs, etc. Such an exposure head includes rows of light-emitting elements arranged in the longitudinal direction of the photosensitive drum and a bar lens array that forms an image of the light from these rows on the photosensitive drum. The LEDs or organic ELs used as light-emitting elements are arrays of light-emitting elements in which the direction of light from the light-emitting surface is parallel to the optical axis of the bar lens array.

[0004] Here, in the exposure head, the length of the light-emitting element array is determined based on the width of the image-forming area on the photosensitive drum, and the spacing between the light-emitting elements is determined based on the printer's image resolution. For example, in a 1200 dpi printer, since the pixel spacing is 21.16 μm (rounded down to two decimal places), the spacing between the light-emitting elements is also 21.16 μm. Because printers using this type of exposure head use fewer components compared to laser scanning systems that use multi-sided motors to perform deflection scanning of the laser beam, it is easier to reduce the size and cost of the device.

[0005] Furthermore, in recent years, techniques for reducing device size by mounting the light-emitting element and driving circuitry on the same chip have also been known. For example, an exposure head is known in which an integrated circuit for driving and electrodes are formed on a Si substrate, and an organic EL film is deposited thereon to integrate the light-emitting element and driving circuitry into a single chip. Additionally, Japanese Patent Publication No. 2015-112856 discloses an exposure head in which a TFT circuit and an organic EL are disposed on a transparent glass substrate.

[0006] However, in exposure heads configured where the light-emitting element and driving circuitry are integrated into a single chip according to relevant technologies, it is necessary to form the integrated circuit using a relatively high-voltage semiconductor process to ensure the forward voltage of the light-emitting element and obtain a predetermined amount of light emission. A problem arises when forming the driving circuitry using such a high-voltage semiconductor process: the transistor size increases, resulting in an increase in chip size. Summary of the Invention

[0007] The object of the present invention is to provide an exposure head that, in a configuration where the light-emitting element and the driving circuit are formed into a single chip, enables the driving circuit to be formed using a low-voltage semiconductor process while ensuring the forward voltage of the light-emitting element and reducing the chip size.

[0008] A representative configuration of the present invention is an exposure head configured to expose a photosensitive drum. The exposure head includes: a substrate; a plurality of strip-shaped semiconductor chips, each strip-shaped semiconductor chip including a plurality of light-emitting elements and a driving circuit for driving the light-emitting elements, the plurality of strip-shaped semiconductor chips being arranged on the substrate; and a lens array configured to collect light from the light-emitting elements onto the photosensitive drum, wherein the driving circuit operates between a first potential and a second potential, the light-emitting elements operate between a third potential and a fourth potential, and the potential difference between the third potential and the fourth potential is equal to or greater than the potential difference between the first potential and the second potential.

[0009] Further features of the invention will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of an image forming apparatus according to a first embodiment of the present invention.

[0011] Figure 2 (a) and Figure 2 (b) is a schematic diagram of the exposure head and photosensitive drum according to the first embodiment of the present invention.

[0012] Figure 3 of (a) Figure 3 (b) and Figure 3 (c) is a schematic diagram illustrating the configuration of the exposure head according to a first embodiment of the present invention.

[0013] Figure 4 This is a schematic diagram of the light-emitting element array chip of the exposure head according to the first embodiment of the present invention.

[0014] Figure 5 It is along Figure 4 The cross-sectional view taken from line AA.

[0015] Figure 6 (a) and Figure 6 (b) is a schematic diagram illustrating the arrangement of light-emitting elements in the light-emitting element array chip of the exposure head according to the first embodiment of the present invention.

[0016] Figure 7 This is a schematic diagram illustrating a modified example of the arrangement of light-emitting elements in the light-emitting element array chip of the exposure head according to the first embodiment of the present invention.

[0017] Figure 8 This is a plan view illustrating the positional relationship between the light-emitting part of the exposure head and the rod lens according to the first embodiment of the present invention.

[0018] Figure 9 This is a block diagram illustrating the configuration of an exposure head according to a first embodiment of the present invention.

[0019] Figure 10 This is a block diagram illustrating the configuration of the light-emitting element array chip of the exposure head according to a first embodiment of the present invention.

[0020] Figure 11 This is a circuit configuration diagram of the data holding section of the light-emitting element array chip of the exposure head according to the first embodiment of the present invention.

[0021] Figure 12 This is a block diagram illustrating the configuration of the simulation section of the exposure head according to a first embodiment of the present invention.

[0022] Figure 13 This is a block diagram illustrating the configuration of the power supply section of the exposure head according to a first embodiment of the present invention.

[0023] Figure 14 This is a flowchart of the operation of the exposure head according to the first embodiment of the present invention.

[0024] Figure 15 This is a timing diagram illustrating the power supply voltage supplied to the light-emitting element array chip of the exposure head according to the first embodiment of the present invention.

[0025] Figure 16 This is a timing diagram of the light-emitting element array chip of the exposure head according to the first embodiment of the present invention.

[0026] Figure 17 This is a block diagram illustrating the configuration of the light-emitting element array chip of the exposure head according to a second embodiment of the present invention.

[0027] Figure 18 This is a block diagram illustrating the configuration of the simulation section of the exposure head according to a second embodiment of the present invention.

[0028] Figure 19 This is a block diagram illustrating the configuration of the power supply section of the exposure head according to a second embodiment of the present invention.

[0029] Figure 20 This is a flowchart of the operation of the exposure head according to the second embodiment of the present invention.

[0030] Figure 21 This is a timing diagram illustrating the power supply voltage supplied to the light-emitting element array chip of the exposure head according to the second embodiment of the present invention. Detailed Implementation

[0031] The embodiments will be described in detail below with reference to the accompanying drawings.

[0032] (First embodiment)

[0033] <Configuration of the image forming apparatus>

[0034] Reference Figure 1 The configuration of the image forming apparatus 1 according to the first embodiment of the present invention will be described in detail below.

[0035] The image forming apparatus 1 includes a scanner unit 100, an image creation unit 103, a fixing unit 104, a feed / transfer unit 105, and an alignment roller 110.

[0036] The scanner unit 100 illuminates the original document placed on the original document substrate to optically read the image of the original document, and converts the read image into an electrical signal to create image data. The scanner unit 100 outputs the created image data to a printer controller (not shown).

[0037] The image creation unit 103 operates under the control of the printer controller to form an image on a sheet conveyed from the alignment roller 110, and then conveys the image-bearing sheet to the fixing unit 104. The image creation unit 103 includes four image creation units that perform a series of electrophotographic processes including charging, exposure, development, and transfer. The image creation unit 103 forms a panchromatic image on the sheet using the four image creation units arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K). After a predetermined time has elapsed since the start of cyan image creation, the four image creation units sequentially perform magenta, yellow, and black image creation operations.

[0038] Specifically, the image creation unit 103 includes a photosensitive drum 102, an exposure head 106, a charger 107, a developing device 108, a transfer belt 111, and an optical sensor 113.

[0039] The photosensitive drum 102, which serves as an image carrier, is attached to the image forming apparatus 1 via an attachment member (not shown) and is driven to rotate.

[0040] Exposure head 106 is attached to image forming apparatus 1 via attachment members (not shown). Exposure head 106 includes four exposure heads 106a, 106b, 106c, and 106d corresponding to four image creation units. Exposure head 106 collects light emitted according to image data onto photosensitive drum 102 and performs exposure to form a latent image (electrostatic latent image) on photosensitive drum 102. Note that details of the configuration of exposure head 106 will be described below.

[0041] Charger 107 charges photosensitive drum 102.

[0042] The developing apparatus 108 supplies toner to the latent image formed on the photosensitive drum 102 and develops the latent image to form a toner image (developer image) on the photosensitive drum 102.

[0043] The transfer belt 111 conveys the sheet from the alignment roller 110 to the fixing unit 104. The toner image developed by the developing equipment 108 is transferred to the sheet conveyed by the transfer belt 111.

[0044] An optical sensor 113 is positioned facing the transfer belt 111 and detects the position of the test pattern printed on the transfer belt 111 to obtain the color offset between image creation units. The optical sensor 113 outputs the detection result of the test pattern position to an image controller unit (not shown). Based on the detection result of the test pattern position input from the optical sensor 113, the image controller unit performs control to obtain the color offset between the image creation units of the image creation unit 103 and correct the image position of each color. A full-color toner image without color offset is transferred to the sheet through control.

[0045] The fixing unit 104 is implemented by a combination of rollers and is equipped with a heat source such as a halogen heater (not shown). The fixing unit 104 dissolves and fixes the toner on the sheet on which the toner image has been transferred by the image creation unit 103 through heat and pressure, and discharges the sheet with the toner fixed to the outside of the image forming apparatus 1 by the discharge roller 112.

[0046] The feeding / transfer unit 105 includes an internal feeding unit 109a, an internal feeding unit 109b, an external feeding unit 109c, and a manual feeding unit 109d, and feeds the sheet from the pre-indicated feeding units and transfers the sheet to the alignment roller 110.

[0047] When the toner image formed in the image creation unit 103 is transferred onto the sheet, the alignment roller 110 conveys the sheet conveyed by the feed / transfer unit 105 to the transfer belt 111.

[0048] The printer controller controls the operation of the scanner unit 100, image creation unit 103, fixing unit 104, and feed / transfer unit 105. The printer controller communicates with the MFP controller that controls the entire MFP (entire image forming apparatus 1), and controls the operation while managing the status of the scanner unit 100, image creation unit 103, fixing unit 104, and feed / transfer unit 105 according to the instructions of the MFP controller.

[0049] <Exposure head configuration>

[0050] Reference Figures 2 to 3The configuration of the exposure head 106 according to the first embodiment of the present invention will be described in detail below.

[0051] Figure 2 Figure (a) illustrates the arrangement of the exposure head 106 relative to the photosensitive drum 102, and Figure 2 (b) illustrates the state in which light emitted from the light-emitting element group 201 is collected on the photosensitive drum 102 by the bar lens array 203.

[0052] Figure 3 Figure (a) illustrates the surface of the printed circuit board 202 opposite to the surface on which the light-emitting element assembly 201 is mounted (hereinafter referred to as the "non-light-emitting element mounting surface"), and Figure 3 Figure (b) illustrates the surface on which the light-emitting element assembly 201 is mounted (hereinafter referred to as the "light-emitting element mounting surface"). Additionally, Figure 3 (c) illustrates the state of the boundary portion between the light-emitting element array chip 400-m (m is an integer of 1 or greater and 19 or less) and 400-m+1.

[0053] The exposure head 106 includes a light-emitting element group 201, a printed circuit board 202, a bar lens array 203, and a housing 204.

[0054] The light-emitting element group 201 is mounted on the light-emitting element mounting surface of the printed circuit board 202, and has 20 strip-shaped light-emitting element array chips 400-1 to 400-20 arranged in two staggered rows. The light-emitting element array chips 400-1 to 400-20 in each row are arranged along the longitudinal direction of the printed circuit board 202.

[0055] In the light-emitting element array chips 400-1 to 400-20 used as semiconductor chips, light-emitting elements 602 are arranged at predetermined spacings in the longitudinal direction (main scanning direction) and the lateral direction (sub-scanning direction) of the light-emitting element array chips 400-1 to 400-20. In each of the light-emitting element array chips 400-1 to 400-20, 748 light-emitting elements 602 are arranged at predetermined image resolution spacings in the X direction, which is the longitudinal direction. Here, the image resolution spacing is 1200 dpi (approximately 21.16 μm). Furthermore, as an example, the end-to-end distance of the 748 light-emitting elements 602 in each of the light-emitting element array chips 400-1 to 400-20 is approximately 15.8 mm.

[0056] In the light-emitting element group 201, since 20 light-emitting element array chips 400-1 to 400-20 are arranged in the longitudinal direction, the number of light-emitting elements that can be exposed is 14,960, and image formation corresponding to an image width of about 316 mm becomes possible.

[0057] In this example, the location is... Figure 3 The image resolution spacing between light-emitting elements 602-n and 602-1 at the boundary between the light-emitting element array chips 400-1 and 400-20 illustrated in (c) is also 1200 dpi (approximately 21.16 μm). Furthermore, the lateral spacing S between light-emitting elements 602-n and 602-1 is approximately 127 μm (six pixels at 1200 dpi and four pixels at 800 dpi). Additionally, the vertical spacing L between light-emitting elements 602-n and 602-1 is approximately 21.16 μm (one pixel at 1200 dpi). Note that the spacings S and L between light-emitting elements 602-n and 602-1 are not limited to the values ​​described above.

[0058] like Figure 3 As illustrated in (a), the printed circuit board 202, used as a board, has connectors 305 and driver ICs (not shown) for driving the light-emitting element group 201 on its non-light-emitting element mounting surface. Figure 3 As illustrated in (b), the light-emitting element group 201 is mounted on the light-emitting element mounting surface, which serves as the surface of the printed circuit board 202.

[0059] Connector 305 is connected via signal lines (not shown) to a driver IC and a power supply (not shown) disposed on the non-mounting surface of the light-emitting element on the printed circuit board 202, and is also connected to the light-emitting element group 201.

[0060] The rod lens array 203 is arranged at a predetermined distance from the light-emitting element group 201 and at a predetermined distance from the photosensitive drum 102, and forms an image of the light emitted from the light-emitting element group 201 on the photosensitive drum 102.

[0061] The bar lens array 203 and the printed circuit board 202 are attached to the housing 204.

[0062] The exposure head 106 with the above configuration is assembled individually in the factory, and focus adjustment and light intensity adjustment are performed to adjust the light spot at the light collection position to a predetermined size. Here, in focus adjustment, the attachment position of the rod lens array 203 is adjusted in such a way that the distance between the rod lens array 203 and the light-emitting element group 201 becomes a desired distance. In light intensity adjustment, each light-emitting element 602 of the light-emitting element group 201 emits light independently and sequentially, and the driving current for each light-emitting element 602 is adjusted in such a way that the light collected on the photosensitive drum 102 by the rod lens array 203 has a predetermined light intensity.

[0063] <Configuration of LED array chips>

[0064] Reference Figure 4 The configuration of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail.

[0065] The light-emitting element array chip 400 is a chip configured by setting a light-emitting element 602 on a Si substrate, and includes a light-emitting substrate 402, a light-emitting part 404, a circuit part 406, and a wiring bonding pad (WB pad) 408.

[0066] The light-emitting substrate 402 is a Si substrate, and the light-emitting part 404 and wiring bonding pad 408 are disposed on the light-emitting substrate 402. The circuit part 406 for controlling the light-emitting part 404 is built into the light-emitting substrate 402. Here, with the development of process technology for forming integrated circuits, Si substrates have been used as substrates for various integrated circuits. Therefore, it is advantageous to form high-speed and high-functionality circuits at high density and to have low-cost large-diameter wafers available.

[0067] The light-emitting part 404 includes a light-emitting element 602. Note that the details of the configuration of the light-emitting part 404 will be described below.

[0068] The circuit section 406 has a circuit configuration including an analog drive circuit, a digital control circuit, or both an analog drive circuit and a digital drive circuit, and controls the light-emitting section 404.

[0069] The wiring bonding pad 408 supplies power to the circuit section 406, or performs signal input and output between the light-emitting element array chip 400 and the outside.

[0070] <Configuration of the light-emitting part>

[0071] Reference Figure 5 The arrangement of the light-emitting portions 404 of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail.

[0072] The light-emitting part 404 includes a portion of the light-emitting substrate 402 and the upper electrode 508 facing each other, and a light-emitting layer 506 in the facing portion, and is configured by sequentially stacking a plurality of lower electrodes 504, light-emitting layers 506 and upper electrodes 508 on the light-emitting substrate 402.

[0073] The lower electrode 504 is a single electrode and is formed on the light-emitting substrate 402. The lower electrode 504 has a width W in the X direction, and a predetermined interval d is provided between multiple lower electrodes 504 adjacent to each other in the X direction. Together with the formation of the circuit section 406, the lower electrode 504 is formed using Si integrated circuit processing technology with a process rule of approximately 0.2 μm and high precision, and the lower electrode 504 is connected to the driving section (not shown) of the circuit section 406. As a result, the lower electrode 504 can be arranged with high density and high precision, and the light-emitting point of the light-emitting element 602 is substantially the same as the light-emitting point of the lower electrode 504; therefore, the light-emitting element 602 can be arranged with high density.

[0074] The lower electrode 504 is preferably formed of a metal with high reflectivity relative to the emission wavelength of the light-emitting layer 506, and is formed of silver (Ag), aluminum (Al), an alloy of silver and aluminum, etc.

[0075] The light-emitting layer 506 is formed on the lower electrode 504 and is, for example, an organic EL film or an inorganic EL film. When the light-emitting layer 506 is an organic EL film, it may be, as needed, a stacked structure including functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer.

[0076] When the light-emitting layer 506 is formed of a material susceptible to moisture, such as an organic or inorganic EL layer, it is desirable to perform a seal to prevent moisture from entering the light-emitting part 404. The light-emitting layer 506 prevents moisture from entering the light-emitting part 404 by forming a sealing film, such as a single thin film of silicon oxide, silicon nitride, or aluminum oxide, or by stacking thin films of silicon nitride, aluminum oxide, etc. As a method for forming the sealing film, a method with excellent covering performance, such as a stepped structure, is preferred, and atomic layer deposition (ALD) can be used, for example.

[0077] The light-emitting layer 506 can be formed continuously or divided into sections with substantially the same dimensions as the lower electrode 504. Furthermore, the materials, configurations, and formation methods of the sealing film are merely examples and are not limited to those described above; appropriate selection of suitable materials, configurations, and formation methods is sufficient.

[0078] The upper electrode 508 is a common electrode and is formed on the light-emitting layer 506. The upper electrode 508 is preferably transparent to the emission wavelength of the light-emitting layer 506, and a transparent electrode formed of indium tin oxide (ITO) can be used.

[0079] The light-emitting unit 404 with the above configuration energizes the light-emitting layer 506 by selecting a lower electrode 504 from among a plurality of lower electrodes 504 and an upper electrode 508, thereby causing the light-emitting layer 506 at the position corresponding to the selected lower electrode 504 to emit light. As a result, the light-emitting unit 404 emits light through the upper electrode 508 located on the side of the light-emitting layer 506 opposite to the side where the light-emitting substrate 402 is located.

[0080] By using a transparent electrode formed of indium tin oxide or the like as the upper electrode 508, the aperture ratio becomes essentially 100%, and the light emitted from the light-emitting layer 506 is emitted as is. Furthermore, by using high-precision Si integrated circuit processing technology to form the lower electrode 504, the lower electrode 504 can be arranged at a high density. Therefore, light can be emitted from essentially the entire area of ​​the light-emitting portion 404, and the utilization efficiency of the light-emitting portion 404 can be enhanced. Here, the area of ​​the light-emitting portion 404 is obtained by adding the total area of ​​the plurality of lower electrodes 504 to the total area of ​​the plurality of intervals d.

[0081] Arrangement of light-emitting elements in the light-emitting section

[0082] Reference Figures 6 to 8 The arrangement of the light-emitting element 602 of the light-emitting portion 404 of the exposure head 106 according to the first embodiment of the present invention will be described in detail.

[0083] exist Figure 6 middle, Figure 6 Figure (a) illustrates an example of multiple light-emitting elements 602 arranged in a row, and Figure 6 (b) is a schematic cross-sectional view of row 604 of the light-emitting element. Figure 7 The figure illustrates an example of configuring the light-emitting part 404 by arranging multiple rows 604 of light-emitting elements in the Y direction.

[0084] exist Figure 6 (a) and Figure 6 In (b), W1 is the width of the light-emitting element 602 in the X direction, and d1 is the spacing between adjacent light-emitting elements 602 in the X direction. Figure 7 In the diagram, W2 is the width of the light-emitting element 602 in the Y direction, and d2 is the spacing between adjacent light-emitting elements 602 in the Y direction.

[0085] In addition, Figure 6 In (b), for example, the light-emitting element 602-3 is a portion surrounded by lines with alternating long and short dashes.

[0086] The row of light-emitting elements 604 is configured by arranging a plurality of light-emitting elements 602 at predetermined intervals (spacing) in the X direction. In the case of an image resolution of 1200 dpi in the Y direction, the predetermined interval is, for example, 21 μm or 16 μm. As an example, W1 is 19.8 μm, and as an example, d1 is 0.68 μm.

[0087] Here, when the light-emitting layer 506 is thin enough, the light-emitting point of the light-emitting element 602 is substantially the same as the light-emitting point of the lower electrode 504, and W1 can be considered as Figure 5 W, and d1 can be regarded as Figure 5 d.

[0088] The light-emitting element row 604 is not limited to such Figure 6 The illustration in (a) shows the case where the light-emitting elements 602 are arranged in a row in the X direction, and the light-emitting elements 602 can also be arranged as follows: Figure 7 The diagram shows multiple rows arranged in the Y direction. Figure 7 The illustration shows 748 light-emitting elements 602 (602-1 to 4-1 to 748) arranged in the X direction and four rows (604-1 to 604-4) arranged in a matrix in the Y direction, which is different from the X direction. Here, W2 is the same as W1, 19.8 μm. Here, d2 is the same as d1, 0.68 μm, and the illustration also shows the case where the light-emitting elements 602 are arranged in the Y direction with a spacing of 21.16 μm (1200 dpi).

[0089] The rod lens array 203 collects the light emitted from the light-emitting element group 201 onto the photosensitive drum 102. Here, the number of light-emitting element rows 604 in the Y direction is, for example, four. Here, as... Figure 8 As shown in the diagram, the spacing of the light-emitting elements 602 in the X direction is 21.16 μm. Here, as... Figure 8 As shown in the diagram, the spacing of the light-emitting elements 602 in the Y direction is 21.16 μm. Here, as... Figure 8 As shown in the diagram, the rod lens array 203 has a diameter of 290 μm. In this example, one rod lens array 203 is configured to collect light emitted from multiple light-emitting elements 602.

[0090] <Circuit configuration of the exposure head>

[0091] Reference Figure 9 The circuit configuration of the exposure head 106 according to the first embodiment of the present invention will be described in detail below.

[0092] In use Figure 9For simplicity, the description will only depict the circuit configuration of one exposure head 106 for a single color, but in reality, each of the four exposure heads 106 for the four colors has the same circuit configuration. These four exposure heads 106 perform parallel processing simultaneously.

[0093] The exposure head 106 includes an image controller unit 700 that sends signals or data for controlling the printed circuit board 202 to the printed circuit board 202 and performs processing of image data and exposure timing. The signals and data sent from the image controller unit 700 to the printed circuit board 202 include clock signals, image data, signals indicating the start of receiving image data (hereinafter referred to as "line synchronization signals"), and communication signals.

[0094] Specifically, the image controller unit 700 includes an image data generation unit 701, a chip data conversion unit 702, a CPU 703, a synchronization signal generation unit 704, a +5V generation circuit 710, a -5V generation circuit 711, and a switch (SW) 714.

[0095] Here, the image controller unit 700 and the printed circuit board 202 are connected via clock signal line 705, horizontal synchronization signal line 706, image data signal line 707, communication signal line 708, +5V power supply line 712, and -5V power supply line 713.

[0096] Clock signal line 705 connects chip data conversion unit 702 to each of light-emitting element array chips 400-1 to 400-20.

[0097] The horizontal synchronization signal line 706 connects the chip data conversion unit 702 and the light-emitting element array chip 400-1.

[0098] Image data signal lines 707 connect the chip data conversion unit 702 to each of the light-emitting element array chips 400-1 to 400-20. Here, there are four image data signal lines 707, which is the same as the number of light-emitting element rows 604.

[0099] Communication signal line 708 connects CPU 703 to each of the light-emitting element array chips 400-1 to 400-20.

[0100] +5 V power line 712 connects +5 V generation circuit 710 to each of the light-emitting element array chips 400-1 to 400-20.

[0101] -5 V power line 713 connects switch (SW) 714 to each of the light-emitting element array chips 400-1 to 400-20.

[0102] The image data generation unit 701 performs dithering processing on image data input from the scanner unit 100 or received and input from outside the image forming apparatus 1 at an image resolution indicated by the CPU 703, to generate image data for print output. For example, the image data generation unit 701 generates one-line × four-row (number of rows of light-emitting elements) image data by performing dithering processing at an image resolution of 1200 dpi in each of the main scanning direction and the sub-scanning direction. The image data generation unit 701 outputs the generated image data to the chip data conversion unit 702.

[0103] The chip data conversion unit 702, in sync with the horizontal synchronization signal input from the synchronization signal generation unit 704, divides the image data input from the image data generation unit 701 for each of the light-emitting element array chips 400-1 to 400-20. The chip data conversion unit 702 outputs the divided image data to each of the light-emitting element array chips 400-1 to 400-20 via the image data signal line 707. Simultaneously, the chip data conversion unit 702 outputs a horizontal synchronization signal to the light-emitting element array chip 400-1 via the horizontal synchronization signal line 706, and outputs a clock signal to the light-emitting element array chips 400-1 to 400-20 via the clock signal line 705.

[0104] The CPU 703 sets a line period to the period during which the surface of the photosensitive drum 102 moves a predetermined pixel size in the rotational direction at a predetermined rotational speed, and indicates the time interval of the signal period to the synchronization signal generation unit 704.

[0105] For example, the CPU 703 sets a line cycle to the period during which the surface of the photosensitive drum 102 moves 1200 dpi (approximately 21.16 μm) of pixel size in the rotational direction at a predetermined rotational speed of the photosensitive drum 102. Then, for example, when performing exposure in the transport direction at a speed of 200 mm / s, the CPU 703 sets a line cycle to 105.8 μs (rounded down to one decimal place) and indicates the time interval of the signal cycle to the synchronization signal generation unit 704. At this time, the CPU 703 calculates the speed in the transport direction by using the setting value (fixed value) of the printing speed set in the speed controller (not shown) that controls the speed of the photosensitive drum 102.

[0106] The CPU 703 instructs the image resolution to the image data generation unit 701. The CPU 703 outputs a power control signal to the switch 714 to turn on the switch 714. The CPU 703 sends and receives communication signals from each of the light-emitting element array chips 400-1 to 400-20 via the communication signal line 708. The CPU 703 sets the setting value in the communication signal based on the header information (described below) stored in the header information storage unit 709, and outputs the communication signal with the set value to the light-emitting element array chips 400-1 to 400-20 via the communication signal line 708.

[0107] The synchronization signal generation unit 704 generates a horizontal synchronization signal based on the time interval of the signal period indicated by the CPU 703, and outputs the generated horizontal synchronization signal to the chip data conversion unit 702.

[0108] The +5 V generation circuit 710 converts the +12 V power supply voltage applied from the +12 V power supply into a +5 V voltage, and supplies this voltage to each of the light-emitting element array chips 400-1 to 400-20 via the +5 V power supply line 712. A general switching regulator circuit can be used as the +5 V generation circuit 710.

[0109] The -5V generation circuit 711 converts the +12V power supply voltage applied from the +12V power supply into a -5V voltage and supplies this voltage to the switch 714. A general switching regulator circuit can be used as the -5V generation circuit 711.

[0110] Depending on whether a power control signal is input from the CPU 703, switch 714, acting as a switching element, is turned on or off, thereby switching whether a -5V voltage is supplied to the light-emitting element array chip 400. When a power control signal is input from the CPU 703, switch 714 is turned on, and a -5V voltage is supplied to each of the light-emitting element array chips 400-1 to 400-20 via the -5V power line 713. When switch 714 is turned off and a -5V voltage is not supplied to the light-emitting element array chips 400-1 to 400-20, the -5V power line 713 is in a floating state.

[0111] The printed circuit board 202 includes light-emitting element array chips 400-1 to 400-20 and a header information storage unit 709.

[0112] Light-emitting element array chips 400-1 and 400-2 are connected via signal line 708-1. Light-emitting element array chips 400-2 and 400-3 are connected via signal line 708-2. Similarly, light-emitting element array chip 400-3 and subsequent light-emitting element array chips are connected one after another via signal line 708-3 and subsequent signal lines.

[0113] Each of the light-emitting element array chips 400-1 to 400-20 generates a line synchronization signal for the next chip based on the input line synchronization signal, and outputs the line synchronization signal to the next light-emitting element array chip 400-1 to 400-20 via signal line 708-1 and subsequent signal lines. Each of the light-emitting element array chips 400-1 to 400-20 causes the light-emitting element 602 to emit light based on the input clock signal, line synchronization signal, image data, and setting values ​​set in the communication signal.

[0114] Head information storage unit 709 is connected to CPU 703 via communication signal line 708. Head information storage unit 709 is a storage device that stores head information such as the light emission amount and installation position information of light-emitting element array chips 400-1 to 400-20.

[0115] <Circuit configuration of light-emitting element array chip>

[0116] Reference Figures 10 to 13 The circuit configuration of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail.

[0117] Since the circuit configurations of the light-emitting element array chips 400-1 to 400-20 are identical, the circuit configuration of the light-emitting element array chip 400-1 will be described, and the descriptions of the circuit configurations of the light-emitting element array chips 400-2 to 400-20 will be omitted. Furthermore, since clock signals are input to all blocks of the digital section 800, clock signal line 705 is connected to all blocks of the digital section 800, but... Figure 10 Its description is omitted.

[0118] The light-emitting element array chip 400-1 includes a light-emitting section 404 and a circuit section 406. The circuit section 406 includes a digital section 800 and an analog section 801.

[0119] Clock signals, image data signals, and horizontal synchronization signals are input to the digital unit 800 from the chip data conversion unit 702, and communication signals are input to the digital unit 800 from the CPU 703. The digital unit 800, in sync with the clock signal, generates a drive signal (pulse signal) for causing the light-emitting element 602 to emit light based on the setting value set in the communication signal, the image data signal, and the horizontal synchronization signal, and outputs the generated drive signal to the analog unit 801. The digital unit 800 generates a horizontal synchronization signal for the next chip based on the horizontal synchronization signal, and outputs the generated horizontal synchronization signal for the next chip to the light-emitting element array chip 400-2, which is the next chip, via signal line 708-1.

[0120] Specifically, the digital unit 800 includes a communication IF unit 802, a register unit 803, a line synchronization signal generation unit 804, a receive signal generation unit 805, and data holding units 806-001 to 806-748.

[0121] The communication IF unit 802 is connected to the CPU 703 via the communication signal line 708.

[0122] The setting value set from the communication signal input from the CPU 703 via the communication IF unit 802 is written into the register unit 803. The register unit 803 reads the setting value written by the CPU 703, outputs the read setting value as drive current information to the analog unit 801, and outputs the read setting value as delay time information to the receive signal generation unit 805. Here, the drive current information is information about the setting current value of the drive current flowing through the light-emitting unit 404, and is a digital value. In addition, the delay time information is information about the delay time for which the output of the data latch signal will be delayed, and is also a digital value.

[0123] The horizontal synchronization signal generation unit 804 delays the horizontal synchronization signal input from the horizontal synchronization signal line 706 by a predetermined time to generate a horizontal synchronization signal for the next chip, and outputs the horizontal synchronization signal to the light-emitting element array chip 400-2 via the signal line 708-1.

[0124] The receiving signal generation unit 805 outputs the data latch signal we001 to the data holding unit 806-001 based on the line synchronization signal input via the line synchronization signal line 706 and the timing of the delay time in the delay time information input from the register unit 803.

[0125] Clock signals and data latch signals wen (n=1 to 748) are input to each of the data holding units 806-001 to 806-748, and at the timing of the input of the data latch signal wen, four lines of image data 1 to 4 are input.

[0126] like Figure 11 As illustrated, each of the data holding units 806-001 to 806-748 includes four flip-flop circuits 807 and four gate circuits 808 that latch input image data 1 to 4, generate drive signals 1 to 4, and output the drive signals to the analog unit 801. Each of the data holding units 806-001 to 806-748 includes a flip-flop circuit 809 that delays the input data latch signal wen by one clock cycle and outputs the delayed data latch signal we(n+1) to the next data holding unit 806-001 to 806-748.

[0127] The analog unit 801 controls the driving of the light-emitting unit 404 based on the driving current information input from the register unit 803 and the driving signals input from the data holding units 806-001 to 806-748.

[0128] Specifically, such as Figure 12 As shown in the figure, the analog section 801 includes a drive circuit 900, which includes a current setting DAC 901, a current control MOSFET 902, and a switching MOSFET 903.

[0129] Each driving circuit 900 is connected one-to-one to a light-emitting element 602, and the number of driving circuits 900 provided is the same as the number of light-emitting elements 602. In this embodiment, 2992 driving circuits 900 (=748 × 4 rows) are provided for one of the light-emitting element array chips 400-1 to 400-20. Since all driving circuits 900 have the same configuration, for the sake of simplicity, the configuration of only one driving circuit 900 will be described.

[0130] The current setting DAC 901 converts the digital value of the drive current flowing through the light-emitting unit 404, indicated by the drive current information input from the register section 803 of the digital section 800, into an analog voltage, and outputs the analog voltage to the gate terminal G of the current control MOSFET 902.

[0131] The current-controlled MOSFET 902 is a Pch MOSFET and has a source terminal S connected to the supply voltage VDD, a gate terminal G connected to the output terminal of the DAC 901, and a drain terminal D connected to the source terminal S of the switching MOSFET 903. The current-controlled MOSFET 902 is configured such that the drive current for the light-emitting element 602 flowing from the source terminal S to the drain terminal D increases with the increase of the analog voltage input from the current-setting DAC 901.

[0132] The switching MOSFET 903 is a Pch MOSFET. The switching MOSFET 903 has a source terminal S connected to the drain terminal D of the current control MOSFET 902, a gate terminal G connected to the output terminal of the data holding section 806, and a drain terminal D connected to the anode terminal A of the light-emitting element 602 of the light-emitting section 404. Binary drive signals 1 to 4, indicating a high or low level, are input from the data holding sections 806-001 to 806-748 to the gate terminal G of the switching MOSFET 903.

[0133] The switching MOSFET 903 is turned on when a high-level drive signal is input to the gate terminal G and turned off when a low-level drive signal is input to the gate terminal G. When a high-level drive signal is input to the gate terminal G and the switching MOSFET 903 is turned on, the current that drives the light-emitting element 602, which is controlled by the current-controlled MOSFET 902, flows from the source terminal S to the drain terminal D.

[0134] Next, we will refer to Figure 13 The power supply configuration for each of the digital section 800, analog section 801, and light-emitting element 602 is described in detail.

[0135] exist Figure 13 In order to simplify the description, the description of the blocks inside the digital section 800 is omitted, and only a driving circuit 900 and a light-emitting element 602 in the analog section 801 are described.

[0136] A +5V voltage is supplied as the power supply voltage from the +5V power line 712 to the digital section 800. The digital section 800 is connected to GND (0V), which serves as a reference potential. Therefore, each block of the digital section 800 operates at voltages between +5V and 0V. A voltage in the range of 0V to 5V is applied to the gate terminal of the switching MOSFET 903.

[0137] A +5V voltage is supplied as a power supply voltage from the +5V power supply line 712 to the current setting DAC 901 of the analog section 801. The current setting DAC 901 is connected to GND (0V), which serves as a reference potential. As a result, a voltage in the range of 0V to 5V is applied to the gate terminal of the current control MOSFET 902. A +5V voltage is supplied as a power supply voltage from the +5V power supply line 712 to the source terminal of the current control MOSFET 902.

[0138] The light-emitting element 602 is, for example, an organic EL, and has an anode terminal A connected to the drain terminal of a switching MOSFET 903 and a cathode terminal K connected to a -5 V power supply line 713. A -5 V voltage is supplied from the -5 V power supply line 713 to the cathode terminal K of the light-emitting element 602. In the light-emitting element 602, a forward voltage of approximately 6 V is typically generated by a drive current of a few μA. In this case, the potential of the anode terminal A of the light-emitting element 602 is approximately +1 V, obtained by adding +6 V to -5 V.

[0139] Since the drain-source voltage of the current-control MOSFET 902 and the switching MOSFET 903 is approximately 1.5 V, by adding the 1.5 V × 2 = 3 V drain-source voltage to the 6 V forward voltage of the light-emitting element 602, a voltage of approximately 9 V is obtained. Therefore, in order for the light-emitting element 602 to emit light, the light-emitting element array chips 400-1 to 400-20 require a voltage of approximately 9 V or greater. Since the light-emitting element array chips 400-1 to 400-20 can drive the light-emitting element 602 within a 10 V range of +5 V and -5 V, the light-emitting element 602 can emit light.

[0140] Until now, in configurations where EL films are stacked on the circuit section via deposition, etc., considering the drain-source voltage of the MOSFET, it is necessary to form the light-emitting element array chip using a semiconductor process of 9 V or greater to ensure a 6 V forward voltage for the light-emitting element. On the other hand, in this embodiment, +5V and -5V are supplied as power supply voltages to drive the light-emitting element 602 within a 10 V range, and the digital section 800 and analog section 801 are configured using a semiconductor process of +5V from GND. As a result, in this embodiment, the size of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip size of the light-emitting element array chips 400-1 to 400-20 can be reduced.

[0141] <Operation of the Exposure Head>

[0142] Reference Figure 14 and Figure 15 The operation of the exposure head 106 according to the first embodiment of the present invention will be described in detail.

[0143] The exposure head 106 begins operation at a time when the main power supply of the image forming apparatus 1 is turned on.

[0144] First, CPU 703 determines whether there is a print job request from the user (S1).

[0145] If there is no print job request from the user (S1: No), CPU 703 repeats step S1.

[0146] On the other hand, when there is a request for a print job from the user (S1: Yes), the CPU 703 writes a setting value into the register section 803 of the light-emitting element array chips 400-1 to 400-20 to perform register setting (S2).

[0147] Next, the CPU 703 outputs a power control signal to the switch 714 to supply a -5V voltage (-5V on) to the cathode electrode of the light-emitting element 602 of the light-emitting element array chips 400-1 to 400-20 (S3).

[0148] Next, the CPU 703 starts outputting image data to the light-emitting element array chips 400-1 to 400-20 at a predetermined timing to expose the photosensitive drum 102 (S4).

[0149] Next, CPU 703 determines whether the print job has been completed (S5).

[0150] If the print job has not yet been completed (S5: No), CPU 703 repeats step S5.

[0151] On the other hand, when the printing job has ended (S5: Yes), the CPU 703 stops sending power control signals to the switch 714, thereby causing the potential of the cathode electrode of the light-emitting element 602 to enter a floating state and ending the operation.

[0152] Next, we will refer to Figure 15 Let's describe the operation of the exposure head 106 in more detail.

[0153] refer to Figure 15 At time t=t0, the power supply to image forming apparatus 1 is turned on, and a +12V power supply voltage is supplied to the +5V generation circuit 710 and the -5V generation circuit 711. As a result, after time t=t1, the voltage of the +5V power supply line 712 becomes +5V. At this time, since switch 714 is turned off, the -5V power supply line 713 is in a floating state (in Figure 15 (0 V).

[0154] At time t=t1, when a job request is received from the user, the CPU 703 outputs a power control signal to the switch 714, thereby changing the potential of the -5V power line 713 to -5V, which can drive the light-emitting element 602.

[0155] At time t=t2, when the operation ends, CPU 703 stops outputting power control signals to switch 714 to turn off switch 714, thereby leaving the -5V power line 713 in a floating state (in Figure 15 (0 V).

[0156] Operation of LED array chip

[0157] Reference Figure 16 The operation of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail.

[0158] Four lines of image data (D1[1] to D1[4]) are simultaneously input to the data holding unit 806-001. The data holding unit 806-001 latches the image data (D1[1] to D1[4]) and generates drive signals (P001[1] to P001[4]) when the data latch signal we001 is input from the receiving signal generation unit 805.

[0159] In addition, the data holding unit 806-001 outputs the data latch signal we002, which is obtained by delaying the input data latch signal we001 by one clock cycle, to the next data holding unit 806-002.

[0160] Similar to the data holding unit 806-001, four lines of image data (D2[1] to D2[4]) are simultaneously input to the data holding unit 806-002. The data holding unit 806-002 latches the image data (D2[1] to D2[4]) at the timing when the data latch signal we002 is input from the data holding unit 806-001, and generates drive signals (P002[1] to P002[4]).

[0161] In addition, the data holding unit 806-002 outputs the data latch signal we003, which is obtained by delaying the input data latch signal we002 by one clock cycle, to the next data holding unit 806-003.

[0162] In this way, the data holding units 806-001 to 806-748 sequentially latch image data while sequentially outputting data latch signals.

[0163] Data holding units 806-001 to 806-748 latch image data and output the latched signal as a drive signal to analog unit 801. Since four lines of image data are latched by a single data latch signal, data holding units 806-001 to 806-748 simultaneously output drive signals for the four lines (for four pixels).

[0164] As described above, in the configuration where the light-emitting element 602 and the analog section 801 are formed on the same chip, a voltage (-5V) lower than the voltage supplied to the analog section 801 (+5V and reference potential (GND)) is supplied to the cathode electrode of the light-emitting element 602. As a result, since the analog section 801 can be formed using a relatively low-voltage semiconductor process, the size of the analog section 801 can be reduced, and the chip size can be reduced as well.

[0165] Furthermore, during non-exposure operations, the potential of the cathode electrode of the light-emitting element 602, which is connected to the -5V power supply line 713, is brought into a floating state. As a result, leakage current from the current control MOSFET 902 and the switching MOSFET 903 to the light-emitting element 602, which generates leakage current even in the off state during non-exposure operations, can be suppressed, and power consumption can be reduced.

[0166] In this embodiment, the analog unit 801 operates between a first potential of +5V and a second potential of 0V, and the light-emitting element 602 operates between a third potential of +1V and a fourth potential of -5V. Furthermore, the potential difference between the third potential of +1V and the fourth potential of -5V is equal to or greater than the potential difference between the first potential of +5V and the second potential of 0V. As a result, in a configuration where the light-emitting element 602 and the analog unit 801 are formed into a single chip, while ensuring the forward voltage of the light-emitting element 602, the analog unit 801 can be formed using a low-voltage semiconductor process, and the chip size can be reduced.

[0167] In this embodiment, the third potential +1 V is lower than the first potential +5 V, and the fourth potential -5 V is lower than the second potential 0 V. The potential difference between the second potential 0 V and the fourth potential -5 V is equal to or greater than the potential difference between the first potential +5 V and the second potential 0 V. The second potential 0 V is the ground potential, the first potential +5 V is a positive potential relative to the ground potential, and the fourth potential -5 V is a negative potential relative to the ground potential.

[0168] Furthermore, in this embodiment, when switch 714 is switched so as not to supply current to light-emitting element 602, the potential of cathode terminal K of light-emitting element 602 becomes a fifth potential of at least 0V higher than the fourth potential -5V. The fifth potential of 0V is equal to the second potential of 0V.

[0169] Furthermore, in this embodiment, the fourth potential -5 V is lower than the first potential +5 V. The second potential 0 V is ground potential. The third potential +1 V is higher than the second potential 0 V.

[0170] In this embodiment, the voltage is not limited to +5 V and -5 V, and any voltage other than +5 V and -5 V can be supplied, as long as the voltage can drive the light-emitting element 602. For example, in addition to a 10 V voltage range of +5 V and -5 V, a 10 V voltage range of +4 V and -6 V can also be ensured.

[0171] In this embodiment, 20 light-emitting element array chips 400-1 to 400-20 are disposed on the printed circuit board 202, but the present invention is not limited thereto, and any number of light-emitting element array chips can be disposed on the printed circuit board 202 as needed.

[0172] (Second Embodiment)

[0173] Due to the configuration of the image forming apparatus according to the second embodiment of the present invention and Figure 1 The image forming apparatus 1 shown in the figure has the same configuration, so its description is omitted. Furthermore, in the configuration of the exposure head according to this embodiment, since the configuration other than the circuit configuration of the exposure head is the same as... Figures 3 to 8 The configuration is the same as in the previous one, so the description of the configuration other than the circuit configuration of the exposure head is omitted.

[0174] The cathode electrode with multiple light-emitting elements 602 in the first embodiment described above has a common configuration, but the anode electrode with multiple light-emitting elements 602 in this embodiment has a common configuration.

[0175] <Circuit configuration of the exposure head>

[0176] Reference Figure 17 The circuit configuration of the exposure head according to the second embodiment of the present invention will be described in detail below.

[0177] exist Figure 17 In, it has the same Figure 9 The parts with the same configuration are indicated by the same reference numerals, and their descriptions are omitted.

[0178] The exposure head according to this embodiment includes an image controller unit 1301 that sends signals or data for controlling the printed circuit board 1302 to the printed circuit board 1302 and performs image data processing and exposure timing processing. The signals and data sent from the image controller unit 1301 to the printed circuit board 1302 include clock signals, image data, line synchronization signals, and communication signals.

[0179] Specifically, the image controller unit 1301 includes an image data generation unit 701, a chip data conversion unit 702, a CPU 703, a synchronization signal generation unit 704, a +5V generation circuit 710, a switch 714, and a +10V generation circuit 1303.

[0180] Here, the image controller unit 1301 and the printed circuit board 1302 are connected via clock signal line 705, horizontal synchronization signal line 706, image data signal line 707, communication signal line 708, +5 V power supply line 712 and +10 V power supply line 1304.

[0181] +10 V power line 1304 connects switch 714 to each of the light-emitting element array chips 1400-1 to 1400-20.

[0182] The +10 V generation circuit 1303 converts the +12 V power supply voltage applied from an external +12 V power supply into a +10 V voltage and supplies this voltage to the switch 714. The -5 V generation circuit 711 can be a general switching regulator circuit.

[0183] Depending on whether a power control signal is input from the CPU 703, switch 714 is turned on or off, thereby switching whether a +10V voltage is supplied to the light-emitting element array chip 1400. When a power control signal is input from the CPU 703, switch 714 is turned on, and a +10V voltage is supplied to each of the light-emitting element array chips 1400-1 to 1400-20 via the +10V power line 1304. When switch 714 is turned off and a +10V voltage is not supplied to the light-emitting element array chips 1400-1 to 1400-20, the +10V power line 1304 is in a floating state.

[0184] Printed circuit board 1302 includes a header information storage unit 709 and light-emitting element array chips 1400-1 to 1400-20. Note that the arrangement and alignment of light-emitting element array chips 1400-1 to 1400-20 on printed circuit board 1302 are the same as those of light-emitting element array chips 400-1 to 400-20 on printed circuit board 302.

[0185] Light-emitting element array chips 1400-1 and 1400-2 are connected via signal line 708-1. Light-emitting element array chips 1400-2 and 1400-3 are connected via signal line 708-2. Similarly, light-emitting element array chip 1400-3 and subsequent light-emitting element array chips are connected one after another via signal line 708-3 and subsequent signal lines.

[0186] Each of the light-emitting element array chips 1400-1 to 1400-20 generates a horizontal synchronization signal for the next chip, and outputs the horizontal synchronization signal to the next light-emitting element array chip 1400-2 to 1400-20 via signal line 708-1 and subsequent signal lines. Each of the light-emitting element array chips 1400-1 to 1400-20 causes the light-emitting element 602 to emit light based on the input clock signal, horizontal synchronization signal, image data, and setting values ​​set in the communication signal.

[0187] Head information storage unit 709 is connected to CPU 703 via communication signal line 708. Head information storage unit 709 is a storage device that stores head information such as the light emission amount and installation position information of light-emitting element array chips 1400-1 to 1400-20.

[0188] Because the light-emitting parts of the light-emitting element array chips 1400-1 to 1400-20 have the same... Figure 5 The configuration of the light-emitting part 404 shown in the middle diagram is the same, so its description is omitted.

[0189] <Circuit configuration of light-emitting element array chip>

[0190] Reference Figure 18 The circuit configuration of the light-emitting element array chips 1400-1 to 1400-20 of the exposure head according to the second embodiment of the present invention will be described in detail.

[0191] Since the circuit configurations of the light-emitting element array chips 1400-1 to 1400-20 are identical, the circuit configuration of light-emitting element array chip 1400-1 will be described, and the descriptions of the circuit configurations of light-emitting element array chips 1400-2 to 1400-20 will be omitted. Figure 18 In, it has the same Figure 12 In the configuration, the parts with the same configuration are represented by the same reference symbols, and their descriptions are omitted.

[0192] The light-emitting element array chip 1400-1 includes a light-emitting section 404 and a circuit section 406. The circuit section 406 includes a digital section 800 and an analog section 801.

[0193] In this embodiment, 2992 driving circuits 900 (=748 × 4 rows) are provided for one of the light-emitting element array chips 1400-1 to 1400-20. Since all driving circuits 900 have the same configuration, for the sake of simplicity, the configuration of only one driving circuit 900 will be described.

[0194] The current-controlled MOSFET 902 is a Pch MOSFET. The current-controlled MOSFET 902 has a source terminal connected to the cathode of the light-emitting element 602, a gate terminal connected to the output terminal of the current-setting DAC 901, and a drain terminal connected to the source terminal of the switching MOSFET 903. The current-controlled MOSFET 902 is configured such that the current flowing from the source terminal to the drain terminal increases with the increase of the analog voltage input from the current-setting DAC 901.

[0195] The switching MOSFET 903 is a Pch MOSFET and has a source terminal connected to the drain terminal of the current control MOSFET 902, a gate terminal connected to the output terminal of the data holding section 806, and a drain terminal connected to GND. Binary drive signals 1 to 4 indicating a high or low level are input to the gate terminal of the switching MOSFET 903 from the data holding sections 806-001 to 806-748.

[0196] The switching MOSFET 903 is turned on when a high-level drive signal is input to the gate terminal and turned off when a low-level drive signal is input to the gate terminal. When a high-level drive signal is input to the gate terminal and the switching MOSFET 903 is turned on, the current that drives the light-emitting element 602, which is controlled by the current-controlled MOSFET 902, flows from the source terminal to the drain terminal.

[0197] Next, we will refer to Figure 19 The power supply configuration of each of the digital unit 800, analog unit 801, and light-emitting element 602 is described in detail.

[0198] exist Figure 19 In, it has the same Figure 11 In the configuration, the same configuration parts are represented by the same reference symbols, and their descriptions are omitted. Additionally, in Figure 19 In order to simplify the description, the description of the blocks inside the digital section 800 is omitted, and only a driving circuit 900 and a light-emitting element 602 in the analog section 801 are described.

[0199] A +10 V voltage is supplied from the +10 V power supply line 1304 to the anode terminal A of the light-emitting element 602, and the cathode terminal is connected to the source terminal of the current-controlled MOSFET 902. The light-emitting element 602 is, for example, an organic EL, and typically generates a forward voltage of about 6 V with a drive current of a few μA. That is, the potential of the cathode terminal K of the light-emitting element 602 becomes about +4 V, which is obtained by subtracting 6 V from +10 V.

[0200] Since the drain-source voltage of the current-controlled MOSFET 902 and the switching MOSFET 903 is approximately 1.5V, by adding the 1.5V × 2 = 3V drain-source voltage to the 6V forward voltage of the light-emitting element 602, a voltage of approximately 9V is obtained. Therefore, in order for the light-emitting element 602 to emit light, the light-emitting element array chips 1400-1 to 1400-20 require a voltage of approximately 9V or greater. Since the light-emitting element array chips 1400-1 to 1400-20 can drive the light-emitting element 602 within a 10V range from GND (0V) to +10V, the light-emitting element 602 can emit light.

[0201] Until now, in configurations where EL films are stacked on the circuit section via deposition, etc., considering the drain-source voltage of the MOSFET, it is necessary to form the light-emitting element array chip using a semiconductor process of 9 V or greater to ensure a 6 V forward voltage for the light-emitting element. On the other hand, in this embodiment, GND and +10V are supplied as power supply voltages to drive the light-emitting element 602 within a 10 V range, and the digital section 800 and analog section 801 are configured using a semiconductor process of +5V from GND. As a result, in this embodiment, the size of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip size of the light-emitting element array chip 1400-1 to 1400-20 can be reduced.

[0202] <Operation of the Exposure Head>

[0203] Reference Figures 20 to 21 The operation of the exposure head 106 according to the second embodiment of the present invention will be described in detail below.

[0204] The exposure head 106 begins operation at a time when the main power supply of the image forming apparatus 1 is turned on.

[0205] First, CPU 703 determines whether there is a print job request from the user (S11).

[0206] If there is no print job request from the user (S11: No), CPU 703 repeats step S11.

[0207] On the other hand, when there is a request for a print job from the user (S11: Yes), the CPU 703 writes a setting value into the register section 803 of the light-emitting element array chips 1400-1 to 1400-20 to perform register setting (S12).

[0208] Next, the CPU 703 outputs a power control signal to the switch 714 to supply a +10V voltage (+10V on) to the anode electrode of the light-emitting element 602 of the light-emitting element array chips 1400-1 to 1400-20 (S13).

[0209] Next, the CPU 703 starts outputting image data to the light-emitting element array chips 1400-1 to 1400-20 at a predetermined timing to expose the photosensitive drum 102 (S14).

[0210] Next, CPU 703 determines whether the print job has been completed (S15).

[0211] If the print job has not yet been completed (S15: No), CPU 703 repeats the operation of step S15.

[0212] On the other hand, when the printing job has ended (S15: Yes), the CPU 703 stops sending power control signals to the switch 714, thereby causing the potential of the anode electrode of the light-emitting element 602 to enter a floating state and ending the operation.

[0213] Next, we will refer to Figure 21 The operation of exposure head 106 is described in more detail.

[0214] refer to Figure 21 At time t=t10, the power supply to image forming apparatus 1 is turned on, and a +12V power supply voltage is supplied to the +5V generation circuit 710 and the +10V generation circuit 1303. As a result, after time t=t10, the voltage of the +5V power supply line 712 becomes +5V. At this time, since switch 714 is turned off, the potential of the +10V power supply line 1304 is in a floating state (in Figure 21 (0 V).

[0215] At time t=t11, when a job request is received from the user, the CPU 703 outputs a power control signal to the switch 714, thereby changing the potential of the +10V power line 1304 to +10V, which can drive the light-emitting element 602.

[0216] At time t=t12, when the operation ends, CPU 703 stops outputting power control signals to switch 714 and turns off switch 714, thereby leaving the +10V power line 1304 in a floating state (at... Figure 21 (0 V).

[0217] As described above, in the configuration where the light-emitting element 602 and the analog section 801 are formed on the same chip, a voltage (+10 V) higher than the voltage supplied to the analog section 801 (+5 V and reference potential (GND)) is supplied to the anode electrode of the light-emitting element 602. As a result, since the analog section 801 can be formed using a relatively low-voltage semiconductor process, the size of the analog section 801 can be reduced, and the chip size can be reduced as well.

[0218] Furthermore, during non-exposure operations, the potential of the anode electrode of the light-emitting element 602, which is connected to the +10V power supply line 1304, is brought into a floating state. As a result, leakage current from the current control MOSFET 902 and the switching MOSFET 903 to GND, which generates leakage current even in the off state during non-exposure operations, can be suppressed, and power consumption can be reduced.

[0219] In this embodiment, the analog unit 801 operates between a first potential of +5V and a second potential of 0V, and the light-emitting element 602 operates between a third potential of +10V and a fourth potential of +4V. Furthermore, the potential difference between the third potential of +10V and the fourth potential of +4V is equal to or greater than the potential difference between the first potential of +5V and the second potential of 0V. As a result, in a configuration where the light-emitting element 602 and the analog unit 801 are formed into a single chip, while ensuring the forward voltage of the light-emitting element 602, the analog unit 801 can be formed using a low-voltage semiconductor process, and the chip size can be reduced.

[0220] In this embodiment, the third potential +10 V is higher than the first potential +5 V, and the fourth potential +4 V is higher than the second potential 0 V. The potential difference between the first potential +5 V and the third potential +10 V is equal to or greater than the potential difference between the first potential +5 V and the second potential 0 V.

[0221] Furthermore, in this embodiment, when switch 714 is switched so as not to supply current to the light-emitting element 602, the potential becomes a fifth potential, which is at least 0V lower than the first potential +5V. The fifth potential 0V is equal to the second potential 0V.

[0222] Furthermore, in this embodiment, the fourth potential +4 V is lower than the first potential +5 V. The second potential 0 V is ground potential. The third potential +10 V is higher than the second potential 0 V.

[0223] In this embodiment, the voltage is not limited to +5V and +10V, and can be any voltage other than 5V and 10V, as long as the light-emitting element 602 can be driven.

[0224] In this embodiment, 20 light-emitting element array chips 1400-1 to 1400-20 are disposed on the printed circuit board 1302. However, the present invention is not limited to this, and any number of light-emitting element array chips can be disposed on the printed circuit board 1302 as needed.

[0225] Needless to say, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0226] Although the invention has been described with reference to exemplary embodiments, the invention is not limited to the disclosed exemplary embodiments. The following claims are given the broadest interpretation to cover all modifications, equivalent structures, and functions.

[0227] This application claims priority based on Japanese Patent Application No. 2020-210272, filed on December 18, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. An exposure head configured to expose a photosensitive drum, the exposure head comprising: substrate; Multiple strip-shaped semiconductor chips, each strip-shaped semiconductor chip including multiple light-emitting elements and a driving circuit for driving the light-emitting elements, the multiple strip-shaped semiconductor chips being arranged on the substrate; as well as A lens array configured to collect light from a light-emitting element onto the photosensitive drum. The driving circuit operates between a first potential and a second potential. The light-emitting element operates between the third and fourth potentials, and The potential difference between the third potential and the fourth potential is equal to or greater than the potential difference between the first potential and the second potential.

2. The exposure head according to claim 1, in, The light-emitting element has an anode terminal connected to the third potential and a cathode terminal connected to the fourth potential. The third potential is lower than the first potential, and The fourth potential is lower than the second potential.

3. The exposure head according to claim 1 or 2, in, The potential difference between the second potential and the fourth potential is equal to or greater than the potential difference between the first potential and the second potential.

4. The exposure head according to claims 1 to 3, in, The second potential is the ground potential. The first potential is a positive potential relative to the ground potential, and The fourth potential is a negative potential relative to the ground potential.

5. The exposure head according to claims 1 to 4, in, The driving circuit includes a switching element arranged between the first potential and the light-emitting element and configured to switch whether to supply current to the light-emitting element.

6. The exposure head according to claim 5, in, When the switching element is switched in such a way that no current is supplied to the light-emitting element, the potential of the cathode terminal of the light-emitting element becomes at least a fifth potential, which is higher than the fourth potential.

7. The exposure head according to claim 6, in, The fifth potential is equal to the second potential.

8. The exposure head according to claim 1, in, The light-emitting element has an anode terminal connected to the third potential and a cathode terminal connected to the fourth potential. The third potential is higher than the first potential, and The fourth potential is higher than the second potential.

9. The exposure head according to claim 8, in, The potential difference between the first potential and the third potential is equal to or greater than the potential difference between the first potential and the second potential.

10. The exposure head according to claim 8 or 9, in, The driving circuit includes a switching element disposed between the third potential and the light-emitting element and configured to switch whether to supply current to the light-emitting element.

11. The exposure head according to claim 10, in, When the switching element is switched so as not to supply current to the light-emitting element, the potential of the anode terminal of the light-emitting element becomes at least a fifth potential, which is lower than the first potential.

12. The exposure head according to claim 11, wherein, The fifth potential is equal to the second potential.

13. The exposure head according to claims 1 to 12, in, The fourth potential is lower than the first potential.

14. The exposure head according to claims 1 to 13, in, The second potential is the ground potential.

15. The exposure head according to claims 1 to 14, in, The third potential is higher than the second potential.

16. The exposure head according to claims 1 to 15, in, The light-emitting element includes an organic EL film.

17. The exposure head according to claim 16, in, The organic EL film is formed on the driving circuit.

18. An image forming apparatus, comprising: A charger configured to charge a photosensitive drum; The exposure head according to claims 1 to 17, wherein the exposure head is configured to expose a photosensitive drum charged by the charger to form an electrostatic latent image on the photosensitive drum; and A developing apparatus configured to develop the electrostatic latent image to form a developer image on the photosensitive drum.

Images