SiC MOSFET gate drain buffer circuit parameter design method and system

Abstract

The invention relates to the field of semiconductor power devices, and relates to a SiC MOSFET gate drain buffer circuit parameter design method and system, and the method comprises the steps: obtaining a preset double-pulse test circuit of a SiC MOSFET gate drain buffer circuit; constructing an expression of the drain-source voltage of the SiC MOSFET in an S domain based on a preset double-pulse test circuit of the gate-drain buffer circuit of the SiC MOSFET; converting the expression of the drain-source voltage of the S C MOSFET in the S domain into an equation expression, wherein the equation expression takes a buffer capacitor as a variable; drawing a root locus diagram according to the equation expression, wherein the root locus diagram comprises root locus change conditions corresponding to different buffer resistors; and analyzing the root locus diagram to obtain the design parameters of the SiC MOSFET gate drain buffer circuit with the damping ratio of 1, the problems that in the prior art, parameters depend on empirical type selection, the design period is long, and optimization matching is difficult are solved, and the parameter design efficiency and precision are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power devices, and more specifically, to a method and system for designing parameters of a SiC MOSFET gate-drain buffer circuit. Background Technology

[0002] SiC MOSFETs are widely used in high-frequency, high-voltage, and high-efficiency power electronics due to their high breakdown voltage and high switching speed. However, their high dv / dt characteristics bring problems such as voltage spikes, oscillations, and electromagnetic interference. In engineering, a snubber circuit is often introduced between the gate and drain to alleviate these problems. However, the selection of parameters for existing snubber circuits often relies on experience or repeated simulation verification, lacking theoretical support. This makes it difficult to adapt to the design requirements of different operating conditions or devices, resulting in long design cycles, low efficiency, and difficulty in achieving optimal matching, thus affecting the adaptability and performance of the circuit in different scenarios. Summary of the Invention

[0003] The purpose of this invention is to provide methods, systems, devices, and readable storage media to improve the above-mentioned problems.

[0004] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0005] On one hand, embodiments of this application provide a method for designing parameters of a SiC MOSFET gate-drain buffer circuit, the method comprising:

[0006] Obtain a pre-defined dual-pulse test circuit for the SiC MOSFET gate-drain buffer circuit;

[0007] Based on the preset SiC MOSFET gate-drain buffer circuit, a dual-pulse test circuit is used to construct an expression for the SiC MOSFET drain-source voltage in the S-domain.

[0008] The expression for the drain-source voltage of the SiC MOSFET in the S-domain is transformed into an equation, with the buffer capacitor as the variable.

[0009] A root locus diagram is plotted based on the equation expression, and the root locus diagram includes the changes in the root locus corresponding to different buffer resistors;

[0010] Analysis of the root locus diagram yields the design parameters for a SiC MOSFET gate-drain buffer circuit with a damping ratio of 1.

[0011] Secondly, embodiments of this application provide a SiC MOSFET gate-drain buffer circuit parameter design system, the system comprising:

[0012] The acquisition module is used to acquire the preset dual-pulse test circuit of the SiC MOSFET gate-drain buffer circuit;

[0013] The first processing module is used to construct an expression for the drain-source voltage of the SiC MOSFET in the S-domain based on the preset dual-pulse test circuit of the SiC MOSFET gate-drain buffer circuit.

[0014] The second processing module is used to convert the expression of the drain-source voltage of the SiC MOSFET in the S-domain into an equation expression, wherein the equation expression uses the buffer capacitor as a variable.

[0015] The third processing module is used to draw a root locus diagram based on the equation expression, and the root locus diagram includes the root locus changes corresponding to different buffer resistors.

[0016] The fourth processing module is used to analyze the root locus diagram to obtain the design parameters of the SiC MOSFET gate-drain buffer circuit with a damping ratio of 1.

[0017] Thirdly, embodiments of this application provide a device for designing parameters of a SiC MOSFET gate-drain buffer circuit, the device including a memory and a processor. The memory is used to store a computer program; the processor is used to execute the computer program to implement the steps of the above-described SiC MOSFET gate-drain buffer circuit parameter design method.

[0018] Fourthly, embodiments of this application provide a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described SiC MOSFET gate-drain buffer circuit parameter design method.

[0019] The beneficial effects of this invention are as follows:

[0020] This invention obtains a preset double-pulse test circuit, constructs an expression for the drain-source voltage in the S-domain based on this circuit, and transforms the circuit characteristics into a quantifiable mathematical model, eliminating reliance on experience. The expression is then transformed into an equation with the buffer capacitor as a variable, and a root locus plot including variations in the buffer resistance is drawn, achieving a direct correlation between parameters and the circuit's dynamic characteristics. Finally, by analyzing the root locus plot, design parameters with a damping ratio of 1 are obtained, ensuring that the parameters can accurately suppress switching oscillations. This invention solves the problems of parameter selection relying on experience, long design cycles, and difficulty in optimization matching in existing technologies. It not only improves design efficiency and parameter accuracy but also adapts to different operating conditions and device requirements, effectively suppressing voltage spikes and oscillations, and enhancing the stability and reliability of the system.

[0021] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the SiC MOSFET gate-drain buffer circuit parameter design method described in this embodiment of the invention.

[0024] Figure 2 This is a schematic diagram of the system structure for designing the SiC MOSFET gate-drain buffer circuit parameters as described in this embodiment of the invention.

[0025] Figure 3 This is a schematic diagram of the device structure for designing the SiC MOSFET gate-drain buffer circuit parameters as described in this embodiment of the invention.

[0026] Figure 4 This is a double-pulse test circuit diagram for a pre-set SiC MOSFET gate-drain buffer circuit.

[0027] Figure 5 This is the simplified equivalent circuit diagram.

[0028] Figure 6 The root locus plots are shown for different gate-drain buffer resistors.

[0029] Figure 7 The root locus is for a gate-drain buffer resistor of 10Ω.

[0030] Figure 8 The graph shows the drain-source voltage curves under different buffer capacitors.

[0031] Figure 9 The graph shows the drain-source voltage curves under different buffer resistors.

[0032] Figure 10 V at a DC side voltage of 400V ds A comparison of the original oscillation waveform and the waveform with the SiC MOSFET gate-drain buffer circuit added.

[0033] Figure 11 V at 800V DC side voltageds A comparison of the original oscillation waveform and the waveform with the SiC MOSFET gate-drain buffer circuit added.

[0034] Figure 12 When the external gate resistance is 0.85Ω, V ds A comparison of the original oscillation waveform and the waveform with the SiC MOSFET gate-drain buffer circuit added.

[0035] Figure 13 When the external gate resistance is 1.7Ω, V ds A comparison of the original oscillation waveform and the waveform with the SiC MOSFET gate-drain buffer circuit added.

[0036] Figure 14 When the external gate resistance is 3.4Ω, V ds A comparison of the original oscillation waveform and the waveform with the SiC MOSFET gate-drain buffer circuit added.

[0037] The diagram is labeled as follows: 800, SiC MOSFET gate-drain buffer circuit parameter design equipment; 801, processor; 802, memory; 803, multimedia component; 804, I / O interface; 805, communication component; 901, acquisition module; 902, first processing module; 903, second processing module; 904, third processing module; 905, fourth processing module. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0039] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] Example 1:

[0041] This embodiment provides a method for designing the gate-drain snubber circuit parameters for a SiC MOSFET. It is understood that this embodiment can be used to illustrate a scenario, such as in a high-frequency, high-voltage power electronic system where SiC MOSFETs experience severe voltage oscillations during switching. Engineers need to quickly determine the gate-drain snubber circuit parameters in such a situation.

[0042] See Figure 1 The figure shows that the method includes steps S1, S2, S3, S4, and S5, which specifically include:

[0043] Step S1: Obtain the preset dual-pulse test circuit of the SiC MOSFET gate-drain buffer circuit;

[0044] In this step, the pre-set double-pulse test circuit of the SiC MOSFET gate-drain buffer circuit is as follows: Figure 4 As shown, it should be noted that Figure 4 C bus A voltage regulator capacitor is connected in parallel at V dc At both ends of the (DC voltage source), the gate of the second SiC MOSFET Q2 is connected to R. g1 (External gate resistor) connected to V g2 The driving voltage (L) and inductor (L) are connected in parallel across the second SiC MOSFET Q2. The source of the second SiC MOSFET Q2 is connected to the drain of the first SiC MOSFET Q1. The gate of the first SiC MOSFET Q1 is connected to the driving voltage V through Rg (external gate resistor). g1 The source of the first SiC MOSFET Q1 is connected to V. dc The negative terminal of the (DC voltage source), and the D in the buffer circuit. snub This is a buffer diode. The anode of the buffer diode is connected to the drain of the first SiC MOSFET Q1, and the cathode of the buffer diode is connected to the buffer capacitor C. snub Connected, buffer capacitor C snub With R snub One end of the buffer resistor is connected, R snub The other end of the (buffer resistor) is connected to the gate of the first SiC MOSFET Q1.

[0045] Step S2: Construct an expression for the drain-source voltage of the SiC MOSFET in the S-domain based on the preset dual-pulse test circuit of the SiC MOSFET gate-drain buffer circuit;

[0046] Step S2 further includes steps S21, S22, S23, S24, and S25, which specifically include:

[0047] Step S21: Obtain simplified rules;

[0048] In this step, the simplified rules are as follows: 1) The load inductance L is approximately an open circuit. 2) C bus The voltage regulator capacitor is approximately short-circuited. 3) During the turn-off period, the SiC MOSFET can be considered as C... gs (Gate-source capacitance), C gd (gate-drain capacitance) and C ds (Drain-source capacitance) delta connection. 4) When the SiC MOSFET gate-drain snubber circuit is working, D snub (Buffer diode) is in the on state.

[0049] Step S22: Simplify the dual-pulse test circuit of the preset SiC MOSFET gate-drain buffer circuit according to the simplification rules to obtain the equivalent circuit;

[0050] In this step, the simplified equivalent circuit is as follows: Figure 5 As shown, it should be noted that Figure 5 The definitions of each component are shown in Table 1.

[0051] Table 1. Component Definitions for Equivalent Circuits

[0052]

[0053] Step S23: Write Kirchhoff's voltage equation and Kirchhoff's current equation based on the equivalent circuit.

[0054] Step S24: Perform Laplace transform on the Kirchhoff voltage equation and the Kirchhoff current equation to obtain the equation set in the S domain.

[0055] In this step, Kirchhoff's voltage equation and current equation in the S-domain are written based on the equivalent circuit, specifically including:

[0056] i p (s)-i snub (s)-s*C gd *V gd (s)-s*C ds *V ds (s)=0 (1)

[0057] i ds (s)-s*C gs *V gs (s)-s*C ds *V ds (s)=0 (2)

[0058] i ds (s)-ig (s)-i p (s)=0 (3)

[0059] R snub *i snub (s)+i snub (s) / (s*C snub )+R snub *(i snub (s)+i g (s))-V gd (s)=0 (4)

[0060] s*L g *i g (s)-L g *i0+R g *i g (s)+R snub *(i snub (s)+i g (s))+V gs (s)+s*L eq *i ds (s)-L eq *i0=0 (5)

[0061] s*L loop *i p (s)-L loop *i0+V ds (s)+s*L eq *i ds (s)-L eq *i0=0 (6)

[0062] V gs (s)+V gd (s)-V ds (s)=0 (7)

[0063] The parameters in the above formulas (1)-(7) are explained in Table 1, and will not be repeated here. i0 represents the initial current.

[0064] Step S25: Determine the expression for the drain-source voltage of the SiC MOSFET in the S-domain based on the set of equations in the S-domain.

[0065] In this step, equations (1)-(7) are simplified and transformed into expressions for the drain-source voltage of a single variable, the SiC MOSFET, as follows:

[0066]

[0067] In the above equation, N(s) represents a polynomial in terms of the complex variable s, reflecting the effect of the initial conditions on the drain-source voltage V of the SiC MOSFET. ds The influence of (s) in the s-domain; also a polynomial in the complex variable s, reflecting the circuit's structure and component parameter characteristics, together constitute the drain-source voltage V in the s-domain. ds The transfer function expression of (s), in addition, a1, a2, a3, b1, b2, b3, b4, b5 all represent algebras.

[0068] Step S3: Transform the expression for the drain-source voltage of the SiC MOSFET in the S-domain into an equation expression, wherein the buffer capacitor is used as a variable.

[0069] Step S3 further includes steps S31 and S32, which specifically include:

[0070] Step S31: Set the denominator polynomial of the expression for the drain-source voltage of the SiC MOSFET in the S-domain to 0;

[0071] Step S32: Transform the expression after setting it to 0 to obtain an equation expression with the buffer capacitor as the variable.

[0072] In this step, let D(s) = 0, and transform the equation into a form with the gate-drain buffer capacitance as the variable, specifically:

[0073]

[0074] In the above formula, c1, c2, c3, c4, d1, d2, d3, d4, and d5 are all algebras.

[0075] Step S4: Draw a root locus diagram based on the equation expression. The root locus diagram includes the changes in the root locus corresponding to different buffer resistors.

[0076] Step S5: Analyze the root locus diagram to obtain the design parameters of the SiC MOSFET gate-drain buffer circuit with a damping ratio of 1.

[0077] In this step, based on the formula with the gate-drain buffer capacitor as the variable, multiple gate-drain buffer resistor values ​​are assumed. By plotting the root locus, an assumed gate-drain buffer resistor parameter value that satisfies the condition that the dominant pole has no oscillation term is found. This parameter value is then used to determine the range of gate-drain buffer capacitor parameter values. Within this range, the selected gate-drain buffer resistor and gate-drain buffer capacitor parameter values ​​can achieve better oscillation suppression.

[0078] Step S5 further includes steps S51, S52, S53, and S54, which specifically include:

[0079] Step 51: Analyze the root locus diagram to determine whether there is an oscillating term at the dominant pole of the root locus for each buffer resistor parameter value, and obtain the judgment result;

[0080] In this step, such as Figure 6 The figure shows the root locus diagrams for different gate-drain buffer resistors. Given gate-drain buffer resistors of 1Ω, 5Ω, 10Ω, 15Ω, and 30Ω, the device datasheet parameters and dual-pulse test circuit parameters are substituted into the equation with the buffer capacitor as the variable. By analyzing the position of the root in the complex plane, and as the gate-drain buffer capacitor gradually increases from 0, the root locus for different values ​​can be obtained. Figure 6 It can be observed that when the gate-drain buffer resistance is 30Ω, the dominant pole of the root locus always has an oscillating term, and the system is in an unstable state. At this point, no parameter with a damping ratio of 1 (complete oscillation suppression) can be found. When the gate-drain buffer resistance is 15Ω, the dominant pole of the root locus does not have an oscillating term, and the system is in a stable state. At this point, a parameter with a damping ratio of 1 (complete oscillation suppression) can be found, and this is the critical value for the system to be in a stable state; exceeding this value, no parameter with a damping ratio of 1 can be found. Therefore, it can be concluded that when the gate-drain buffer resistance is greater than 15Ω, the dominant pole of the root locus always has an oscillating term. It is understood that the manual parameters and double-pulse test circuit parameters used in the calculation are shown in Table 2.

[0081] Table 2. Schematic diagram of manual parameters and dual-pulse test circuit parameters.

[0082] symbol numerical values symbol numerical values <![CDATA[L eq ]]> 6.38nH <![CDATA[L loop ]]> 170nH <![CDATA[C gd ]]> 8pF <![CDATA[L g ]]> 10.4863nH <![CDATA[C gs ]]> 3349pF <![CDATA[R gint ]]> 1.7Ω <![CDATA[C ds ]]> 121pF <![CDATA[R g ]]> 1.7Ω

[0083] Step 52: Filter the buffer resistor parameter values ​​according to the judgment result to obtain the filtering result;

[0084] In this step, based on the judgment results, it can be determined that the gate-drain buffer resistance should be less than or equal to 15Ω.

[0085] Step 53: Determine the range of values ​​for the buffer resistor parameter based on the screening results;

[0086] Step 54: Determine the corresponding range of values ​​for the buffer capacitor parameters based on the range of values ​​for the buffer resistor parameters.

[0087] In this step, see Figure 7 As shown, when the gate-drain buffer resistance is 10Ω, the root locus can be obtained under continuously changing gate-drain buffer capacitance. Figure 7As can be seen, with the continuous increase of the gate-drain buffer capacitance, the poles of the system gradually move closer to the real axis, showing a gradual transition from an underdamped state to a critically damped state. To keep the damping ratio at 1, the gate-drain buffer capacitance must be greater than or equal to 4.89 nF.

[0088] Following step S54, steps S55, S56, and S57 are further included, which specifically include:

[0089] Step S55: Based on the range of values ​​for the buffer resistor parameter and the range of values ​​for the buffer capacitor parameter, select multiple parameter combinations for simulation processing to obtain the drain-source voltage waveform diagram corresponding to each combination;

[0090] Step S56: Compare and analyze the drain-source voltage waveforms corresponding to each combination to obtain analysis results, including the voltage oscillation and overshoot suppression effect corresponding to each combination;

[0091] Step S57: Determine the parameter values ​​of the buffer capacitor and the buffer resistor based on the analysis results.

[0092] In this embodiment, a specific implementation method is as follows: Figure 8 As shown, with the gate-drain buffer capacitance known to be greater than or equal to 4.89nF, simulations were conducted by continuously changing the gate-drain buffer capacitance. Multiple drain-source voltage waveforms obtained from the simulations were compared, and the gate-drain buffer capacitance value with the best voltage oscillation and overshoot suppression effect was selected as the final result. With the gate-drain buffer resistance set to 10Ω, comparisons of the Vds (drain-source voltage) waveforms when the gate-drain buffer capacitance was 5nF, 10nF, and 20nF revealed that: as the gate-drain buffer capacitance increased, the voltage peak value gradually increased; when the gate-drain buffer capacitance was too small, Vds still oscillated slightly when returning to the vicinity of the bus voltage, causing the oscillation time to increase. Under 600V operating conditions, the overshoot of the original voltage oscillation is about 718V, and the oscillation time is 0.6μs. After adopting a gate-drain buffer circuit with a gate-drain buffer capacitor of 10nF, the peak voltage drops to about 640V, the oscillation time is shortened to 0.15μs, and the voltage overshoot is reduced from 19.67% to 6.67%. The suppression effect of the SiC MOSFET gate-drain buffer circuit is obvious. Therefore, a gate-drain buffer capacitor of 10nF is selected.

[0093] like Figure 9As shown, when the gate-drain buffer capacitor is determined to be 10nF, the waveforms of Vds under different gate-drain buffer resistors are compared to verify whether a gate-drain buffer resistor of 10Ω is the optimal solution for completely suppressing voltage oscillations and overshoot. By comparing the Vds waveforms with gate-drain buffer resistors of 6Ω, 10Ω, and 14Ω, it can be found that as the gate-drain buffer resistor increases, the voltage peak value increases significantly; as the gate-drain buffer resistor decreases, the oscillation time gradually increases, and when the gate-drain buffer resistor is too small, Vds still oscillates slightly when it returns to near the bus voltage. Therefore, a gate-drain buffer resistor of 10Ω is selected.

[0094] Following step S57, steps S58, S59, and S510 are further included, which specifically include:

[0095] Step S58: Calculate the time constant based on the parameter values ​​of the buffer capacitor and the buffer resistor;

[0096] In this step, the buffer capacitor parameter value and the buffer resistor parameter are multiplied together to obtain the time constant.

[0097] Step S59: Determine whether the time constant is less than the preset turn-off time, and obtain the determination result;

[0098] In this step, the preset shutdown time is 2µs.

[0099] Step S510: Determine whether the parameter values ​​of the buffer capacitor and the buffer resistor need to be optimized based on the judgment result.

[0100] In this step, to ensure that the buffer circuit can completely release the absorbed energy during the working phase, the time constant of this branch must be less than the working time of this phase. If the obtained time constant is greater than the turn-off time, the parameters of the buffer capacitor and the buffer resistor need to be re-evaluated within a reasonable range.

[0101] It should be noted that the parameters and selection of the SiC MOSFET gate-drain snubber circuit in this application are as follows: the snubber resistor is 10Ω, the snubber capacitor is 10nF, and the snubber diode is VS-E5PX6012. The circuit's performance was verified under different operating conditions using these parameters. Figure 10 and Figure 11 The figures show the effect verification at 400V and 800V, respectively. Figure 10 It can be seen that under 400V operating conditions, the overshoot of the original voltage oscillation is approximately 453V, and the oscillation duration is 0.6μs. After using a gate-drain snubber circuit, the peak voltage is reduced to approximately 419V, the oscillation time is shortened to 0.15μs, and the voltage overshoot is reduced from 13.25% to 4.75%. Figure 11It can be seen that under the condition of 800V, the overshoot of the original voltage oscillation is about 1010V and the oscillation duration is 0.6μs. After using the gate-drain buffer circuit, the voltage peak is reduced to about 870V, the oscillation time is reduced to 0.15μs, and the overshoot is reduced from 26.25% to 8.75%.

[0102] like Figures 12-14 The image shows the effect verification of different external gate resistors at 800V. The external gate resistor values ​​are 0.85Ω, 1.7Ω, and 3.4Ω, respectively. Figure 12 It can be seen that when the external gate resistance is 0.85Ω, the peak voltage decreases from 1002V to approximately 866V; Figure 13 It can be seen that when the external gate resistance is 1.7Ω, the peak voltage decreases from 1010V to approximately 870V; Figure 14 It can be seen that when the external gate resistance is 3.4Ω, the peak voltage drops from 1023V to approximately 874V. Therefore, under different DC voltage conditions or with different external gate resistance values, this set of parameters can effectively suppress voltage oscillation and overshoot, indicating that the parameter selection has good adaptability and rationality.

[0103] Example 2:

[0104] like Figure 2 As shown, this embodiment provides a SiC MOSFET gate-drain buffer circuit parameter design system. The system includes an acquisition module 901, a first processing module 902, a second processing module 903, a third processing module 904, and a fourth processing module 905, specifically including:

[0105] The acquisition module 901 is used to acquire the preset double-pulse test circuit of the SiC MOSFET gate-drain buffer circuit;

[0106] The first processing module 902 is used to construct an expression for the drain-source voltage of the SiC MOSFET in the S-domain based on the preset dual-pulse test circuit of the SiC MOSFET gate-drain buffer circuit.

[0107] The second processing module 903 is used to convert the expression of the drain-source voltage of the SiC MOSFET in the S-domain into an equation expression, wherein the equation expression uses the buffer capacitor as a variable.

[0108] The third processing module 904 is used to draw a root locus diagram based on the equation expression, and the root locus diagram includes the root locus changes corresponding to different buffer resistors.

[0109] The fourth processing module 905 is used to analyze the root locus diagram to obtain the design parameters of the SiC MOSFET gate-drain buffer circuit with a damping ratio of 1.

[0110] In one specific embodiment of this disclosure, the first processing module further includes an acquisition unit, a first processing unit, a second processing unit, a third processing unit, and a fourth processing unit, specifically including:

[0111] The acquisition unit is used to acquire simplified rules;

[0112] The first processing unit is used to simplify the double-pulse test circuit of the preset SiC MOSFET gate-drain buffer circuit according to the simplification rules to obtain an equivalent circuit.

[0113] The second processing unit is used to write Kirchhoff's voltage equation and Kirchhoff's current equation based on the equivalent circuit.

[0114] The third processing unit is used to perform Laplace transform on the Kirchhoff voltage equation and the Kirchhoff current equation to obtain a set of equations in the S-domain.

[0115] The fourth processing unit is used to determine the expression of the drain-source voltage of the SiC MOSFET in the S-domain based on the set of equations in the S-domain.

[0116] In one specific embodiment of this disclosure, the second processing module further includes a fifth processing unit and a sixth processing unit, specifically including:

[0117] The fifth processing unit is used to set the denominator polynomial of the expression for the drain-source voltage of the SiC MOSFET in the S-domain to 0;

[0118] The sixth processing unit is used to transform the expression after setting it to 0 to obtain an equation expression with the buffer capacitor as the variable.

[0119] In one specific embodiment of this disclosure, the fourth processing module further includes a seventh processing unit, an eighth processing unit, a ninth processing unit, and a tenth processing unit, specifically comprising:

[0120] The seventh processing unit is used to analyze the root locus diagram, determine whether there is an oscillating term at the dominant pole of the root locus for each buffer resistor parameter value, and obtain the determination result.

[0121] The eighth processing unit is used to filter the buffer resistor parameter values ​​according to the judgment result to obtain the filtering result;

[0122] The ninth processing unit is used to determine the range of values ​​for the buffer resistor parameter based on the screening results.

[0123] The tenth processing unit is used to determine the corresponding range of buffer capacitor parameters based on the range of values ​​for the buffer resistor parameters.

[0124] In one specific embodiment of this disclosure, the tenth processing unit is followed by an eleventh processing unit, a twelfth processing unit, and a thirteenth processing unit, specifically including:

[0125] The eleventh processing unit is used to select multiple parameter combinations for simulation processing based on the value range of the buffer resistor parameter and the value range of the buffer capacitor parameter, and obtain the drain-source voltage waveform diagram corresponding to each combination.

[0126] The twelfth processing unit is used to compare and analyze the drain-source voltage waveforms corresponding to each combination to obtain analysis results, including the voltage oscillation and overshoot suppression effect corresponding to each combination.

[0127] The thirteenth processing unit is used to determine the parameter values ​​of the buffer capacitor and the buffer resistor based on the analysis results.

[0128] In one specific embodiment of this disclosure, the thirteenth processing unit is followed by a fourteenth processing unit, a fifteenth processing unit, and a sixteenth processing unit, specifically including:

[0129] The fourteenth processing unit is used to calculate the time constant based on the buffer capacitor parameter value and the buffer resistor parameter value;

[0130] The fifteenth processing unit is used to determine whether the time constant is less than the preset shutdown time and obtain the determination result;

[0131] The sixteenth processing unit is used to determine whether the parameter values ​​of the buffer capacitor and the buffer resistor need to be optimized based on the judgment result.

[0132] It should be noted that the specific methods by which each module performs operations in the system described in the above embodiments have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0133] Example 3:

[0134] Corresponding to the above method embodiments, this embodiment also provides a SiC MOSFET gate-drain buffer circuit parameter design device. The SiC MOSFET gate-drain buffer circuit parameter design device described below and the SiC MOSFET gate-drain buffer circuit parameter design method described above can be referred to each other.

[0135] Figure 3 This is a block diagram illustrating a SiC MOSFET gate-drain buffer circuit parameter design device 800 according to an exemplary embodiment. Figure 3As shown, the SiC MOSFET gate-drain buffer circuit parameter design device 800 may include: a processor 801 and a memory 802. The SiC MOSFET gate-drain buffer circuit parameter design device 800 may also include one or more of a multimedia component 803, an I / O interface 804, and a communication component 805.

[0136] The processor 801 controls the overall operation of the SiC MOSFET gate-drain buffer circuit parameter design device 800 to complete all or part of the steps in the aforementioned SiC MOSFET gate-drain buffer circuit parameter design method. The memory 802 stores various types of data to support the operation of the SiC MOSFET gate-drain buffer circuit parameter design device 800. This data may include, for example, instructions for any application or method operating on the SiC MOSFET gate-drain buffer circuit parameter design device 800, as well as application-related data such as contact data, sent and received messages, images, audio, video, etc. The memory 802 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The multimedia component 803 may include a screen and an audio component. The screen may be, for example, a touchscreen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in the memory 802 or transmitted via the communication component 805. The audio component also includes at least one speaker for outputting audio signals. I / O interface 804 provides an interface between processor 801 and other interface modules, such as keyboards, mice, and buttons. These buttons can be virtual or physical. Communication component 805 is used for wired or wireless communication between the SiC MOSFET gate-drain buffer circuit parameter design device 800 and other devices. Wireless communication includes Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination thereof. Therefore, the corresponding communication component 805 may include a Wi-Fi module, a Bluetooth module, or an NFC module.

[0137] In an exemplary embodiment, the SiC MOSFET gate-drain buffer circuit parameter design device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the SiC MOSFET gate-drain buffer circuit parameter design method described above.

[0138] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided. When executed by a processor, these program instructions implement the steps of the SiC MOSFET gate-drain buffer circuit parameter design method described above. For example, the computer-readable storage medium may be the memory 802 including the program instructions described above. These program instructions may be executed by the processor 801 of the SiC MOSFET gate-drain buffer circuit parameter design device 800 to complete the SiC MOSFET gate-drain buffer circuit parameter design method described above.

[0139] Example 4:

[0140] Corresponding to the above method embodiments, this embodiment also provides a readable storage medium. The readable storage medium described below can be referred to in conjunction with the SiC MOSFET gate-drain buffer circuit parameter design method described above.

[0141] A readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the SiC MOSFET gate-drain buffer circuit parameter design method described in the above method embodiments.

[0142] Specifically, the readable storage medium can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other readable storage medium capable of storing program code.

[0143] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0144] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for designing a SiC MOSFET gate-drain snubber circuit parameter, characterized in that, The method comprises the following steps: acquiring a preset double-pulse test circuit of a SiC MOSFET gate-drain buffer circuit; constructing an expression of SiC MOSFET drain-source voltage in S domain based on the preset double-pulse test circuit of the SiC MOSFET gate-drain buffer circuit; transforming the expression of SiC MOSFET drain-source voltage in S domain into an equation expression with buffer capacitance as a variable; drawing a root locus graph according to the equation expression, wherein the root locus graph comprises root locus variation conditions corresponding to different buffer resistances; analyzing the root locus graph to obtain design parameters of the SiC MOSFET gate-drain buffer circuit with a damping ratio of 1.

2. The SiC MOSFET gate-drain snubber circuit parameter design method according to claim 1, characterized in that, The method of constructing an expression of SiC MOSFET drain-source voltage in S domain based on the preset double-pulse test circuit of the SiC MOSFET gate-drain buffer circuit comprises the following steps: acquiring a simplification rule; simplifying the preset double-pulse test circuit of the SiC MOSFET gate-drain buffer circuit according to the simplification rule to obtain an equivalent circuit; writing Kirchhoff voltage equations and Kirchhoff current equations according to the equivalent circuit; performing Laplace transform processing on the Kirchhoff voltage equations and the Kirchhoff current equations to obtain an equation group in S domain; determining the expression of SiC MOSFET drain-source voltage in S domain according to the equation group in S domain.

3. The SiC MOSFET gate-drain snubber circuit parameter design method of claim 1, wherein, The method of transforming the expression of SiC MOSFET drain-source voltage in S domain into an equation expression with buffer capacitance as a variable comprises the following steps: setting a denominator polynomial of the expression of SiC MOSFET drain-source voltage in S domain to 0; transforming the expression after setting to 0 to obtain the equation expression with buffer capacitance as a variable.

4. The SiC MOSFET gate-drain snubber circuit parameter design method of claim 1, wherein, The method of analyzing the root locus graph to obtain design parameters of the SiC MOSFET gate-drain buffer circuit with a damping ratio of 1 comprises the following steps: analyzing the root locus graph to determine whether there is an oscillation term in a root locus dominant pole of each buffer resistance parameter value, and obtaining a determination result; screening buffer resistance parameter values according to the determination result, and obtaining a screening result; determining a buffer capacitance parameter value range according to the buffer resistance parameter value range; determining a corresponding buffer capacitance parameter value range according to the buffer resistance parameter value range.

5. The SiC MOSFET gate-drain snubber circuit parameter design method according to claim 4, characterized in that, After determining the corresponding buffer capacitance parameter value range according to the buffer resistance parameter value range, the method further comprises the following steps: selecting a plurality of parameter combinations according to the buffer resistance parameter value range and the buffer capacitance parameter value range to perform simulation processing, and obtaining drain-source voltage waveform graphs corresponding to each combination; comparing and analyzing the drain-source voltage waveform graphs corresponding to each combination to obtain an analysis result, wherein the analysis result comprises voltage oscillation and overshoot suppression effects corresponding to each combination; determining buffer capacitance parameter values and buffer resistance parameter values according to the analysis result.

6. A SiC MOSFET gate-drain snubber circuit parameter design system, characterized by, The method comprises the following steps: an acquiring module is configured to acquire a preset double-pulse test circuit of a SiC MOSFET gate-drain buffer circuit; The first processing module is configured to construct an expression of SiC MOSFET drain-source voltage in S domain based on the preset double-pulse test circuit of the SiC MOSFET gate-drain buffer circuit; The second processing module is configured to convert the expression of SiC MOSFET drain-source voltage in S domain into an equation expression with buffer capacitance as a variable; The third processing module is configured to draw a root locus diagram according to the equation expression, and the root locus diagram includes root locus change conditions corresponding to different buffer resistances; The fourth processing module is configured to analyze the root locus diagram to obtain design parameters of the SiC MOSFET gate-drain buffer circuit with a damping ratio of 1.

7. The SiC MOSFET gate-drain snubber circuit parameter design system of claim 6, wherein, The first processing module comprises: An acquisition unit configured to acquire a simplification rule; A first processing unit configured to simplify the preset double-pulse test circuit of the SiC MOSFET gate-drain buffer circuit according to the simplification rule to obtain an equivalent circuit; A second processing unit configured to write Kirchhoff voltage equations and Kirchhoff current equations according to the equivalent circuit; A third processing unit configured to perform Laplace transform processing on the Kirchhoff voltage equations and the Kirchhoff current equations to obtain an equation group in S domain; A fourth processing unit configured to determine an expression of SiC MOSFET drain-source voltage in S domain according to the equation group in S domain.

8. The SiC MOSFET gate-drain snubber circuit parameter design system of claim 6, wherein, The second processing module comprises: A fifth processing unit configured to set a denominator polynomial of the expression of SiC MOSFET drain-source voltage in S domain to 0; A sixth processing unit configured to deform the expression after setting to 0 to obtain an equation expression with buffer capacitance as a variable.

9. The SiC MOSFET gate-drain snubber circuit parameter design system of claim 6, wherein, The fourth processing module comprises: A seventh processing unit configured to analyze the root locus diagram to determine whether an oscillation term exists in a root locus dominant pole of each buffer resistance parameter value, and obtain a determination result; An eighth processing unit configured to filter buffer resistance parameter values according to the determination result, and obtain a filtering result; A ninth processing unit configured to determine a buffer resistance parameter value range according to the filtering result; A tenth processing unit configured to determine a corresponding buffer capacitance parameter value range according to the buffer resistance parameter value range.

10. The SiC MOSFET gate-drain snubber circuit parameter design system of claim 9, wherein, The tenth processing unit further comprises: An eleventh processing unit configured to select a plurality of parameter combinations according to the buffer resistance parameter value range and the buffer capacitance parameter value range, and perform simulation processing to obtain drain-source voltage waveform diagrams corresponding to the combinations; A twelfth processing unit configured to compare and analyze the drain-source voltage waveform diagrams corresponding to the combinations to obtain an analysis result, and the analysis result includes voltage oscillation and overshoot suppression effects corresponding to each combination; A thirteenth processing unit configured to determine buffer capacitance parameter values and buffer resistance parameter values according to the analysis result.

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