Memory and testing method

Abstract

The invention provides a memory and a test method, the memory comprises a plurality of memory areas, a command address circuit and a data circuit, the input end of the command address circuit receives a command address signal and a test enable signal; the test enable signal represents whether a compression test mode is started or not, when the test enable signal represents that the compression test mode is started, the command address circuit decodes the command address signal to generate a target activation signal, a first row address and a parallel writing instruction which are used for activating all storage areas, and the data circuit is connected with the command address circuit; the data circuit receives a parallel writing instruction, the data circuit supplements the bit number of initial test data based on the parallel writing instruction and outputs supplemented test data, each storage area is connected with the data circuit, each storage area is connected with the command address circuit, and each storage area is activated by a target activation signal; and writing the supplemented test data into the storage unit corresponding to the first row address.

Description

Technical Field

[0001] This application relates to, but is not limited to, a memory and a testing method. Background Technology

[0002] With the development of memory technology, memory has been widely used in many fields. For example, Dynamic Random Access Memory (DRAM) is widely used.

[0003] As we all know, memory chips need to undergo a series of tests after tape-out before they can be finally released to the market. Improving the testing efficiency of memory chips is an important area for improvement. Summary of the Invention

[0004] This application provides a memory, including: multiple memory areas, a command address circuit, and a data circuit;

[0005] The input of the command address circuit receives the command address signal and the test enable signal. The test enable signal indicates whether the compression test mode is enabled. When the test enable signal indicates that the compression test mode is enabled, the command address circuit generates the target activation signal, the first row address, and the parallel write instruction for activating all memory areas based on the decoding of the command address signal.

[0006] The data circuit is connected to the command address circuit. The data circuit receives parallel write instructions and outputs supplementary test data based on the number of bits in the initial test data according to the parallel write instructions.

[0007] Each storage area is connected to the data circuit, each storage area is connected to the command address circuit, each storage area is activated by the target activation signal, and supplementary test data is written into the storage unit corresponding to the first row address.

[0008] In some embodiments, the command address circuit includes a first decoding circuit and a second decoding circuit;

[0009] The input of the first decoding circuit receives the command address signal and the test enable signal, and decodes the command address signal and the test enable signal to generate the memory area address, the activation command, and the second line address; the first line address is generated based on the second line address.

[0010] The input of the second decoding circuit is connected to the output of the first decoding circuit. The second decoding circuit receives the memory area address and activation command. The second decoding circuit also receives a test enable signal and a forced activation signal. The forced activation signal indicates whether all memory areas are activated. The second decoding circuit outputs a target activation signal.

[0011] In some embodiments, the command address circuit further includes a first driving circuit and a row address latching circuit;

[0012] The input terminal of the first driving circuit is connected to the output terminal of the first decoding circuit, and the output terminal of the first driving circuit is connected to the input terminal of the second decoding circuit. The first driving circuit outputs the address of the storage area after signal enhancement.

[0013] The input of the row address latch circuit is connected to the output of the first decoding circuit, and the output of the row address latch circuit is connected to each storage area. The row address latch circuit latches the second row address based on the activation command and then outputs the first row address, which is then output to the storage area.

[0014] In some embodiments, the data circuitry includes a supplementary circuitry, a replication circuitry, and a control circuitry.

[0015] The input terminal of the control circuit receives the parallel write command and outputs supplementary control signal and copy control signal according to the parallel write command;

[0016] The input terminal of the supplementary circuit is connected to the data port. The initial test data enters the supplementary circuit through the data port. The control terminal of the supplementary circuit receives the supplementary control signal. Based on the supplementary control signal, the supplementary circuit supplements the number of bits of the initial test data and outputs the first intermediate test data.

[0017] The input terminal of the replication circuit is connected to the output terminal of the supplementation circuit; the control terminal of the replication circuit receives the replication control signal, and the replication circuit replicates the first intermediate test data at least once and outputs the supplemented test data; wherein the number of bits in the supplemented test data is an integer multiple of the number of bits in the first intermediate test data.

[0018] In some embodiments, the replication control signal includes a first replication control sub-signal and a second replication control sub-signal, and the replication circuit includes a first transmission circuit, a writing circuit, and multiple port circuits.

[0019] Each port circuit is connected to the output of the supplementary circuit via a first data line group; each port circuit is used to transmit first intermediate test data; wherein, the number of bits of the first intermediate test data is equal to the number of data lines in the first data line group;

[0020] Each port circuit is connected to the input of the first transmission circuit through a set of second data lines. Each port circuit simultaneously sends first intermediate test data to the first transmission circuit. The control terminal of the first transmission circuit also receives a first copy control sub-signal. Under the control of the first copy control sub-signal, the first transmission circuit enhances the signal of multiple first intermediate test data and outputs second intermediate test data. The number of bits of the second intermediate test data is N times the number of bits of the first intermediate test data, where N is the number of port circuits.

[0021] The writing circuit is connected to the output of the first transmission circuit. The control terminal of the writing circuit receives the second copy control sub-signal. Under the control of the second copy control sub-signal, the writing circuit copies the second intermediate test data and outputs supplementary test data. The number of bits in the supplementary test data is twice the number of bits in the second intermediate test data.

[0022] In some embodiments, the memory includes multiple write circuits, the first transmission circuit includes multiple transmission paths, and one write circuit is connected to the output of one transmission path in the first transmission circuit; the write circuit copies the second intermediate test data output from the corresponding transmission path and outputs supplementary test data.

[0023] A write circuit is connected to multiple memory regions, and any two write circuits are connected to different memory regions. The write circuit writes supplementary test data to the memory regions connected to it.

[0024] In some embodiments, the memory includes multiple memory groups, each memory group includes multiple memory regions, a write circuit is connected to multiple memory groups, and any two write circuits are connected to different memory groups, and a write circuit writes supplementary test data to multiple memory groups.

[0025] In some embodiments, the number of data ports is half the number of data lines in the first data line group; the supplementary circuitry includes multiple supplementary sub-circuits.

[0026] Each supplementary sub-circuit has an input terminal connected to a data port, a control terminal of each supplementary sub-circuit receiving a supplementary control signal, which represents the replication mode, an input terminal of each supplementary sub-circuit receiving 1 bit of initial test data, an output terminal of each supplementary sub-circuit outputting 2 bits of first intermediate test data, and multiple supplementary sub-circuits outputting 2L bits of first intermediate test data, where L is the number of data ports.

[0027] In some embodiments, each supplementary subcircuit connects to two non-adjacent data lines in the first data line group, and each supplementary subcircuit connects to different data lines.

[0028] In some embodiments, the memory further includes a write register;

[0029] The data circuit is also connected to the write register, which is used to write the supplemented test data into the write register.

[0030] In some embodiments, the memory further includes a plurality of readout circuits and a detection circuit;

[0031] A readout circuit is connected to a storage area, and each readout circuit is used to read the supplementary test data in the corresponding storage area;

[0032] The detection circuit is connected to each readout circuit and is used to receive supplementary post-test data read from each storage area.

[0033] The detection circuit is also connected to the write register. The detection circuit also reads the supplemented test data from the write register and compares the supplemented test data read from each storage area with the supplemented test data read from the write register to obtain the test result for each storage area.

[0034] Some embodiments of this application also provide a method for testing a memory, the memory including multiple storage areas, the method comprising:

[0035] Receive command address signal and test enable signal; wherein, the test enable signal indicates whether the compression test mode is enabled, the command address signal and the test enable signal are used to generate target activation signal, first line address and parallel write instruction, the parallel write instruction is used to supplement the initial test data with bits and output the supplemented test data;

[0036] When the test enable signal indicates that the compression test mode is enabled, a target activation signal, the first row address, and supplemented test data are sent to each storage area. After each storage area is activated by the target activation signal, the supplemented test data is written into the storage unit corresponding to the first row address.

[0037] In some embodiments, the memory further includes a write register, and the method further includes:

[0038] Write the supplemented test data into the write register.

[0039] In some embodiments, the method further includes:

[0040] Read the supplemented test data from each storage area and read the supplemented test data from the write register;

[0041] The supplemented test data read from each storage area is compared with the supplemented test data read from the write register to obtain the test results for each storage area.

[0042] The memory and testing method provided in this application's first embodiment output supplemented test data from the data circuit, and the target activation signal output by the command address circuit is used to activate all memory areas. Based on the first row address output by the command address circuit, the supplemented test data is written to each memory area. There is no need to write the data to the mode register first, and then read the data from the mode register and write it to the memory area. This can reduce the data writing time in the compressed test mode and occupy less resources. Since there is no need to use the mode register to store the test data, the test data can be written accurately, improving the test accuracy. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0044] Figure 1 This is a diagram of a memory architecture;

[0045] Figure 2 for Figure 1 The diagram shows the timing of the memory in parallel write mode.

[0046] Figure 3 and Figure 4 A schematic diagram of the memory architecture provided for some embodiments of this application;

[0047] Figure 5 for Figure 3 and Figure 4 The timing control diagram of the memory is shown;

[0048] Figure 6 This is a circuit schematic diagram of a data circuit;

[0049] Figure 7 A schematic diagram of the circuit structure of a supplementary sub-circuit 30;

[0050] Figure 8A and Figure 8B for Figure 7 The timing diagram of the supplementary sub-circuit is shown;

[0051] Figure 9 This is a schematic diagram of a supplementary circuit architecture;

[0052] Figure 10 This is a circuit schematic diagram of a first transmission circuit 40;

[0053] Figure 11 This is a circuit schematic of a writing circuit 50.

[0054] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0055] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0056] Currently, memory technology is developing rapidly. Taking DRAM as an example, the main types of memory used include Synchronous Dynamic Random-Access Memory (SDRAM), Double Data Rate (DDR) SDRAM of various generations, and Low Power Double Data Rate (LPDDR) SDRAM of various generations.

[0057] As is well known, DRAM chips undergo chip probe (CP) testing and final test (FT) after tape-out before being released to the market. CP testing primarily targets the memory cells of the DRAM, requiring rapid detection of faulty cells for repair. To achieve rapid detection of faulty memory cells, a parallel write mode is typically employed. The parallel write mode of memory is described below.

[0058] Figure 1 This is a diagram of a memory architecture. (For example...) Figure 1 As shown, the memory includes a command decoding circuit 110, a first receiver 130, a second receiver 140, a third decoding circuit 150, a fourth decoding circuit 120, a mode register 160, a memory array 180, and port circuitry 170. The memory array 180 includes multiple memory regions.

[0059] Command decoding circuit 110 is connected to the fourth decoding circuit 120 and the third decoding circuit 150. Command decoding circuit 110 receives the test mode signal, column address strobe pulse signal CAS, row address strobe pulse signal RAS, chip select signal CS, and external activation instruction ACTex. When the test mode signal indicates entry into parallel write mode, command decoding circuit 110 outputs the internal activation instruction ACTin, the mode register write instruction MPR WR, the mode register read instruction MPR RD, and the write instruction WR.

[0060] The mode register write instruction MPR WR is used to write test data into mode register 160, the mode register read instruction MPR RD is used to read test data from mode register 160, the internal activation instruction ACTin is used to activate memory array 180, and the write instruction WR is used to write the test data read from mode register 160 into various memory areas of memory array 180.

[0061] The first receiver 130 receives the memory region address BG / BK at its input terminal, and its output terminal is connected to the input terminal of the third decoding circuit 150. The first receiver 130 sends the received memory region address BG / BK to the third decoding circuit 150. The third decoding circuit 150 also receives the mode register write instruction MPR WR, and decodes the memory region address BG / BK under the control of the mode register write instruction MPR WR, outputting the mode register selection signal MR SEL.

[0062] The input terminal of the second receiver 140 receives the memory cell address AD, and the output terminal of the second receiver 140 is connected to the input terminal of the mode register 160. The mode register selection signal MR SEL and the memory cell address AD are used to write test data into the corresponding mode register 160 or read test data from the corresponding mode register 160.

[0063] The input of the fourth decoding circuit 120 is also connected to the first receiver 130. The fourth decoding circuit 120 receives the memory region address BG / BK from the first receiver 130. The input of the fourth decoding circuit 120 is also connected to the second receiver 140. The fourth decoding circuit 120 receives the memory cell address AD from the second receiver 140. The input of the fourth decoder is connected to the output of the command decoding circuit 110. The fourth decoding circuit 120 receives the write instruction WR and the internal activation instruction ACTin from the command decoding circuit 110. The fourth decoding circuit 120 also receives the forced activation signal TM ALLACT, which is used to activate all memory regions. The output of the fourth decoding circuit 120 is connected to the memory array 180. The fourth decoding circuit 120 determines the memory region address based on the forced activation signal TM ALLACT. The ALLACT, write instruction WR, internal activation instruction ACTin, memory region address BG / BK, and memory cell address AD generate activation signals for each memory region. The output of mode register 160 is connected to memory array 180. The activation signal for each memory region is used to write the test data read from mode register 160 into the corresponding memory cell of the memory region. The output of mode register 160 is also connected to port circuit 170. The test data read from mode register 160 is output through port circuit 170, so that the memory can compare the test data output by port circuit 170 with the data read from the memory region to determine the test result.

[0064] Figure 2 for Figure 1 The diagram shows the timing of the memory in parallel write mode. Figure 2 As shown, when the command decoding circuit 110 receives the test mode signal indicating that it will enter the parallel write mode, it sequentially generates the mode register write instruction MPRWR, the mode register read instruction MPRRD, the internal activation instruction ACTin, and the write instruction WR.

[0065] At the first clock cycle of the chip select signal CS, the command decoding circuit 110 outputs the mode register write instruction MPR WR, the third decoding circuit 150 decodes the memory area address BG / BK received by the first receiver 130 and outputs the mode register select signal MR SEL, the second receiver 140 transmits the memory cell address AD to the mode register 160, and writes test data to the mode register 160 based on the mode register select signal MR SEL and the memory cell address AD.

[0066] At the second clock cycle of the chip select signal CS, the command decoding circuit 110 outputs the mode register read instruction MPR RD. According to the third decoding circuit 150, the memory area address BG / BK is decoded and the mode register select signal MR SEL is output. The mode register 160 also receives the memory cell address AD. According to the mode register select signal MR SEL and the memory cell address AD, the test data is read from the mode register 160. The test data is written to the memory array 180 and also output to the port circuit 170.

[0067] At the third clock cycle of the chip select signal CS, the command decoding circuit 110 outputs the internal activation instruction ACTin, and the fourth decoding circuit 120 also receives the forced activation signal TMALLACT. Based on the internal activation instruction ACTin, the forced activation signal TMALLACT, the memory cell address AD, and the memory area address BG / BK, the activation signal PDANKG for each memory area is generated.

[0068] At the fourth clock cycle of the chip select signal CS, the command decoding circuit 110 outputs the write instruction WR. The write instruction WR is used to read test data from the mode register 160 and write test data to the memory area according to the memory area activation signal PDANKBG, the memory area address BG / BK, and the memory cell address AD. 64 bits of data are written to one memory area, and 1024 bits of data are written to 16 memory areas at once.

[0069] However, writing test data to each memory area requires four instructions, which consumes significant resources and increases circuit area. Since the test data is pseudo-random, the quality of the written pseudo-random numbers is affected by the data quality stored in mode register 160. Furthermore, the writing process is relatively time-consuming, increasing the overall test time.

[0070] Some aspects of the embodiments of this disclosure relate to the above considerations. The following describes the solutions by way of example with reference to some embodiments of this disclosure.

[0071] Figure 3 and Figure 4 This is a schematic diagram of the memory architecture provided for some embodiments of this application. For example... Figure 3 and Figure 4 As shown, some embodiments of this application provide a memory, which includes multiple storage areas, a command address circuit 210, and a data circuit 220.

[0072] The input of the command address circuit 210 receives the command address signal CA and the test enable signal TPARAT. The test enable signal TPARAT indicates whether the compression test mode is enabled. When the test enable signal TPARAT indicates that the compression test mode is enabled, the command address circuit 210 generates the target activation signal PMCBAB, the first row address ACT_RA, and the parallel write instruction PARA WR based on the decoding of the command address signal CA.

[0073] The data circuit 220 is connected to the command address circuit 210. The data circuit 220 receives the parallel write instruction PARA WR and supplements the number of bits of the initial test data based on the parallel write instruction PARA WR, and outputs the supplemented test data.

[0074] Each storage area is connected to the data circuit 220 and the command address circuit 210. When the test enable signal TPARAT indicates that the compression test mode is enabled, each storage area is activated by the target activation signal PMCBAB and supplementary test data is written into the storage unit corresponding to the first row address ACT_RA.

[0075] This example illustrates a memory comprising 8 memory groups, each containing 4 memory regions, for a total of 32 memory regions. When the test enable signal TPARAT indicates that the compression test mode is enabled, the command address circuit 210 outputs the target activation signal PMCBAB to activate all 32 memory regions. For each activated memory region, the corresponding word line is enabled according to the first row address ACT_RA, and supplementary test data is written to the memory cells where the word line is enabled. This allows supplementary test data to be written to each of the 32 memory regions simultaneously.

[0076] With this configuration, the supplemented test data is output by the data circuit 220, and the target activation signal PMCBAB output by the command address circuit 210 is used to activate all storage areas. Based on the first row address ACT_RA output by the command address circuit 210, the supplemented test data is written to each storage area. There is no need to write the data to the mode register 160 first, and then read the data from the mode register 160 and write it to the storage area. This can reduce the data writing time in the compressed test mode and consume less resources. Since there is no need to use the mode register 160 to store the test data, the test data can be written accurately, improving the test accuracy.

[0077] Continue to refer to Figure 3 and Figure 4The command address circuit 210 includes a first decoding circuit 211 and a second decoding circuit 212. The input of the first decoding circuit 211 receives a command address signal CA and a test enable signal TPARAT, and decodes CA and TPARAT to generate a memory region address BG / BK, an activation command PARA_ACT, and a second row address RA. The first row address ACT_RA is generated based on the second row address RA. The input of the second decoding circuit 212 is connected to the output of the first decoding circuit 211. The second decoding circuit 212 receives the memory region address BG / BK and the activation command PARA_ACT. It also receives the test enable signal TPARAT and a forced activation signal TM_ALLACT. The forced activation signal TM_ALLACT indicates whether all memory regions are activated. The second decoding circuit 212 outputs a target activation signal PMCBAB.

[0078] When the test enable signal TPARAT indicates that the compression test mode is enabled, the forced activation signal TM ALLACT indicates that all memory regions are activated. The memory region address BG / BK includes the memory group address BG and the memory region's own address BK. The second decoding circuit 212 processes the memory region address BG / BK and the activation command PARA ACT according to the test enable signal TPARAT and the forced activation signal TM ALLACT, and outputs the target activation signal PMCBAB. The target activation signal PMCBAB is used to activate all memory regions. With this setting, the target activation signal PMCBAB that activates all memory regions can be output.

[0079] Continue to refer to Figure 3 and Figure 4 The command address circuit 210 also includes a first driving circuit 213 and a row address latch circuit 214. The input of the first driving circuit 213 is connected to the output of the first decoding circuit 211, and the output of the first driving circuit 213 is connected to the input of the second decoding circuit 212. The first driving circuit 213 amplifies the signal of the storage area address BG / BK before outputting it. By setting the first driving circuit 213 to amplify the signal of the storage area address BG / BK, the signal strength of the target activation signal PMCBAB generated based on the storage area address BG / BK can be enhanced, so that the target activation signal PMCBAB can activate all storage areas.

[0080] The input of the row address latch circuit 214 is connected to the output of the first decoding circuit 211, and the output of the row address latch circuit 214 is connected to each memory region. The row address latch circuit 214 latches the second row address RA based on the activation command PARA ACT and then outputs the first row address ACT_RA, which is then sent to the memory region. By configuring the row address latch circuit 214 to latch the second row address RA according to the activation command PARA ACT, the timing relationship between the output of the first row address ACT_RA by the row address latch circuit 214 and the target activation signal PMCBAB output by the second decoding circuit 212 can be controlled. This allows for the activation of the memory cell corresponding to the first row address ACT_RA in each memory region, and the writing of test data into the memory cell.

[0081] This example illustrates a memory comprising 8 memory groups, each containing 4 memory regions, resulting in a total of 32 memory regions. The memory group address BG is represented by 3 bits (BG<2:0>), and the memory region address BK within each group is represented by 2 bits (BK<1:0>). Both the second row address RA and the first row address ACT_RA are 16 bits. Taking the second row address RA as an example, RA<15:13> represents the memory group it belongs to. The second decoding circuit 212 processes the memory group address BG<2:0>, the memory region address BK<1:0>, and the activation command PARA ACT based on the test enable signal TPARAT and the forced activation signal TM ALLACT, outputting a 32-bit target activation signal PMCBAB. Each bit indicates whether one of the memory regions is activated. For example: PMCBAB <0> Indicates whether to activate the first storage region, PMCBAB <1> This indicates whether to activate the second storage area, and so on.

[0082] Continue to refer to Figure 3 The data circuit 220 includes a supplementary circuit 221, a copying circuit 222, and a control circuit 223. The input terminal of the control circuit 223 receives the parallel write instruction PARA WR and outputs the supplementary control signal BCTRL and the copying control signal CoCTRL according to the parallel write instruction PARA WR.

[0083] The input terminal of the supplementary circuit 221 is connected to the data port. The initial test data enters the supplementary circuit 221 through the data port. The control terminal of the supplementary circuit 221 receives the supplementary control signal BCTRL. Based on the supplementary control signal BCTRL, the supplementary circuit 221 supplements the number of bits of the initial test data and outputs the first intermediate test data.

[0084] The input of the copying circuit 222 is connected to the output of the supplementation circuit 221. The control terminal of the copying circuit 222 receives the copying control signal CoCTRL. The copying circuit 222 copies the first intermediate test data at least once and outputs the supplemented test data. The number of bits in the supplemented test data is an integer multiple of the number of bits in the first intermediate test data.

[0085] In the above technical solution, the control circuit 223 generates the supplementary control signal BCTRL of the control supplementary circuit 221 and the copy control signal CoCTRL of the control copy circuit 222 based on the parallel write instruction PARA WR. This causes the supplementary circuit 221 to first supplement the initial test data with bits, and then the copy circuit 222 to perform at least one copy to expand the initial test data to meet the data writing requirements. After the supplementary test data meets the data writing requirements under the control of the target activation signal PMCBAB and the first row address ACT_RA, the test data is written to each storage area.

[0086] It's important to clarify here that copying data can be interpreted as follows: the original data had M bits, and the copied data has 2M bits. The voltage level of the first M bits of the copied data is the same as that of the original data; for example, if the original data was 1010, the first 4 bits of the copied data will also be 1010. Alternatively, the voltage level of the first M bits of the copied data can be opposite to that of the original data; for example, if the original data was 1010, the first 4 bits of the copied data will be 0101.

[0087] The voltage level of the last M bits of the copied data is the same as that of the original data. For example, if the original data was 1010, the first 4 bits of the copied data will also be 1010. The voltage level of the last M bits of the copied data is opposite to that of the original data. For example, if the original data was 1010, the last 4 bits of the copied data will be 0101.

[0088] In other words, if the data before copying is 1010, the data after copying can be one of four things: 10101010, 10100101, 01011010, or 01010101.

[0089] Figure 5 for Figure 3 and Figure 4 The timing control diagram of the memory is shown. Figure 5As shown, there are multiple clock cycles CLK within one instruction cycle T. When the chip select signal CS is low, the command address circuit 210 receives the command address instruction, decodes it, and outputs the first row address ACT_RA and the parallel write instruction PARA WR. The first driver circuit outputs the enhanced memory group address BGT and the enhanced memory region address BKT. In the previous instruction cycle, the test enable signal TPARAT is low, indicating that the parallel compression test mode is not enabled. In the target activation signal PMCBAB output by the command address circuit, bits 2 to 32 are all 0, and bit 1 is 1, indicating that only the first memory region is activated. In the next instruction cycle, the test enable signal TPARAT is high, indicating that the parallel compression test mode is enabled. All bits in the target activation signal PMCBAB output by the command address circuit are 1, indicating that the 32nd memory region is activated.

[0090] In some embodiments, continue to refer to Figure 3 The memory also includes a write register 230, and a data circuit 220 is connected to the write register 230. The data circuit 220 is used to write supplementary test data to the write register 230 to facilitate subsequent data comparison and determination of test results.

[0091] In some embodiments, the memory further includes a plurality of readout circuits (not shown) and a detection circuit 240. Each readout circuit is connected to a storage area, and each readout circuit is used to read supplementary post-test data from the corresponding storage area.

[0092] A detection circuit is connected to each readout circuit and receives supplementary test data read from each memory region. The detection circuit 240 is also connected to a write register 230, reads supplementary test data from the write register 230, and compares the supplementary test data read from each memory region with the supplementary test data read from the write register 230 to obtain a test result for each memory region. The test result is used to characterize whether there are faulty memory cells in the memory region.

[0093] After the command address circuit 210 generates the corresponding instruction and the data circuit 220 outputs the supplemented test data, the supplemented test data is directly written to all memory areas based on the instruction generated by the command address circuit 210. The data circuit 220 also stores the supplemented test data in the write register 230 for easy comparison of test data and to obtain test results. Furthermore, compared to... Figure 1 The architecture shown eliminates the need to write test data into registers before writing it into the storage area, reducing pre-write instructions, improving test efficiency, reducing resource consumption, and enhancing test accuracy.

[0094] Figure 6 Here is a circuit schematic of a data circuit 220, such as... Figure 6 As shown, the replication control signal CoCTRL includes the first replication control sub-signal DRV_ON and the second replication control sub-signal PDSD4. The replication circuit 222 includes the first transmission circuit 40, the writing circuit, and multiple port circuits 170.

[0095] Each port circuit 170 is connected to the output of the supplementary circuit 221 via a first data line group 301, and each port circuit 170 is used to transmit first intermediate test data. The number of bits in the first intermediate test data is equal to the number of data lines in the first data line group.

[0096] Each port circuit 170 is connected to the input terminal of the first transmission circuit 40 through a set of second data lines 302. Each port circuit 170 simultaneously sends first intermediate test data to the first transmission circuit 40. The control terminal of the first transmission circuit 40 also receives the first replication control sub-signal DRV_ON. Under the control of the first replication control sub-signal DRV_ON, the first transmission circuit 40 amplifies the signals of multiple first intermediate test data and outputs second intermediate test data. The number of bits of the second intermediate test data is N times the number of bits of the first intermediate test data, where N is the number of port circuits 170.

[0097] The writing circuit 50 is connected to the output terminal of the first transmission circuit 40. The control terminal of the writing circuit 50 receives the second copy control sub-signal PDSD4. Under the control of the second copy control sub-signal PDSD4, the writing circuit 50 copies the second intermediate test data and outputs supplementary test data. The number of bits of the supplementary test data is twice the number of bits of the second intermediate test data.

[0098] Taking the replication circuit 222, which includes eight port circuits 170, as an example, eight sets of first data line groups 301 are correspondingly provided. The input of the first port is connected to the output of the supplementary circuit 221 through the first set of first data line groups 301; the input of the second port is connected to the output of the supplementary circuit 221 through the second set of first data line groups 301, and so on, with the input of the eighth port connected to the output of the supplementary circuit 221 through the eighth set of first data line groups 301. The number of bits of the first intermediate test data is equal to the number of data lines in the first data line group 301. With this configuration, the first intermediate test data can be transmitted through one first data line group 301 to the input of one port circuit 170, and the port circuit 170 then transmits the first intermediate test data to its output.

[0099] Accordingly, eight sets of second data line groups 302 are provided. The first port circuit 170 is connected to the input terminal of the first transmission circuit 40 through the first set of second data line groups 302, the second port circuit 170 is connected to the input terminal of the first transmission circuit 40 through the second set of second data line groups 302, and so on, with the eighth port circuit 170 connected to the input terminal of the first transmission circuit 40 through the eighth set of second data line groups 302. This allows the first transmission circuit 40 to receive the first intermediate test data transmitted by the eight port circuits 170. Under the control of the first replication control sub-signal DRV_ON, the first transmission circuit 40 simultaneously outputs the first intermediate test data transmitted by the eight port circuits 170 to the write circuit 50. Through this configuration, replication of the first intermediate test data can be achieved. The number of bits in the second intermediate test data output by the first transmission circuit 40 is eight times the number of bits in the first intermediate test data.

[0100] In the above technical solution, the existing port circuit 170 in the memory can be used to supplement the initial test data with bits by the supplementary circuit 221, so that the first intermediate test data meets the data line transmission requirements of the input terminal of the port circuit 170. That is, the number of bits of the first intermediate test data is equal to the total number of data lines in the first group of data lines. Then, multiple port circuits 170 simultaneously transmit the first intermediate test data to the first transmission circuit 40. The first transmission circuit 40 outputs the received multiple first intermediate test data simultaneously, realizing the replication of test data. This can adapt to the existing structure of the memory and reduce costs.

[0101] In some embodiments, the memory includes multiple write circuits 50, and the first transmission circuit 40 includes multiple transmission paths. One write circuit 50 is connected to the output of one transmission path within the first transmission circuit 40. The write circuit 50 copies second intermediate test data output from the corresponding transmission path and outputs supplementary test data. One write circuit 50 is connected to multiple storage regions, and any two write circuits 50 are connected to different storage regions. The write circuit 50 writes supplementary test data to the storage region connected to it.

[0102] By setting up multiple write circuits 50, each write circuit 50 writes supplementary test data to a portion of the storage area, reducing the storage area driven by each write circuit 50 and improving the accuracy of writing data to the storage area by the write circuit 50. The multiple write circuits 50 are connected to the first transmission circuit 40, and each write circuit 50 receives second intermediate test data from the first transmission circuit 40, which simplifies the structure of the data circuit 220.

[0103] In some embodiments, the memory includes multiple memory groups, each memory group including multiple memory regions. A write circuit 50 is connected to multiple memory groups, and any two write circuits 50 are connected to different memory groups. The write circuit 50 writes supplementary test data to multiple memory groups. With this configuration, the distance between each memory region in each memory group and the write circuit 50 is close, and memory regions in the same memory group are connected to the same write circuit 50, which can ensure the accuracy of data writing.

[0104] This example illustrates a memory comprising 8 memory groups, each containing 4 memory regions, resulting in a total of 32 memory regions. Initial test data is input to the supplementary circuit 221 via 4 data ports, with each port receiving 1 bit of initial test data. Under the control of the supplementary control signal BCTRL, the supplementary circuit 221 outputs 8 bits of first intermediate test data.

[0105] Accordingly, there are 8 port circuits 170. Each port circuit 170 outputs 8 bits of first intermediate test data. The first transmission circuit 40 outputs the 8 bits of first intermediate test data simultaneously, which means the second intermediate test data is 64 bits. After the writing circuit 50 copies the second intermediate test data, each writing circuit 50 outputs 128 bits of supplementary test data.

[0106] The memory has two write circuits 50, see reference. Figure 3 and Figure 4 The eight memory groups are labeled as Memory Group 1 (BGA), Memory Group 2 (BGB), Memory Group 3 (BGC), Memory Group 4 (BGD), Memory Group 5 (BGE), Memory Group 6 (BGF), Memory Group 7 (BGG), and Memory Group 8 (BGH). The first write circuit 50 is used to write supplemented test data to each memory area in Memory Groups 1 (BGA), 2 (BGB), 3 (BGC), and 4 (BGD), i.e., writing 128 bits of supplemented test data to 16 memory areas. The second write circuit 50 is used to write supplemented test data to each memory area in Memory Groups 5 (BGE), 6 (BGF), 7 (BGG), and 8 (BGH), i.e., writing 128 bits of supplemented test data to 16 memory areas. This achieves the writing of 128 bits of supplemented test data to all 32 memory areas, resulting in a total of 4096 bits of test data written.

[0107] The specific structure of the supplementary circuit 221 can be designed according to requirements and is not limited here. Here, we take a design where the number of data ports is half the number of data lines in the first data line group 301. The supplementary circuit 221 includes multiple supplementary sub-circuits 30. The input terminal of each supplementary sub-circuit 30 is connected to a data port. The control terminal of each supplementary sub-circuit 30 receives a supplementary control signal BCTRL, which represents the replication mode. The input terminal of each supplementary sub-circuit 30 receives 1 bit of initial test data, and the output terminal of each supplementary sub-circuit 30 outputs 2 bits of first intermediate test data. The output terminals of the multiple supplementary sub-circuits 30 output 2L bits of first intermediate test data, where L is the number of data ports. Through this configuration, the initial test data is supplemented bit by bit to form the first intermediate test data.

[0108] In some embodiments, when the supplementary control signal BCTRL represents the first copy mode, each bit of the copied 2-bit data is the same as the original data. When the supplementary control signal BCTRL represents the second copy mode, one bit of the copied 2-bit data is the same as the original data, and the other bit of the copied 2-bit data is the opposite of the original data.

[0109] More specifically, Figure 7 A schematic diagram of the circuit structure of a supplementary sub-circuit 30, as shown below. Figure 7 As shown, each supplementary sub-circuit 30 includes a first sampling circuit 310 and a second sampling circuit 320. The first sampling circuit 310 includes a first AND gate 312, a second AND gate 313, a first NOR gate 315, a first inverter 311, a second inverter 314, a third inverter 316, a fourth inverter 317, and a fifth inverter 318. The input of the first inverter 311 receives 1 bit of initial test data SDR_DIN. The output of the first inverter 311 is connected to the first input of the first AND gate 312. The second input of the first AND gate 312 is grounded to VSS. The output of the first AND gate 312 is connected to the first input of the first NOR gate 315. The first input of the second AND gate 313 receives 1 bit of initial test data SDR_DIN. The second input of the second AND gate 313 is connected to the output of the second inverter 314. The input of the second inverter 314 is grounded to VSS. The second input of the first NOR gate 315 is connected to the output of the second AND gate 313. The output of the first NOR gate 315 is connected to the input of the third inverter 316. The output of the third inverter 316 is connected to the input of the fourth inverter 317. The output of the fourth inverter 317 is connected to the input of the fifth inverter 318. The output of the fifth inverter 318 outputs 1 bit of the first intermediate test data.

[0110] The second sampling circuit 320 includes a third AND gate 322, a fourth AND gate 323, a second NOR gate 325, a sixth inverter 321, a seventh inverter 324, an eighth inverter 326, a ninth inverter 327, and a tenth inverter 328. The input of the sixth inverter 321 receives 1 bit of initial test data SDR_DIN. The output of the sixth inverter 321 is connected to the first input of the third AND gate 322. The second input of the third AND gate 322 receives the supplementary control signal BCTRL. The output of the third AND gate 322 is connected to the first input of the second NOR gate 325. The first input of the fourth AND gate 323 receives 1 bit of initial test data SDR_DIN. The second input of the fourth AND gate 323 is connected to the output of the seventh inverter 324. The input of the seventh inverter 324 receives the supplementary control signal BCTRL. The second input of the second NOR gate 325 is connected to the output of the fourth AND gate 323. The output of the second NOR gate 325 is connected to the input of the eighth inverter 326. The output of the eighth inverter 326 is connected to the input of the ninth inverter 327. The output of the ninth inverter 327 is connected to the input of the tenth inverter 328. The output of the tenth inverter 328 outputs 1 bit of the first intermediate test data.

[0111] Figure 8A and Figure 8B for Figure 7 The timing diagram of the supplementary sub-circuit 30 is shown. (See example...) Figure 8A and Figure 8B As shown, since the second input of the first AND gate 312 is low, the output of the first AND gate 312 always outputs a low level. The input of the second inverter 314 is grounded, and the output of the second inverter 314 outputs a high level. The input of the second AND gate 313 is high, and the output of the second AND gate 313 outputs 1 bit of initial test data SDR_DIN. The output of the first NOR gate 315 outputs the inverted data SDR_DINB of the 1 bit of initial test data. After passing through the third inverter 316, the fourth inverter 317, and the fifth inverter 318 for three NOT logic operations, the output data level of the fifth inverter 318 is the same as the level of the 1 bit of initial test data SDR_DIN.

[0112] When the supplementary control signal BCTRL is low, each bit of the copied 2-bit data is the same as the original data. When the supplementary control signal BCTRL is high, one bit of the copied 2-bit data is the same as the original data, and the other bit of the copied 2-bit data is the opposite of the original data.

[0113] like Figure 8AAs shown, when the supplementary control signal BCTRL is low, since the second input of the third AND gate 322 is low, the output of the third AND gate 322 always outputs a low level. The input of the seventh inverter 324 is low, and its output outputs a high level. The input of the fourth AND gate 323 is high, and its output outputs 1 bit of the initial test data SDR_DIN. The output of the second NOR gate 325 outputs the inverted 1 bit of the initial test data SDR_DINB. After three NOT logic operations by the eighth inverter 326, the ninth inverter 327, and the tenth inverter 328, the level of the data output by the tenth inverter 328 is the same as the level of the 1 bit of the initial test data SDR_DIN.

[0114] like Figure 8B As shown, when the supplementary control signal BCTRL is high, the second input of the third AND gate 322 is high, the first input of the third AND gate 322 receives the inverted 1-bit initial test data SDR_DINB, and the output of the third AND gate 322 is also the inverted 1-bit initial test data SDR_DINB. When the supplementary control signal BCTRL is high, the input of the seventh inverter 324 is high, and the output of the seventh inverter 324 is low. The second input of the fourth AND gate 323 is low, and the output of the fourth AND gate 323 always outputs a low level. The 1-bit initial test data SDR_DINB output of the second NOR gate 325 is NOT processed three times by the eighth inverter 326, the ninth inverter 327, and the tenth inverter 328, making the level of the data output by the tenth inverter 328 the same as the level of the inverted 1-bit initial test data SDR_DINB.

[0115] In some embodiments, each supplementary sub-circuit 30 connects to two non-adjacent data lines in the first data line group 301, and each supplementary sub-circuit 30 connects to different data lines. Figure 9 This is a schematic diagram of a supplementary circuit architecture. (For example...) Figure 9As shown, the first data line group 301 includes 8 data lines, each labeled as the first data line BUS. <0> Second data line BUS <1> Third data line BUS <2> Fourth data line BUS <3> Fifth data line BUS <4> Sixth data line BUS <5> 7th Data Line BUS <6> And the eighth data line BUS <7> Accordingly, there are four supplementary sub-circuits 30. The first supplementary sub-circuit 30 is connected to the fifth data port LDQ4 through the second transmission circuit. The second supplementary sub-circuit 30 is connected to the sixth data port LDQ5 through the second transmission circuit. The third supplementary sub-circuit 30 is connected to the seventh data port LDQ6 through the second transmission circuit. The fourth supplementary sub-circuit 30 is connected to the eighth data port LDQ7 through the second transmission circuit.

[0116] The first output terminal of the first supplementary sub-circuit 30 is connected to the first data line BUS. <0> The second output terminal of the first supplementary sub-circuit 30 is connected to the fifth data line BUS. <4> The first output terminal of the second supplementary sub-circuit 30 is connected to the second data line BUS. <1> The sixth output terminal of the second supplementary sub-circuit 30 is connected to the sixth data line BUS. <5> The first output terminal of the third supplementary sub-circuit 30 is connected to the third data line BUS. <2> The second output terminal of the third supplementary sub-circuit 30 is connected to the seventh data line BUS. <6> The first output terminal of the fourth supplementary sub-circuit 30 is connected to the fourth data line BUS. <3> The second output terminal of the fourth supplementary sub-circuit 30 is connected to the eighth data line BUS. <7> .

[0117] The specific structure of the first transmission circuit 40 can be designed according to requirements, and no restrictions are imposed here. Figure 10 Here is a circuit schematic of a first transmission circuit 40, such as... Figure 10 As shown. The first transmission circuit 40 includes two transmission paths, namely a first transmission path 410 and a second transmission path 420.

[0118] The following describes the sub-circuit structure for transmitting 1 bit of first intermediate test data via the first transmission path 410. Multiple sub-circuit structures can transmit multiple bits of first intermediate test data. For example, when there is 64 bits of first intermediate test data in parallel, there are 64 sub-circuit structures.

[0119] The first transmission path includes a first latch 411, a second latch 412, an eleventh inverter 415, and a twelfth inverter 416. The input of the first latch 411 receives 1 bit of first intermediate test data, and its control terminal CK receives the inverted signal DRV_ONB of the first replication control sub-signal. The inverting control terminal CKB of the first latch 411 receives the first replication control sub-signal DRV_ON. The output of the first latch 411 is connected to the input of the second latch 412. The control terminal CK of the second latch 412 receives the first replication control sub-signal DRV_ON, and its inverting control terminal CKB receives the inverted signal DRV_ONB. The output of the second latch 412 is connected to the input of the eleventh inverter 415, the output of the eleventh inverter 415 is connected to the input of the twelfth inverter 416, and the output of the twelfth inverter 416 outputs the second intermediate test data.

[0120] The sub-circuit structure for transmitting 1 bit of first intermediate test data in the second transmission path 420 is given below. Multiple sub-circuit structures can transmit multiple bits of first intermediate test data. For example, when there is 64 bits of first intermediate test data in parallel, there are 64 sub-circuit structures.

[0121] The second transmission path 420 includes a third latch 413, a fourth latch 414, a thirteenth inverter 417, and a fourteenth inverter 418. The input of the third latch 413 receives parallel first intermediate test data output from the multiple port circuit 170. The control terminal CK of the third latch 413 receives the inverted signal DRV_ONB of the first replication control sub-signal. The inverting control terminal CKB of the third latch 413 receives the first replication control sub-signal DRV_ON. The output of the third latch 413 is connected to the input of the fourth latch 414. The control terminal CK of the fourth latch 414 receives the first replication control sub-signal DRV_ON, and the inverting control terminal CKB of the fourth latch 414 receives the inverted signal DRV_ONB of the first replication control sub-signal. The output of the fourth latch 414 is connected to the input of the thirteenth inverter 417, the output of the thirteenth inverter 417 is connected to the input of the fourteenth inverter 418, and the output of the fourteenth inverter 418 outputs the second intermediate test data.

[0122] In each transmission path, the parallel first intermediate test data output from multiple port circuits 170 is latched by two stages of latching circuits before being output, ensuring the synchronization of data output. The signal is then amplified by two stages of inverters to ensure the accuracy of data transmission.

[0123] The specific structure of the writing circuit 50 can be designed according to requirements, and there are no restrictions here. Figure 11This is a circuit schematic of a writing circuit 50. (Example) Figure 11 As shown, the write circuit 50 includes a third sampling circuit 510, a fourth sampling circuit 520, and a fifteenth inverter 513.

[0124] The input of the third sampling circuit 510 receives the second intermediate test data, samples the second intermediate test data, and outputs it. The input of the fifteenth inverter 513 receives the second intermediate test data, and the output of the fifteenth inverter 513 is connected to the input of the fourth sampling circuit 520. The fourth sampling circuit 520 samples the inverted data of the second intermediate test data and outputs it. The supplemented test data includes the second intermediate test data and the inverted data of the second intermediate test data.

[0125] The sub-circuit structure for the third sampling circuit 510 to sample 1 bit of the second intermediate test data is given below. Multiple sub-circuit structures can be used to sample multiple bits of the second intermediate test data. For example, when there is 64 bits of parallel second intermediate test data, there are 64 sub-circuit structures.

[0126] The third sampling circuit 510 includes a fifth latch 511, a sixth latch 512, a sixteenth inverter 515, and a seventeenth inverter 516. The input of the fifth latch 511 receives 1 bit of second intermediate test data. The control terminal of the fifth latch 511 receives the inverted signal PDSD4B of the second copy control sub-signal. The inverting control segment of the fifth latch 511 receives the second copy control sub-signal PDSD4. The output of the fifth latch 511 is connected to the input of the sixth latch 512. The control terminal of the sixth latch 512 receives the second copy control sub-signal PDSD4. The inverting control segment of the sixth latch 512 receives the inverted signal PDSD4B of the second copy control sub-signal. The output of the sixth latch 512 is connected to the input of the sixteenth inverter 515. The output of the sixteenth inverter 515 is connected to the input of the seventeenth inverter 516. The output of the seventeenth inverter 516 serves as the first output of the write circuit 50. The output of the seventeenth inverter 516 outputs the supplemented test data.

[0127] The sub-circuit structure for the fourth sampling circuit 520 to sample 1 bit of the second intermediate test data is given below. Multiple sub-circuit structures can be used to sample multiple bits of the second intermediate test data. For example, when there is 64 bits of parallel second intermediate test data, there are 64 sub-circuit structures.

[0128] The fourth sampling circuit 520 includes a seventh latch 514, an eighteenth inverter 517, and a nineteenth inverter 518. The input of the seventh latch 514 receives the inverted data of the second intermediate test data. The control terminal of the seventh latch 514 receives the second copy control sub-signal PDSD4. The inverting control segment of the seventh latch 514 receives the inverted signal PDSD4B of the second copy control sub-signal. The output of the seventh latch 514 is connected to its input. The output of the seventh latch 514 is connected to the input of the eighteenth inverter 517. The output of the eighteenth inverter 517 is connected to the input of the nineteenth inverter 518. The output of the nineteenth inverter 518 serves as the second output of the writing circuit 50, and the output of the nineteenth inverter 518 outputs the supplemented test data.

[0129] In the above technical solution, the third sampling circuit 510 includes two latches and two inverters. The second intermediate test data is latched by two stages of latches and then driven by two stages of inverters before being output. The fourth sampling circuit 520 includes one latch and two inverters. The inverted data of the second intermediate data is latched by one stage of latches and then driven by two stages of inverters before being output. The third sampling circuit 510 and the fourth sampling circuit 520 differ by one stage of latches, which can eliminate the time delay between the second intermediate test data and the inverted data of the second intermediate test data caused by the use of the fifteenth inverter 513 to perform NOT logic processing on the second intermediate test data. This ensures time synchronization between the second intermediate test data output by the third sampling circuit 510 and the inverted data of the second intermediate test data output by the fourth sampling circuit 520.

[0130] Continue to refer to Figure 11 The writing circuit 50 also includes a second driving circuit 530 and a third driving circuit 540. The input terminal of the second driving circuit 530 is connected to the output terminal of the third sampling circuit 510, and the input terminal of the third driving circuit 540 is connected to the output terminal of the fourth sampling circuit 520. Data enhancement is performed through the second driving circuit 530 and the third driving circuit 540 to increase the reliability of data transmission.

[0131] The second driving circuit includes a first NAND gate 521, a third NOR gate 522, a first P-type transistor P1, and a first N-type transistor N1. The second input terminal of the first NAND gate 521 is connected to the first input terminal of the third NOR gate 522, and then connected to the output terminal of the seventeenth inverter 516. The first input terminal of the first NAND gate 521 receives the driving control signal PDT, and the second input terminal of the third NOR gate 522 receives the inverted signal PDTB of the driving control signal. The output terminal of the first NAND gate 521 is connected to the control terminal of the first P-type transistor P1, and the control terminal of the first N-type transistor N1 is connected to the output terminal of the third NOR gate 522. The second terminal of the first P-type transistor P1 is connected to the first terminal of the first N-type transistor N1 and then serves as the output terminal of the second driving circuit. The first terminal of the first P-type transistor P1 is connected to the power supply VDD, and the second terminal of the first N-type transistor N1 is grounded to VSS.

[0132] The third driving circuit includes a second NAND gate 523, a fourth NOR gate 524, a second P-type transistor P2, and a second N-type transistor N2. The second input terminal of the second NAND gate 523 is connected to the first input terminal of the fourth NOR gate 524 and the output terminal of the nineteenth inverter 518. The first input terminal of the second NAND gate 523 receives the driving control signal PDT, and the second input terminal of the fourth NOR gate 524 receives the inverted signal PDTB of the driving control signal. The output terminal of the second NAND gate 523 is connected to the control terminal of the second P-type transistor P2, and the control terminal of the second N-type transistor N2 is connected to the output terminal of the fourth NOR gate 524. The second terminal of the second P-type transistor P2 is connected to the first terminal of the second N-type transistor N2 and serves as the output terminal of the third driving circuit. The first terminal of the second P-type transistor P2 is connected to the power supply, and the second terminal of the second N-type transistor N2 is grounded.

[0133] Some embodiments of this application provide a method for testing a memory, the memory including multiple storage areas and control circuitry. The testing method is applied to the control circuitry and includes:

[0134] S101, the control circuit receives the command address signal CA and the test enable signal TPARAT.

[0135] Among them, the test enable signal TPARAT indicates whether the compression test mode is enabled. The command address signal CA and the test enable signal TPARAT are used to generate the target activation signal PMCBAB, the first row address ACT_RA, and the parallel write instruction PARAWR. The parallel write instruction PARAWR is used to supplement the initial test data with bits and output the supplemented test data.

[0136] More specifically, the control circuit receives the command address signal CA and the test enable signal TPARAT. The test enable signal TPARAT indicates whether the compression test mode is enabled. When the test enable signal TPARAT indicates that the compression test mode is enabled, the control circuit generates the target activation signal PMCBAB, the first row address ACT_RA, and the parallel write instruction PARA WR based on the decoding of the command address signal CA. The control circuit also supplements the initial test data by adjusting the number of bits according to the parallel write instruction PARA WR, outputting supplemented test data.

[0137] S102. When the test enable signal TPARAT indicates that the compression test mode is enabled, send the target activation signal PMCBAB, the first row address ACT_RA and the supplemented test data to each storage area. After each storage area is activated by the target activation signal PMCBAB, the supplemented test data is written into the storage unit corresponding to the first row address ACT_RA.

[0138] With this configuration, the control circuit supplements the initial test data and outputs the supplemented test data. The target activation signal PMCBAB output by the control circuit is used to activate all storage areas, and the supplemented test data is written to each storage area based on the first row address ACT_RA. There is no need to write the data to the mode register 160 first, and then read the data from the mode register 160 and write it to the storage area. This can reduce the data writing time in the compressed test mode and consume less resources. Since there is no need to use the mode register 160 to store the test data, the test data can be written accurately, improving the test accuracy.

[0139] In some embodiments, the testing method further includes the following steps:

[0140] Write supplementary test data to write register 230.

[0141] By setting such rough parameters, it is easier to compare data and determine the test results later.

[0142] In some embodiments, the testing method further includes:

[0143] The supplemented test data is read from each storage area and from write register 230.

[0144] The supplemented test data read from each storage area is compared with the supplemented test data read from the write register 230 to obtain the test results for each storage area.

[0145] In the above technical solution, the control circuit generates corresponding instructions and supplementary test data. Based on the instructions, it directly writes the supplementary test data to all memory areas. The control circuit also stores the supplementary test data in a write register for easy comparison of test data and to obtain test results. Furthermore, compared to... Figure 1 The architecture shown eliminates the need to write test data into registers before writing it into the storage area, reducing pre-write instructions, improving test efficiency, reducing resource consumption, and enhancing test accuracy.

[0146] It should be noted that the terms "high level" and "low level" in the above embodiments are relative concepts (i.e., the voltage value of a high level is higher than the voltage value of its corresponding low level), and there is no limitation on the specific voltage value of the high level or the specific voltage value of the low level. Furthermore, it is not limited that the high voltage applied to different signal lines in this specific embodiment is equal; for example, the high level on the bit line and the high level on the word line can be different voltages. It is also not limited that the high level of a specific signal line is equal at different stages; for example, the high level applied to the bit line during a write operation and during a read operation can be different voltage values. Those skilled in the art should understand that the values ​​of the corresponding high and low levels can be set according to process nodes, speed requirements, reliability requirements, etc.

[0147] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0148] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A memory, characterized in that, include: Multiple storage areas, command address circuits, and data circuits; The input terminal of the command address circuit receives the command address signal and the test enable signal; The test enable signal indicates whether the compression test mode is enabled. When the test enable signal indicates that the compression test mode is enabled, the command address circuit generates a target activation signal, a first row address, and a parallel write instruction for activating all storage areas based on the decoding of the command address signal. The data circuit is connected to the command address circuit. The data circuit receives the parallel write instruction and supplements the number of bits of the initial test data based on the parallel write instruction, then outputs the supplemented test data. Each of the storage areas is connected to the data circuit and the command address circuit. Each of the storage areas is activated by the target activation signal, and the supplementary test data is written into the storage unit corresponding to the first row address.

2. The memory according to claim 1, characterized in that, The command address circuit includes a first decoding circuit and a second decoding circuit; The input terminal of the first decoding circuit receives the command address signal and the test enable signal, and decodes the command address signal and the test enable signal to generate a storage area address, an activation command, and a second line address; The first row address was generated based on the second row address; The input terminal of the second decoding circuit is connected to the output terminal of the first decoding circuit. The second decoding circuit receives the memory area address and the activation command. The second decoding circuit also receives the test enable signal and the forced activation signal. The forced activation signal indicates whether all memory areas are activated. The second decoding circuit outputs the target activation signal.

3. The memory according to claim 2, characterized in that, The command address circuit also includes a first driving circuit and a row address latching circuit; The input terminal of the first driving circuit is connected to the output terminal of the first decoding circuit, and the output terminal of the first driving circuit is connected to the input terminal of the second decoding circuit. The first driving circuit outputs the address of the storage area after signal enhancement. The input terminal of the row address latch circuit is connected to the output terminal of the first decoding circuit, and the output terminal of the row address latch circuit is connected to each of the storage areas. The row address latch circuit latches the second row address based on the activation command and then outputs the first row address, and outputs the first row address to the storage area.

4. The memory according to any one of claims 1 to 3, characterized in that, The data circuit includes a supplementary circuit, a replication circuit, and a control circuit. The input terminal of the control circuit receives the parallel write instruction and outputs supplementary control signal and copy control signal according to the parallel write instruction; The input terminal of the supplementary circuit is connected to the data port. The initial test data enters the supplementary circuit through the data port. The control terminal of the supplementary circuit receives the supplementary control signal. Based on the supplementary control signal, the supplementary circuit supplements the number of bits of the initial test data and outputs the first intermediate test data. The input terminal of the replication circuit is connected to the output terminal of the supplementation circuit; the control terminal of the replication circuit receives the replication control signal, and the replication circuit copies the first intermediate test data at least once to output the supplemented test data; wherein the number of bits in the supplemented test data is an integer multiple of the number of bits in the first intermediate test data.

5. The memory according to claim 4, characterized in that, The replication control signal includes a first replication control sub-signal and a second replication control sub-signal, and the replication circuit includes a first transmission circuit, a writing circuit, and multiple port circuits. Each of the port circuits is connected to the output of the supplementary circuit via a set of first data lines; each of the port circuits is used to transmit the first intermediate test data; wherein the number of bits in the first intermediate test data is equal to the number of data lines in the first data line set; Each of the port circuits is connected to the input terminal of the first transmission circuit via a set of second data lines. Each of the port circuits simultaneously sends the first intermediate test data to the first transmission circuit. The control terminal of the first transmission circuit also receives the first copy control sub-signal. Under the control of the first copy control sub-signal, the first transmission circuit enhances the signal of the multiple first intermediate test data and outputs the second intermediate test data. The number of bits of the second intermediate test data is N times the number of bits of the first intermediate test data, where N is the number of the port circuits. The writing circuit is connected to the output terminal of the first transmission circuit. The control terminal of the writing circuit receives the second copy control sub-signal. Under the control of the second copy control sub-signal, the writing circuit copies the second intermediate test data and outputs the supplemented test data. The number of bits in the supplemented test data is twice the number of bits in the second intermediate test data.

6. The memory according to claim 5, characterized in that, The memory includes multiple write circuits, the first transmission circuit includes multiple transmission paths, and one write circuit is connected to the output of one transmission path in the first transmission circuit; the write circuit copies the second intermediate test data output from the corresponding transmission path and outputs the supplemented test data. One of the write circuits is connected to a plurality of the storage regions, and any two of the write circuits are connected to different storage regions. The write circuit writes the supplementary test data to the storage region connected to the write circuit.

7. The memory according to claim 6, characterized in that, The memory includes multiple memory groups, each memory group includes multiple memory areas, one write circuit is connected to multiple memory groups, and any two write circuits are connected to different memory groups, and one write circuit writes the supplementary test data to multiple memory groups.

8. The memory according to claim 5, characterized in that, The number of data ports is half the number of data lines in the first data line group; the supplementary circuit includes multiple supplementary sub-circuits. Each of the supplementary sub-circuits has an input terminal connected to a data port, a control terminal of each supplementary sub-circuit receives a supplementary control signal, the supplementary control signal characterizing the replication mode, an input terminal of each supplementary sub-circuit receives 1 bit of initial test data, an output terminal of each supplementary sub-circuit outputs 2 bits of first intermediate test data, and multiple output terminals of the supplementary sub-circuit output 2L bits of first intermediate test data, where L is the number of data ports.

9. The memory according to claim 8, characterized in that, Each of the supplementary sub-circuits connects to two non-adjacent data lines in the first data line group, and each of the supplementary sub-circuits connects to different data lines.

10. The memory according to claim 1, characterized in that, The memory also includes a write register; The data circuit is also connected to the write register, and the data circuit is used to write the supplemented test data into the write register.

11. The memory according to claim 10, characterized in that, The memory also includes multiple readout circuits and detection circuits; One of the readout circuits is connected to one of the storage areas, and each of the readout circuits is used to read the supplemented test data in the corresponding storage area; The detection circuit is connected to each of the readout circuits, and the detection circuit is used to receive supplementary post-test data read from each of the storage areas; The detection circuit is also connected to the write register. The detection circuit also reads the supplemented test data from the write register and compares the supplemented test data read from each of the storage areas with the supplemented test data read from the write register to obtain the test result for each storage area.

12. A method for testing a memory, characterized in that, The memory includes multiple storage areas, and the method includes: Receive command address signal and test enable signal; wherein, the test enable signal indicates whether the compression test mode is enabled, the command address signal and the test enable signal are used to generate target activation signal, first line address and parallel write instruction, and the parallel write instruction is used to output supplemented test data after supplementing the initial test data with bits; When the test enable signal indicates that the compression test mode is enabled, the target activation signal, the first row address, and the supplemented test data are sent to each of the storage areas. After each of the storage areas is activated by the target activation signal, the supplemented test data is written into the storage unit corresponding to the first row address.

13. The test method according to claim 12, characterized in that, The memory further includes a write register, and the method further includes: The supplemented test data is written to the write register.

14. The test method according to claim 13, characterized in that, The method further includes: The supplemented test data is read from each of the storage areas and from the write register; The supplemented test data read from each of the storage areas is compared with the supplemented test data read from the write register to obtain the test results for each storage area.

Images