VALVE SENSING IN Flyback POWER CONVERTER

Abstract

The invention relates to trough sensing in flyback power converters. In an example, circuitry implementing the techniques is configured to detect (603) a positive turn at the beginning of a leakage reset portion of a switch terminal signal, and blank (605) the leakage reset portion. The circuitry is also configured to detect (609) a negative revolution of a leakage ringing portion of the switch terminal signal, and to blank (613) any false valley detection occurring during the leakage ringing portion. The blanking period may be fixed or variable. The circuitry may also be configured to discriminate (615) a difference between a true trough within a magnetized ringing portion to zero voltage and a false trough within the leaked ringing portion.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of Indian (IN) Provisional Patent Application No. 202441059286, filed on August 6, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] This specification relates to power converters, and more specifically, to trough sensing in flyback power converters. Background Technology

[0004] A flyback power converter is a switch-mode power supply that converts an AC or DC input voltage into one or more regulated DC output voltages. A flyback converter topology typically includes an input capacitor, a primary-side switching element (e.g., a metal-oxide-semiconductor field-effect transistor, or MOSFET), a coupling inductor called a flyback transformer, an output diode or rectifier, and an output capacitor. The transformer allows for energy storage, energy transfer, and current isolation between the input and any output. The turns ratio between the primary and secondary windings of the transformer can be configured such that the output voltage is lower or higher than the input voltage. In operation, when the primary-side switching element is closed (on-time, or TON), the primary winding of the transformer is connected to the input voltage and the primary-side current ramps up, thus storing energy in the transformer's gaps or core. During this on-time, the output diode is reverse-biased and off, and the output capacitor supplies the load current. When the primary-side switching element is open (off-time, or TOFF), the current in the transformer moves to the secondary and flows through the now forward-biased output diode, thereby replenishing the output capacitor and supplying the load current. During this process, the secondary current ramps down as the transformer core demagnetizes. Some flyback converters use auxiliary transformer windings for trough sensing and overvoltage protection, and generate a low-voltage bias supply. Flyback power converters still face some significant challenges. Summary of the Invention

[0005] In one example, an apparatus includes: a first logic circuit configured to blank a leakage reset portion of a switch terminal signal in response to a first blanking signal; a second logic circuit configured to blank a leakage ringing portion of the switch terminal signal in response to a second blanking signal; a third logic circuit configured to distinguish the leakage ringing portion of the switch terminal signal from a trough reaching zero volts in response to a zero-voltage detection (ZVD) signal, the trough being contained in a magnetized ringing portion of the switch terminal signal; and a fourth logic circuit configured to declare one or more troughs contained in the magnetized ringing portion of the switch terminal signal in response to inputs from the second and third logic circuits.

[0006] In another example, an apparatus includes: a first circuit configured to receive a switching terminal signal of a flyback power converter, the first circuit further configured to detect a leakage reset portion of the switching terminal signal and detect one or more troughs of the switching terminal signal; a second circuit configured to generate a blanking signal at least partially corresponding to the leakage reset portion of the switching terminal signal; and a third circuit configured to receive the detection from the first circuit and the blanking signal from the second circuit. The third circuit is further configured to: blank the leakage reset portion of the switching terminal signal in response to the blanking signal; and distinguish between troughs included in a magnetized ringing portion of the switching terminal signal and troughs included in a leakage ringing portion of the switching terminal signal.

[0007] In another example, an apparatus includes: a slewing detection circuit having a switching terminal input and further including a comparator having a threshold voltage input and a comparator output; a zero-current detection circuit having an input coupled to the comparator output and further including a blanking signal input and a zero-current detection signal output; a first threshold voltage switchably coupled to the threshold voltage input of the comparator; a second threshold voltage switchably coupled to the threshold voltage input of the comparator; and an adaptive blanking circuit having a timing input terminal coupled to the comparator output and further including a blanking signal output coupled to the blanking signal input of the zero-current detection circuit.

[0008] In another example, a method includes: receiving a switch terminal signal comprising a leakage reset portion, a leakage ringing portion, and a magnetized ringing portion; detecting a positive rotation of the leakage reset portion; generating a blanking signal to blank the leakage reset portion; and detecting a negative rotation of the signal. In response to detecting a trough in the signal, the method further includes: declaring a trough if a leakage filter has expired, the leakage filter having a period longer than the period of the leakage ringing portion of the switch terminal signal, or declaring a trough if the detected trough has reached zero volts. Attached Figure Description

[0009] Figure 1 A block diagram of a flyback power converter system with a trough sensing detection circuit is shown in the example.

[0010] Figure 2 Example signals of the switching terminals of a flyback power converter are shown.

[0011] Figure 3 Example shown Figure 1 Block diagram of the valley sensing detection circuit of the system.

[0012] Figure 4A Example shown Figure 1 and 3 A schematic diagram of the valley sensing detection circuit of the system.

[0013] Figure 4B Example shown Figure 4A A schematic diagram of the system's variable blanking delay circuit.

[0014] Figure 4C Example shown Figure 4A A schematic diagram of the leakage filter circuit of the system.

[0015] Figure 5A The example shown is when N*VOUT is less than or equal to VIN. Figure 1 A diagram of the signals generated by the system.

[0016] Figure 5B The example shown is when N*VOUT is greater than VIN. Figure 1 A diagram of the signals generated by the system.

[0017] Figure 6 A flowchart illustrating a method for valley sensing in a flyback power converter is shown in the example.

[0018] Figure 7 The diagram shows a block diagram of a system comprising a flyback power converter configured for trough sensing without the use of an auxiliary winding. Detailed Implementation

[0019] This document describes a technique for valley detection in flyback power converters. This technique allows a given power converter to perform valley switching and can be implemented without auxiliary transformer windings and associated discrete components. Valley detection is performed on the signal at the switching node or terminals of the flyback power converter. When switching of the power converter occurs at a given valley, the efficiency of the power converter can be improved because the switching node is at zero voltage or the valley voltage at the valley. The technique further allows for the differentiation between false valleys and true valleys. More specifically, in addition to one or more true valleys contained in the magnetized ringing portion of the switching terminal signal, the switching terminal signal may also contain, for example, one or more false valleys contained in the leakage reset portion and / or the leakage ringing portion of the switching terminal signal. In an example, the circuitry implementing the technique is configured to detect a positive slew at the beginning of the leakage reset portion of the switching terminal signal and to blank the leakage reset portion. The circuit system is also configured to detect the negative slew of the leakage ringing portion of the switch terminal signal and to detect any spurious troughs occurring during the leakage ringing portion. The blanking period can be fixed or variable. The circuit system can also be configured to distinguish between a true trough reaching zero voltage within the magnetized ringing portion and a spurious trough within the leakage ringing portion. This is useful because each of these two trough types can have a negative slew that takes a similar amount of time to reach the corresponding trough, but only the true trough will reach zero voltage. Therefore, the technique allows for high-confidence true trough declarations.

[0020] General Overview

[0021] As described above, flyback power converters still present some significant challenges. More specifically, existing flyback power converter topologies use an auxiliary winding of the flyback transformer to facilitate functions such as trough sensing. This auxiliary-based sensing may further require additional discrete components (e.g., high-voltage linear regulators) and separate package pins. The auxiliary winding, additional discrete components, and pins increase the overall cost and footprint of the converter. Therefore, eliminating the auxiliary winding, associated discrete components, and pins would be beneficial. However, doing so necessitates a novel approach to perform trough sensing. One possible method is to sense the trough of the signal at the switching terminals of the flyback power converter. However, this signal can be associated with multiple parasitic trough-like manifestations (false troughs), which must be distinguished from the true troughs that occur during the resonant period of the switching cycle (also known as magnetization ringing, or dead time). For example, a relatively high-frequency ringing (sometimes called leakage ringing) may occur on the switching terminals immediately after the start of the off-time of the switching cycle. This is primarily caused by the parasitic capacitance of the switching elements and the transformer. Additionally, a relatively high-amplitude pulse (sometimes called a leakage reset pulse) may occur between the start of the off-time and the start of the high-frequency leakage ringing. Switches at spurious troughs in the leakage reset and leakage ringing portions of the switching terminal signal can cause problems (e.g., input and output short circuits) and should be avoided.

[0022] Therefore, this document describes a technique for providing valley sensing in a flyback power converter topology without the use of an auxiliary winding. In an example, this technique can be implemented using circuitry configured to sense valleys in a switching terminal signal (sometimes referred to as a switching node signal). The switching terminal signal may include a leakage reset portion, a leakage ringing portion, and a magnetized ringing (or resonant) portion. The target valley to be sensed by the circuitry is contained within the magnetized ringing portion (true valley), but valleys contained in other portions of the switching terminal signal (false valleys) can also be sensed. For this purpose, the circuitry is further configured to distinguish between false and true valleys, such that only true valleys are declared, and false valleys are ignored or otherwise not used for switching. Therefore, a controller of a flyback power converter including or otherwise cooperating with said circuitry can access one or more true valley declaration signals and can select any declared valley for the on-time transition to the next switching cycle to facilitate low switching losses.

[0023] In this example, the circuit is configured to receive a switch terminal signal, which includes a leakage reset portion, a leakage ringing portion, and a magnetization ringing portion. The circuit is further configured to detect a positive rotation of the leakage reset portion and generate a blanking signal to blank the leakage reset portion. The circuit is further configured to detect a negative rotation of a "possible" trough that occurs after the leakage reset portion. The possible trough may include false troughs to be distinguished from true troughs. For this purpose, in response to detecting a trough, the circuit is further configured to determine whether a leakage filter has expired, the leakage filter having a period longer than the period of the leakage ringing portion of the switch terminal signal. If the leakage filter has expired when a trough is detected (indicating a true trough), then the circuit is configured to declare the trough a true trough. However, if the leakage filter has not yet expired (potentially indicating a false trough), then the circuit is further configured to determine whether the detected trough reaches zero volts (indicating a true trough). If the detected trough reaches zero volts, the circuit is configured to declare the trough a true trough; and if the detected trough does not reach zero volts (indicating a false trough), the circuit can distinguish the trough from a true trough (e.g., not declare a trough). Trough declaration can be made, for example, via the output of a logic circuit, where a logic 1 output signifies a trough declaration and a logic 0 output signifies no trough declaration. The circuit can detect and declare one or more true troughs contained in the magnetized ringing section. The controller can receive one or more trough declaration signals and cause a switching element to turn on at the time corresponding to the occurrence of a true trough.

[0024] Circuit architecture

[0025] Figure 1 A block diagram of a flyback power converter system 100 with a trough sensing detection circuit is shown in the example. As shown, system 100 includes an integrated circuit (IC) 101, a flyback transformer 111, an output diode DOUT, an output capacitor COUT, a feedback circuit 113, an electromagnetic interference (EMI) filter 115, and a rectifier 117. In this example, the flyback power converter system 100 converts an AC input voltage (VAC) to a DC input voltage (VIN), which is then converted by system 100 into a regulated DC output voltage (VOUT). In other examples, the DC input voltage VIN is obtained directly, rather than from the AC input voltage VAC.

[0026] As further illustrated, IC 101 includes a trough sensing detection circuit 103, a control circuit 105, a driver 107, a sensing circuit 108, and a switching element 109, all of which can be filled on or part of an integrated circuit die within a given substrate, such as an integrated circuit package (e.g., a leaded ceramic flat package, a dual in-line package, a ball grid array, a pin grid array, a planar grid array, a leaded chip carrier, a quad flat-no-leads, to name a few), or on or part of a printed circuit board (e.g., a single-sided, double-sided, multilayer, flexible, to name a few), or on or part of any other suitable substrate on which a circuit system can be formed and / or filled. In this example, each of the flyback transformer 111, DOUT, COUT, feedback circuit 113, EMI filter 115, and rectifier 117 is shown external to IC 101, but in other examples, any one or more of these components or circuits may be integrated within IC 101. The electronic system to be powered may also be coupled between the VOUT terminal of system 100 and the ground terminal. The electronic system (referred to herein as load current (ILOAD)) can be configured to suit any number of applications (e.g., automotive systems, computing systems, communication systems, gaming systems, home appliances and consumer electronics systems, mobile electronic systems such as smartphones, or any other application utilizing regulated power). Other instances of the flyback power converter system 100 may include additional components not shown and / or be configured differently, and any of these systems can benefit from the techniques described herein.

[0027] EMI filter 115 removes unwanted noise from the line voltage, and rectifier 117 rectifies the AC input. Any suitable EMI filter and rectifier circuitry can be used. Other examples may apply VIN directly, rather than obtaining it from an AC source as shown. In these cases, system 100 may not include VAC, EMI filter 115, and rectifier 117. Transformer 111 allows for energy storage, energy transfer, and current isolation between the input VIN and the output VOUT. The turns ratio between the primary winding 111p and the secondary winding 111s can be set such that VOUT is below or above VIN. Any suitable flyback transformer can be used. In this example, flyback transformer 111 does not include any auxiliary winding for trough sensing. Other examples may include one or more auxiliary windings, for example, to provide an alternative for trough detection and / or for providing overvoltage protection and / or bias power.

[0028] Switching element 109 can be any suitable switching element technology, such as a gallium nitride field-effect transistor (GaNFET) or other power FETs, or a power bipolar junction transistor (BJT). In this example, switching element 109 is coupled between the SW terminal of IC 101 and the ground terminal via its current terminals (e.g., the source / drain terminals of the FET, or the emitter / collector terminals of the BJT), wherein sensing circuitry 108 is coupled between switching element 109 and ground. Control terminals of switching element 109 (e.g., the gate terminal of the FET, or the base terminal of the BJT) are coupled to the output of driver 107. When switching element 109 is closed (on-time, or TON), primary winding 111p is connected to the input voltage VIN and the primary-side current ramps up, thus storing energy in the core of transformer 111. During this on-time, diode DOUT is reverse biased and off, and capacitor COUT supplies load current. When switching element 109 is turned off (off time, or TOFF), the energy stored in the core of transformer 111 is transferred to the secondary winding 111s and flows through diode DOUT (now forward biased), thereby replenishing capacitor COUT and supplying the load current ILOAD. During this process, the secondary current ramps down as the core of transformer 111 demagnetizes. The closing and opening of switching element 109, including trough switching, is controlled by IC 101, as explained further below.

[0029] Sensing circuit 108 senses the primary-side peak current IPK and provides this current information (which may be a scaled version of the actual primary-side peak current IPK) to control circuit 105. The peak current IPK depends on ILOAD and input line conditions. Any suitable current sensing circuitry system that allows control circuit 105 to receive or otherwise determine the primary-side peak current IPK can be used, such as a resistor-based current sensing circuitry comprising a sensing FET or BJT as a scaled-down replica of the switching element 109. In some instances, sensing circuit 108 may also compare IPK for a given switching cycle with a reference current, and if IPK exceeds the reference current, generate a current limit signal. In these cases, the current limit signal may be provided to control circuit 105, which may then initiate one or more remedial actions (e.g., asserting a current clamping circuit, shutting down the converter, disconnecting VIN, etc.). Feedback circuitry system 113 senses the output voltage and provides a feedback voltage VFB signal to control circuit 105. The VFB signal may be, for example, a scaled-down version of VOUT. Any suitable feedback circuit system that allows the control circuit 105 to receive or otherwise determine VOUT can be used, such as resistive voltage dividers and / or optocoupler feedback circuits sometimes used in flyback topologies.

[0030] As further illustrated, an input voltage VIN is applied to one terminal of the primary winding, and the other terminal of the primary winding is coupled to the switching node (SW) terminal of IC 101, causing IC 101 to receive a switching node voltage (VSW) signal. Additionally, system ground (GND) is coupled to the ground terminal of IC 101, the IPK signal generated by sensing circuit 108 is coupled to the current sensing (CS) terminal of IC 101, and the VFB signal generated by feedback circuit 113 is coupled to the feedback (FB) terminal of IC 101. Furthermore, a power supply voltage VDD can be generated on IC 101 or received via another terminal of IC 101 and can be used to power the circuitry therein as needed. Other embodiments may be configured differently and / or include other components, and any of these configurations may benefit from the techniques described herein.

[0031] In practical operation, the valley sensing detection circuit 103 receives the VSW signal from the SW terminal and the blanking control signal from the control circuit 105, and generates one or more zero-current detection (ZCD) signals. In some instances, multiple ZCD signals are generated, which may be collectively referred to as a valley train. In any of these cases, a given ZCD signal identifies when the voltage across the switching element 109 is low. Switching at any of these valleys (also referred to as a valley switch) allows for relatively low switching losses compared to switching when the current through the switching element 109 is high. The control circuit 105 receives the VFB signal at its FB input terminal, the IPK signal at its CS terminal, and one or more ZCD signals at its valley sensing (VS) input terminal, and provides a corresponding drive voltage (VDRV) signal at its DRV output terminal. A VDRV signal (which may be, for example, a pulse width modulation (PWM) signal) is applied to the control terminal of the switching element 109 via the driver 107 and can be configured by the control circuit 105 to promote valley switching based on one or more ZCD signals.

[0032] In some instances, and as further described below, the blanking control signal provided by control circuitry 105 indicates a trough contained in a given trough sequence at which control circuitry 105 is currently switching, and this trough determines the blanking time used by trough sensing detection circuitry 103. In some such instances, the blanking time is highest for the first (deepest) trough, and relatively shorter for subsequent trough groups. Control circuitry 105 can be any suitable flyback converter control circuitry configured for trough switching, the difference being that control circuitry 105 can be modified or otherwise further configured to provide a blanking control signal indicating the trough in which switching is taking place; in this instance, the blanking control signal is provided at a dedicated trough indication (VI) output terminal. Other instances may provide the blanking control signal via, for example, a general-purpose output terminal, and still other instances may be configured to provide a trough-sensing blanking time (rather than configuring trough sensing detection circuitry 103 to determine the trough-sensing blanking time based on the number of troughs received from control circuitry 105). See below for reference. Figures 2 to 6 The example further describes the valley sensing detection circuit 103.

[0033] Figure 2 Example signals of the switching terminals (or switching nodes, or switch nodes, which are used interchangeably herein) of a flyback power converter are shown. Figure 1 In example system 100, the signal can be, for example, the VSW signal at the SW terminal of IC 101. The signal is not intended to be drawn to scale, but is provided to illustrate various illustrative aspects of the signal, and the signal may vary from example to example. As shown, a single switching cycle of the signal includes an on-time (TON) portion and an off-time (TOFF) portion. The TOFF portion includes a demagnetizing (TDEMAG) portion and a resonant or no-load time (TDEAD) portion. The TDEMAG portion includes a leakage reset (TRESET) portion and a leakage ringing portion. The TDEAD portion includes a magnetizing ringing portion, which includes multiple troughs (V1, V2, ...). In this example, switching occurs on the second trough V2, and a new switching cycle begins. Depending on the peak current IPK, other examples may switch on the first trough V1 or a later trough (e.g., V3, V4, etc.). For example, the highest IPK range can be provided by switching at trough V1, the second highest IPK range by switching at trough V2, and the remaining lower IPK ranges by switching at trough V3. Other examples may use valley switching depending on the specific scheme.

[0034] like Figure 2The diagram further illustrates that a positive oscillation SL1 exists at the beginning of the TRESET portion. The peak shape of the TRESET portion can vary depending on the configuration, but in this example, it slopes slightly downwards from left to right. Other examples may show an upward oscillation and / or a more pronounced oscillation, or a more curved shape, or no oscillation or curvature at all. Furthermore, the duration of the TRESET varies with the peak current IPK. The higher the value of the peak current IPK, the longer the duration of the TRESET. At the end of the TRESET window, a steep negative oscillation SL2 exists, which can be confused with the negative oscillation SL4 in the magnetized ringing portion. Therefore, in this example, the power converter system 100 is configured with a positive oscillation detector for detecting SL1 and initiates an IPK-sensing blanking time that extends the duration of the TRESET portion. In this way, false trough claims in response to the negative oscillation SL2 are avoided.

[0035] like Figure 2 The diagram further illustrates that the leakage ringing section includes multiple occurrences of negative rotation SL3, which can be confused with the negative rotation SL4 in the magnetized ringing section. However, in the examples, the negative rotation SL3 can be distinguished from the negative rotation SL4. More specifically, the ringing in the leakage ringing section is caused by parasitic effects of the switching nodes (e.g., parasitic capacitances of the switching elements and transformers) and has a relatively higher frequency than the ringing in the magnetized ringing section. The ringing in the magnetized ringing section occurs when the secondary winding energy drops to (or reaches) zero. For a given application, the slowest leakage ringing can, for example, be twice as long as the fastest magnetized ringing. This means that any given rotation SL3 will end faster than the rotation SL4 at the first trough V1. Therefore, in this example, system 100 is configured with a negative oscillation detector that works in conjunction with a leakage filter. The period of the leakage filter is longer than any signal period of the leakage ringing, but shorter than the time required for the oscillation SL4 of the first trough to end, so that only detected troughs that occur after the leakage filter has expired are declared. In this way, false trough declarations in response to any negative oscillation SL3 in the leakage ringing portion are avoided.

[0036] like Figure 2The diagram further illustrates that the trough V1 is rounded because it does not reach ground. This occurs when N*VOUT is less than or equal to VIN, where N is the turns ratio of transformer 111. In these cases, the corresponding rotary SL4 operates naturally without reaching zero voltage, and the leakage filter described above expires before reaching the trough voltage, thus allowing a non-zero voltage trough to be declared. However, when N*VOUT is greater than VIN, then the trough V1 reaches zero voltage and the corresponding rotary SL4 terminates more quickly. In these cases, the leakage filter described above may not have expired when reaching the zero voltage level, which may result in the inability to declare the trough V1. Therefore, in this example, system 100 is configured with a zero-voltage detection (ZVD) circuit for detecting when zero voltage is reached, and logic for detecting the simultaneous occurrence of ZVD (zero voltage) and ZCD (zero current or trough detection) conditions. The ZVD circuit also acts as a rotation detector, so its output may switch in response to rotation; however, its output is consistent with the output of the negative rotation detector described above only when the voltage VSW at the switching terminal SW becomes zero (ground). Otherwise, the corresponding output waveforms of the two rotation detection circuits are reversed relative to each other. The logic is configured to sense the consistency of the two circuits, and thus distinguish between false troughs in the leakage ringing section and true troughs in the magnetized ringing section. In this way, a true trough declaration in response to a negative rotation SL4 reaching zero voltage before the leakage filter expires can be made, while false trough declarations caused solely by leakage ringing can be avoided.

[0037] Valley sensing detection circuit

[0038] Figure 3 Example shown Figure 1 A block diagram of the trough sensing detection circuit 103 of system 100 is shown. As illustrated, circuit 103 includes a rotation detection circuit 301, an adaptive blanking circuit 303, a zero-voltage detection (ZVD) circuit 305, and a zero-current detection (ZCD) circuit 307. Other embodiments may be configured differently and with different integration schemes, but still operate to provide similar functionality. For example, in another embodiment, each of the rotation detection circuit 301, the adaptive blanking circuit 303, and the zero-voltage detection (ZVD) circuit 305 may be integrated into the ZCD circuit 307. In the example operation, circuit 103 receives a switching terminal signal VSW at its input and generates one or more ZCD signals at its output. The VSW signal includes a leakage reset portion, a leakage ringing portion, and a magnetization ringing portion. Each ZCD signal indicates the presence of a trough within the magnetization ringing portion of the VSW signal. Flyback converter control circuitry (e.g., 105) can use the ZCD signals to provide trough switching. Advantageously, no auxiliary winding is required when generating one or more ZCD signals.

[0039] The rotation detection circuit 301 includes an input that receives a power supply VDD and another input that receives a switch terminal signal VSW (from the SW terminal of system 100). The rotation detection circuit 301 is configured to detect positive rotation at the start of a leakage reset portion of the VSW signal and negative rotation at one or more troughs of the VSW signal. As described above, the troughs can be dummy troughs of a leakage ringing portion or true troughs of a magnetized ringing portion. As further shown, the rotation detection circuit 301 further includes a threshold voltage input that receives an adjustable threshold voltage from the adaptive blanking circuit 303, which in turn allows the rotation detection circuit 301 to detect positive rotation (e.g., when the threshold voltage is high or otherwise set to a first value, such as 600 millivolts (mV)) or negative rotation (when the threshold voltage is low or otherwise set to a second value, such as ground or 0 volts). The output of the rotation detection circuit 301 is provided to both the adaptive blanking circuit 303 and the ZCD circuit 307.

[0040] The adaptive blanking circuit 303 includes an input receiving the power supply VDD, another input receiving the output of the slewing detection circuit 301, and another input receiving the VDRV signal generated by the control circuit 105, and an output providing a threshold voltage to the slewing detection circuit 301. In an example, the adaptive blanking circuit 303 is configured to provide one of a first and a second threshold voltage based on the three inputs, wherein the first threshold voltage allows the slewing detection circuit 301 to operate as a positive slewing detector configured to detect the leakage reset portion of the VSW signal, and the second threshold voltage allows the slewing detection circuit 301 to operate as a negative slewing detector configured to detect one or more troughs of the VSW signal. The adaptive blanking circuit 303 further includes another input receiving a blanking control signal generated by the control circuit 105 and is configured to generate a corresponding IPK-sensing blanking signal, which is then provided to the ZCD circuit 307 via another output of the adaptive blanking circuit 303.

[0041] ZVD circuit 305 includes an input for receiving the VSW signal and is configured to generate a zero-voltage detection (ZVD) signal in response to a trough in the magnetized ringing portion of the VSW signal reaching zero volts. The ZVD signal is provided to ZCD circuit 307 via the output of ZVD circuit 305.

[0042] ZCD circuit 307 includes an input receiving the detection from rotation detection circuit 301 and another input receiving the blanking signal from adaptive blanking circuit 303. ZCD circuit 307 is configured to blank the rotation detection associated with the leakage reset portion of the VSW signal in response to the blanking signal, and is further configured to distinguish true valleys contained in the magnetized ringing portion of the VSW signal from false valleys contained in the leakage ringing portion of the VSW signal. ZCD circuit 307 further includes another input receiving a ZVD signal from ZVD circuit 305, and is further configured to distinguish true valleys containing the magnetized ringing portion of the VSW signal that reach zero volts from false valleys contained in the leakage ringing portion of the VSW signal. A valley declaration in the form of a zero-current detection (ZCD) signal generated by ZCD circuit 307 is provided at the output of ZCD circuit 307, which in turn is provided to the VS terminal of control circuit 105. In an example, control circuit 105 can use the ZCD signal to perform valley switching.

[0043] Figure 4A Example shown Figure 3 A schematic diagram of the valley sensing detection circuit 103 is provided. The description of circuit 103 above also applies here, and is further extended through example arrangements of circuit systems to achieve the functions described herein. Other examples may be configured differently, but still achieve similar functions.

[0044] In this example, the gyration detection circuit 301 is configured to use capacitive gyration detection to sense the trough of the switching node VSW signal and includes a sensor 402 and a comparator 404. Sensor 402 includes a current source IBIAS1, a capacitor C1, a resistor R1, and a clamp including diodes D1 and D2. Each of these components can be rated to meet the specifications of a given application (e.g., a high-voltage automotive application where VSW can vary over a wide range, such as from -2 volts to 1000 volts). Although sensor 402 is shown as a separate circuit, some or all of it can be integrated with other components. For example, in some instances, capacitor C1 is a high-voltage metal-insulator-metal (MIM) capacitor (e.g., 150 picofarads, 700 volts) integrated with a semiconductor die that also includes a switching element 109 (e.g., a GaN power FET). Resistor R1 and current source IBIAS1 can be configured to provide a bias voltage level (e.g., just above ground potential, for example, in the range of 50mV to 100mV) at the output node of sensor 402. For example, continuing with the example above where capacitor C1 is approximately 150 nanofarads (e.g., rated at 700 volts), resistor R1 can be set to approximately 50kΩ, and current source IBIAS1 can be set to approximately 1.0 to 1.25 microamps to bias the output node of sensor 402 to approximately 50mV to 62.5mV. In example operation, IBIAS1, C1, and R1 effectively convert the SW node rotation into current, with its D1-D2 clamps used to limit the voltage swing (e.g., to approximately 0.6 volts or 0.7 volts for a silicon diode). Other suitable rotation detector configurations can be used.

[0045] As further illustrated, comparator 404 receives the sensor signal from sensor 402 at its non-inverting input and a threshold voltage at its inverting input, and generates a gyration comparator signal at its output. In this example, the threshold voltage is variable and set by adaptive blanking circuit 303 based on the gyration comparator signal from comparator 404 and the drive signal VDRV from control circuit 105. Generally, when drive signal VDRV is high (TON portion of the switching cycle), a first threshold voltage is applied to the inverting input of comparator 404, which allows comparator 404 to detect a positive gyration at the start of the leakage reset portion of the VSW signal after drive signal VDRV goes low (TOFF portion of the switching cycle); and after detecting a positive gyration, a second threshold voltage is applied to the inverting input of comparator 404, which allows comparator 404 to detect a negative gyration of the VSW signal occurring after the leakage reset portion. In this example, the first threshold voltage is 600mV (within acceptable tolerances for a given application, such as + / -10mV), and the second threshold voltage is ground potential (e.g., 0 volts + / -10mV).

[0046] Further reference Figure 4A In this example, the adaptive blanking circuit 303 is configured to provide a variable threshold voltage and a variable blanking signal that at least partially corresponds to the leakage reset portion of the VSW signal. As described above, the variable threshold voltage can be set to the bias rotation detection circuit 301 to detect positive rotation (first threshold voltage value) or negative rotation (second threshold voltage value), and the blanking signal effectively allows the leakage reset portion of the VSW signal to be ignored for the purpose of trough detection. As shown, the adaptive blanking circuit 303 includes logic 416, inverter 418, variable blanking delay 420, switches S1 and S2, and voltage source V1. In this example, logic 416 is implemented by a D-type synchronous, active-high-reset, positive-edge-triggered flip-flop, wherein a drive signal VDRV is applied to the reset input of logic 416, the data (D) input of logic 416 is held high via power supply VDD, and the clock input of logic 416 receives the rotation comparator signal from circuit 301 via inverter 422. The threshold voltage control signal at the Q output of logic 416, combined with inverter 418, controls switches S1 and S2 in a complementary manner as follows: when the Q output of logic 416 is high, switch S1 is open and switch S2 is closed; and when the Q output of logic 416 is low, switch S1 is closed and switch S2 is open.

[0047] In this example operation, when the VDRV signal is high (during the TON portion of the VSW signal for the current switching cycle), logic 416 resets, and the threshold voltage control signal at the Q output of logic 416 is low. This causes switch S1 to close and switch S2 to open, making the threshold voltage at the inverting input of comparator 404 equal to the value of voltage source V1 (e.g., 600mV). When the VDRV signal goes low (during the TOFF portion of the VSW signal for the current switching cycle), logic 416 becomes set or otherwise ready to be triggered by the next positive edge received at the clock input of logic 416. In this way, logic 416 effectively waits for the first (next) positive edge on its clock input, which in this example corresponds to the first negative (falling) edge of the sensor signal, as inverted by inverter 422. The first negative (falling) edge occurs just after the first positive (rising) edge of the sensor signal, which corresponds to the positive rotation SL1 of the VSW signal at the start of the leakage reset portion. Figure 2More specifically, when the slewing SL1 reaches its peak, the sensor signal output by sensor 402 stops rising and begins to fall. This falling edge of the sensor signal is converted into a positive edge by inverter 422 and is received at the clock input of logic 416. This positive edge triggers the threshold voltage control signal at the Q output of logic 416 to change from low to high, which in turn causes switch S2 to close (to connect the inverting input of comparator 404 to ground) and switch S1 to open (to disconnect V1). This high state of the threshold voltage control signal at the Q output of logic 416 is maintained until VDRV goes high again (which initiates the TON portion of the next switching cycle), which resets logic 416 and thus causes the threshold voltage control signal at the Q output of logic 416 to go low, which in turn causes switch S1 to close (to reconnect the inverting input of comparator 404 to V1) and switch S2 to open (to disconnect ground at the inverting input of comparator 404). The process is repeated within the switching cycle, and so on.

[0048] like Figure 4A The diagram further illustrates that the variable blanking delay 420 receives a threshold voltage control signal from the Q output of logic 416 and further receives a blanking control signal from control circuitry 105. As explained above, in response to the VDRV signal transitioning from low to high, the threshold voltage control signal from the Q output of logic 416 transitions from low to high at the start of the TON portion of a given switching cycle. The blanking control signal indicates the number of troughs that require switching. In this way, the blanking signal provided by the variable blanking delay 420 is set based on the number of troughs, which is analogous to the corresponding peak current IPK.

[0049] More specifically, the leakage reset time (TRESET, in Figure 2 The display in the middle can be identified as:

[0050]

[0051] Where IPK is the peak current through the primary-side inductor, LK is the leakage inductance of the flyback power converter, VOUT is the output voltage of the flyback power converter, N is the turns ratio of the flyback transformer, and VCLAMP is the clamping voltage (in Figure 2 Displayed in, and by Figure 7 (Provided by buffer 710 in the buffer). VCLAMP can be calculated as follows:

[0052] VCLAMP = Tolerance% * VFETMAX - VINMAX (Equation 2)

[0053] Where VFETMAX is the maximum rated voltage of switching element 109, the tolerance percentage (%) provides some tolerance at said maximum rated voltage, and VINMAX is the peak DC voltage based on the general AC line range. Total demagnetization time (TDEMAG, in Figure 2 The display in the middle can be identified as:

[0054]

[0055] Where Lm is the magnetizing inductance. For a given flyback power converter system, the maximum TRESET can be higher than the minimum TDEMAG. In this example, to address this issue, the variable blanking delay 420 can be configured to provide an adaptive reset blanking period based on IPK (via a blanking signal at its output). In this example, the number of troughs can be used as an analogue to the IPK information to achieve this adaptive reset blanking period. Table 1 below shows some such examples.

[0056] As shown in Table 1, N is about 6 or 7.5, Lm is in the range of about 150 microhenries (μH) to 350 μH, LK is in the range of about 1.5 μH to 7 μH, the tolerance percentage (%) is about 0.95, VFETMAX is about 650 volts (e.g., the maximum voltage of a GaN power FET), the general AC line range is about 85VAC to 264VAC, 47Hz to 60Hz, VINMAX is about 375 volts (e.g., 264VAC*sqrt(2)), VOUT is about 20 volts, IPK is about 3.5 amps, and the resulting TRESET is in the range of about 43 nanoseconds (ns) to 265 ns. Therefore, the blanking time reflected in the blanking signal generated by the variable blanking delay 420 can be IPK-aware and, for a given configuration, can be set slightly longer than TRESET, for example, in instances where the blanking time reflected in the blanking signal is set to approximately TRESET plus approximately 50ns to 500ns (or other tolerances suitable for a given application). Other instances can be configured differently and therefore have different parameter values ​​(e.g., N, Lm, LK, tolerance %, VFETMAX, VINMAX, VOUT, and IPK), and therefore different TRESET values. See below for reference. Figure 4B Examples further illustrate instances of such IPK-aware (and valley-aware) blanking signal schemes.

[0057] Table 1: Instance parameter values ​​used to calculate TRESET

[0058]

[0059] Figure 4B Example shown Figure 4AA schematic diagram of the system's variable blanking delay 420 is shown. As illustrated, the variable blanking delay 420 includes capacitors C2, C3, and C4, a current source IBIAS2, a Schmitt trigger 426, transistors (switches) MN3, MN4, and MN5, and an inverter 428. Capacitors C2, C3, and C4 are coupled between the input of the Schmitt trigger 426 and ground. Capacitors C3 and C4 can be switched via transistors MN4 and MN5 based on the value of a blanking control signal (in this example, a 2-bit control signal), respectively, and capacitor C2 can be switched via transistor MN3 based on a threshold voltage control signal from the Q output of logic 416. In this example, each of transistors MN3, MN4, and MN5 is implemented using an n-type field-effect transistor (NFET), but any suitable switching technology can be used (e.g., a p-type FET, a unipolar, single-throw switch, or any other controllable switch). Other examples may be configured differently but achieve similar functionality.

[0060] In the example operation, when the threshold voltage control signal from the Q output of logic 416 goes low (in response to the VDRV signal going high during the TON portion of the VSW signal), the output of inverter 428 goes high, which in turn turns on (closes) transistor MN3, thereby pulling the input node of Schmitt trigger 426 low, which in turn causes the blanking signal output of Schmitt trigger 426 to go low. Subsequently, when the threshold voltage control signal from the Q output of logic 416 goes high (in response to the VDRV signal going low during the TOFF portion of the VSW signal), the output of inverter 428 goes low, which in turn turns off (opens) transistor MN3, thereby releasing the pull-down on the input node of Schmitt trigger 426 and allowing capacitors C2, as well as C3 and C4 (when switched via MN4 and MN5 respectively), to charge through the constant current source IBIAS2. When the voltage at the input nodes of the Schmitt trigger 426 (and across one or more of capacitors C2, C3, and C4) reaches the high threshold (VTH_SCHMITT_426) of the Schmitt trigger 426, the blanking signal output of the Schmitt trigger 426 goes high and remains high until the start of the next switching cycle. The duration of the low state of the blanking signal before the threshold voltage control signal goes high can be ignored because it corresponds to the TON portion of the VSW signal (no trough switching). However, the duration of the low state of the blanking signal after the threshold voltage control signal goes high corresponds to the actual blanking time and can be determined as follows:

[0061] Blanking time = total capacitance * VTH_SCHMITT_426 / IBIAS2 (Equation 4).

[0062] The blanking time can be increased by turning on one or both of MN4 and MN5. As described above, a longer blanking time is appropriate when switching on the first or second trough, which in turn corresponds to a higher peak current IPK and a longer TRESET duration.

[0063] Table 2 below shows how the blanking time can be set depending on the number of troughs in the switching (e.g., the duration for which the blanking signal remains in its low state, as measured from when the threshold control voltage signal goes high), and how the blanking control signal from control circuit 105 can be set to provide the blanking time to the variable blanking delay 420. For this example, the following example values ​​for the variable blanking delay 420 are used: C2 is 400 nanofarads, C3 and C4 are each 200 nanofarads, IBIAS2 is approximately 2 microamps, and the high threshold (VTH_SCHMITT_426) of the Schmitt trigger 426 is 1.25 volts. Other examples can be configured differently, for example, with different component values, fewer or more optional blanking times (e.g., 1 or 2 blanking times, or 4 or 5 blanking times), and smaller or larger control signals (e.g., 1-bit control signal, or 3-bit control signal).

[0064] Table 2: Blanking Signal Schemes for Valley Sensing (and IPK Sensing)

[0065]

[0066] Further reference Figure 4AIn this example, ZVD circuit 305 receives the VSW signal and is configured to generate a ZVD signal in response to a trough in the magnetized ringing portion of the VSW signal reaching zero volts. The ZVD signal is provided to ZCD circuit 307. In this example, ZVD circuit 305 includes transistors MN1 and MN2, resistor R3, diode D3, capacitor CPAR, comparator 424, and negative voltage supply -VT. Capacitor CPAR represents the parasitic capacitance between the SW node and the source terminal of transistor MN1, and diode D3 acts as the body diode of transistor MN2. Although shown as different components, CPAR may be inherent in circuit 103, and D3 may be within MN2. Other ZVD configurations can be used. As further illustrated, each of transistors MN1 and MN2 is an n-type FET with its gate terminal coupled to ground. The drain of transistor MN1 is coupled to the switching terminal SW, and its source is coupled to the inverting input of comparator 424. The drain of transistor MN2 is coupled to the inverting input of comparator 424, and its source is coupled to ground via resistor R3. A voltage supply -VT is coupled between ground and the non-inverting input of comparator 424. Transistor MN1 can be, for example, a scaled-down replica of switching element 109, such as in the case where both MN1 and switching element 109 are GaN FETs. For example, in some such instances, the width-to-length ratio (W / L) of switching element 109 is N times larger than the W / L ratio of FET MN1, where N is any integer greater than one (e.g., 800), and the width W and length L are the channel parameters (actual dimensions of the current-carrying region) of the respective transistors. Any scaling ratio suitable for a given application can be used. If desired, voltage scaling circuitry can also be used to reduce VSW to a low voltage domain (e.g., 5 volts). Transistor MN2 can be, for example, an n-type metal-oxide-semiconductor FET (e.g., a 5-volt silicon NMOS FET with a silicon body diode D3). In this example, resistor R3 can be 50 kΩ, and voltage supply -VT can be -500 mV or just below ground potential.

[0067] In practical operation, when N*VOUT is less than or equal to VIN, the given trough does not reach ground (~0 volts), and causes the negative loop run of the true trough to take longer than that of the leakage filter 408 (meaning that the filter 408 will expire before reaching the non-zero true trough), thus allowing the AND-gate 410 to make a correct trough declaration, as described below. However, when N*VOUT is greater than VIN, the bottom of the trough is grounded due to the third quadrant conduction of transistor MN1. In these cases, the time it takes for the negative loop of this true trough to reach ground may be comparable to or even closer to the negative loop run time of the dummy trough in the leakage ringing portion of the VSW signal, making it difficult to distinguish the true zero voltage trough of the magnetized ringing portion from the dummy trough of the leakage ringing portion. For example, and referring to Figure 4AIn this example, comparator 404 can indicate a true trough signal earlier than the expiration of leakage filter 408. In this instance, without further action, the true zero voltage trough will not be declared by AND gate 410. ZVD circuit 305 (in conjunction with logic 414) can be used to help solve this problem.

[0068] More specifically, to determine whether this trough is genuine, comparator 424 monitors the source of MN1, which becomes negative due to third-quadrant conduction of MN1 (MN1 conducts in reverse when VSW becomes negative). This, in turn, turns on the body diode D3 of MN2 (dragging the inverting input of comparator 424 below ground), which can be detected using comparator 424. When the source of MN1 becomes more negative than the negative voltage supply -VT, the output of comparator 424 goes high to indicate that zero voltage has been reached. Additionally, the parasitic capacitor CPAR effectively makes the ZVD circuit 305 a gyratory detector, allowing the ZVD signal at the output of comparator 424 to switch with trough or leakage ringing. However, in practice, this switching is distinguishable. Specifically, the corresponding outputs of comparator 424 and comparator 404 coincide only when a genuine ZVS condition (zero voltage detected) exists. Otherwise, the outputs of comparators 404 and 424 are inverted relative to each other. Therefore, in this example, and as further described below, the AND gate 414 of the ZCD circuit 307 is configured to detect when the outputs of comparators 404 and 424 are reversed (false trough) or the same (true trough).

[0069] Further reference Figure 4A In this example, the ZCD circuit 307 receives the gyration comparator signal from the gyration detection circuit 301, the blanking signal from the adaptive blanking circuit 303, and the ZVD signal from the ZVD circuit 305, and is configured to: blank the gyration detection associated with the leakage reset portion of the VSW signal in response to the blanking signal; distinguish the true valley contained in the magnetized ringing portion of the VSW signal from the false valley contained in the leakage ringing portion of the VSW signal in response to the filter signal; and distinguish the false valley contained in the leakage ringing portion of the VSW signal from the true valley contained in the magnetized ringing portion of the VSW signal and reaching zero volts. The ZCD signal provided by the ZCD circuit 307 goes high to declare a detected valley as a true valley, and otherwise goes low. The control circuit 105 can use these ZCD signals to perform valley switching.

[0070] like Figure 4A The example further demonstrates that the ZCD circuit 307 uses logic to distinguish between true and false troughs and to declare true troughs, and further includes a leakage filter 408. The logic includes 2-input AND gates 406, 410, and 414 (indicated by the & symbol) and a 2-input OR gate 412 (indicated by the ≥1 symbol). Figure 4CAn example implementation of a leakage filter 408 is shown. As shown, the leakage filter 408 includes a capacitor C5, a current source IBIAS3, a Schmitt trigger 430, and a transistor (switch) MN6. The capacitor C5 is coupled between the input of the Schmitt trigger 430 and ground and can be switched via the transistor MN6 based on a trough detection signal from the AND gate 406. In this example, the transistor MN6 is implemented using an NFET, but any suitable switching technique can be used, as described above with respect to MN3 through MN5. The example operation of the leakage filter 408 is as follows.

[0071] When the trough detection signal from AND gate 406 goes low (e.g., in response to the gyration comparator signal going low, thus indicating the start of a negative gyration towards a possible trough), transistor MN6 turns off (opens), thereby releasing the pull-down on the input node of Schmitt trigger 430 and allowing capacitor C5 to charge through the constant current source IBIAS3. When the voltage at the input node of Schmitt trigger 430 (and across capacitor C5) reaches the high threshold (VTH_SCHMITT_430) of Schmitt trigger 430, the filtered signal at the output of Schmitt trigger 430 goes high and is provided to one of the inputs of AND gate 410. Subsequently, when the trough detection signal from AND gate 406 goes high (in response to the blanking signal still being high and the gyration comparator signal going high because a trough has been reached and a positive gyration has begun), transistor MN6 turns on (closes), thereby pulling the input node of Schmitt trigger 430 low, which in turn causes the filtered signal output of Schmitt trigger 430 to go low. The time from when the trough detection signal from AND gate 406 goes low to when the output of Schmitt trigger 430 goes high corresponds to the leakage filter time. In this way, the filtered signal is a blanking signal, which prevents AND gate 410 from declaring a trough with a negative rotation that runs less than the leakage filter time, such as a false trough in the leakage ringing portion of a VSW signal. The value of the leakage filter time can be determined as:

[0072] Leakage filter time = C5_CAPACITANCE*VTH_SCHMITT_430 / IBIAS3 (Equation 5).

[0073] In one instance, the following values ​​are used: C5 is 448 femtofarads, IBIAS3 is approximately 2 microamps, and the high threshold (VTH_SCHMITT_430) of the Schmitt trigger 430 is 1.25 volts. This causes the filtered signal to transition to its high state approximately 280 ns after the trough detection signal from the AND gate 406 goes low. More generally, the leakage filter time can be set to some time between the signal period of the leakage ringing section and the signal period of the magnetized ringing section. More specifically, according to some examples, the slowest frequency of the leakage ringing section is approximately two times or more faster than the fastest frequency of the magnetized ringing section, such that the shortest signal period of the magnetized ringing section is approximately two times or more longer than the longest signal period of the leakage ringing section. In this way, the value of the leakage filter time can be set to be greater than the signal period of the leakage ringing section but less than the signal period of the magnetized ringing section. These signal periods can vary depending on the power converter configuration and can be determined empirically or theoretically (e.g., circuit modeling and analysis). Other instances can use different logic or be configured in other ways to provide similar functionality. Although in this example, leakage filter 408 provides a fixed leakage filter time, in other examples it can be configured to provide an adjustable leakage filter time. For example, it can be configured to provide an adjustable leakage filter time by referring to... Figure 4B The leakage filter 408 is configured in a similar manner to the blanking time described by the variable blanking delay 420 to increase the leakage filter time, selectively adding more capacitors to increase the leakage filter duration as needed to blank leakage ringing.

[0074] Further reference Figure 4A An example operation of the ZCD circuit 307 is as follows. AND gate 406 receives a gyroscope signal from comparator 404 at one of its inputs and an IPK-sensing blanking signal from variable blanking delay 420 at the other of its inputs. It generates a positive (high) valley detection signal at its output only when both inputs are high, and a negative (low) valley detection signal otherwise. In this way, AND gate 406 is configured to blank the leakage reset portion of the VSW signal in response to the IPK-sensing (and valley-sensing) blanking signals, and to indicate the valley that appears after the reset blanking period.

[0075] Leakage filter 408 receives a trough detection signal at its input and provides a filtered signal at its output, as described above. AND gate 410 receives a trough detection signal from AND gate 406 at one of its inputs and a filtered signal from leakage filter 408 at the other of its inputs, generating a positive (high) trough detection signal at its output when both inputs are high, and a negative (low) trough detection signal otherwise. In this way, AND gate 410 is configured to blank the leakage ringing portion of the VSW signal in response to the filtered signal, thereby distinguishing any true trough detection generated by AND gate 406 from any false trough detection generated by AND gate 406 due to the leakage ringing portion of the VSW signal.

[0076] AND gate 414 receives a trough detection signal from AND gate 406 at one of its inputs and a ZVD signal from comparator 424 at the other of its inputs. It generates a positive (high) trough detection signal at its output when both inputs are high, and a negative (low) trough detection signal otherwise. In this way, AND gate 414 is configured to distinguish between spurious troughs in the leakage ringing portion of the VSW signal and true troughs that reach zero volts before the leakage filter 408 expires.

[0077] OR gate 412 receives the output from AND gate 410 at one of its inputs and the output of AND gate 414 at the other of its inputs, and generates a positive (high) valley detection signal at its output when one or both of the inputs are high, and a negative (low) valley detection signal otherwise. In this way, OR gate 412 is configured to declare one or more true valleys contained in the magnetized ringing portion of the VSW signal in response to inputs from AND gate 410 and / or AND gate 414. Figure 5A The example further demonstrates that the first trough reaches approximately 320 volts.

[0078] Figure 5A The example shown is when N*VOUT is less than or equal to VIN. Figure 1 A diagram of the signals generated by the system. (Reference) Figure 4A This can further enhance understanding, and the relevant descriptions above also apply here. Figure 5AThe first (topmost) figure shows the VSW signal from the switching node SW of a power converter (e.g., power converter 100). In this example, the VSW signal ranges from approximately 0 volts to approximately 600 volts. As shown on the time scale axis, the TON and TOFF portions of the depicted switching cycle begin at approximately 25.1 μs and approximately 27 μs, respectively. Furthermore, the leakage reset blanking period ends at approximately 27.6 μs (indicated by the dashed line marked A), corresponding to the leakage reset portion of the VSW signal and possibly some of the leakage ringing portions. Additionally, a flat region (which may also contain some of the leakage ringing portions) extends from point A to approximately 33 μs, and the first true trough of the magnetized ringing portion of the VSW signal occurs at approximately 33.8 μs (indicated by the dashed line marked B) and reaches approximately 320 volts. Subsequent troughs of the magnetized ringing portion gradually become shallower. Switching can occur at any of the true troughs.

[0079] Further reference Figure 5A The second figure from the top shows the threshold voltage at the inverting input of comparator 404. Recall that when the VDRV signal goes high (the TON portion of the VSW signal that initiates the next switching cycle), logic 416 of the adaptive blanking circuit 303 resets, and the threshold voltage control signal at the Q output of logic 416 goes low (as shown above). Figure 5A (As shown in the fifth figure from the top), this in turn causes switch S1 to close and switch S2 to open, causing the threshold voltage at the inverting input of comparator 404 to change from its low value to its high value (voltage source V1). Figure 5A In the examples, these are 0 volts and 600mV respectively. Further reiterating above, when the VDRV signal goes low (the TOFF portion of the VSW signal that initiates the current switching cycle), logic 416 becomes set and waits for the next positive edge on its clock input, in this example, the next positive edge corresponding to the first falling edge of the sensor signal, as inverted by inverter 422. More specifically, and as... Figure 5A As shown in the third figure from the top of the example, this first falling edge of the sensor signal occurs approximately 27.1 μs after the first rising edge of the sensor signal, which is the positive rotation SL1 of sensor 402 for the VSW signal at the beginning of the leakage reset section. Figure 2 The falling edge of the sensor signal is converted to a positive edge by inverter 422 and received at the clock input of logic 416. This positive edge causes the threshold voltage control signal at the Q output of logic 416 to change from low to high (also around 27.1 μs, as shown in Figure 5 from the top), which in turn causes switch S2 to close and switch S1 to open, thereby causing the threshold voltage to change from its high value of approximately 600 volts to its low value of approximately 0 volts (also around 27.1 μs, as shown in Figure 2 from the top). Figure 5A As further shown in the fifth figure from the top, the threshold voltage control signal is kept high until VDRV goes high again (to initiate the next switching cycle), which resets logic 416 and thus causes the threshold voltage control signal to go low, which in turn causes switch S1 to close and switch S2 to open, thus causing the threshold voltage to change from its low value of 0 volts to its high value of 600mV (as shown in the second figure from the top).

[0080] Further reference Figure 5A The third figure, starting from the top, shows the sensor signal provided by sensor 402 to the non-inverting input of comparator 404. As shown, capacitor C1 causes the sensor signal to: return to a low state or otherwise move towards a low state in response to a falling edge of the VSW signal; return to a high state or otherwise move towards a high state in response to a rising edge of the VSW signal; and remain in an intermediate state in response to the flat (non-returning) portion of the VSW signal. In this example, the low state is approximately -0.5 volts, the high state is approximately 0.7 volts (due to clamps D1 to D2), and the intermediate state is in the range of approximately 50 mV to 100 mV (just above ground potential according to IBIAS1 and resistor R1, as described above).

[0081] Further reference Figure 5A The fourth figure, starting from the top, shows the gyration comparator signal provided by comparator 404. As shown, the gyration comparator signal provided by comparator 404 is high if the voltage of the sensor signal at the non-inverting input of comparator 404 minus the threshold voltage at the inverting input of comparator 404 is greater than approximately 0 volts; and low if the voltage of the sensor signal at the non-inverting input of comparator 404 minus the threshold voltage at the inverting input of comparator 404 is less than or equal to 0 volts. It can be further seen that the gyration comparator signal provided by comparator 404 is high during the flat region of the VSW signal after the more aggressive leakage ringing stabilizes (around dashed line A) until the negative gyration of the first trough of the magnetized ringing portion of the VSW signal begins. This is because the threshold voltage at the inverting input of comparator 404 will be set to ground potential, and the sensor signal bias during the flat region is just above ground potential. In response to a negative rotation, the rotation comparator signal provided by comparator 404 then switches from high to low and remains low until a trough is reached and the opposite (positive) rotation begins. At this point, the rotation comparator signal switches from low to high and remains high until a peak is reached and the opposite (negative) rotation begins. In this way, the true trough of the magnetized ringing section can be identified by the rising edge of the rotation comparator signal. This switching of the rotation comparator signal can be repeated until the control circuit 105 initiates the next switching cycle (TON) or the resonance of the TDEAD cycle of the switching cycle stops or is further reduced to a non-trigger level.

[0082] Further reference Figure 5A The sixth figure from the top illustrates the blanking signal provided by the Schmitt trigger 426. As shown, when the threshold voltage control signal from the Q output of logic 416 (the fifth figure from the top) goes low (in response to the VDRV signal going high during the TON portion of the VSW signal), the blanking signal provided by the Schmitt trigger 426 goes low. Subsequently, when the threshold voltage control signal from the Q output of logic 416 goes high (in response to the VDRV signal going low during the TOFF portion of the VSW signal), a timing blanking cycle is initiated, as described above. When the voltage at the input node of the Schmitt trigger 426 reaches the high threshold of the Schmitt trigger 426, the blanking signal provided by the Schmitt trigger 426 goes high and remains high until the next switching cycle begins. Figure 5A As further illustrated in the sixth figure from the top, the duration of the low state of the blanking signal that occurs before the threshold voltage control signal (Figure 5) goes high can be ignored, as it corresponds to the TON portion of the VSW signal (without trough switching). However, the duration of the low state of the blanking signal that occurs after the threshold voltage control signal goes high corresponds to the actual blanking time (in... Figure 5A (marked in the middle), and can be determined as described above. Figure 5A In this example, the blanking time is approximately 504 ns (M2-M1). See above for reference. Figure 4B This blanking time is provided as described (e.g., by switching capacitors C2, C3, and C4).

[0083] Further reference Figure 5AFigure 7, starting from the top, illustrates the filtered signal provided by the Schmitt trigger 430. As a preliminary note, it should be observed that, assuming the blanking signal is high and allowing for some propagation delay, the trough detection signal at the output of AND gate 406 primarily tracks the gyration comparator signal at the input of AND gate 406. When the trough detection signal from AND gate 406 is high (in response to both the gyration comparator signal and the blanking signal being high), the filtered signal output of the Schmitt trigger 430 is low, as described above. Subsequently, when the trough detection signal from AND gate 406 goes low (e.g., in response to the gyration comparator signal going low, thus indicating the start of a negative gyration towards a possible trough), the pull-down on the input node of the Schmitt trigger 430 is released, and the leakage filter time period is initiated, as further described above. After the leakage filter time expires, the filtered signal at the output of Schmitt trigger 430 goes high and remains high until the trough detection signal from AND gate 406 goes high again (e.g., in response to the gyration comparator signal going high again, thus indicating the start of forward rotation). This causes the filtered signal output of Schmitt trigger 430 to go low, and the process is repeated for subsequent troughs. Therefore, the leakage filter time, from the trough detection signal from AND gate 406 going low to the filtered signal at the output of Schmitt trigger 430 going high, is approximately 290 ns (M4-M3) in this example. See above for reference. Figure 4C The description provides the timing for this leakage filter.

[0084] Further reference Figure 5A Figure 8, starting from the top, shows the ZCD signal provided by OR gate 412. As a preliminary note, it should be observed that, assuming the blanking signal is high, the filter signal is high, and some propagation delay is allowed, the output of AND gate 410 primarily tracks the gyrocomparator signal on the input of AND gate 406. Further note should be observed that... Figure 5A In this example, the ZVD signal is low because none of the troughs have reached zero volts. Therefore, the input from AND gate 414 to OR gate 412 will be low. As shown, when the outputs from AND gates 410 and 414 are both low, the ZCD signal at the output of OR gate 412 is low. However, as further shown, when both the blanking signal and the filter signal are high and the gyroscope comparator signal transitions from low to high (indicating a trough), the ZCD signal at the output of OR gate 412 transitions from low to high, thus declaring or otherwise signaling a trough. This declaration is repeated for each subsequent occurrence of both the blanking signal and the filter signal being high and the gyroscope comparator signal transitioning high (indicating the next trough) to provide a set of ZCD signals, also known as a trough sequence, which the control circuit 105 can use to switch.

[0085] With Figure 5A In a similar way, Figure 5B Shown by Figure 1The diagram shows the signals generated by the system, but the difference lies in the example. Figure 5B This demonstrates the case where N*VOUT is greater than VIN. (See reference) Figure 4A This can further enhance understanding, and the relevant descriptions above also apply here. Figure 5B The first (topmost) figure shows the VSW signal from the switching node SW of a power converter (e.g., power converter 100). In this example, the VSW signal is in the range of approximately 0 volts to approximately 265 volts. As shown on the time scale axis, the TON and TOFF portions of the depicted switching cycle begin at approximately 21.2 μs and approximately 27.1 μs, respectively. Furthermore, in this example, the first true trough of the magnetization ringing portion of the VSW signal occurs at approximately 29 μs and reaches ground potential (indicated by the dashed lines marked C and D). This occurs when N*VOUT is greater than VIN. More detailed, and as... Figure 2 As best illustrated, VIN is effectively the average value of the VSW signal, and N*VOUT is the voltage in the flat region of the VSW signal relative to VIN. Figure 5B In this example, the value of N*VOUT is greater than the value of VIN. Subsequent troughs in the magnetized ringing section gradually become shallower and, in this example, do not reach ground potential, including a second true trough (specified by the dashed line marked E). In other examples, the second, third, and subsequent true troughs may also reach ground potential. Switching can occur at any point within the true troughs.

[0086] Further reference Figure 5B The second and third figures, starting from the top, are superimposed on each other and show the threshold voltage at the inverting input of comparator 404 and the sensor signal at the non-inverting input of comparator 404. Figure 5A The above descriptions of the second and third figures, starting from the top, also apply here, including descriptions relative to the following: circuit function, the value of the threshold voltage (e.g., 0 volts and 600 mV), the first falling edge of the sensor signal occurring at approximately 27.1 μs, the threshold voltage that responsively transitions from its high value (e.g., approximately 600 mV) to its low value (e.g., approximately 0 volts), and the low, intermediate, and high states of the sensor signal (e.g., -0.5 volts, 50 mV to 100 mV, and 0.7 volts). Other examples may be configured differently and have different parameter values ​​and timings, but still provide similar functionality.

[0087] Further reference Figure 5B The fourth figure, starting from the top, shows the gyroscope comparator signal provided by comparator 404. Figure 5A The description above for the fourth figure (starting from the top) also applies here, including a description of the circuit's function. Other examples may be configured differently and have different parameter values ​​and timings, but still provide similar functionality. For example... Figure 5BAs shown in the example, the gyration comparator signal provided by comparator 404 is high during the flat region until the negative gyration begins at the first trough. At this point, the gyration comparator signal switches from high to low and remains low until the trough is reached. In this example, the trough is at 0 volts (indicated by the dashed line marked C). At this point, the gyration comparator signal switches from low to high and remains high until the next peak is reached and the opposite (negative) gyration begins. As... Figure 5A In some cases, the trough can be identified by the rising edge of the gyroscope comparator signal, and the switching of the gyroscope comparator signal can be repeated until the control circuit 105 initiates the next switching cycle (TON) or the resonance of the TDEAD cycle of the switching cycle stops or is otherwise reduced to a non-trigger level.

[0088] Further reference Figure 5B The fifth figure, starting from the top, shows the ZVD signal provided by comparator 424. Figure 5A In this example, none of the troughs reach ground potential, as described above; therefore, the ZVD signal in this example will remain in its low state. However, in Figure 5B In this example, the first trough reaches the ground potential. As further described above, due to CPAR, the ZVD circuit 305 also acts as a slewing detector. More detailed, and as... Figure 5B As shown in the example, the ZVD signal will go high in response to a negative rotation of the VSW signal and low in response to a positive rotation. Additionally, the ZVD signal will also go high when zero volts are detected. As described above, this paper focuses on the case where both the ZVD signal and the gyration comparator signal are high simultaneously, as detected by AND gate 414. Conversely, the case where the ZVD signal is high when the gyration comparator signal is low can be ignored. Figure 5B As shown in the example, the ZVD signal and the gyrocomparator signal are both high from approximately 28.9 μs to approximately 29.2 μs (indicated by the dashed lines marked C and D). This is the only time period in this example that satisfies the condition, therefore AND gate 414 will declare a true trough.

[0089] Further reference Figure 5B The sixth and seventh figures, starting from the top, are superimposed on each other and show the threshold voltage control signal provided by the adaptive blanking circuit 303 and the blanking signal provided by the Schmitt trigger 426. Relative to... Figure 5A The above descriptions of the threshold voltage control signal and the blanking signal also apply here. As described above, the duration of the low state of the blanking signal that occurs before the threshold voltage control signal goes high can be ignored because it corresponds to the TON portion of the VSW signal (no valley switching). However, the duration of the low state of the blanking signal that occurs after the threshold voltage control signal goes high corresponds to the actual blanking time (in Figure 5B(marked in the middle), and can be determined as described above. Figure 5B In this example, the blanking time is approximately 504 ns (M6-M5). Again, please refer to the above. Figure 4B This blanking time is provided as described (e.g., by switching in capacitors C2, C3, and C4).

[0090] Further reference Figure 5B The eighth figure, starting from the top, shows the filtered signal provided by the Schmitt trigger 430. (Relative to...) Figure 5A The above description of the filtered signal and leakage filter time also applies here. As described above, the leakage filter time begins when the trough detection signal from AND gate 406 goes low (e.g., in response to the gyration comparator signal going low, thus indicating the start of a negative gyration towards a possible trough) and ends when the filtered signal at the output of Schmitt trigger 430 goes high, and in this example is approximately 290 ns (M8-M7). Again, refer to the above... Figure 4C The leakage filter time is provided as described.

[0091] Further reference Figure 5B The bottom diagram shows the ZCD signal provided by OR gate 412. Relative to... Figure 5A The above descriptions of the filtered signal and leakage filter time also apply here. Unlike Figure 5A One example of a ZVD signal is low (because none of the troughs reach zero volts). Figure 5B The first trough reaches ground and the ZVD signal is therefore high. Therefore, the input from AND gate 414 to OR gate 412 will be high. For example... Figure 5B The example further demonstrates that when the outputs from AND gates 410 and 414 are both low, the ZCD signal at the output of OR gate 412 is low. However, as... Figure 5B The diagram further illustrates that when either the blanking signal or the filter signal or the ZVD signal is high and the gyroscope comparator signal transitions from low to high (indicating a trough), the ZCD signal at the output of OR gate 412 transitions from low to high, thereby declaring or otherwise signaling a trough. This declaration is repeated for each subsequent occurrence of the blanking signal and the filter signal (or the ZVD signal) being high and the gyroscope comparator signal transitioning high (indicating the next trough), to provide a set of ZCD signals (a trough sequence) that the control circuit 105 can use for switching.

[0092] method

[0093] Figure 6 A flowchart illustrating a method for valley sensing in a flyback power converter is shown in the example. For instance, the method can be achieved through… Figure 1The system 100 shown in the figure can be used for valley switching, but other systems can use the VSW signal at the switching node of a given system.

[0094] At 601, the method includes receiving a switch terminal signal (VSW). As shown, the signal includes a leakage reset time portion (T). RESET ( ), leakage ringing section and magnetized ringing section. The trough to be connected is in the magnetized ringing section.

[0095] At 603, the method continues to detect the forward rotation of the leak reset section (designated as SL1, at the beginning of the TDEMAG section, as shown below). Figure 2 (As shown above). Figure 4A , 5A As described in 5B, this forward rotation detection can be performed, for example, by the sensor 402 and comparator 404 of the rotation detection circuit 301, through the operation of the adaptive blanking circuit 303 and in response to VDRV, when the threshold voltage at the inverting input of the comparator 404 is set to the value of the voltage source V1. The method continues to 605, where a blanking signal configured to blank the leakage reset portion is generated. As described above, the duration of the leakage reset blanking period configured in the blanking signal can be based on the peak current (IPK) through the primary winding and the number of troughs to be turned on, in order to provide IPK-sensing (and trough-sensing) blanking time. As described above relative to Figure 4A , 4B Further described in 5A and 5B, this blanking signal can be generated, for example, by a variable blanking delay 420 of adaptive blanking circuit 303, in response to a threshold voltage control signal from logic 416 and blanking control from control circuit 105. Figure 6 The diagram further demonstrates that the detection at 603 and the generation at 605 can be used to bypass or otherwise ignore the TRESET portion of the switch terminal signal. After the leakage reset blanking cycle has ended, the blanking signal from the variable delay 420 is then combined with the gyroscope signal from the comparator 404 via AND gate 406 to generate a trough detection signal.

[0096] If the leakage reset (TRESET) portion of the switching terminal signal is blanked, the method continues by initializing a trough counter at 607 (e.g., setting X to 1) and detecting one or more possible troughs for negative rotation at 609. More specifically, and as further described above, one or more troughs may appear after the blanked TRESET portion of the switching terminal signal, and these troughs may include false troughs (e.g., troughs in the leakage ringing portion) and true troughs (e.g., troughs in the magnetized ringing portion). For example, a trough can be identified when the negative rotation detected at 609 stops (e.g., when the rate of change becomes zero, such as when zero voltage is reached or when the negative rotation transitions to positive rotation). As described above relative to... Figure 4A , 5A As further described in 5B, negative slewing detection can be performed, for example, by the sensor 402 and comparator 404 of the slewing detection circuit 301, through the operation of the adaptive blanking circuit 303 and in response to VDRV, when the threshold voltage at the inverting input of comparator 404 is set to ground potential. In this example, the slewing comparator signal generated by comparator 404 transitions from high to low at the start of negative slewing.

[0097] The method continues to step 611, where it is determined whether a trough has been detected. As described above, for example, the logic of AND gate 406 can be used in conjunction with the rotation detection circuit 301 to detect whether a trough has occurred. More specifically, and while the blanking signal from the variable blanking delay 420 is still high (because the leakage reset blanking cycle has ended), the rotation comparator signal from comparator 404 will remain low because the negative rotation detected at 609 continues. This means that a trough has not yet been detected at 611. In this case, the method is configured to continue searching for the trough by returning to 609, where monitoring for negative rotation continues. Eventually, the rotation comparator signal from comparator 404 changes from low to high in response to a negative rotation detected at 609 changing to zero voltage (no rotation) or a positive rotation, thus indicating the presence of a trough. This causes the trough detection signal generated by AND gate 406 to go high, meaning that a trough has been detected at 611.

[0098] When a trough is detected at 611, the method further includes determining at 613 whether the leakage filter has expired. As explained above, the leakage filter is configured to ensure that the detected trough has a sufficient amount of negative rotation time, because a false trough in the leakage ringing section can be detected before the leakage filter expires, while a true trough in the magnetized ringing section will be detected after the leakage filter expires. As described above relative to... Figure 4A , 5AAs further described in 5B, the expiration of the leakage filter can be determined, for example, by the logic of AND gate 410 of ZCD circuit 301. If the leakage filter at 613 has expired when the trough detection signal from AND gate 406 changes from low to high (indicating a positive trough at 611), then the filtered signal from the leakage filter at 408 will also be high at this time, thus making AND gate 410 high, thereby allowing a positive declaration of the trough. In this case, the method continues to 617, where the trough detected at 611 is declared a true trough. In this example, the declared trough is assigned a number X (e.g., 1st trough, 2nd trough, etc.) and can be one of a plurality of declared true troughs. This declaration at 617 can be made, for example, by the logic of OR gate 412, which receives the high signal generated by AND gate 410, which in turn makes the ZCD signal at the output of OR gate 412 high. The ZCD signal can be used by control circuit 105 in a trough switching control scheme.

[0099] However, if the trough detection signal from AND gate 406 changes from low to high as described above (indicating a positive trough at 611), but the leakage filter at 613 has not yet expired, then the filtered signal from the leakage filter at 408 will be low, thus causing AND gate 410 to go low, potentially suppressing a positive assertion of the trough. In this case, the method can perform another determination to see if the detected trough is still a true trough for other reasons. More detailed, and further reference... Figure 6 The method proceeds to 615, where it is determined whether the detected trough that occurred before the leakage filter expires has reached zero voltage (ZVD condition). If the trough detected at 611 does not achieve the ZVD condition, the method is configured to continue searching for the trough by returning to 609, where monitoring of negative rotation continues. However, if the trough detected at 611 achieves the ZVD condition, the method proceeds to 617, where the trough detected at 611 is declared a true trough.

[0100] As mentioned above, in contrast to Figure 4A , 5AAs further described in 5B, the determination at 615 whether the trough detected at 611 satisfies the ZVD condition can be made, for example, by combining the logic of, for example, AND gate 414 with ZVD circuit 305. Furthermore, the declaration at 617 can be made, for example, by the logic of, for example, OR gate 412. For instance, in some such instances, if the ZVD condition indicated by ZVD circuit 305 is true when the trough detection signal from AND gate 406 is high, then the output of AND gate 414 will be high, thereby indicating that the trough detected at 611 is a true trough. OR gate 412 receives the high signal generated by AND gate 414, which in turn causes the ZCD signal at the output of OR gate 412 to go high. However, if the ZVD condition indicated by ZVD circuit 305 is false when the trough detection signal from AND gate 406 is high, then the output of AND gate 414 will be low, thereby indicating that the trough detected at 611 is a false trough. OR gate 412 receives the low signal generated by AND gate 414, which in turn causes the ZCD signal at the output of OR gate 412 to go low (assuming the output of AND gate 410 is also low). As described above, the ZCD signal can be used by control circuit 105 in a trough switch control scheme. Further reference Figure 6 After declaring a true trough at 617, the method continues by incrementing the trough counter (X = X + 1) and is configured to look for the next trough by returning to 609, where monitoring of negative rotation continues.

[0101] Power System

[0102] Figure 7 A block diagram of a system 700, as shown in the example, includes a flyback power converter configured for trough sensing without the use of an auxiliary winding. As illustrated, system 700 includes a buffer 710, a flyback transformer 711, an EMI filter 715, a rectifier 717, an AC sensing circuit 718, a synchronous rectifier transistor QSR, a synchronous rectifier (SR) controller 720, an output capacitor COUT, an output transistor QOUT, a port 722, a feedback circuit 713 including a USB-PD controller 724 and an optocoupler 726, and a controller 728 including an IC 101. In this example, system 700 converts an AC input voltage (VAC) to a DC input voltage (VIN), which is then converted by the flyback power converter to a regulated DC output voltage (VOUT). VOUT is coupled to port 722, to which a load can be coupled. In other examples, the DC input voltage VIN is obtained directly, rather than from the AC input voltage VAC.

[0103] EMI filter 715 removes unwanted noise from the line voltage, rectifier 717 rectifies the AC input, and AC sensing circuit 718 allows controller 728 to detect the presence of VAC. Any suitable EMI filter, rectifier, and sensing circuit system can be used. Other examples may directly apply VIN instead of obtaining it from the AC source shown. In these cases, system 700 may not include VAC, EMI filter 115, rectifier 117, or AC sensing circuit 718. Transformer 711 allows energy storage, energy transfer, and current isolation between input VIN and output VOUT. Any suitable flyback transformer can be used. In this example, flyback transformer 111 does not include any auxiliary winding for trough sensing. Other examples may include one or more auxiliary windings, for example, to provide an alternative for trough detection and / or for providing overvoltage protection and / or bias power. Buffer 710 provides the clamping voltage VCLAMP and can be implemented by any suitable buffer circuit. QSR and SR controller 720 jointly provide a synchronous rectifier (not...) Figure 1 The DOUT in the topology can be used to improve the efficiency of flyback topologies.

[0104] Capacitor COUT is referenced above. Figure 1 The operation is similar to that described herein. In this example, port 722 is a type-C USB port, and controller 724 is a USB-PD controller. Other general-purpose and proprietary port technologies can be used. For example, if an overvoltage or high-current condition is detected, QOUT can be used to disconnect the load in response to the control of controller 724. Optocoupler 726 provides the feedback voltage VFB from the secondary to the primary in an isolated manner. Controller 728 can be implemented by any suitable flyback converter control circuitry and is further configured with IC 101, enabling controller 728 to perform trough switching without the use of an auxiliary winding based on the VSW signal received at the SW terminal, as described differently herein. In this example, controller 728 may further include a switching element coupled between SW and ground, and may also include sensing circuitry (e.g., Figure 1 (As shown in 109 and 108). In other instances, the switching elements (and sensing circuitry, if present) may be implemented externally to the controller 728.

[0105] Other examples

[0106] Example 1 is an apparatus comprising: a first logic circuit (e.g., 406) configured to blank a leakage reset portion of a switch terminal signal in response to a first blanking signal; a second logic circuit (e.g., 410) configured to blank a leakage ringing portion of the switch terminal signal in response to a second blanking signal; a third logic circuit (e.g., 414) configured to distinguish the leakage ringing portion of the switch terminal signal from a trough reaching zero volts in response to a zero-voltage detection (ZVD) signal, the trough being contained in a magnetized ringing portion of the switch terminal signal; and a fourth logic circuit (e.g., 412) configured to declare one or more troughs contained in the magnetized ringing portion of the switch terminal signal in response to inputs from the second and third logic circuits.

[0107] Example 2 includes the apparatus according to Example 1, and further includes a rotation detection circuit (e.g., 301) configured to detect rotation of a switch terminal signal.

[0108] Example 3 includes the apparatus according to Example 2, and further includes: a first threshold voltage (e.g., V1) that allows the slewing detection circuit to operate as a positive slewing detector; and a second threshold voltage (e.g., ground) that allows the slewing detection circuit to operate as a negative slewing detector.

[0109] Example 4 includes an apparatus according to any one of Examples 1 to 3, wherein: the first logic circuit includes an AND gate; the second logic circuit includes an AND gate; the third logic circuit includes an AND gate; and the fourth logic circuit includes an OR gate.

[0110] Example 5 includes an apparatus according to any one of Examples 1 to 3, wherein: the first logic circuit is an AND gate; the second logic circuit is an AND gate; the third logic circuit is an AND gate; and the fourth logic circuit is an OR gate.

[0111] Example 6 includes the apparatus according to any one of Examples 1 to 5, wherein the first blanking signal has a duration that varies based on the peak current of the power converter.

[0112] Example 7 includes the apparatus according to any one of Examples 1 to 6, wherein the second blanking signal has a fixed duration based on the signal period of the leakage ringing portion.

[0113] Example 8 includes the apparatus according to any one of Examples 1 to 7, and further includes a zero-voltage detection (ZVD) circuit configured to detect a trough reaching zero volts and generate a ZVD signal.

[0114] Example 9 is a system comprising: an apparatus according to any one of Examples 1 to 8; an input voltage terminal; an output voltage terminal; a switch terminal providing a switch terminal signal; a feedback terminal; a transformer having a primary winding and a secondary winding coupled between the input voltage terminal and the switch terminal; and a feedback circuit coupled between the output voltage terminal and the feedback terminal.

[0115] Example 10 is an apparatus comprising: a first circuit (e.g., 301) configured to receive a switching terminal signal of a flyback power converter, the first circuit further configured to detect a leakage reset portion of the switching terminal signal and detect one or more troughs of the switching terminal signal; a second circuit (e.g., 303) configured to generate a blanking signal at least partially corresponding to the leakage reset portion of the switching terminal signal; and a third circuit (e.g., 307) configured to receive the detection from the first circuit and the blanking signal from the second circuit, the third circuit further configured to blank the leakage reset portion of the switching terminal signal in response to the blanking signal and to distinguish troughs contained in a magnetized ringing portion of the switching terminal signal from troughs contained in a leakage ringing portion of the switching terminal signal.

[0116] Example 11 includes the apparatus according to Example 10, and further includes: a fourth circuit (e.g., 305) configured to generate a zero voltage detection (ZVD) signal in response to a trough contained in the magnetized ringing portion of the switch terminal signal reaching zero volts; wherein the third circuit is further configured to receive the ZVD signal from the fourth circuit and to distinguish the zero voltage trough contained in the magnetized ringing portion of the switch terminal signal from the trough contained in the leakage ringing portion of the switch terminal signal.

[0117] Example 12 includes the apparatus according to Example 11, wherein the fourth circuitry includes a comparator having a ZVD signal output coupled to the third circuitry, the comparator further having a first comparator input coupled to a switch terminal input via a bias circuitry and a second comparator input coupled to a negative voltage reference.

[0118] Example 13 includes an apparatus according to any one of Examples 10 to 12, wherein a third circuit is configured to assert a zero-current detection (ZCD) signal in response to a first and a second condition, the first condition comprising a trough detection performed after a negative slew cycle lasting at least one preset time period, and the second condition comprising a trough detection performed when the trough reaches zero volts.

[0119] Example 14 includes the apparatus according to Example 13, wherein the frequency of the leakage ringing portion is higher than the frequency of the magnetized ringing portion, and the preset time period is greater than the signal period associated with the leakage ringing portion.

[0120] Example 15 includes an apparatus according to any one of Examples 10 to 14, wherein the first circuitry includes: a switch terminal input; a comparator having first and second comparator inputs and a comparator output; and a sensor circuitry coupled between the switch terminal and the first comparator input, the sensor circuitry including a high-pass filter and a voltage clamp.

[0121] Example 16 includes the apparatus according to Example 15, wherein a second comparator input is switchably coupled to each of a first threshold voltage and a second threshold voltage, and wherein the first threshold voltage allows the first circuitry to operate as a positive rotation detector configured to detect a leakage reset portion of a switch terminal signal, and the second threshold voltage allows the first circuitry to operate as a negative rotation detector configured to detect one or more troughs of a switch terminal signal.

[0122] Example 17 includes an apparatus according to any one of Examples 10 to 16, wherein the second circuitry includes: a variable blanking delay circuit having a blanking signal output coupled to a third circuitry, the variable blanking delay circuitry further including a blanking control input; a trigger having a timing input coupled to the output of the first circuitry and a trigger output coupled to the variable blanking delay circuitry; a first switch coupled between a first threshold voltage terminal and a threshold voltage input of the first circuitry, the first switch having a control input coupled to the trigger output; and a second switch coupled between a second threshold voltage terminal and the threshold voltage input of the first circuitry, the second switch having a control input coupled to the trigger output via an inverter.

[0123] Example 18 includes the apparatus according to Example 17, wherein the inverter is a first inverter, and the second circuitry further includes a second inverter coupled between the trigger timing input and the first circuitry output.

[0124] Example 19 includes the apparatus according to Example 17 or 18, wherein the second circuitry further includes a drive signal input coupled to a reset input of a flip-flop.

[0125] Example 20 is an apparatus comprising: a slewing detection circuit having a switching terminal input and further comprising a comparator having a threshold voltage input and a comparator output; a zero-current detection circuit having an input coupled to the comparator output and further comprising a blanking signal input and a zero-current detection (ZCD) signal output; a first threshold voltage switchably coupled to the threshold voltage input of the comparator; a second threshold voltage switchably coupled to the threshold voltage input of the comparator; and an adaptive blanking circuit having a timing input terminal coupled to the comparator output and further comprising a blanking signal output coupled to the blanking signal input of the zero-current detection circuit.

[0126] Example 21 includes the apparatus according to Example 20, wherein the zero current detection circuit further includes a zero voltage detection (ZVD) signal input, and the apparatus further includes: a zero voltage detection circuit having an input coupled to a switch terminal input of a slewing detection circuit, and an output coupled to the ZVD signal input of the zero current detection circuit.

[0127] Example 22 includes the apparatus according to Example 21, wherein the comparator of the gyration detection circuit is a first comparator, and the zero-voltage detection circuit further includes: a second comparator having an output coupled to the output of the zero-voltage detection circuit, the second comparator further having a first input coupled to a switch terminal input of the gyration detection circuit via a bias circuit, and a second input coupled to a negative voltage reference.

[0128] Example 23 includes an apparatus according to any one of Examples 20 to 22, wherein the adaptive blanking circuit further includes a variable blanking delay circuit having an output coupled to a blanking signal output, and the variable blanking delay circuit further includes a blanking control input.

[0129] Example 24 includes the apparatus according to Example 23, wherein the adaptive blanking circuit further includes: a flip-flop coupled to a timing input and having a flip-flop output coupled to a variable blanking delay circuit; a first switch coupled between a first threshold voltage and a threshold voltage input of a comparator, the first switch having a control input coupled to the flip-flop output; and a second switch coupled between a second threshold voltage and a threshold voltage input of a comparator, the second switch having a control input coupled to the flip-flop output via an inverter.

[0130] Example 25 includes the apparatus according to Example 24, wherein the inverter is a first inverter and the trigger is coupled to the timing input via a second inverter.

[0131] Example 26 includes an apparatus according to any one of Examples 20 to 25, wherein the adaptive blanking circuit further includes a drive signal input coupled to a reset input of a flip-flop.

[0132] Example 27 includes the apparatus according to any one of Examples 20 to 26, wherein the threshold voltage input of the comparator is a first input of the comparator, and the rotation detection circuit further includes: a sensor circuit coupled between a switch terminal input and a second input of the comparator, the sensor circuit including a resistor-capacitor filter and a voltage clamp; and a current source coupled between a power supply terminal and the second input of the comparator.

[0133] Example 28 includes the apparatus according to any one of Examples 20 to 27, wherein the zero-current detection circuit further includes: a first AND gate having a first input and a second input coupled to a comparator output and a blanking signal input, respectively, and an output; a leakage filter having an input coupled to the output of the first AND gate, and an output; and a second AND gate having a first input and a second input coupled to the output of the first AND gate and the output of the leakage filter, respectively.

[0134] Example 29 includes the apparatus according to Example 28, and further includes: a zero-voltage detection circuit having an input coupled to a switch terminal input of a rotation detection circuit, and an output. In some such examples, the zero-current detection circuit further includes: a third AND gate having a first input and a second input coupled to the output of a first AND gate and the output of the zero-voltage detection circuit, respectively, and an output; and an OR gate having a first input and a second input coupled to the output of a second AND gate and the output of a third AND gate, respectively, and an output coupled to the ZCD signal output.

[0135] Example 30 is a method comprising: receiving a switch terminal signal, the switch terminal signal including a leakage reset portion, a leakage ringing portion, and a magnetized ringing portion; detecting a positive rotation of the leakage reset portion; generating a blanking signal to blank the leakage reset portion; and detecting a negative rotation of the switch terminal signal. In response to detecting a trough in the switch terminal signal, the method further comprises: declaring a trough if a leakage filter has expired, the leakage filter having a period longer than the period of the leakage ringing portion of the switch terminal signal, or declaring a trough if the detected trough has reached zero volts.

[0136] Example 31 includes the method according to Example 30, wherein in response to the detected trough not having reached zero volts, the method includes not declaring the trough.

[0137] Example 32 includes the method according to Example 30 or 31, wherein the duration of the blanking signal is based on the peak current through the primary winding of the flyback converter.

[0138] Example 33 includes the method according to any one of Examples 30 to 32, and further includes: repeating the method forward from detecting a negative rotation of the switch terminal signal for one or more additional troughs contained in the magnetized ringing portion of the switch terminal signal.

[0139] Example 34 includes the method according to any one of Examples 30 to 33, wherein declaring a trough when the leakage filter has expired includes: determining whether the leakage filter has expired before declaring the trough; and declaring the trough in response to the leakage filter having expired.

[0140] Example 35 includes the method according to any one of Examples 30 to 34, wherein declaring a trough when the detected trough has reached zero volts includes: determining whether the detected trough has reached zero volts; and declaring a trough in response to the detected trough having reached zero volts.

[0141] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0142] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. This configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.

[0143] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0144] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0145] While the use of specific transistors is described herein, other transistors (or equivalent devices) can be used alternatively. For example, a p-channel field-effect transistor (PFET) can be used instead of an n-channel field-effect transistor (NFET) with little or no change to the circuit. Furthermore, other types of transistors (such as bipolar junction transistors (BJTs)) can be used. Additionally, the device can be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate, to name just a few.

[0146] In this article, "FET" being "on" means that there is a conduction channel in the FET and drain current can flow through it. "FET" being "off" means that there is no conduction channel and drain current does not flow through it. However, an off-state FET can still have current flowing through its body diode.

[0147] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. In another instance, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0148] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of said parameter.

[0149] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An apparatus comprising: A first logic circuit configured to blank the leakage reset portion of the switch terminal signal in response to a first blanking signal; A second logic circuit is configured to blank the leakage ringing portion of the switch terminal signal in response to a second blanking signal; A third logic circuit is configured to distinguish the leakage ringing portion of the switch terminal signal from the trough reaching zero volts in response to a zero-voltage detection (ZVD) signal, the trough being contained in the magnetized ringing portion of the switch terminal signal. as well as A fourth logic circuit configured to declare one or more troughs contained in the magnetized ringing portion of the switch terminal signal in response to inputs from the second and third logic circuits.

2. The apparatus of claim 1, further comprising a rotation detection circuit configured to detect rotation of the switch terminal signal.

3. The apparatus according to claim 2, further comprising: A first threshold voltage, which allows the slewing detection circuit to operate as a forward slewing detector; as well as A second threshold voltage allows the slewing detection circuit to operate as a negative slewing detector.

4. The apparatus according to claim 1, wherein: The first logic circuit includes an AND gate; The second logic circuit includes an AND gate; The third logic circuit includes an AND gate; and The fourth logic circuit includes an OR gate.

5. The apparatus of claim 1, wherein the first blanking signal has a duration that varies based on the peak current of the power converter.

6. The apparatus of claim 1, wherein the second blanking signal has a fixed duration based on the signal period of the leaking ringing portion.

7. The apparatus of claim 1, further comprising a zero-voltage detection circuit configured to detect the trough reaching zero volts and generate the ZVD signal.

8. A system comprising: The apparatus according to claim 1; Input voltage terminals; Output voltage terminals; A switch terminal, at which the switch terminal signal is provided; Feedback terminal; A transformer having a primary winding and a secondary winding, the primary winding being coupled between the input voltage terminal and the switching terminal; as well as A feedback circuit is coupled between the output voltage terminal and the feedback terminal.

9. An apparatus comprising: A slewing detection circuit having a switch terminal input and further including a comparator having a threshold voltage input and a comparator output; A zero-current detection circuit having an input coupled to the comparator output, and further including a blanking signal input and a zero-current detection ZCD signal output; A first threshold voltage, which is switchably coupled to the threshold voltage input of the comparator; A second threshold voltage, which is switchably coupled to the threshold voltage input of the comparator; as well as An adaptive blanking circuit has a timing input terminal coupled to the comparator output and further includes a blanking signal output coupled to the blanking signal input of the zero current detection circuit.

10. The apparatus of claim 9, wherein the zero-current detection circuit further comprises a zero-voltage detection (ZVD) signal input, and the apparatus further comprises: A zero-voltage detection circuit having an input coupled to the switch terminal input of the slewing detection circuit and an output coupled to the ZVD signal input of the zero-current detection circuit.

11. The apparatus of claim 10, wherein the comparator of the rotation detection circuit is a first comparator, and the zero-voltage detection circuit further comprises: A second comparator having an output coupled to the output of the zero-voltage detection circuit, the second comparator further having a first input coupled to the switch terminal input of the gyration detection circuit via a bias circuit, and a second input coupled to a negative voltage reference.

12. The apparatus of claim 9, wherein the adaptive blanking circuit further comprises a variable blanking delay circuit having an output coupled to the blanking signal output, and the variable blanking delay circuit further comprises a blanking control input.

13. The apparatus of claim 12, wherein the adaptive blanking circuit further comprises: A flip-flop coupled to the timing input and having a flip-flop output coupled to the variable blanking delay circuit; A first switch is coupled between the first threshold voltage and the threshold voltage input of the comparator, and the first switch has a control input coupled to the output of the trigger. as well as A second switch is coupled between the second threshold voltage and the threshold voltage input of the comparator, and the second switch has a control input coupled to the output of the trigger via an inverter.

14. The apparatus of claim 13, wherein the inverter is a first inverter and the trigger is coupled to the timing input via a second inverter.

15. The apparatus of claim 9, wherein the adaptive blanking circuit further includes a drive signal input coupled to a reset input of the flip-flop.

16. The apparatus of claim 9, wherein the threshold voltage input of the comparator is a first input of the comparator, and the slewing detection circuit further comprises: A sensor circuit, coupled between the switch terminal input and the second input of the comparator, includes a resistor-capacitor filter and a voltage clamp; and A current source is coupled between the power supply terminal and the second input of the comparator.

17. The apparatus of claim 9, wherein the zero-current detection circuit further comprises: A first AND gate has a first input and a second input, respectively coupled to the comparator output and the blanking signal input, and an output; A leakage filter having an input coupled to the output of the first AND gate, and an output; and The second AND gate has a first input and a second input respectively coupled to the output of the first AND gate and the output of the leakage filter.

18. The apparatus of claim 17, further comprising: A zero-voltage detection circuit having an input coupled to the switch terminal input of the rotation detection circuit, and an output; The zero-current detection circuit further includes A third AND gate has a first input and a second input, respectively coupled to the output of the first AND gate and the output of the zero-voltage detection circuit, and an output; and An OR gate having a first input and a second input coupled to the output of a second AND gate and the output of a third AND gate, respectively, and an output coupled to the output of the ZCD signal.

19. A method comprising: Receives a switch terminal signal, the switch terminal signal including a leakage reset part, a leakage ringing part, and a magnetization ringing part; Detect the forward rotation of the leakage reset section; A blanking signal is generated to blank the leakage reset section; Detecting the negative rotation of the switch terminal signal; and In response to the detection of a trough in the signal at the switch terminal, A trough is declared when the leakage filter has expired, wherein the leakage filter has a period longer than the period of the leakage ringing portion of the switch terminal signal, or A trough is declared when the detected trough has reached zero volts.

20. The method of claim 19, wherein: The valley is declared to contain the condition that the leakage filter has expired. Before declaring the trough, determine whether the leakage filter has expired, and In response to the leakage filter having expired, a trough is declared; and The valley is declared to contain voltages when the detected valley has reached zero volts. Determine whether the detected trough reaches zero volts, and In response to the detected trough reaching zero volts, a trough is declared.

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