A circuit to reduce PMOSFET leakage current

Abstract

This invention discloses a circuit for reducing PMOSFET leakage current, belonging to the field of semiconductor technology. It includes: a PMOSFET testing circuit and an adaptive leakage current bias circuit; the PMOSFET testing circuit includes a test PMOSFET transistor and a test resistor; the test resistor is connected between the source and substrate of the test PMOSFET transistor; the adaptive leakage current bias circuit adjusts the current based on the voltage V output from the substrate of the test PMOSFET transistor. ctrl Perform adaptive voltage regulation to generate bias voltage V B(P) ; the bias voltage V B(P) This invention reduces the leakage current of a PMOSFET by inputting its substrate. The leakage current is detected through testing the PMOSFET, and an adaptive leakage current bias circuit is used to adjust the PMOSFET substrate in the integrated circuit. This reduces the leakage current without increasing the on-resistance, achieving a simple and efficient solution.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a circuit for reducing leakage current of a PMOSFET. Background Technology

[0002] Field-effect transistors (MOSFETs) are essential components in modern electronic circuits and are widely used. However, their leakage current can negatively impact circuit performance. Therefore, suppressing MOSFET leakage current has always been a goal in the integrated circuit field, especially important in low-nanometer, large-scale integrated circuits. MOSFET leakage current refers to the current leakage caused by the MOSFET in the off state. Its causes are mainly twofold: first, reverse breakdown of the PN junction, including avalanche breakdown and Zener breakdown; second, the tunneling effect, a quantum effect that can induce PN junction current. Both of these factors lead to an increase in the leakage current of MOSFET devices.

[0003] To reduce MOSFET leakage current, the industry has proposed some feasible methods, such as introducing high dielectric constant materials or optimizing the structure, but these methods will lead to an increase in on-resistance. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention reduces the leakage current of PMOSFETs by adjusting the substrate bias voltage.

[0005] To achieve the above objectives, the present invention provides a circuit for reducing PMOSFET leakage current, comprising: a PMOSFET testing circuit and an adaptive leakage current biasing circuit;

[0006] The test PMOSFET circuit includes a test PMOSFET transistor and a test resistor; the test resistor is connected between the source and substrate of the test PMOSFET transistor; the adaptive leakage current bias circuit is based on the voltage V output from the substrate of the test PMOSFET transistor. ctrl Perform adaptive voltage regulation to generate bias voltage V B(P) ; the bias voltage V B(P) Input the substrate of the PMOSFET whose leakage current needs to be reduced, and thus reduce the leakage current of the PMOSFET;

[0007] The adaptive leakage current bias circuit includes: a pulse generator, an operational amplifier OPA1, a buffer, a charge pump circuit, a current source, a first inverter, a second inverter, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fourth capacitor C4. The output of the pulse generator is connected to one end of the fourth resistor R4 and the buffer. The other end of the fourth resistor R4 is connected to the first inverter and the second inverter in sequence. The output of the buffer, as well as the outputs of the first and second inverters, are input to the charge pump circuit. The output of the charge pump circuit is the bias voltage V. B(P) The first resistor R1 and the second resistor R2 are connected in sequence and then grounded; the positive input terminal of the operational amplifier OPA1 is connected to the junction of the first resistor R1 and the second resistor R2; its negative input terminal is connected to the voltage V output from the substrate of the test PMOSFET. ctrl Its output terminal controls the current source through an RC filter circuit consisting of the third resistor R3 and the fourth capacitor C4. The output terminal of the operational amplifier OPA1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth capacitor C4, which is also connected to the control terminal of the current source. The other end of the fourth capacitor C4 is grounded. The current source is connected between the connection point of the fourth resistor R4 and the first inverter and ground.

[0008] Furthermore, the charge pump circuit includes a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, a first capacitor C1, a second capacitor C2, and a third capacitor C3;

[0009] The output of the buffer is connected to the gate of the second MOSFET Q2 and the gate of the fourth MOSFET Q4; the output of the first inverter is connected to the gate of the first MOSFET Q1; and the output of the second inverter is connected to the gate of the third MOSFET Q3. The source of the first MOSFET Q1 is connected to the power supply voltage V. DD Simultaneously, the source of the third MOSFET Q3 is connected to ground via the second capacitor C2; the drain of the first MOSFET Q1 is connected to the drain of the second MOSFET Q2, and the drain of the third MOSFET Q3 and the drain of the fourth MOSFET Q4 are connected via the first capacitor C1; the source of the fourth MOSFET Q4 is connected to the power supply voltage V. DD The source of the second MOSFET Q2 is grounded through the third capacitor C3, which serves as the bias voltage V. B(P) Output.

[0010] Furthermore, the first MOSFET Q1 and the fourth MOSFET Q4 are PMOSFETs, and the second MOSFET Q2 and the third MOSFET Q3 are NMOSFETs.

[0011] The beneficial effects of this invention are:

[0012] This invention uses a test PMOSFET to detect leakage current and adjusts the PMOSFET substrate in the integrated circuit according to the detection result through an adaptive leakage current bias circuit to reduce the leakage current of the PMOSFET. This can reduce the leakage current without increasing the on-resistance, achieving simplicity and high efficiency. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the circuit structure for reducing PMOSFET leakage current according to an embodiment of the present invention.

[0014] Figure 2 This is a schematic diagram of a PMOSFET circuit according to an embodiment of the present invention.

[0015] Figure 3 This is a schematic diagram of a digital circuit unit with bias voltage according to an embodiment of the present invention. Detailed Implementation

[0016] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0017] like Figure 1 As shown, this embodiment of the invention provides a circuit for reducing PMOSFET leakage current, including: a PMOSFET test circuit and an adaptive leakage current bias circuit.

[0018] The PMOSFET test circuit includes a test PMOSFET Q5 and a test resistor R5, with the test resistor R5 connected between the source and the substrate of the test PMOSFET Q5.

[0019] like Figure 2 As shown, the substrate voltage control principle of PMOSFET is as follows:

[0020] In a MOSFET, electrons in the channel generate electron-hole pairs in the drain depletion region through lattice collisions. Some of the holes flow to the substrate to form a substrate current, while the electrons flow to the drain. This is equivalent to a controlled current source connected in series from the drain to the substrate. The order of magnitude of the substrate current depends on the voltage drop across the drain depletion region and the drain current.

[0021] Taking a P-channel enhancement-mode MOSFET as an example, its threshold voltage With substrate bias voltage That is, the voltage between the substrate and the source, the source voltage. Relatively fixed, The more negative, The value increases as the positive value increases, and the relationship is as follows:

[0022]

[0023] in: The threshold voltage at zero bias. The volume effect coefficient (related to device manufacturing process). The Fermi potential (depends on the substrate doping concentration).

[0024] At the same time, according to:

[0025]

[0026]

[0027] It can be seen that, I D The larger, I DB The larger.

[0028] in: I D Leakage current; This is the gate-source voltage; For electron mobility, The capacitance per unit area of ​​the gate oxide layer reflects the conductivity of the material, while W / L is the gate aspect ratio, which affects the current density. I DB Substrate current; K 1. K 2 represents the process parameters; V DS This is the drain-source voltage; V DS(act) Minimum required for transistors to enter the amplification region V DS (i.e., the threshold voltage at which the current effect begins to be significant).

[0029] Therefore, this embodiment of the invention utilizes the above principle to add a test resistor between the source and substrate of the PMOSFET to obtain the voltage V output from the substrate. ctrl V ctrl An adaptive leakage current bias circuit is used to perform adaptive voltage regulation, adjusting the input voltage V. DD The substrate bias voltage V required to convert to PMOSFET B(P) .

[0030] The adaptive leakage current bias circuit includes: a pulse generator, an operational amplifier OPA1, a buffer, a charge pump circuit, a current source, a first inverter, a second inverter, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fourth capacitor C4.

[0031] The output of the pulse generator is connected to one end of the fourth resistor R4 and the buffer; the other end of the fourth resistor R4 is connected to the first inverter and the second inverter in sequence; the output of the buffer, as well as the outputs of the first inverter and the second inverter, are input to the charge pump circuit; the output of the charge pump circuit is the bias voltage V. B(P) The first resistor R1 and the second resistor R2 are connected in sequence and then grounded; the positive input terminal of the operational amplifier OPA1 is connected to the junction of the first resistor R1 and the second resistor R2; its negative input terminal is connected to the voltage V output from the substrate of the test PMOSFET Q5. ctrl Its output terminal controls the current source through an RC filter circuit consisting of the third resistor R3 and the fourth capacitor C4. The output terminal of the operational amplifier OPA1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth capacitor C4, which is also connected to the control terminal of the current source. The other end of the fourth capacitor C4 is grounded. The current source is connected between the connection point of the fourth resistor R4 and the first inverter and ground.

[0032] The charge pump circuit includes a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0033] The output of the buffer is connected to the gates (G2) of the second MOSFET Q2 and the fourth MOSFET Q4. The output of the first inverter is connected to the gate (G1) of the first MOSFET Q1, and the output of the second inverter is connected to the gate of the third MOSFET Q3. The source of the first MOSFET Q1 is connected to the power supply voltage V. DD Simultaneously, the source of the third MOSFET Q3 is connected to ground via the second capacitor C2; the drain of the first MOSFET Q1 is connected to the drain of the second MOSFET Q2, and the drain of the third MOSFET Q3 and the drain of the fourth MOSFET Q4 are connected via the first capacitor C1; the source of the fourth MOSFET Q4 is connected to the power supply voltage V. DD The source of the second MOSFET Q2 is grounded through the third capacitor C3, which also serves as the bias voltage V. B(P) Output.

[0034] Bias voltage V B(P) Input the substrate of the PMOSFET that needs to have reduced leakage current to achieve the reduction of PMOSFET leakage current.

[0035] like Figure 3 As shown, V B(P) The substrate of the PMOSFET, which needs to reduce leakage current when fed into the digital circuit unit, significantly reduces the leakage current of the PMOSFET compared to traditional digital circuit units.

[0036] The working principle of this invention embodiment is as follows:

[0037] Using the test resistor R5, the substrate voltage V of the test PMOSFET Q5 is obtained. ctrl V ctrl Due to leakage current I DB Dynamic control, I DB The larger V is ctrl The smaller. V ctrl The charge pump's output voltage is controlled by the RC filter circuit composed of R3 and C4, which controls the current source. This current source, along with the PWM pulse signal output from the pulse generator, adjusts the signal frequency of the gates of each MOSFET in the charge pump, thus achieving the charge pump's output voltage regulation function. Ultimately, the input voltage V of the charge pump is... DD The substrate bias voltage required to be converted into a PMOSFET This reduces the leakage current of the PMOSFET.

[0038] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and various changes or modifications can be made to these embodiments without departing from the principles and essence of the present invention.

Claims

1. A circuit for reducing PMOSFET leakage current, characterized in that, include: Test the PMOSFET circuit and the adaptive leakage current bias circuit; The test PMOSFET circuit includes a test PMOSFET transistor and a test resistor; The test resistor is connected between the source and substrate of the PMOSFET being tested; the adaptive leakage current bias circuit is based on the voltage V output from the substrate of the PMOSFET being tested. ctrl Perform adaptive voltage regulation to generate bias voltage V B(P) ; the bias voltage V B(P) Input the substrate of the PMOSFET whose leakage current needs to be reduced, and thus reduce the leakage current of the PMOSFET; The adaptive leakage current bias circuit includes: a pulse generator, an operational amplifier OPA1, a buffer, a charge pump circuit, a current source, a first inverter, a second inverter, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fourth capacitor C4. The output of the pulse generator is connected to one end of the fourth resistor R4 and the buffer. The other end of the fourth resistor R4 is connected to the first inverter and the second inverter in sequence. The output of the buffer, as well as the outputs of the first and second inverters, are input to the charge pump circuit. The output of the charge pump circuit is the bias voltage V. B(P) The first resistor R1 and the second resistor R2 are connected in sequence and then grounded; the positive input terminal of the operational amplifier OPA1 is connected to the junction of the first resistor R1 and the second resistor R2; its negative input terminal is connected to the voltage V output from the substrate of the test PMOSFET. ctrl Its output terminal controls the current source through an RC filter circuit consisting of the third resistor R3 and the fourth capacitor C4. The output terminal of the operational amplifier OPA1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth capacitor C4, which is also connected to the control terminal of the current source. The other end of the fourth capacitor C4 is grounded. The current source is connected between the connection point of the fourth resistor R4 and the first inverter and ground.

2. The circuit for reducing PMOSFET leakage current according to claim 1, characterized in that: The charge pump circuit includes a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, a first capacitor C1, a second capacitor C2, and a third capacitor C3; The output of the buffer is connected to the gate of the second MOSFET Q2 and the gate of the fourth MOSFET Q4; the output of the first inverter is connected to the gate of the first MOSFET Q1; and the output of the second inverter is connected to the gate of the third MOSFET Q3. The source of the first MOSFET Q1 is connected to the power supply voltage V. DD Simultaneously, the source of the third MOSFET Q3 is connected to ground via the second capacitor C2; the drain of the first MOSFET Q1 is connected to the drain of the second MOSFET Q2, and the drain of the third MOSFET Q3 and the drain of the fourth MOSFET Q4 are connected via the first capacitor C1; the source of the fourth MOSFET Q4 is connected to the power supply voltage V. DD The source of the second MOSFET Q2 is grounded through the third capacitor C3, which serves as the bias voltage V. B(P) Output.

3. The circuit for reducing PMOSFET leakage current according to claim 2, characterized in that: The first MOSFET Q1 and the fourth MOSFET Q4 are PMOSFETs, and the second MOSFET Q2 and the third MOSFET Q3 are NMOSFETs.

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