A shielded gate trench power semiconductor device and a method of manufacturing the same

Abstract

The application provides a shield gate trench power semiconductor device and a preparation method thereof, and belongs to the technical field of power semiconductors, comprising a first gate, a source electrode and a drain electrode, and further comprising: a second gate connected to an external circuit control unit; a polycrystalline resistor connected between the first gate and the second gate; a trigger channel connected between the drain electrode and the first gate, and the breakdown voltage of the trigger channel is less than the breakdown voltage of the device. Advantageous effects: when a surge event occurs, the trigger channel first breaks down, and the surge current is discharged to the ground through the polycrystalline resistor and the external circuit control unit; at the same time, the voltage drop generated by the current on the polycrystalline resistor acts on the first gate, and when the voltage drop is greater than the threshold voltage of the device, the device is turned on, and the subsequent surge current is discharged to the ground, so that the surge protection function and the anti-burning function of the device itself are integrated on the same chip, one core is used for multiple purposes, the chip area is saved, the packaging size is reduced, and the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a shielded gate trench type power semiconductor device and its fabrication method. Background Technology

[0002] Mobile devices such as smartphones are an indispensable part of people's lives. Over time and with prolonged use, moisture-containing dust inevitably accumulates inside the charging ports of these devices, easily causing short-circuit contact failures. Especially under high-current charging conditions, contact failures will cause the charging port temperature to rise sharply, damaging the charging port and surrounding circuits, and even posing a risk of serious safety accidents such as fires.

[0003] To address this issue, the industry currently widely employs negative temperature coefficient (NTC) thermistors to monitor the charging port temperature in real time. When an excessively high temperature is detected, the NTC sensor transitions from a blocking state to a low-resistance state. Subsequently, the analog-to-digital converter (ADC) converts the analog signal into a digital signal, causing the central processing unit (CPU) to output a high level, thereby turning on the metal-oxide-semiconductor field-effect transistor (MOSFET). Once the MOSFET is turned on, it shorts the VBUS bus power supply port to ground, using a sufficiently large short-circuit current to trigger the charger / adapter's overcurrent protection (OCP) operation, thereby cutting off the charging current and protecting the downstream charging integrated circuit (Charger IC).

[0004] With the continuous innovation of charging technology, high-voltage, high-current fast charging technology has gradually become the mainstream trend. However, in daily use, some improper operations can easily lead to abnormal output voltage at the VBUS bus power port. If the abnormal voltage exceeds the tolerance value of the internal chip, it will cause irreversible damage to the chip and seriously affect the normal use of the device. Therefore, in port protection design, a bidirectional transient voltage suppressor (TVS) is usually connected in parallel at the VBUS bus power port to prevent large surges from damaging subsequent sensitive components. The basic structure of traditional TVS devices is composed of a PN junction, which can resist the risks caused by abnormal voltage to a certain extent.

[0005] Currently, the widely adopted protection scheme circuit topology in the industry is as follows: Figure 1 As shown, the surge-protected TVS device and the MOSFET device with heat-resistant function are designed independently and used in separate packages. This design increases the cost of use, occupies a large amount of motherboard space, and is not conducive to the development of miniaturization and integration of equipment, thus limiting the performance improvement and market competitiveness of the product to a certain extent. Summary of the Invention

[0006] To address the above technical problems, this invention provides a shielded gate trench power semiconductor device; furthermore, it also provides a method for fabricating a shielded gate trench power semiconductor device.

[0007] The technical problem solved by this invention can be achieved by the following technical solution: A shielded gate trench power semiconductor device, comprising a first gate, a source, and a drain, further comprising: a second gate, the second gate being connected to an external circuit control unit for receiving a first control signal; a polycrystalline resistor formed between the first gate and the second gate, for generating a second control signal at the first gate based on a voltage drop across the polycrystalline resistor generated by at least one of the first control signal and a surge current, so as to control the on / off state of the shielded gate trench power semiconductor device according to the second control signal; a trigger channel formed between the drain and the first gate, the breakdown voltage of the trigger channel being less than the device breakdown voltage, for discharging the surge current from the drain sequentially through the trigger channel, the polycrystalline resistor, and the external circuit control unit to ground when the surge voltage of the drain exceeds the breakdown voltage of the trigger channel but does not exceed the device breakdown voltage.

[0008] Preferably, it further includes: an electrostatic discharge (ESD) protection diode, which is connected between the second gate and the source, and the ESD protection diode is a bidirectional ESD protection diode.

[0009] Preferably, the device further includes: a substrate of a first conductivity type, the substrate including at least a cell region and a peripheral region located around the cell region; an epitaxial layer of the first conductivity type formed on the upper surface of the substrate; a plurality of shielding gate trenches formed in the epitaxial layer, each of the shielding gate trenches having a shielding gate polysilicon layer and a first gate polysilicon layer of the first conductivity type; a second polysilicon layer of the second conductivity type formed in the first gate polysilicon layer of the peripheral region, and the second polysilicon layer of the second conductivity type and the first gate polysilicon layer of the first conductivity type are alternately arranged to form a diode string as the electrostatic discharge protection diode.

[0010] Preferably, it further includes: a body region of a second conductivity type formed in the epitaxial layer; an implantation region of a first conductivity type formed in the body region; and a first via implantation region of the second conductivity type formed below the implantation region.

[0011] Preferably, it further includes: a deep well region of a first conductivity type formed in the epitaxial layer, and the deep well region being located below the body region of the peripheral region; a second via injection region of the first conductivity type formed in the body region above the deep well region, and the second via injection region being located below the injection region; the first via injection region being formed in the remaining body regions except for the body region above the deep well region.

[0012] Preferably, it further includes: a buried layer of a second conductivity type, formed on at least a portion of the upper surface of the substrate, the epitaxial layer being located on the upper surfaces of the substrate and the buried layer; the buried layer being located below the shielding gate trench where the polycrystalline resistor is located, and the shielding gate trench adjacent to the shielding gate trench where the polycrystalline resistor is located extending into the buried layer in the direction of the buried layer; a first via injection region above the buried layer being formed in the epitaxial layer, and other first via injection regions besides the first via injection region above the buried layer being formed in the body region.

[0013] Preferably, the device further includes: a dielectric layer formed on the upper surface of the epitaxial layer, wherein a plurality of contact holes are etched in the dielectric layer, the plurality of contact holes including a first gate lead-out corresponding to the first gate polysilicon layer of the cell region, a second gate lead-out corresponding to the first gate polysilicon layer of the peripheral region, a shielding gate lead-out corresponding to the shielding gate polysilicon layer, and a plurality of source lead-out corresponding to the implantation region; a front metal layer formed on the upper surface of the dielectric layer and filling the contact holes, the front metal layer including a first gate metal region, a second gate metal region, and a source metal region, wherein the first gate metal region is in ohmic contact with the first gate polysilicon layer of the cell region, the second gate metal region is in ohmic contact with the first gate polysilicon layer of the peripheral region, and the source metal region is in ohmic contact with the shielding gate polysilicon layer and the implantation region; and a back metal layer formed on the lower surface of the substrate, the back metal layer serving as the device drain.

[0014] Preferably, the polysilicon resistor is the resistor formed by the first gate polysilicon layer between the first gate lead-out and the second gate lead-out.

[0015] Preferably, the resistance of the polycrystalline resistor is 200Ω~1000Ω.

[0016] On the other hand, a method for fabricating a shielded gate trench power semiconductor device is also provided. This method involves fabricating the shielded gate trench power semiconductor device as described above, the device including a first gate, a source, and a drain. The method includes: forming a second gate to receive a first control signal from an external circuit control unit; forming a polycrystalline resistor between the first gate and the second gate; generating a second control signal at the first gate based on a voltage drop across the polycrystalline resistor caused by at least one of the first control signal and a surge current, to control the on / off state of the shielded gate trench power semiconductor device according to the second control signal; forming a trigger channel between the drain and the first gate, the breakdown voltage of the trigger channel being less than the device breakdown voltage, so that when the surge voltage of the drain exceeds the breakdown voltage of the trigger channel but does not exceed the device breakdown voltage, the surge current is discharged from the drain sequentially through the trigger channel, the polycrystalline resistor, and the external circuit control unit to ground.

[0017] The advantages or beneficial effects of the technical solution of this invention are as follows: By adding a second gate and forming a polycrystalline resistor between the second gate and the first gate, and forming a trigger channel between the drain and the first gate, when a surge event occurs, since the breakdown voltage of the trigger channel is less than the drain-source breakdown voltage of the device itself, the trigger channel breaks down first, and the surge current is discharged to ground through the polycrystalline resistor and the external circuit control unit; at the same time, the voltage drop generated by the current on the polycrystalline resistor acts on the first gate. When the voltage drop is greater than the device threshold voltage, the device conducts, and the subsequent surge current is discharged to ground through the conducting device, thereby realizing the surge discharge function. Thus, the surge protection function and the device's own burn-out prevention function are integrated into the same chip, achieving the effect of one chip for multiple uses, saving chip area, reducing package size, reducing cost, and improving the market competitiveness of the product. Attached Figure Description

[0018] Figure 1 This is a circuit topology diagram for port protection in the prior art;

[0019] Figure 2 The equivalent circuit diagram of the shielded gate trench power semiconductor device in the preferred embodiment 1 of the present invention;

[0020] Figure 3 This is a schematic diagram of the front structure of a shielded gate trench power semiconductor device in a preferred embodiment 1 of the present invention;

[0021] Figure 4 This is a schematic diagram of the back structure of a shielded gate trench power semiconductor device in a preferred embodiment 1 of the present invention;

[0022] Figure 5 This is a schematic diagram of the layout structure of a shielded gate trench power semiconductor device in a preferred embodiment 1 of the present invention;

[0023] Figure 6-11 This is a schematic diagram of the structure of each step in the fabrication method of the shielded gate trench power semiconductor device in a preferred embodiment 1 of the present invention;

[0024] Figure 12 A waveform comparison of surge clamping voltage and discharge current of a conventional TVS and a shielded gate trench power semiconductor device in the preferred embodiment 1 of the present invention;

[0025] Figure 13 This is a front view of the shielded gate trench power semiconductor device in a preferred embodiment 2 of the present invention.

[0026] Explanation of reference numerals in the attached figures: 1. Polysilicon resistor; 2. Trigger channel; 3. Electrostatic discharge diode; 101. Substrate; 102. Epitaxial region; 103. Shielding gate polysilicon layer; 104. First gate polysilicon layer; 105. Body region; 106. Deep well region; 107. Field oxide layer; 108. First via implantation region; 109. Implantation region; 110. Contact hole; 1101. First gate lead-out hole; 1102. Second gate lead-out hole; 1103. Shielding gate lead-out hole; 1104. Source lead-out hole; 111. Dielectric layer; 112. First gate metal region; 113. Second gate metal region; 114. Source metal region; 115. Drain metal region; 116. Second polysilicon layer; 117. Second via implantation region; 118. Gate oxide layer. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0029] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0030] Example 1

[0031] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a shielded gate trench power semiconductor device is provided, the equivalent circuit of which is as follows: Figure 2As shown, the device includes a first gate G, a source S, and a drain D, and further includes: a second gate G' connected to an external circuit control unit (not shown) for receiving a first control signal; a polycrystalline resistor 1 formed between the first gate G and the second gate G' for generating a second control signal at the first gate G based on a voltage drop across the polycrystalline resistor 1 caused by at least one of the first control signal and a surge current, so as to control the on and off states of the shielded gate trench power semiconductor device according to the second control signal; and a trigger channel 2 formed between the drain D and the first gate G, wherein the breakdown voltage of the trigger channel 2 is less than the device breakdown voltage, and is used to discharge the surge current from the drain D through the trigger channel 2, the polycrystalline resistor 1, and the external circuit control unit to ground when the surge voltage of the drain D exceeds the breakdown voltage of the trigger channel 2 but does not exceed the device breakdown voltage.

[0032] Specifically, in existing protection circuit topologies, surge protection TVS devices and heat-resistant MOSFET devices are used in separate packages, which increases costs and wastes space. In this embodiment, the surge protection function of TVS and the heat-resistant function of MOSFET are integrated on the same MOSFET chip, realizing a multi-functional shielded trench MOSFET device, saving chip area, thereby reducing costs and improving the market competitiveness of the product.

[0033] In this embodiment, the first gate G, source S, and drain D are the original electrodes of the MOSFET chip, and the MOSFET chip itself has a burn-out prevention function.

[0034] To further optimize the device performance, a second gate G' is added, and a polysilicon resistor 1 is formed between the second gate G' and the first gate G, and a trigger channel 2 is formed between the drain D and the first gate G.

[0035] When a surge event occurs, because the breakdown voltage of trigger channel 2 is less than the drain-source breakdown voltage of the MOSFET device itself, trigger channel 2 will break down before the MOSFET. When trigger channel 2 breaks down, the surge current will pass through polysilicon resistor 1 and then be discharged to ground through the external circuit control unit.

[0036] Simultaneously, during this process, the voltage drop generated by the current across the polycrystalline resistor 1 acts on the first gate G of the MOSFET. When the voltage drop exceeds the MOSFET's threshold voltage, the MOSFET channel is in the ON state, and subsequent larger surge currents will be discharged to ground along the MOSFET channel, achieving the surge discharge function of a traditional TVS and protecting the device from surge voltage impacts. Based on this, the device of the present invention simultaneously possesses the surge discharge function of a traditional TVS and its built-in burn-out prevention function.

[0037] Furthermore, such as Figure 2 As shown, the shielded gate trench power semiconductor device also includes an electrostatic discharge (ESD) diode 3, which is connected between the second gate G' and the source S. The ESD diode 3 is a bidirectional ESD diode.

[0038] Specifically, in this embodiment, bidirectional electrostatic discharge (ESD) protection is achieved between the second gate G' and the source S through a bidirectional ESD protection diode, preventing ESD from damaging the device and further improving the device's reliability and stability.

[0039] Furthermore, the front-side structure of shielded gate trench power semiconductor devices is as follows: Figure 3 As shown, the back structure is as follows Figure 4 As shown, the device structure includes: a substrate 101 of a first conductivity type, the substrate 101 including at least a cell region and a peripheral region located around the cell region; preferably, the substrate 101 is a heavily doped substrate; an epitaxial layer 102 of the first conductivity type is formed on the upper surface of the substrate 101; preferably, the epitaxial layer 102 is a lightly doped epitaxial layer, the thickness of the epitaxial layer 102 is 1~10μm, and the resistivity is 0.1~1.0 ohm·cm; by changing the resistivity of the epitaxial layer, the MOSFET's resistance can be adjusted. The breakdown voltage and on-resistance can be flexibly adjusted; multiple shielding gate trenches are formed in the epitaxial layer 102, and each shielding gate trench has a shielding gate polysilicon layer 103 and a first gate polysilicon layer 104 of the first conductivity type; preferably, a field oxide layer 107 is formed at the bottom and lower sidewall of the shielding gate trench, and a gate oxide layer 118 is formed on the upper sidewall and between the shielding gate polysilicon layer 103 and the first gate polysilicon layer 104; a second polysilicon layer 116 of the second conductivity type is formed in the peripheral region. In the first gate polysilicon layer 104, a second polysilicon layer 116 of the second conductivity type is alternately disposed with the first gate polysilicon layer 104 of the first conductivity type to form a diode string as an electrostatic discharge (ESD) diode; a deep well region 106 of the first conductivity type is formed in the epitaxial layer 102; preferably, the junction depth of the deep well region 106 is 0.5~1.5μm; a body region 105 of the second conductivity type is formed in the epitaxial layer 102 in other areas except for the shielding gate trench; preferably, the junction depth of the body region 105 is... The deep well region 106, with a depth of approximately 0.3~0.8μm, is located below the body region 105 of the peripheral region. The junction breakdown voltage between the body region 105 and the deep well region 106 is lower than the junction breakdown voltage between the body region 105 and the epitaxial layer 102. An implantation region 109 of the first conductivity type is formed in the body region 105. Preferably, the implantation region 109 is a heavily doped implantation region, serving as the source of the MOSFET device. The junction depth of the implantation region 109 is 0.15μm-0.35μm, and the doping concentration ranges from 1.0*10⁻⁶. 18 cm 3 ~1.0*10 20 cm3 A dielectric layer 111 is formed on the upper surface of the epitaxial layer 102. Multiple contact holes 110 are etched in the dielectric layer 111. These contact holes 110 include a first gate lead-out hole 1101 corresponding to the first gate polysilicon layer of the cell region, a second gate lead-out hole 1102 corresponding to the first gate polysilicon layer of the peripheral region, a shielding gate lead-out hole 1103 corresponding to the shielding gate polysilicon layer 103, and multiple source lead-out holes 1104 corresponding to the implantation region 109. Preferably, the dielectric layer 111 is an interlayer dielectric (ILD) layer, formed by tetraethyl orthosilicate (TEOS) and boron phosphosilicate glass. Formed after reflow of Glass (BPSG); preferably, the thickness of dielectric layer 111 is 3000-10000 Å; a first hole injection region 108 of the second conductivity type is formed in the remaining body regions 105 except for the body region above the deep well region 106, and the first hole injection region 108 is located below the injection region 109; preferably, the first hole injection region 108 is a heavily doped injection region; a second hole injection region 117 of the first conductivity type is formed in the body region 105 above the deep well region 106, and the second hole injection region 117 is located below the injection region 109; preferably, the second hole injection region 111... 7 is a heavily doped implantation region; a front metal layer is formed on the upper surface of the dielectric layer 111 and fills the contact hole 110. The front metal layer includes a first gate metal region 112, a second gate metal region 113, and a source metal region 114. The first gate metal region 112 is in ohmic contact with the first gate polysilicon layer of the cell region, the second gate metal region 113 is in ohmic contact with the first gate polysilicon layer of the peripheral region, and the source metal region 114 is in ohmic contact with the shielding gate polysilicon layer 103 and the implantation region 109; a back metal layer is formed on the lower surface of the substrate. The back metal layer is the drain metal region 115, which serves as the device drain.

[0040] Furthermore, the polysilicon resistor 1 is the resistor formed by the first gate polysilicon layer 104 between the first gate lead-out via 1101 and the second gate lead-out via 1102; furthermore, the resistance value of the polysilicon resistor 1 is 200Ω~1000Ω; in some embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. This invention will be described using an example where the first conductivity type is N-type and the second conductivity type is P-type.

[0041] The front view of the device structure of the present invention is shown below. Figure 3As shown, its structure, from bottom to top, includes an N+ type substrate 101, an N- type epitaxial region 102, a shielding gate polysilicon layer 103, an N-type gate polysilicon region 104, a P-type body region 105, an N-type deep well region 106, a field oxide layer 107, a gate oxide layer 118, a P+ type first hole injection region 108, an N+ type injection region 109, an N+ type second hole injection region 117, a contact hole 110 (including a first gate lead-out hole 1101, a second gate lead-out hole 1102, a shielding gate lead-out hole 1103, and a source lead-out hole 1104), an ILD dielectric layer 111, a first gate metal region 112, a second gate metal region 113, a source metal region 114, and a drain metal region 115.

[0042] The back structure of the device of the present invention is as follows Figure 4 As shown, a P-type second polysilicon layer 116 is formed by ion implantation within the first gate polysilicon layer 104 in the outer perimeter shielding trench. The second polysilicon layer 116 and the first gate polysilicon layer 104 are alternately arranged and have opposite conductivity types, forming a diode string. Bidirectional electrostatic discharge (ESD) protection is achieved between the second gate G' and the source S through a bidirectional ESD protection diode formed by multiple polysilicon diodes connected in series within the outer perimeter trench.

[0043] The device layout structure of the present invention is as follows: Figure 5 As shown, on a projection plane perpendicular to the substrate 101, the source metal region 114 covers a portion of the cell trench and extends to cover the peripheral trench on the first side. The first gate metal region 112 is arranged along the other three side edges of the device (excluding the first side) and at least covers a portion of the cell trench, forming a C-shape and surrounding the source metal region 114. The second gate metal region 113 is located at one of the corners of the device. Furthermore, the first gate metal region 112, the second gate metal region 113, and the source metal region 114 do not overlap. The second polysilicon layer 116 is located within the peripheral trench and alternates with the first gate polysilicon layer 104.

[0044] This invention provides a method for fabricating a shielded gate trench power semiconductor device, used to fabricate the shielded gate trench power semiconductor device as described above. The device includes a first gate, a source, and a drain. The method includes: forming a second gate G' to receive a first control signal from an external circuit control unit; forming a polycrystalline resistor 1 between the first gate G and the second gate G'; generating a second control signal at the first gate G based on the voltage drop across the polycrystalline resistor 1 caused by at least one of the first control signal and a surge current, to control the on / off state of the shielded gate trench power semiconductor device according to the second control signal; forming a trigger channel 2 between the drain D and the first gate G, wherein the breakdown voltage of the trigger channel 2 is less than the device breakdown voltage, so that when the surge voltage of the drain D exceeds the breakdown voltage of the trigger channel 2 but does not exceed the device breakdown voltage, the surge current is discharged from the drain D sequentially through the trigger channel 2, the polycrystalline resistor 1, and the external circuit control unit to ground.

[0045] The method for fabricating the device of the present invention includes the following steps:

[0046] Step 1: An N-type epitaxial region 102 is grown on an N+ type substrate 101. The thickness of the N-type epitaxial region 102 is 1~10 μm and the resistivity is 0.1~1.0 ohm·cm.

[0047] Step 2, as follows Figure 6 As shown, a deep trench is formed on the N-type epitaxial region 102 by etching and then oxidized to form a field oxide layer 107 at the bottom and lower sidewall of the deep trench. The thickness of the field oxide layer 107 is 1000~2000 Å.

[0048] Step 3: Form the shielding gate polysilicon layer 103 through N-type polysilicon deposition and etching processes;

[0049] Step 4: A gate oxide layer 118 is grown on the shielding gate polysilicon layer 103 and the upper sidewall of the deep trench, and N-type polysilicon is deposited and etched to form a first gate polysilicon layer 104.

[0050] Step 5, as follows Figure 7 As shown, a P-type second polysilicon layer 116 is formed in the first gate polysilicon layer 104 of the peripheral region by boron ion implantation; a diode string with N / P region spacing is formed in the trench of the peripheral region to achieve bidirectional electrostatic protection;

[0051] Step 6, as follows Figure 8 As shown, an N-type deep well region 106 is formed by ion implantation and high-temperature push-in, and the junction depth of the N-type deep well region 106 is about 0.5~1.5μm;

[0052] Step 7, as follows Figure 9As shown, a P-type body region 105 is formed by ion implantation and push-well formation. This ion implantation step does not require a mask. The junction depth of the P-type body region 105 is about 0.3~0.8μm. The P-type body region 105 and the N-type deep well region 106 formed by the above process steps achieve a junction breakdown voltage that is lower than that of the P-type body region 105 and the N-type epitaxial layer 102.

[0053] Step 8, as follows Figure 10 As shown, the N+ type implantation region 109 is formed by ion implantation and annealing, a process that does not require a mask; the junction depth of the N+ type implantation region 109 is 0.15μm-0.35μm; as the source of the MOSFET, its doping concentration ranges from 1.0*10⁻⁶. 18 cm 3 ~1.0*10 20 cm 3 ;

[0054] Step 9: Deposition to form ILD dielectric layer 111. ILD dielectric layer 111 is formed by reflow of TEOS and BPSG, and the final thickness of dielectric layer 111 is 3000-10000 Å.

[0055] Step 10: Etching to form contact holes 110, including a first gate lead-out hole 1101, a second gate lead-out hole 1102, a shielding gate lead-out hole 1103, and a source lead-out hole 1104; forming a P+ type first hole implantation region 108 and an N+ type second hole implantation region 117 by ion implantation; a polycrystalline resistor 1 formed by polycrystalline silicon doping is located between the first gate lead-out hole 1101 and the second gate lead-out hole 1102.

[0056] Step 11, as follows Figure 11 As shown, a front metal layer is deposited on the dielectric layer 111, including a first gate metal region 112, a second gate metal region 113, and a source metal region 114; and a back metal layer is deposited on the lower surface of the substrate 101, including a drain metal region 115; in this embodiment, the metal layer is made of aluminum-silicon-copper material, and its thickness is 3μm-5μm; after metal etching, it serves as the source S, the first gate G, the second gate G', and the drain D.

[0057] In this embodiment, trigger channel 2 is an NPN type trigger channel.

[0058] The device structure proposed in this invention integrates the surge protection function of TVS and the burn-out prevention function of MOSFET itself into the same MOSFET chip. Compared with the prior art where the breakdown voltage of MOSFET is determined by the PN junction of N-type epitaxial layer 102 and P-type body region 105, in this embodiment, the surge protection function proposed in this invention is integrated into the existing MOSFET technology by designing the breakdown mode of the existing MOSFET.

[0059] Specifically, by introducing an N-type deep well region 106, a first trigger channel from the drain to the source of the MOSFET is constructed in the MOSFET cell region. This first trigger channel is an NPN type low trigger voltage channel consisting of an N+ type substrate 101, an N-type epitaxial region 102, an N-type deep well region 106, a P-type body region 105, and an N+ type second hole injection region 117.

[0060] The first gate G passes through an N-type polycrystalline resistor 1 to the second gate G', which is connected to an external circuit control unit. This polycrystalline resistor 1 is a POLY resistor, which enables the first gate drive function of the MOSFET during surge protection. When the drain D detects a surge event, the NPN low-trigger channel will break down first because its breakdown voltage is lower than the drain-source breakdown voltage of the MOSFET itself. At this time, the current will first pass through the 200-1000Ω N-type polycrystalline resistor 1 between the first and second gates, and then be discharged to ground via the external circuit control unit.

[0061] Simultaneously, during this discharge process, the voltage drop generated by the current across the N-type polycrystalline resistor 1 will act on the first gate G of the MOSFET. When the voltage drop exceeds the threshold voltage of the MOSFET, the MOSFET channel will open, and a larger surge current will be discharged to ground along the MOSFET channel, thereby realizing the surge discharge function of a traditional TVS and protecting subsequent ICs from surge damage.

[0062] A comparison of the surge clamping voltage and discharge current waveforms of a conventional TVS and the shielded gate trench power semiconductor device in the preferred embodiment 1 of this invention. Figure 12 As shown. Because the shielded gate trench MOSFET has a low on-resistance, the structure proposed in this invention has a lower dynamic resistance than the traditional TVS during surge discharge. That is, as the discharge current Ipp increases or decreases, the clamping voltage Vc remains almost stable, providing stronger protection for the subsequent charging IC.

[0063] Similarly, an NPN-type trigger channel path exists between the first gate G and the drain D, realizing a bidirectional voltage-resistant structure. This bidirectional voltage-resistant structure not only forms a low-voltage trigger path, but also ensures that the signal of the second gate G' is fully applied to the drain D, ensuring that the first gate G of the MOSFET functions normally.

[0064] A low-trigger voltage trigger channel 2 is formed between the drain D and the first gate G. This trigger channel 2 is a bidirectional device to ensure that the voltage applied to the second gate G' by the external control unit does not attenuate when it passes through the N-type polysilicon resistor 1 and is applied to the first gate G. Experiments show that if the low-trigger device between the first gate G and the drain D is a unidirectional device, the voltage of the second gate G' will flow along the first gate G to the drain D, thereby limiting the turn-on state of the MOSFET.

[0065] The present invention also achieves bidirectional electrostatic discharge protection by setting a trench polycrystalline diode string between the second gate and the source, thereby further enhancing the stability and reliability of the device.

[0066] This invention integrates two functional chips through process integration, achieving a multi-functional single chip, saving package size, and reducing costs. Through packaging design, this invention can achieve miniaturized packaging of traditional DFN2020-6L and smaller sizes, providing strong support for the miniaturization and integration of electronic devices.

[0067] Example 2

[0068] This invention provides a shielded gate trench power semiconductor device, the front structure of which is as follows: Figure 13 As shown, the device in this embodiment 2 differs from that in embodiment 1 in that: a P-type buried layer 125 is added, and part of the shielding gate trench extends downward to the P-type buried layer 125; at the same time, the outer periphery region or the body region 105 closest to the outer periphery region is removed, and the N+ type second hole injection region 117 is replaced by a P+ type first hole injection region 108. Other structures are the same as in embodiment 1, and will not be described again here.

[0069] The device structure of this embodiment includes: a substrate 101 of a first conductivity type, the substrate 101 including at least a cell region and a peripheral region located around the cell region; a buried layer 125 of a second conductivity type formed on at least a portion of the upper surface of the substrate 101; an epitaxial layer 102 of the first conductivity type formed on the upper surface of the substrate 101 and the buried layer 125; a plurality of shielding gate trenches formed in the epitaxial layer 102, each shielding gate trench having a shielding gate polysilicon layer 103 and a first gate polysilicon layer 104 of the first conductivity type; a field oxide layer 107 formed at the bottom and lower sidewalls of the shielding gate trench, and a gate oxide layer formed at the upper sidewalls and between the shielding gate polysilicon layer 103 and the first gate polysilicon layer 104. The epitaxial layer 118; wherein, the buried layer 125 is located below the shielding gate trench where the polycrystalline resistor 1 is located, and the shielding gate trench adjacent to the shielding gate trench where the polycrystalline resistor 1 is located extends into the buried layer 125 in the direction of the buried layer 125; a second polycrystalline silicon layer 116 of the second conductivity type is formed in the first gate polycrystalline silicon layer 104 of the peripheral region, and the second polycrystalline silicon layer 116 of the second conductivity type and the first gate polycrystalline silicon layer 104 of the first conductivity type are alternately arranged to form a diode string as an electrostatic discharge protection diode; a body region 105 of the second conductivity type is formed in the other regions of the epitaxial layer 102 except for the shielding gate trench; an implantation region 109 of the first conductivity type is formed in the body region 105; A dielectric layer 111 is formed on the upper surface of the epitaxial layer 102. Multiple contact holes 110 are etched in the dielectric layer 111. These contact holes 110 include a first gate lead-out hole 1101 corresponding to the first gate polysilicon layer of the cell region, a second gate lead-out hole 1102 corresponding to the first gate polysilicon layer of the peripheral region, a shielding gate lead-out hole 1103 corresponding to the shielding gate polysilicon layer 103, and multiple source lead-out holes 1104 corresponding to the implantation region 109. A first via implantation region 108 of the second conductivity type is formed in the body region 105 and the epitaxial layer 102, and the first via implantation region 108 is located below the implantation region 109. The first via implantation region 108 above the buried layer 125 is formed in the epitaxial layer 102. In 02, the first hole injection regions 108, except for the first hole injection region above the buried layer 125, are formed in the body region 105; the front metal layer is formed on the upper surface of the dielectric layer 111 and fills the contact hole 110. The front metal layer includes a first gate metal region 112, a second gate metal region 113, and a source metal region 114. The first gate metal region 112 is in ohmic contact with the first gate polysilicon layer of the cell region, the second gate metal region 113 is in ohmic contact with the first gate polysilicon layer of the peripheral region, and the source metal region 114 is in ohmic contact with the shielding gate polysilicon layer 103 and the injection region 109; the back metal layer is formed on the lower surface of the substrate. The back metal layer is the drain metal region 115, which serves as the device drain.

[0070] In this embodiment, trigger channel 2 is an NPNP type trigger channel. An NPNP type low trigger voltage trigger channel is formed by an N+ type substrate 101, a P-type buried layer 125, an N-type epitaxial layer 102, and a P-type first via injection region 108. This NPNP type low breakdown voltage path can also achieve the withstand voltage from the first gate G to the drain D; simultaneously, the shielding gate trench closest to the peripheral region extends downwards to the P-type buried layer 125, forming a deep trench isolation structure, which can suppress parasitic problems between the low trigger channel and the MOSFET cell region, increasing surge protection while ensuring the normal operation of the MOSFET itself.

[0071] Furthermore, the present invention can also provide a control method for a shielded gate trench power semiconductor device, comprising the following steps: a second gate G' receives a first control signal from an external circuit control unit; a second control signal is generated at the first gate G based on the voltage drop across the polycrystalline resistor 1 between the second gate G' and the first gate G, according to at least one of the first control signal and the surge current, to control the on / off state of the shielded gate trench power semiconductor device according to the second control signal; when the surge voltage of the drain D exceeds the breakdown voltage of the trigger channel 2 but does not exceed the device breakdown voltage, the surge current is discharged from the drain D sequentially through the trigger channel 2, the polycrystalline resistor 1 and the external circuit control unit to ground.

[0072] The protection scheme mentioned in this invention can effectively protect against abnormal surges or short circuits caused by foreign objects in the charging ports of widely used consumer electronics and industrial equipment.

[0073] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A shielded gate trench type power semiconductor device, comprising a first gate, a source, and a drain, characterized in that, Also includes: The second gate is connected to an external circuit control unit and is used to receive the first control signal; A polycrystalline resistor, formed between the first gate and the second gate, is used to generate a second control signal at the first gate based on a voltage drop generated on the polycrystalline resistor according to at least one of the first control signal and a surge current, so as to control the on / off state of the shielded gate trench power semiconductor device according to the second control signal. A trigger channel is formed between the drain and the first gate. The breakdown voltage of the trigger channel is less than the device breakdown voltage. When the surge voltage of the drain exceeds the breakdown voltage of the trigger channel but does not exceed the device breakdown voltage, the surge current is discharged from the drain to ground through the trigger channel, the polycrystalline resistor and the external circuit control unit in sequence. A substrate of a first conductivity type, the substrate comprising at least a cell region and a peripheral region located around the cell region; An epitaxial layer of the first conductivity type is formed on the upper surface of the substrate; A body region of the second conductivity type is formed in the epitaxial layer; An injection region of the first conductivity type is formed in the body region; A deep well region of a first conductivity type is formed in the epitaxial layer, and the deep well region is located below the body region of the peripheral region; A second hole injection region of a first conductivity type is formed in the body region above the deep well region, and the second hole injection region is located below the injection region; A dielectric layer is formed on the upper surface of the epitaxial layer. A plurality of contact holes are etched in the dielectric layer. These contact holes include a first gate lead-out corresponding to the first gate polysilicon layer of the cell region, a second gate lead-out corresponding to the first gate polysilicon layer of the peripheral region, a shielding gate lead-out corresponding to the shielding gate polysilicon layer, and a plurality of source leads-out corresponding to the implantation region. The polysilicon resistance is the resistance formed by the first gate polysilicon layer between the first gate lead-out and the second gate lead-out. A front metal layer is formed on the upper surface of the dielectric layer and fills the contact hole. The front metal layer includes a first gate metal region, a second gate metal region, and a source metal region. The first gate metal region is in ohmic contact with the first gate polysilicon layer of the cell region. The second gate metal region is in ohmic contact with the first gate polysilicon layer of the peripheral region. The source metal region is in ohmic contact with the shielding gate polysilicon layer and the implantation region. A back metal layer is formed on the lower surface of the substrate, and the back metal layer serves as the device drain.

2. A shielded gate trench type power semiconductor device, comprising a first gate, a source, and a drain, characterized in that, Also includes: The second gate is connected to an external circuit control unit and is used to receive the first control signal; A polycrystalline resistor, formed between the first gate and the second gate, is used to generate a second control signal at the first gate based on a voltage drop generated on the polycrystalline resistor according to at least one of the first control signal and a surge current, so as to control the on / off state of the shielded gate trench power semiconductor device according to the second control signal. A trigger channel is formed between the drain and the first gate. The breakdown voltage of the trigger channel is less than the device breakdown voltage. When the surge voltage of the drain exceeds the breakdown voltage of the trigger channel but does not exceed the device breakdown voltage, the surge current is discharged from the drain to ground through the trigger channel, the polycrystalline resistor and the external circuit control unit in sequence. A substrate of a first conductivity type, the substrate comprising at least a cell region and a peripheral region located around the cell region; An epitaxial layer of the first conductivity type is formed on the upper surface of the substrate; A body region of the second conductivity type is formed in the epitaxial layer; An injection region of the first conductivity type is formed in the body region; A first hole injection region of the second conductivity type is formed below the injection region; A buried layer of a second conductivity type is formed on at least a portion of the upper surface of the substrate, and the epitaxial layer is located on the upper surfaces of the substrate and the buried layer; The buried layer is located below the shielding trench where the polycrystalline resistor is located, and the shielding trench adjacent to the shielding trench where the polycrystalline resistor is located extends into the buried layer in the direction of the buried layer. A dielectric layer is formed on the upper surface of the epitaxial layer. A plurality of contact holes are etched in the dielectric layer. These contact holes include a first gate lead-out corresponding to the first gate polysilicon layer of the cell region, a second gate lead-out corresponding to the first gate polysilicon layer of the peripheral region, a shielding gate lead-out corresponding to the shielding gate polysilicon layer, and a plurality of source leads-out corresponding to the implantation region. The polysilicon resistance is the resistance formed by the first gate polysilicon layer between the first gate lead-out and the second gate lead-out. A front metal layer is formed on the upper surface of the dielectric layer and fills the contact hole. The front metal layer includes a first gate metal region, a second gate metal region, and a source metal region. The first gate metal region is in ohmic contact with the first gate polysilicon layer of the cell region. The second gate metal region is in ohmic contact with the first gate polysilicon layer of the peripheral region. The source metal region is in ohmic contact with the shielding gate polysilicon layer and the implantation region. A back metal layer is formed on the lower surface of the substrate, and the back metal layer serves as the device drain.

3. The shielded gate trench power semiconductor device according to claim 1 or 2, characterized in that, Also includes: An electrostatic discharge (ESD) protection diode is connected between the second gate and the source, and the ESD protection diode is a bidirectional ESD protection diode.

4. The shielded gate trench power semiconductor device according to claim 3, characterized in that, Also includes: Multiple shielding gate trenches are formed in the epitaxial layer, and each shielding gate trench contains a shielding gate polysilicon layer and a first gate polysilicon layer of a first conductivity type. A second polysilicon layer of the second conductivity type is formed in the first gate polysilicon layer of the peripheral region, and the second polysilicon layer of the second conductivity type and the first gate polysilicon layer of the first conductivity type are alternately arranged to form a diode string as the electrostatic discharge protection diode.

5. The shielded gate trench power semiconductor device according to claim 1, characterized in that, Also includes: The first hole injection region of the second conductivity type is formed below the injection region.

6. The shielded gate trench power semiconductor device according to claim 5, characterized in that, The first injection region is formed in the remaining body regions except for the body region above the deep well region.

7. The shielded gate trench power semiconductor device according to claim 2, characterized in that, The first hole injection region above the buried layer is formed in the epitaxial layer, and other first hole injection regions besides the first hole injection region above the buried layer are formed in the body region.

8. The shielded gate trench power semiconductor device according to claim 1 or 2, characterized in that, The resistance of the polycrystalline resistor is 200Ω~1000Ω.

9. A method for fabricating a shielded gate trench power semiconductor device, characterized in that, A method for fabricating a shielded gate trench power semiconductor device as described in any one of claims 1-8, the device comprising a first gate, a source, and a drain, comprising: A second gate is formed to receive the first control signal from the external circuit control unit; A polycrystalline resistor is formed between the first gate and the second gate. A second control signal is generated at the first gate based on the voltage drop generated on the polycrystalline resistor by at least one of the first control signal and the surge current, so as to control the on / off state of the shielded gate trench power semiconductor device according to the second control signal. A trigger channel is formed between the drain and the first gate. The breakdown voltage of the trigger channel is less than the device breakdown voltage. When the surge voltage of the drain exceeds the breakdown voltage of the trigger channel but does not exceed the device breakdown voltage, the surge current is discharged from the drain to ground through the trigger channel, the polycrystalline resistor and the external circuit control unit in sequence.

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